2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_LIVENESS_ANALYSIS
27 #define USE_TCG_OPTIMIZATIONS
31 /* Define to jump the ELF file used to communicate with GDB. */
34 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
35 /* define it to suppress various consistency checks (faster) */
39 #include "qemu-common.h"
40 #include "qemu/cache-utils.h"
41 #include "qemu/host-utils.h"
42 #include "qemu/timer.h"
44 /* Note: the long term plan is to reduce the dependancies on the QEMU
45 CPU definitions. Currently they are used for qemu_ld/st
47 #define NO_CPU_IO_DEFS
52 #if TCG_TARGET_REG_BITS == 64
53 # define ELF_CLASS ELFCLASS64
55 # define ELF_CLASS ELFCLASS32
57 #ifdef HOST_WORDS_BIGENDIAN
58 # define ELF_DATA ELFDATA2MSB
60 # define ELF_DATA ELFDATA2LSB
65 /* Forward declarations for functions declared in tcg-target.c and used here. */
66 static void tcg_target_init(TCGContext *s);
67 static void tcg_target_qemu_prologue(TCGContext *s);
68 static void patch_reloc(uint8_t *code_ptr, int type,
69 tcg_target_long value, tcg_target_long addend);
71 /* The CIE and FDE header definitions will be common to all hosts. */
73 uint32_t len __attribute__((aligned((sizeof(void *)))));
79 uint8_t return_column;
82 typedef struct QEMU_PACKED {
83 uint32_t len __attribute__((aligned((sizeof(void *)))));
85 tcg_target_long func_start;
86 tcg_target_long func_len;
87 } DebugFrameFDEHeader;
89 static void tcg_register_jit_int(void *buf, size_t size,
90 void *debug_frame, size_t debug_frame_size)
91 __attribute__((unused));
93 /* Forward declarations for functions declared and used in tcg-target.c. */
94 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
95 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
96 tcg_target_long arg2);
97 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
98 static void tcg_out_movi(TCGContext *s, TCGType type,
99 TCGReg ret, tcg_target_long arg);
100 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
101 const int *const_args);
102 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
103 tcg_target_long arg2);
104 static int tcg_target_const_match(tcg_target_long val,
105 const TCGArgConstraint *arg_ct);
107 TCGOpDef tcg_op_defs[] = {
108 #define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
112 const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
114 static TCGRegSet tcg_target_available_regs[2];
115 static TCGRegSet tcg_target_call_clobber_regs;
117 static inline void tcg_out8(TCGContext *s, uint8_t v)
122 static inline void tcg_out16(TCGContext *s, uint16_t v)
124 uint8_t *p = s->code_ptr;
129 static inline void tcg_out32(TCGContext *s, uint32_t v)
131 uint8_t *p = s->code_ptr;
136 /* label relocation processing */
138 static void tcg_out_reloc(TCGContext *s, uint8_t *code_ptr, int type,
139 int label_index, long addend)
144 l = &s->labels[label_index];
146 /* FIXME: This may break relocations on RISC targets that
147 modify instruction fields in place. The caller may not have
148 written the initial value. */
149 patch_reloc(code_ptr, type, l->u.value, addend);
151 /* add a new relocation entry */
152 r = tcg_malloc(sizeof(TCGRelocation));
156 r->next = l->u.first_reloc;
157 l->u.first_reloc = r;
161 static void tcg_out_label(TCGContext *s, int label_index, void *ptr)
165 tcg_target_long value = (tcg_target_long)ptr;
167 l = &s->labels[label_index];
170 r = l->u.first_reloc;
172 patch_reloc(r->ptr, r->type, value, r->addend);
179 int gen_new_label(void)
181 TCGContext *s = &tcg_ctx;
185 if (s->nb_labels >= TCG_MAX_LABELS)
187 idx = s->nb_labels++;
190 l->u.first_reloc = NULL;
194 #include "tcg-target.c"
196 /* pool based memory allocation */
197 void *tcg_malloc_internal(TCGContext *s, int size)
202 if (size > TCG_POOL_CHUNK_SIZE) {
203 /* big malloc: insert a new pool (XXX: could optimize) */
204 p = g_malloc(sizeof(TCGPool) + size);
206 p->next = s->pool_first_large;
207 s->pool_first_large = p;
218 pool_size = TCG_POOL_CHUNK_SIZE;
219 p = g_malloc(sizeof(TCGPool) + pool_size);
223 s->pool_current->next = p;
232 s->pool_cur = p->data + size;
233 s->pool_end = p->data + p->size;
237 void tcg_pool_reset(TCGContext *s)
240 for (p = s->pool_first_large; p; p = t) {
244 s->pool_first_large = NULL;
245 s->pool_cur = s->pool_end = NULL;
246 s->pool_current = NULL;
249 void tcg_context_init(TCGContext *s)
251 int op, total_args, n;
253 TCGArgConstraint *args_ct;
256 memset(s, 0, sizeof(*s));
259 /* Count total number of arguments and allocate the corresponding
262 for(op = 0; op < NB_OPS; op++) {
263 def = &tcg_op_defs[op];
264 n = def->nb_iargs + def->nb_oargs;
268 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
269 sorted_args = g_malloc(sizeof(int) * total_args);
271 for(op = 0; op < NB_OPS; op++) {
272 def = &tcg_op_defs[op];
273 def->args_ct = args_ct;
274 def->sorted_args = sorted_args;
275 n = def->nb_iargs + def->nb_oargs;
283 void tcg_prologue_init(TCGContext *s)
285 /* init global prologue and epilogue */
286 s->code_buf = s->code_gen_prologue;
287 s->code_ptr = s->code_buf;
288 tcg_target_qemu_prologue(s);
289 flush_icache_range((tcg_target_ulong)s->code_buf,
290 (tcg_target_ulong)s->code_ptr);
293 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
294 size_t size = s->code_ptr - s->code_buf;
295 qemu_log("PROLOGUE: [size=%zu]\n", size);
296 log_disas(s->code_buf, size);
303 void tcg_set_frame(TCGContext *s, int reg,
304 tcg_target_long start, tcg_target_long size)
306 s->frame_start = start;
307 s->frame_end = start + size;
311 void tcg_func_start(TCGContext *s)
315 s->nb_temps = s->nb_globals;
316 for(i = 0; i < (TCG_TYPE_COUNT * 2); i++)
317 s->first_free_temp[i] = -1;
318 s->labels = tcg_malloc(sizeof(TCGLabel) * TCG_MAX_LABELS);
320 s->current_frame_offset = s->frame_start;
322 #ifdef CONFIG_DEBUG_TCG
323 s->goto_tb_issue_mask = 0;
326 s->gen_opc_ptr = s->gen_opc_buf;
327 s->gen_opparam_ptr = s->gen_opparam_buf;
329 #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
330 /* Initialize qemu_ld/st labels to assist code generation at the end of TB
331 for TLB miss cases at the end of TB */
332 s->qemu_ldst_labels = tcg_malloc(sizeof(TCGLabelQemuLdst) *
334 s->nb_qemu_ldst_labels = 0;
338 static inline void tcg_temp_alloc(TCGContext *s, int n)
340 if (n > TCG_MAX_TEMPS)
344 static inline int tcg_global_reg_new_internal(TCGType type, int reg,
347 TCGContext *s = &tcg_ctx;
351 #if TCG_TARGET_REG_BITS == 32
352 if (type != TCG_TYPE_I32)
355 if (tcg_regset_test_reg(s->reserved_regs, reg))
358 tcg_temp_alloc(s, s->nb_globals + 1);
359 ts = &s->temps[s->nb_globals];
360 ts->base_type = type;
366 tcg_regset_set_reg(s->reserved_regs, reg);
370 TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
374 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
375 return MAKE_TCGV_I32(idx);
378 TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
382 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
383 return MAKE_TCGV_I64(idx);
386 static inline int tcg_global_mem_new_internal(TCGType type, int reg,
387 tcg_target_long offset,
390 TCGContext *s = &tcg_ctx;
395 #if TCG_TARGET_REG_BITS == 32
396 if (type == TCG_TYPE_I64) {
398 tcg_temp_alloc(s, s->nb_globals + 2);
399 ts = &s->temps[s->nb_globals];
400 ts->base_type = type;
401 ts->type = TCG_TYPE_I32;
403 ts->mem_allocated = 1;
405 #ifdef TCG_TARGET_WORDS_BIGENDIAN
406 ts->mem_offset = offset + 4;
408 ts->mem_offset = offset;
410 pstrcpy(buf, sizeof(buf), name);
411 pstrcat(buf, sizeof(buf), "_0");
412 ts->name = strdup(buf);
415 ts->base_type = type;
416 ts->type = TCG_TYPE_I32;
418 ts->mem_allocated = 1;
420 #ifdef TCG_TARGET_WORDS_BIGENDIAN
421 ts->mem_offset = offset;
423 ts->mem_offset = offset + 4;
425 pstrcpy(buf, sizeof(buf), name);
426 pstrcat(buf, sizeof(buf), "_1");
427 ts->name = strdup(buf);
433 tcg_temp_alloc(s, s->nb_globals + 1);
434 ts = &s->temps[s->nb_globals];
435 ts->base_type = type;
438 ts->mem_allocated = 1;
440 ts->mem_offset = offset;
447 TCGv_i32 tcg_global_mem_new_i32(int reg, tcg_target_long offset,
452 idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
453 return MAKE_TCGV_I32(idx);
456 TCGv_i64 tcg_global_mem_new_i64(int reg, tcg_target_long offset,
461 idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
462 return MAKE_TCGV_I64(idx);
465 static inline int tcg_temp_new_internal(TCGType type, int temp_local)
467 TCGContext *s = &tcg_ctx;
474 idx = s->first_free_temp[k];
476 /* There is already an available temp with the
479 s->first_free_temp[k] = ts->next_free_temp;
480 ts->temp_allocated = 1;
481 assert(ts->temp_local == temp_local);
484 #if TCG_TARGET_REG_BITS == 32
485 if (type == TCG_TYPE_I64) {
486 tcg_temp_alloc(s, s->nb_temps + 2);
487 ts = &s->temps[s->nb_temps];
488 ts->base_type = type;
489 ts->type = TCG_TYPE_I32;
490 ts->temp_allocated = 1;
491 ts->temp_local = temp_local;
494 ts->base_type = TCG_TYPE_I32;
495 ts->type = TCG_TYPE_I32;
496 ts->temp_allocated = 1;
497 ts->temp_local = temp_local;
503 tcg_temp_alloc(s, s->nb_temps + 1);
504 ts = &s->temps[s->nb_temps];
505 ts->base_type = type;
507 ts->temp_allocated = 1;
508 ts->temp_local = temp_local;
514 #if defined(CONFIG_DEBUG_TCG)
520 TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
524 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
525 return MAKE_TCGV_I32(idx);
528 TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
532 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
533 return MAKE_TCGV_I64(idx);
536 static inline void tcg_temp_free_internal(int idx)
538 TCGContext *s = &tcg_ctx;
542 #if defined(CONFIG_DEBUG_TCG)
544 if (s->temps_in_use < 0) {
545 fprintf(stderr, "More temporaries freed than allocated!\n");
549 assert(idx >= s->nb_globals && idx < s->nb_temps);
551 assert(ts->temp_allocated != 0);
552 ts->temp_allocated = 0;
556 ts->next_free_temp = s->first_free_temp[k];
557 s->first_free_temp[k] = idx;
560 void tcg_temp_free_i32(TCGv_i32 arg)
562 tcg_temp_free_internal(GET_TCGV_I32(arg));
565 void tcg_temp_free_i64(TCGv_i64 arg)
567 tcg_temp_free_internal(GET_TCGV_I64(arg));
570 TCGv_i32 tcg_const_i32(int32_t val)
573 t0 = tcg_temp_new_i32();
574 tcg_gen_movi_i32(t0, val);
578 TCGv_i64 tcg_const_i64(int64_t val)
581 t0 = tcg_temp_new_i64();
582 tcg_gen_movi_i64(t0, val);
586 TCGv_i32 tcg_const_local_i32(int32_t val)
589 t0 = tcg_temp_local_new_i32();
590 tcg_gen_movi_i32(t0, val);
594 TCGv_i64 tcg_const_local_i64(int64_t val)
597 t0 = tcg_temp_local_new_i64();
598 tcg_gen_movi_i64(t0, val);
602 #if defined(CONFIG_DEBUG_TCG)
603 void tcg_clear_temp_count(void)
605 TCGContext *s = &tcg_ctx;
609 int tcg_check_temp_count(void)
611 TCGContext *s = &tcg_ctx;
612 if (s->temps_in_use) {
613 /* Clear the count so that we don't give another
614 * warning immediately next time around.
623 void tcg_register_helper(void *func, const char *name)
625 TCGContext *s = &tcg_ctx;
627 if ((s->nb_helpers + 1) > s->allocated_helpers) {
628 n = s->allocated_helpers;
634 s->helpers = realloc(s->helpers, n * sizeof(TCGHelperInfo));
635 s->allocated_helpers = n;
637 s->helpers[s->nb_helpers].func = (tcg_target_ulong)func;
638 s->helpers[s->nb_helpers].name = name;
642 /* Note: we convert the 64 bit args to 32 bit and do some alignment
643 and endian swap. Maybe it would be better to do the alignment
644 and endian swap in tcg_reg_alloc_call(). */
645 void tcg_gen_callN(TCGContext *s, TCGv_ptr func, unsigned int flags,
646 int sizemask, TCGArg ret, int nargs, TCGArg *args)
653 #if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
654 for (i = 0; i < nargs; ++i) {
655 int is_64bit = sizemask & (1 << (i+1)*2);
656 int is_signed = sizemask & (2 << (i+1)*2);
658 TCGv_i64 temp = tcg_temp_new_i64();
659 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
661 tcg_gen_ext32s_i64(temp, orig);
663 tcg_gen_ext32u_i64(temp, orig);
665 args[i] = GET_TCGV_I64(temp);
668 #endif /* TCG_TARGET_EXTEND_ARGS */
670 *s->gen_opc_ptr++ = INDEX_op_call;
671 nparam = s->gen_opparam_ptr++;
672 if (ret != TCG_CALL_DUMMY_ARG) {
673 #if TCG_TARGET_REG_BITS < 64
675 #ifdef TCG_TARGET_WORDS_BIGENDIAN
676 *s->gen_opparam_ptr++ = ret + 1;
677 *s->gen_opparam_ptr++ = ret;
679 *s->gen_opparam_ptr++ = ret;
680 *s->gen_opparam_ptr++ = ret + 1;
686 *s->gen_opparam_ptr++ = ret;
693 for (i = 0; i < nargs; i++) {
694 #if TCG_TARGET_REG_BITS < 64
695 int is_64bit = sizemask & (1 << (i+1)*2);
697 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
698 /* some targets want aligned 64 bit args */
700 *s->gen_opparam_ptr++ = TCG_CALL_DUMMY_ARG;
704 /* If stack grows up, then we will be placing successive
705 arguments at lower addresses, which means we need to
706 reverse the order compared to how we would normally
707 treat either big or little-endian. For those arguments
708 that will wind up in registers, this still works for
709 HPPA (the only current STACK_GROWSUP target) since the
710 argument registers are *also* allocated in decreasing
711 order. If another such target is added, this logic may
712 have to get more complicated to differentiate between
713 stack arguments and register arguments. */
714 #if defined(TCG_TARGET_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
715 *s->gen_opparam_ptr++ = args[i] + 1;
716 *s->gen_opparam_ptr++ = args[i];
718 *s->gen_opparam_ptr++ = args[i];
719 *s->gen_opparam_ptr++ = args[i] + 1;
724 #endif /* TCG_TARGET_REG_BITS < 64 */
726 *s->gen_opparam_ptr++ = args[i];
729 *s->gen_opparam_ptr++ = GET_TCGV_PTR(func);
731 *s->gen_opparam_ptr++ = flags;
733 *nparam = (nb_rets << 16) | (real_args + 1);
735 /* total parameters, needed to go backward in the instruction stream */
736 *s->gen_opparam_ptr++ = 1 + nb_rets + real_args + 3;
738 #if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
739 for (i = 0; i < nargs; ++i) {
740 int is_64bit = sizemask & (1 << (i+1)*2);
742 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
743 tcg_temp_free_i64(temp);
746 #endif /* TCG_TARGET_EXTEND_ARGS */
749 #if TCG_TARGET_REG_BITS == 32
750 void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
751 int c, int right, int arith)
754 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
755 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
756 } else if (c >= 32) {
760 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
761 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
763 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
764 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
767 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
768 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
773 t0 = tcg_temp_new_i32();
774 t1 = tcg_temp_new_i32();
776 tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
778 tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
780 tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
781 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
782 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
783 tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
785 tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
786 /* Note: ret can be the same as arg1, so we use t1 */
787 tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
788 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
789 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
790 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
792 tcg_temp_free_i32(t0);
793 tcg_temp_free_i32(t1);
799 static void tcg_reg_alloc_start(TCGContext *s)
803 for(i = 0; i < s->nb_globals; i++) {
806 ts->val_type = TEMP_VAL_REG;
808 ts->val_type = TEMP_VAL_MEM;
811 for(i = s->nb_globals; i < s->nb_temps; i++) {
813 if (ts->temp_local) {
814 ts->val_type = TEMP_VAL_MEM;
816 ts->val_type = TEMP_VAL_DEAD;
818 ts->mem_allocated = 0;
821 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
822 s->reg_to_temp[i] = -1;
826 static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
831 assert(idx >= 0 && idx < s->nb_temps);
833 if (idx < s->nb_globals) {
834 pstrcpy(buf, buf_size, ts->name);
837 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
839 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
844 char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
846 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
849 char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
851 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
854 static int helper_cmp(const void *p1, const void *p2)
856 const TCGHelperInfo *th1 = p1;
857 const TCGHelperInfo *th2 = p2;
858 if (th1->func < th2->func)
860 else if (th1->func == th2->func)
866 /* find helper definition (Note: A hash table would be better) */
867 static TCGHelperInfo *tcg_find_helper(TCGContext *s, tcg_target_ulong val)
873 if (unlikely(!s->helpers_sorted)) {
874 qsort(s->helpers, s->nb_helpers, sizeof(TCGHelperInfo),
876 s->helpers_sorted = 1;
881 m_max = s->nb_helpers - 1;
882 while (m_min <= m_max) {
883 m = (m_min + m_max) >> 1;
897 static const char * const cond_name[] =
899 [TCG_COND_NEVER] = "never",
900 [TCG_COND_ALWAYS] = "always",
901 [TCG_COND_EQ] = "eq",
902 [TCG_COND_NE] = "ne",
903 [TCG_COND_LT] = "lt",
904 [TCG_COND_GE] = "ge",
905 [TCG_COND_LE] = "le",
906 [TCG_COND_GT] = "gt",
907 [TCG_COND_LTU] = "ltu",
908 [TCG_COND_GEU] = "geu",
909 [TCG_COND_LEU] = "leu",
910 [TCG_COND_GTU] = "gtu"
913 void tcg_dump_ops(TCGContext *s)
915 const uint16_t *opc_ptr;
919 int i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
924 opc_ptr = s->gen_opc_buf;
925 args = s->gen_opparam_buf;
926 while (opc_ptr < s->gen_opc_ptr) {
928 def = &tcg_op_defs[c];
929 if (c == INDEX_op_debug_insn_start) {
931 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
932 pc = ((uint64_t)args[1] << 32) | args[0];
939 qemu_log(" ---- 0x%" PRIx64, pc);
941 nb_oargs = def->nb_oargs;
942 nb_iargs = def->nb_iargs;
943 nb_cargs = def->nb_cargs;
944 } else if (c == INDEX_op_call) {
947 /* variable number of arguments */
949 nb_oargs = arg >> 16;
950 nb_iargs = arg & 0xffff;
951 nb_cargs = def->nb_cargs;
953 qemu_log(" %s ", def->name);
957 tcg_get_arg_str_idx(s, buf, sizeof(buf),
958 args[nb_oargs + nb_iargs - 1]));
960 qemu_log(",$0x%" TCG_PRIlx, args[nb_oargs + nb_iargs]);
962 qemu_log(",$%d", nb_oargs);
963 for(i = 0; i < nb_oargs; i++) {
965 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
968 for(i = 0; i < (nb_iargs - 1); i++) {
970 if (args[nb_oargs + i] == TCG_CALL_DUMMY_ARG) {
973 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
974 args[nb_oargs + i]));
977 } else if (c == INDEX_op_movi_i32 || c == INDEX_op_movi_i64) {
978 tcg_target_ulong val;
981 nb_oargs = def->nb_oargs;
982 nb_iargs = def->nb_iargs;
983 nb_cargs = def->nb_cargs;
984 qemu_log(" %s %s,$", def->name,
985 tcg_get_arg_str_idx(s, buf, sizeof(buf), args[0]));
987 th = tcg_find_helper(s, val);
989 qemu_log("%s", th->name);
991 if (c == INDEX_op_movi_i32) {
992 qemu_log("0x%x", (uint32_t)val);
994 qemu_log("0x%" PRIx64 , (uint64_t)val);
998 qemu_log(" %s ", def->name);
999 if (c == INDEX_op_nopn) {
1000 /* variable number of arguments */
1005 nb_oargs = def->nb_oargs;
1006 nb_iargs = def->nb_iargs;
1007 nb_cargs = def->nb_cargs;
1011 for(i = 0; i < nb_oargs; i++) {
1015 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1018 for(i = 0; i < nb_iargs; i++) {
1022 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1026 case INDEX_op_brcond_i32:
1027 case INDEX_op_setcond_i32:
1028 case INDEX_op_movcond_i32:
1029 case INDEX_op_brcond2_i32:
1030 case INDEX_op_setcond2_i32:
1031 case INDEX_op_brcond_i64:
1032 case INDEX_op_setcond_i64:
1033 case INDEX_op_movcond_i64:
1034 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1035 qemu_log(",%s", cond_name[args[k++]]);
1037 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1045 for(; i < nb_cargs; i++) {
1050 qemu_log("$0x%" TCG_PRIlx, arg);
1054 args += nb_iargs + nb_oargs + nb_cargs;
1058 /* we give more priority to constraints with less registers */
1059 static int get_constraint_priority(const TCGOpDef *def, int k)
1061 const TCGArgConstraint *arg_ct;
1064 arg_ct = &def->args_ct[k];
1065 if (arg_ct->ct & TCG_CT_ALIAS) {
1066 /* an alias is equivalent to a single register */
1069 if (!(arg_ct->ct & TCG_CT_REG))
1072 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1073 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1077 return TCG_TARGET_NB_REGS - n + 1;
1080 /* sort from highest priority to lowest */
1081 static void sort_constraints(TCGOpDef *def, int start, int n)
1083 int i, j, p1, p2, tmp;
1085 for(i = 0; i < n; i++)
1086 def->sorted_args[start + i] = start + i;
1089 for(i = 0; i < n - 1; i++) {
1090 for(j = i + 1; j < n; j++) {
1091 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1092 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1094 tmp = def->sorted_args[start + i];
1095 def->sorted_args[start + i] = def->sorted_args[start + j];
1096 def->sorted_args[start + j] = tmp;
1102 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1110 if (tdefs->op == (TCGOpcode)-1)
1113 assert((unsigned)op < NB_OPS);
1114 def = &tcg_op_defs[op];
1115 #if defined(CONFIG_DEBUG_TCG)
1116 /* Duplicate entry in op definitions? */
1120 nb_args = def->nb_iargs + def->nb_oargs;
1121 for(i = 0; i < nb_args; i++) {
1122 ct_str = tdefs->args_ct_str[i];
1123 /* Incomplete TCGTargetOpDef entry? */
1124 assert(ct_str != NULL);
1125 tcg_regset_clear(def->args_ct[i].u.regs);
1126 def->args_ct[i].ct = 0;
1127 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1129 oarg = ct_str[0] - '0';
1130 assert(oarg < def->nb_oargs);
1131 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1132 /* TCG_CT_ALIAS is for the output arguments. The input
1133 argument is tagged with TCG_CT_IALIAS. */
1134 def->args_ct[i] = def->args_ct[oarg];
1135 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1136 def->args_ct[oarg].alias_index = i;
1137 def->args_ct[i].ct |= TCG_CT_IALIAS;
1138 def->args_ct[i].alias_index = oarg;
1141 if (*ct_str == '\0')
1145 def->args_ct[i].ct |= TCG_CT_CONST;
1149 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1150 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1151 ct_str, i, def->name);
1159 /* TCGTargetOpDef entry with too much information? */
1160 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1162 /* sort the constraints (XXX: this is just an heuristic) */
1163 sort_constraints(def, 0, def->nb_oargs);
1164 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1170 printf("%s: sorted=", def->name);
1171 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1172 printf(" %d", def->sorted_args[i]);
1179 #if defined(CONFIG_DEBUG_TCG)
1181 for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
1182 const TCGOpDef *def = &tcg_op_defs[op];
1183 if (def->flags & TCG_OPF_NOT_PRESENT) {
1184 /* Wrong entry in op definitions? */
1186 fprintf(stderr, "Invalid op definition for %s\n", def->name);
1190 /* Missing entry in op definitions? */
1192 fprintf(stderr, "Missing op definition for %s\n", def->name);
1203 #ifdef USE_LIVENESS_ANALYSIS
1205 /* set a nop for an operation using 'nb_args' */
1206 static inline void tcg_set_nop(TCGContext *s, uint16_t *opc_ptr,
1207 TCGArg *args, int nb_args)
1210 *opc_ptr = INDEX_op_nop;
1212 *opc_ptr = INDEX_op_nopn;
1214 args[nb_args - 1] = nb_args;
1218 /* liveness analysis: end of function: all temps are dead, and globals
1219 should be in memory. */
1220 static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1223 memset(dead_temps, 1, s->nb_temps);
1224 memset(mem_temps, 1, s->nb_globals);
1225 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
1228 /* liveness analysis: end of basic block: all temps are dead, globals
1229 and local temps should be in memory. */
1230 static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1235 memset(dead_temps, 1, s->nb_temps);
1236 memset(mem_temps, 1, s->nb_globals);
1237 for(i = s->nb_globals; i < s->nb_temps; i++) {
1238 mem_temps[i] = s->temps[i].temp_local;
1242 /* Liveness analysis : update the opc_dead_args array to tell if a
1243 given input arguments is dead. Instructions updating dead
1244 temporaries are removed. */
1245 static void tcg_liveness_analysis(TCGContext *s)
1247 int i, op_index, nb_args, nb_iargs, nb_oargs, arg, nb_ops;
1248 TCGOpcode op, op_new;
1250 const TCGOpDef *def;
1251 uint8_t *dead_temps, *mem_temps;
1255 s->gen_opc_ptr++; /* skip end */
1257 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
1259 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1260 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1262 dead_temps = tcg_malloc(s->nb_temps);
1263 mem_temps = tcg_malloc(s->nb_temps);
1264 tcg_la_func_end(s, dead_temps, mem_temps);
1266 args = s->gen_opparam_ptr;
1267 op_index = nb_ops - 1;
1268 while (op_index >= 0) {
1269 op = s->gen_opc_buf[op_index];
1270 def = &tcg_op_defs[op];
1278 nb_iargs = args[0] & 0xffff;
1279 nb_oargs = args[0] >> 16;
1281 call_flags = args[nb_oargs + nb_iargs];
1283 /* pure functions can be removed if their result is not
1285 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
1286 for(i = 0; i < nb_oargs; i++) {
1288 if (!dead_temps[arg] || mem_temps[arg]) {
1289 goto do_not_remove_call;
1292 tcg_set_nop(s, s->gen_opc_buf + op_index,
1297 /* output args are dead */
1300 for(i = 0; i < nb_oargs; i++) {
1302 if (dead_temps[arg]) {
1303 dead_args |= (1 << i);
1305 if (mem_temps[arg]) {
1306 sync_args |= (1 << i);
1308 dead_temps[arg] = 1;
1312 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1313 /* globals should be synced to memory */
1314 memset(mem_temps, 1, s->nb_globals);
1316 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1317 TCG_CALL_NO_READ_GLOBALS))) {
1318 /* globals should go back to memory */
1319 memset(dead_temps, 1, s->nb_globals);
1322 /* input args are live */
1323 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
1325 if (arg != TCG_CALL_DUMMY_ARG) {
1326 if (dead_temps[arg]) {
1327 dead_args |= (1 << i);
1329 dead_temps[arg] = 0;
1332 s->op_dead_args[op_index] = dead_args;
1333 s->op_sync_args[op_index] = sync_args;
1338 case INDEX_op_debug_insn_start:
1339 args -= def->nb_args;
1345 case INDEX_op_discard:
1347 /* mark the temporary as dead */
1348 dead_temps[args[0]] = 1;
1349 mem_temps[args[0]] = 0;
1354 case INDEX_op_add2_i32:
1355 op_new = INDEX_op_add_i32;
1357 case INDEX_op_sub2_i32:
1358 op_new = INDEX_op_sub_i32;
1360 case INDEX_op_add2_i64:
1361 op_new = INDEX_op_add_i64;
1363 case INDEX_op_sub2_i64:
1364 op_new = INDEX_op_sub_i64;
1369 /* Test if the high part of the operation is dead, but not
1370 the low part. The result can be optimized to a simple
1371 add or sub. This happens often for x86_64 guest when the
1372 cpu mode is set to 32 bit. */
1373 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1374 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1377 /* Create the single operation plus nop. */
1378 s->gen_opc_buf[op_index] = op = op_new;
1381 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1382 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 3);
1383 /* Fall through and mark the single-word operation live. */
1389 case INDEX_op_mulu2_i32:
1390 case INDEX_op_muls2_i32:
1391 op_new = INDEX_op_mul_i32;
1393 case INDEX_op_mulu2_i64:
1394 case INDEX_op_muls2_i64:
1395 op_new = INDEX_op_mul_i64;
1400 /* Likewise, test for the high part of the operation dead. */
1401 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1402 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1405 s->gen_opc_buf[op_index] = op = op_new;
1408 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1409 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 1);
1410 /* Fall through and mark the single-word operation live. */
1416 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1417 args -= def->nb_args;
1418 nb_iargs = def->nb_iargs;
1419 nb_oargs = def->nb_oargs;
1421 /* Test if the operation can be removed because all
1422 its outputs are dead. We assume that nb_oargs == 0
1423 implies side effects */
1424 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
1425 for(i = 0; i < nb_oargs; i++) {
1427 if (!dead_temps[arg] || mem_temps[arg]) {
1432 tcg_set_nop(s, s->gen_opc_buf + op_index, args, def->nb_args);
1433 #ifdef CONFIG_PROFILER
1439 /* output args are dead */
1442 for(i = 0; i < nb_oargs; i++) {
1444 if (dead_temps[arg]) {
1445 dead_args |= (1 << i);
1447 if (mem_temps[arg]) {
1448 sync_args |= (1 << i);
1450 dead_temps[arg] = 1;
1454 /* if end of basic block, update */
1455 if (def->flags & TCG_OPF_BB_END) {
1456 tcg_la_bb_end(s, dead_temps, mem_temps);
1457 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1458 /* globals should be synced to memory */
1459 memset(mem_temps, 1, s->nb_globals);
1462 /* input args are live */
1463 for(i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1465 if (dead_temps[arg]) {
1466 dead_args |= (1 << i);
1468 dead_temps[arg] = 0;
1470 s->op_dead_args[op_index] = dead_args;
1471 s->op_sync_args[op_index] = sync_args;
1478 if (args != s->gen_opparam_buf) {
1483 /* dummy liveness analysis */
1484 static void tcg_liveness_analysis(TCGContext *s)
1487 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
1489 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1490 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
1491 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1492 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
1497 static void dump_regs(TCGContext *s)
1503 for(i = 0; i < s->nb_temps; i++) {
1505 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
1506 switch(ts->val_type) {
1508 printf("%s", tcg_target_reg_names[ts->reg]);
1511 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1513 case TEMP_VAL_CONST:
1514 printf("$0x%" TCG_PRIlx, ts->val);
1526 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1527 if (s->reg_to_temp[i] >= 0) {
1529 tcg_target_reg_names[i],
1530 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
1535 static void check_regs(TCGContext *s)
1541 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1542 k = s->reg_to_temp[reg];
1545 if (ts->val_type != TEMP_VAL_REG ||
1547 printf("Inconsistency for register %s:\n",
1548 tcg_target_reg_names[reg]);
1553 for(k = 0; k < s->nb_temps; k++) {
1555 if (ts->val_type == TEMP_VAL_REG &&
1557 s->reg_to_temp[ts->reg] != k) {
1558 printf("Inconsistency for temp %s:\n",
1559 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
1561 printf("reg state:\n");
1569 static void temp_allocate_frame(TCGContext *s, int temp)
1572 ts = &s->temps[temp];
1573 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1574 /* Sparc64 stack is accessed with offset of 2047 */
1575 s->current_frame_offset = (s->current_frame_offset +
1576 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1577 ~(sizeof(tcg_target_long) - 1);
1579 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1583 ts->mem_offset = s->current_frame_offset;
1584 ts->mem_reg = s->frame_reg;
1585 ts->mem_allocated = 1;
1586 s->current_frame_offset += (tcg_target_long)sizeof(tcg_target_long);
1589 /* sync register 'reg' by saving it to the corresponding temporary */
1590 static inline void tcg_reg_sync(TCGContext *s, int reg)
1595 temp = s->reg_to_temp[reg];
1596 ts = &s->temps[temp];
1597 assert(ts->val_type == TEMP_VAL_REG);
1598 if (!ts->mem_coherent && !ts->fixed_reg) {
1599 if (!ts->mem_allocated) {
1600 temp_allocate_frame(s, temp);
1602 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1604 ts->mem_coherent = 1;
1607 /* free register 'reg' by spilling the corresponding temporary if necessary */
1608 static void tcg_reg_free(TCGContext *s, int reg)
1612 temp = s->reg_to_temp[reg];
1614 tcg_reg_sync(s, reg);
1615 s->temps[temp].val_type = TEMP_VAL_MEM;
1616 s->reg_to_temp[reg] = -1;
1620 /* Allocate a register belonging to reg1 & ~reg2 */
1621 static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1626 tcg_regset_andnot(reg_ct, reg1, reg2);
1628 /* first try free registers */
1629 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
1630 reg = tcg_target_reg_alloc_order[i];
1631 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1635 /* XXX: do better spill choice */
1636 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
1637 reg = tcg_target_reg_alloc_order[i];
1638 if (tcg_regset_test_reg(reg_ct, reg)) {
1639 tcg_reg_free(s, reg);
1647 /* mark a temporary as dead. */
1648 static inline void temp_dead(TCGContext *s, int temp)
1652 ts = &s->temps[temp];
1653 if (!ts->fixed_reg) {
1654 if (ts->val_type == TEMP_VAL_REG) {
1655 s->reg_to_temp[ts->reg] = -1;
1657 if (temp < s->nb_globals || ts->temp_local) {
1658 ts->val_type = TEMP_VAL_MEM;
1660 ts->val_type = TEMP_VAL_DEAD;
1665 /* sync a temporary to memory. 'allocated_regs' is used in case a
1666 temporary registers needs to be allocated to store a constant. */
1667 static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
1671 ts = &s->temps[temp];
1672 if (!ts->fixed_reg) {
1673 switch(ts->val_type) {
1674 case TEMP_VAL_CONST:
1675 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1677 ts->val_type = TEMP_VAL_REG;
1678 s->reg_to_temp[ts->reg] = temp;
1679 ts->mem_coherent = 0;
1680 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1683 tcg_reg_sync(s, ts->reg);
1694 /* save a temporary to memory. 'allocated_regs' is used in case a
1695 temporary registers needs to be allocated to store a constant. */
1696 static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1698 #ifdef USE_LIVENESS_ANALYSIS
1699 /* The liveness analysis already ensures that globals are back
1700 in memory. Keep an assert for safety. */
1701 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1703 temp_sync(s, temp, allocated_regs);
1708 /* save globals to their canonical location and assume they can be
1709 modified be the following code. 'allocated_regs' is used in case a
1710 temporary registers needs to be allocated to store a constant. */
1711 static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
1715 for(i = 0; i < s->nb_globals; i++) {
1716 temp_save(s, i, allocated_regs);
1720 /* sync globals to their canonical location and assume they can be
1721 read by the following code. 'allocated_regs' is used in case a
1722 temporary registers needs to be allocated to store a constant. */
1723 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1727 for (i = 0; i < s->nb_globals; i++) {
1728 #ifdef USE_LIVENESS_ANALYSIS
1729 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1730 s->temps[i].mem_coherent);
1732 temp_sync(s, i, allocated_regs);
1737 /* at the end of a basic block, we assume all temporaries are dead and
1738 all globals are stored at their canonical location. */
1739 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
1744 for(i = s->nb_globals; i < s->nb_temps; i++) {
1746 if (ts->temp_local) {
1747 temp_save(s, i, allocated_regs);
1749 #ifdef USE_LIVENESS_ANALYSIS
1750 /* The liveness analysis already ensures that temps are dead.
1751 Keep an assert for safety. */
1752 assert(ts->val_type == TEMP_VAL_DEAD);
1759 save_globals(s, allocated_regs);
1762 #define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
1763 #define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
1765 static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1766 uint16_t dead_args, uint8_t sync_args)
1769 tcg_target_ulong val;
1771 ots = &s->temps[args[0]];
1774 if (ots->fixed_reg) {
1775 /* for fixed registers, we do not do any constant
1777 tcg_out_movi(s, ots->type, ots->reg, val);
1779 /* The movi is not explicitly generated here */
1780 if (ots->val_type == TEMP_VAL_REG)
1781 s->reg_to_temp[ots->reg] = -1;
1782 ots->val_type = TEMP_VAL_CONST;
1785 if (NEED_SYNC_ARG(0)) {
1786 temp_sync(s, args[0], s->reserved_regs);
1788 if (IS_DEAD_ARG(0)) {
1789 temp_dead(s, args[0]);
1793 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
1794 const TCGArg *args, uint16_t dead_args,
1797 TCGRegSet allocated_regs;
1799 const TCGArgConstraint *arg_ct, *oarg_ct;
1801 tcg_regset_set(allocated_regs, s->reserved_regs);
1802 ots = &s->temps[args[0]];
1803 ts = &s->temps[args[1]];
1804 oarg_ct = &def->args_ct[0];
1805 arg_ct = &def->args_ct[1];
1807 /* If the source value is not in a register, and we're going to be
1808 forced to have it in a register in order to perform the copy,
1809 then copy the SOURCE value into its own register first. That way
1810 we don't have to reload SOURCE the next time it is used. */
1811 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
1812 || ts->val_type == TEMP_VAL_MEM) {
1813 ts->reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1814 if (ts->val_type == TEMP_VAL_MEM) {
1815 tcg_out_ld(s, ts->type, ts->reg, ts->mem_reg, ts->mem_offset);
1816 ts->mem_coherent = 1;
1817 } else if (ts->val_type == TEMP_VAL_CONST) {
1818 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1820 s->reg_to_temp[ts->reg] = args[1];
1821 ts->val_type = TEMP_VAL_REG;
1824 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
1825 /* mov to a non-saved dead register makes no sense (even with
1826 liveness analysis disabled). */
1827 assert(NEED_SYNC_ARG(0));
1828 /* The code above should have moved the temp to a register. */
1829 assert(ts->val_type == TEMP_VAL_REG);
1830 if (!ots->mem_allocated) {
1831 temp_allocate_frame(s, args[0]);
1833 tcg_out_st(s, ots->type, ts->reg, ots->mem_reg, ots->mem_offset);
1834 if (IS_DEAD_ARG(1)) {
1835 temp_dead(s, args[1]);
1837 temp_dead(s, args[0]);
1838 } else if (ts->val_type == TEMP_VAL_CONST) {
1839 /* propagate constant */
1840 if (ots->val_type == TEMP_VAL_REG) {
1841 s->reg_to_temp[ots->reg] = -1;
1843 ots->val_type = TEMP_VAL_CONST;
1846 /* The code in the first if block should have moved the
1847 temp to a register. */
1848 assert(ts->val_type == TEMP_VAL_REG);
1849 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
1850 /* the mov can be suppressed */
1851 if (ots->val_type == TEMP_VAL_REG) {
1852 s->reg_to_temp[ots->reg] = -1;
1855 temp_dead(s, args[1]);
1857 if (ots->val_type != TEMP_VAL_REG) {
1858 /* When allocating a new register, make sure to not spill the
1860 tcg_regset_set_reg(allocated_regs, ts->reg);
1861 ots->reg = tcg_reg_alloc(s, oarg_ct->u.regs, allocated_regs);
1863 tcg_out_mov(s, ots->type, ots->reg, ts->reg);
1865 ots->val_type = TEMP_VAL_REG;
1866 ots->mem_coherent = 0;
1867 s->reg_to_temp[ots->reg] = args[0];
1868 if (NEED_SYNC_ARG(0)) {
1869 tcg_reg_sync(s, ots->reg);
1874 static void tcg_reg_alloc_op(TCGContext *s,
1875 const TCGOpDef *def, TCGOpcode opc,
1876 const TCGArg *args, uint16_t dead_args,
1879 TCGRegSet allocated_regs;
1880 int i, k, nb_iargs, nb_oargs, reg;
1882 const TCGArgConstraint *arg_ct;
1884 TCGArg new_args[TCG_MAX_OP_ARGS];
1885 int const_args[TCG_MAX_OP_ARGS];
1887 nb_oargs = def->nb_oargs;
1888 nb_iargs = def->nb_iargs;
1890 /* copy constants */
1891 memcpy(new_args + nb_oargs + nb_iargs,
1892 args + nb_oargs + nb_iargs,
1893 sizeof(TCGArg) * def->nb_cargs);
1895 /* satisfy input constraints */
1896 tcg_regset_set(allocated_regs, s->reserved_regs);
1897 for(k = 0; k < nb_iargs; k++) {
1898 i = def->sorted_args[nb_oargs + k];
1900 arg_ct = &def->args_ct[i];
1901 ts = &s->temps[arg];
1902 if (ts->val_type == TEMP_VAL_MEM) {
1903 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1904 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1905 ts->val_type = TEMP_VAL_REG;
1907 ts->mem_coherent = 1;
1908 s->reg_to_temp[reg] = arg;
1909 } else if (ts->val_type == TEMP_VAL_CONST) {
1910 if (tcg_target_const_match(ts->val, arg_ct)) {
1911 /* constant is OK for instruction */
1913 new_args[i] = ts->val;
1916 /* need to move to a register */
1917 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1918 tcg_out_movi(s, ts->type, reg, ts->val);
1919 ts->val_type = TEMP_VAL_REG;
1921 ts->mem_coherent = 0;
1922 s->reg_to_temp[reg] = arg;
1925 assert(ts->val_type == TEMP_VAL_REG);
1926 if (arg_ct->ct & TCG_CT_IALIAS) {
1927 if (ts->fixed_reg) {
1928 /* if fixed register, we must allocate a new register
1929 if the alias is not the same register */
1930 if (arg != args[arg_ct->alias_index])
1931 goto allocate_in_reg;
1933 /* if the input is aliased to an output and if it is
1934 not dead after the instruction, we must allocate
1935 a new register and move it */
1936 if (!IS_DEAD_ARG(i)) {
1937 goto allocate_in_reg;
1942 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1943 /* nothing to do : the constraint is satisfied */
1946 /* allocate a new register matching the constraint
1947 and move the temporary register into it */
1948 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1949 tcg_out_mov(s, ts->type, reg, ts->reg);
1953 tcg_regset_set_reg(allocated_regs, reg);
1957 /* mark dead temporaries and free the associated registers */
1958 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1959 if (IS_DEAD_ARG(i)) {
1960 temp_dead(s, args[i]);
1964 if (def->flags & TCG_OPF_BB_END) {
1965 tcg_reg_alloc_bb_end(s, allocated_regs);
1967 if (def->flags & TCG_OPF_CALL_CLOBBER) {
1968 /* XXX: permit generic clobber register list ? */
1969 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1970 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
1971 tcg_reg_free(s, reg);
1975 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1976 /* sync globals if the op has side effects and might trigger
1978 sync_globals(s, allocated_regs);
1981 /* satisfy the output constraints */
1982 tcg_regset_set(allocated_regs, s->reserved_regs);
1983 for(k = 0; k < nb_oargs; k++) {
1984 i = def->sorted_args[k];
1986 arg_ct = &def->args_ct[i];
1987 ts = &s->temps[arg];
1988 if (arg_ct->ct & TCG_CT_ALIAS) {
1989 reg = new_args[arg_ct->alias_index];
1991 /* if fixed register, we try to use it */
1993 if (ts->fixed_reg &&
1994 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1997 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1999 tcg_regset_set_reg(allocated_regs, reg);
2000 /* if a fixed register is used, then a move will be done afterwards */
2001 if (!ts->fixed_reg) {
2002 if (ts->val_type == TEMP_VAL_REG) {
2003 s->reg_to_temp[ts->reg] = -1;
2005 ts->val_type = TEMP_VAL_REG;
2007 /* temp value is modified, so the value kept in memory is
2008 potentially not the same */
2009 ts->mem_coherent = 0;
2010 s->reg_to_temp[reg] = arg;
2017 /* emit instruction */
2018 tcg_out_op(s, opc, new_args, const_args);
2020 /* move the outputs in the correct register if needed */
2021 for(i = 0; i < nb_oargs; i++) {
2022 ts = &s->temps[args[i]];
2024 if (ts->fixed_reg && ts->reg != reg) {
2025 tcg_out_mov(s, ts->type, ts->reg, reg);
2027 if (NEED_SYNC_ARG(i)) {
2028 tcg_reg_sync(s, reg);
2030 if (IS_DEAD_ARG(i)) {
2031 temp_dead(s, args[i]);
2036 #ifdef TCG_TARGET_STACK_GROWSUP
2037 #define STACK_DIR(x) (-(x))
2039 #define STACK_DIR(x) (x)
2042 static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
2043 TCGOpcode opc, const TCGArg *args,
2044 uint16_t dead_args, uint8_t sync_args)
2046 int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params;
2047 TCGArg arg, func_arg;
2049 tcg_target_long stack_offset, call_stack_size, func_addr;
2050 int const_func_arg, allocate_args;
2051 TCGRegSet allocated_regs;
2052 const TCGArgConstraint *arg_ct;
2056 nb_oargs = arg >> 16;
2057 nb_iargs = arg & 0xffff;
2058 nb_params = nb_iargs - 1;
2060 flags = args[nb_oargs + nb_iargs];
2062 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
2063 if (nb_regs > nb_params)
2064 nb_regs = nb_params;
2066 /* assign stack slots first */
2067 call_stack_size = (nb_params - nb_regs) * sizeof(tcg_target_long);
2068 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2069 ~(TCG_TARGET_STACK_ALIGN - 1);
2070 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2071 if (allocate_args) {
2072 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2073 preallocate call stack */
2077 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
2078 for(i = nb_regs; i < nb_params; i++) {
2079 arg = args[nb_oargs + i];
2080 #ifdef TCG_TARGET_STACK_GROWSUP
2081 stack_offset -= sizeof(tcg_target_long);
2083 if (arg != TCG_CALL_DUMMY_ARG) {
2084 ts = &s->temps[arg];
2085 if (ts->val_type == TEMP_VAL_REG) {
2086 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2087 } else if (ts->val_type == TEMP_VAL_MEM) {
2088 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2090 /* XXX: not correct if reading values from the stack */
2091 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2092 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2093 } else if (ts->val_type == TEMP_VAL_CONST) {
2094 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2096 /* XXX: sign extend may be needed on some targets */
2097 tcg_out_movi(s, ts->type, reg, ts->val);
2098 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2103 #ifndef TCG_TARGET_STACK_GROWSUP
2104 stack_offset += sizeof(tcg_target_long);
2108 /* assign input registers */
2109 tcg_regset_set(allocated_regs, s->reserved_regs);
2110 for(i = 0; i < nb_regs; i++) {
2111 arg = args[nb_oargs + i];
2112 if (arg != TCG_CALL_DUMMY_ARG) {
2113 ts = &s->temps[arg];
2114 reg = tcg_target_call_iarg_regs[i];
2115 tcg_reg_free(s, reg);
2116 if (ts->val_type == TEMP_VAL_REG) {
2117 if (ts->reg != reg) {
2118 tcg_out_mov(s, ts->type, reg, ts->reg);
2120 } else if (ts->val_type == TEMP_VAL_MEM) {
2121 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2122 } else if (ts->val_type == TEMP_VAL_CONST) {
2123 /* XXX: sign extend ? */
2124 tcg_out_movi(s, ts->type, reg, ts->val);
2128 tcg_regset_set_reg(allocated_regs, reg);
2132 /* assign function address */
2133 func_arg = args[nb_oargs + nb_iargs - 1];
2134 arg_ct = &def->args_ct[0];
2135 ts = &s->temps[func_arg];
2136 func_addr = ts->val;
2138 if (ts->val_type == TEMP_VAL_MEM) {
2139 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2140 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2142 tcg_regset_set_reg(allocated_regs, reg);
2143 } else if (ts->val_type == TEMP_VAL_REG) {
2145 if (!tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2146 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2147 tcg_out_mov(s, ts->type, reg, ts->reg);
2150 tcg_regset_set_reg(allocated_regs, reg);
2151 } else if (ts->val_type == TEMP_VAL_CONST) {
2152 if (tcg_target_const_match(func_addr, arg_ct)) {
2154 func_arg = func_addr;
2156 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2157 tcg_out_movi(s, ts->type, reg, func_addr);
2159 tcg_regset_set_reg(allocated_regs, reg);
2166 /* mark dead temporaries and free the associated registers */
2167 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
2168 if (IS_DEAD_ARG(i)) {
2169 temp_dead(s, args[i]);
2173 /* clobber call registers */
2174 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2175 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2176 tcg_reg_free(s, reg);
2180 /* Save globals if they might be written by the helper, sync them if
2181 they might be read. */
2182 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2184 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2185 sync_globals(s, allocated_regs);
2187 save_globals(s, allocated_regs);
2190 tcg_out_op(s, opc, &func_arg, &const_func_arg);
2192 /* assign output registers and emit moves if needed */
2193 for(i = 0; i < nb_oargs; i++) {
2195 ts = &s->temps[arg];
2196 reg = tcg_target_call_oarg_regs[i];
2197 assert(s->reg_to_temp[reg] == -1);
2198 if (ts->fixed_reg) {
2199 if (ts->reg != reg) {
2200 tcg_out_mov(s, ts->type, ts->reg, reg);
2203 if (ts->val_type == TEMP_VAL_REG) {
2204 s->reg_to_temp[ts->reg] = -1;
2206 ts->val_type = TEMP_VAL_REG;
2208 ts->mem_coherent = 0;
2209 s->reg_to_temp[reg] = arg;
2210 if (NEED_SYNC_ARG(i)) {
2211 tcg_reg_sync(s, reg);
2213 if (IS_DEAD_ARG(i)) {
2214 temp_dead(s, args[i]);
2219 return nb_iargs + nb_oargs + def->nb_cargs + 1;
2222 #ifdef CONFIG_PROFILER
2224 static int64_t tcg_table_op_count[NB_OPS];
2226 static void dump_op_count(void)
2230 f = fopen("/tmp/op.log", "w");
2231 for(i = INDEX_op_end; i < NB_OPS; i++) {
2232 fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, tcg_table_op_count[i]);
2239 static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
2244 const TCGOpDef *def;
2248 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
2255 #ifdef CONFIG_PROFILER
2256 s->opt_time -= profile_getclock();
2259 #ifdef USE_TCG_OPTIMIZATIONS
2260 s->gen_opparam_ptr =
2261 tcg_optimize(s, s->gen_opc_ptr, s->gen_opparam_buf, tcg_op_defs);
2264 #ifdef CONFIG_PROFILER
2265 s->opt_time += profile_getclock();
2266 s->la_time -= profile_getclock();
2269 tcg_liveness_analysis(s);
2271 #ifdef CONFIG_PROFILER
2272 s->la_time += profile_getclock();
2276 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
2277 qemu_log("OP after optimization and liveness analysis:\n");
2283 tcg_reg_alloc_start(s);
2285 s->code_buf = gen_code_buf;
2286 s->code_ptr = gen_code_buf;
2288 args = s->gen_opparam_buf;
2292 opc = s->gen_opc_buf[op_index];
2293 #ifdef CONFIG_PROFILER
2294 tcg_table_op_count[opc]++;
2296 def = &tcg_op_defs[opc];
2298 printf("%s: %d %d %d\n", def->name,
2299 def->nb_oargs, def->nb_iargs, def->nb_cargs);
2303 case INDEX_op_mov_i32:
2304 case INDEX_op_mov_i64:
2305 tcg_reg_alloc_mov(s, def, args, s->op_dead_args[op_index],
2306 s->op_sync_args[op_index]);
2308 case INDEX_op_movi_i32:
2309 case INDEX_op_movi_i64:
2310 tcg_reg_alloc_movi(s, args, s->op_dead_args[op_index],
2311 s->op_sync_args[op_index]);
2313 case INDEX_op_debug_insn_start:
2314 /* debug instruction */
2324 case INDEX_op_discard:
2325 temp_dead(s, args[0]);
2327 case INDEX_op_set_label:
2328 tcg_reg_alloc_bb_end(s, s->reserved_regs);
2329 tcg_out_label(s, args[0], s->code_ptr);
2332 args += tcg_reg_alloc_call(s, def, opc, args,
2333 s->op_dead_args[op_index],
2334 s->op_sync_args[op_index]);
2339 /* Sanity check that we've not introduced any unhandled opcodes. */
2340 if (def->flags & TCG_OPF_NOT_PRESENT) {
2343 /* Note: in order to speed up the code, it would be much
2344 faster to have specialized register allocator functions for
2345 some common argument patterns */
2346 tcg_reg_alloc_op(s, def, opc, args, s->op_dead_args[op_index],
2347 s->op_sync_args[op_index]);
2350 args += def->nb_args;
2352 if (search_pc >= 0 && search_pc < s->code_ptr - gen_code_buf) {
2361 #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
2362 /* Generate TB finalization at the end of block */
2363 tcg_out_tb_finalize(s);
2368 int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
2370 #ifdef CONFIG_PROFILER
2373 n = (s->gen_opc_ptr - s->gen_opc_buf);
2375 if (n > s->op_count_max)
2376 s->op_count_max = n;
2378 s->temp_count += s->nb_temps;
2379 if (s->nb_temps > s->temp_count_max)
2380 s->temp_count_max = s->nb_temps;
2384 tcg_gen_code_common(s, gen_code_buf, -1);
2386 /* flush instruction cache */
2387 flush_icache_range((tcg_target_ulong)gen_code_buf,
2388 (tcg_target_ulong)s->code_ptr);
2390 return s->code_ptr - gen_code_buf;
2393 /* Return the index of the micro operation such as the pc after is <
2394 offset bytes from the start of the TB. The contents of gen_code_buf must
2395 not be changed, though writing the same values is ok.
2396 Return -1 if not found. */
2397 int tcg_gen_code_search_pc(TCGContext *s, uint8_t *gen_code_buf, long offset)
2399 return tcg_gen_code_common(s, gen_code_buf, offset);
2402 #ifdef CONFIG_PROFILER
2403 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
2405 TCGContext *s = &tcg_ctx;
2408 tot = s->interm_time + s->code_time;
2409 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2411 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2413 s->tb_count1 - s->tb_count,
2414 s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2415 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2416 s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
2417 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2419 (double)s->del_op_count / s->tb_count : 0);
2420 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
2422 (double)s->temp_count / s->tb_count : 0,
2425 cpu_fprintf(f, "cycles/op %0.1f\n",
2426 s->op_count ? (double)tot / s->op_count : 0);
2427 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2428 s->code_in_len ? (double)tot / s->code_in_len : 0);
2429 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2430 s->code_out_len ? (double)tot / s->code_out_len : 0);
2433 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2434 (double)s->interm_time / tot * 100.0);
2435 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2436 (double)s->code_time / tot * 100.0);
2437 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2438 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2440 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2441 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2442 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2444 cpu_fprintf(f, " avg cycles %0.1f\n",
2445 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
2450 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
2452 cpu_fprintf(f, "[TCG profiler not compiled]\n");
2456 #ifdef ELF_HOST_MACHINE
2457 /* In order to use this feature, the backend needs to do three things:
2459 (1) Define ELF_HOST_MACHINE to indicate both what value to
2460 put into the ELF image and to indicate support for the feature.
2462 (2) Define tcg_register_jit. This should create a buffer containing
2463 the contents of a .debug_frame section that describes the post-
2464 prologue unwind info for the tcg machine.
2466 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2469 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2476 struct jit_code_entry {
2477 struct jit_code_entry *next_entry;
2478 struct jit_code_entry *prev_entry;
2479 const void *symfile_addr;
2480 uint64_t symfile_size;
2483 struct jit_descriptor {
2485 uint32_t action_flag;
2486 struct jit_code_entry *relevant_entry;
2487 struct jit_code_entry *first_entry;
2490 void __jit_debug_register_code(void) __attribute__((noinline));
2491 void __jit_debug_register_code(void)
2496 /* Must statically initialize the version, because GDB may check
2497 the version before we can set it. */
2498 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2500 /* End GDB interface. */
2502 static int find_string(const char *strtab, const char *str)
2504 const char *p = strtab + 1;
2507 if (strcmp(p, str) == 0) {
2514 static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2515 void *debug_frame, size_t debug_frame_size)
2517 struct __attribute__((packed)) DebugInfo {
2524 uintptr_t cu_low_pc;
2525 uintptr_t cu_high_pc;
2528 uintptr_t fn_low_pc;
2529 uintptr_t fn_high_pc;
2538 struct DebugInfo di;
2543 struct ElfImage *img;
2545 static const struct ElfImage img_template = {
2547 .e_ident[EI_MAG0] = ELFMAG0,
2548 .e_ident[EI_MAG1] = ELFMAG1,
2549 .e_ident[EI_MAG2] = ELFMAG2,
2550 .e_ident[EI_MAG3] = ELFMAG3,
2551 .e_ident[EI_CLASS] = ELF_CLASS,
2552 .e_ident[EI_DATA] = ELF_DATA,
2553 .e_ident[EI_VERSION] = EV_CURRENT,
2555 .e_machine = ELF_HOST_MACHINE,
2556 .e_version = EV_CURRENT,
2557 .e_phoff = offsetof(struct ElfImage, phdr),
2558 .e_shoff = offsetof(struct ElfImage, shdr),
2559 .e_ehsize = sizeof(ElfW(Shdr)),
2560 .e_phentsize = sizeof(ElfW(Phdr)),
2562 .e_shentsize = sizeof(ElfW(Shdr)),
2563 .e_shnum = ARRAY_SIZE(img->shdr),
2564 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
2565 #ifdef ELF_HOST_FLAGS
2566 .e_flags = ELF_HOST_FLAGS,
2569 .e_ident[EI_OSABI] = ELF_OSABI,
2577 [0] = { .sh_type = SHT_NULL },
2578 /* Trick: The contents of code_gen_buffer are not present in
2579 this fake ELF file; that got allocated elsewhere. Therefore
2580 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2581 will not look for contents. We can record any address. */
2583 .sh_type = SHT_NOBITS,
2584 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2586 [2] = { /* .debug_info */
2587 .sh_type = SHT_PROGBITS,
2588 .sh_offset = offsetof(struct ElfImage, di),
2589 .sh_size = sizeof(struct DebugInfo),
2591 [3] = { /* .debug_abbrev */
2592 .sh_type = SHT_PROGBITS,
2593 .sh_offset = offsetof(struct ElfImage, da),
2594 .sh_size = sizeof(img->da),
2596 [4] = { /* .debug_frame */
2597 .sh_type = SHT_PROGBITS,
2598 .sh_offset = sizeof(struct ElfImage),
2600 [5] = { /* .symtab */
2601 .sh_type = SHT_SYMTAB,
2602 .sh_offset = offsetof(struct ElfImage, sym),
2603 .sh_size = sizeof(img->sym),
2605 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2606 .sh_entsize = sizeof(ElfW(Sym)),
2608 [6] = { /* .strtab */
2609 .sh_type = SHT_STRTAB,
2610 .sh_offset = offsetof(struct ElfImage, str),
2611 .sh_size = sizeof(img->str),
2615 [1] = { /* code_gen_buffer */
2616 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2621 .len = sizeof(struct DebugInfo) - 4,
2623 .ptr_size = sizeof(void *),
2625 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2627 .fn_name = "code_gen_buffer"
2630 1, /* abbrev number (the cu) */
2631 0x11, 1, /* DW_TAG_compile_unit, has children */
2632 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2633 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2634 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2635 0, 0, /* end of abbrev */
2636 2, /* abbrev number (the fn) */
2637 0x2e, 0, /* DW_TAG_subprogram, no children */
2638 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2639 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2640 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2641 0, 0, /* end of abbrev */
2642 0 /* no more abbrev */
2644 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2645 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
2648 /* We only need a single jit entry; statically allocate it. */
2649 static struct jit_code_entry one_entry;
2651 uintptr_t buf = (uintptr_t)buf_ptr;
2652 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2654 img = g_malloc(img_size);
2655 *img = img_template;
2656 memcpy(img + 1, debug_frame, debug_frame_size);
2658 img->phdr.p_vaddr = buf;
2659 img->phdr.p_paddr = buf;
2660 img->phdr.p_memsz = buf_size;
2662 img->shdr[1].sh_name = find_string(img->str, ".text");
2663 img->shdr[1].sh_addr = buf;
2664 img->shdr[1].sh_size = buf_size;
2666 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2667 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2669 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2670 img->shdr[4].sh_size = debug_frame_size;
2672 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2673 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2675 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2676 img->sym[1].st_value = buf;
2677 img->sym[1].st_size = buf_size;
2679 img->di.cu_low_pc = buf;
2680 img->di.cu_high_pc = buf + buf_size;
2681 img->di.fn_low_pc = buf;
2682 img->di.fn_high_pc = buf + buf_size;
2685 /* Enable this block to be able to debug the ELF image file creation.
2686 One can use readelf, objdump, or other inspection utilities. */
2688 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2690 if (fwrite(img, img_size, 1, f) != img_size) {
2691 /* Avoid stupid unused return value warning for fwrite. */
2698 one_entry.symfile_addr = img;
2699 one_entry.symfile_size = img_size;
2701 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2702 __jit_debug_descriptor.relevant_entry = &one_entry;
2703 __jit_debug_descriptor.first_entry = &one_entry;
2704 __jit_debug_register_code();
2707 /* No support for the feature. Provide the entry point expected by exec.c,
2708 and implement the internal function we declared earlier. */
2710 static void tcg_register_jit_int(void *buf, size_t size,
2711 void *debug_frame, size_t debug_frame_size)
2715 void tcg_register_jit(void *buf, size_t buf_size)
2718 #endif /* ELF_HOST_MACHINE */