target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31 #include "kvm_arm.h"
  32
  33 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  34 {
  35     ARMCPU *cpu = ARM_CPU(cs);
  36
  37     cpu->env.regs[15] = value;
  38 }
  39
  40 static bool arm_cpu_has_work(CPUState *cs)
  41 {
  42     ARMCPU *cpu = ARM_CPU(cs);
  43
  44     return !cpu->powered_off
  45         && cs->interrupt_request &
  46         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  47          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  48          | CPU_INTERRUPT_EXITTB);
  49 }
  50
  51 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  52 {
  53     /* Reset a single ARMCPRegInfo register */
  54     ARMCPRegInfo *ri = value;
  55     ARMCPU *cpu = opaque;
  56
  57     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  58         return;
  59     }
  60
  61     if (ri->resetfn) {
  62         ri->resetfn(&cpu->env, ri);
  63         return;
  64     }
  65
  66     /* A zero offset is never possible as it would be regs[0]
  67      * so we use it to indicate that reset is being handled elsewhere.
  68      * This is basically only used for fields in non-core coprocessors
  69      * (like the pxa2xx ones).
  70      */
  71     if (!ri->fieldoffset) {
  72         return;
  73     }
  74
  75     if (cpreg_field_is_64bit(ri)) {
  76         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  77     } else {
  78         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  79     }
  80 }
  81
  82 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  83 {
  84     /* Purely an assertion check: we've already done reset once,
  85      * so now check that running the reset for the cpreg doesn't
  86      * change its value. This traps bugs where two different cpregs
  87      * both try to reset the same state field but to different values.
  88      */
  89     ARMCPRegInfo *ri = value;
  90     ARMCPU *cpu = opaque;
  91     uint64_t oldvalue, newvalue;
  92
  93     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
  94         return;
  95     }
  96
  97     oldvalue = read_raw_cp_reg(&cpu->env, ri);
  98     cp_reg_reset(key, value, opaque);
  99     newvalue = read_raw_cp_reg(&cpu->env, ri);
 100     assert(oldvalue == newvalue);
 101 }
 102
 103 /* CPUClass::reset() */
 104 static void arm_cpu_reset(CPUState *s)
 105 {
 106     ARMCPU *cpu = ARM_CPU(s);
 107     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 108     CPUARMState *env = &cpu->env;
 109
 110     acc->parent_reset(s);
 111
 112     memset(env, 0, offsetof(CPUARMState, features));
 113     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 114     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 115
 116     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 117     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 118     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 119     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 120
 121     cpu->powered_off = cpu->start_powered_off;
 122     s->halted = cpu->start_powered_off;
 123
 124     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 125         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 126     }
 127
 128     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 129         /* 64 bit CPUs always start in 64 bit mode */
 130         env->aarch64 = 1;
 131 #if defined(CONFIG_USER_ONLY)
 132         env->pstate = PSTATE_MODE_EL0t;
 133         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 134         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 135         /* and to the FP/Neon instructions */
 136         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 137 #else
 138         /* Reset into the highest available EL */
 139         if (arm_feature(env, ARM_FEATURE_EL3)) {
 140             env->pstate = PSTATE_MODE_EL3h;
 141         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 142             env->pstate = PSTATE_MODE_EL2h;
 143         } else {
 144             env->pstate = PSTATE_MODE_EL1h;
 145         }
 146         env->pc = cpu->rvbar;
 147 #endif
 148     } else {
 149 #if defined(CONFIG_USER_ONLY)
 150         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 151         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 152 #endif
 153     }
 154
 155 #if defined(CONFIG_USER_ONLY)
 156     env->uncached_cpsr = ARM_CPU_MODE_USR;
 157     /* For user mode we must enable access to coprocessors */
 158     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 159     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 160         env->cp15.c15_cpar = 3;
 161     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 162         env->cp15.c15_cpar = 1;
 163     }
 164 #else
 165     /* SVC mode with interrupts disabled.  */
 166     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 167     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 168     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 169      * clear at reset. Initial SP and PC are loaded from ROM.
 170      */
 171     if (IS_M(env)) {
 172         uint32_t initial_msp; /* Loaded from 0x0 */
 173         uint32_t initial_pc; /* Loaded from 0x4 */
 174         uint8_t *rom;
 175
 176         env->daif &= ~PSTATE_I;
 177         rom = rom_ptr(0);
 178         if (rom) {
 179             /* Address zero is covered by ROM which hasn't yet been
 180              * copied into physical memory.
 181              */
 182             initial_msp = ldl_p(rom);
 183             initial_pc = ldl_p(rom + 4);
 184         } else {
 185             /* Address zero not covered by a ROM blob, or the ROM blob
 186              * is in non-modifiable memory and this is a second reset after
 187              * it got copied into memory. In the latter case, rom_ptr
 188              * will return a NULL pointer and we should use ldl_phys instead.
 189              */
 190             initial_msp = ldl_phys(s->as, 0);
 191             initial_pc = ldl_phys(s->as, 4);
 192         }
 193
 194         env->regs[13] = initial_msp & 0xFFFFFFFC;
 195         env->regs[15] = initial_pc & ~1;
 196         env->thumb = initial_pc & 1;
 197     }
 198
 199     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 200      * executing as AArch32 then check if highvecs are enabled and
 201      * adjust the PC accordingly.
 202      */
 203     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 204         env->regs[15] = 0xFFFF0000;
 205     }
 206
 207     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 208 #endif
 209     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 210     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 211     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 212     set_float_detect_tininess(float_tininess_before_rounding,
 213                               &env->vfp.fp_status);
 214     set_float_detect_tininess(float_tininess_before_rounding,
 215                               &env->vfp.standard_fp_status);
 216     tlb_flush(s, 1);
 217
 218 #ifndef CONFIG_USER_ONLY
 219     if (kvm_enabled()) {
 220         kvm_arm_reset_vcpu(cpu);
 221     }
 222 #endif
 223
 224     hw_breakpoint_update_all(cpu);
 225     hw_watchpoint_update_all(cpu);
 226 }
 227
 228 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 229 {
 230     CPUClass *cc = CPU_GET_CLASS(cs);
 231     CPUARMState *env = cs->env_ptr;
 232     uint32_t cur_el = arm_current_el(env);
 233     bool secure = arm_is_secure(env);
 234     uint32_t target_el;
 235     uint32_t excp_idx;
 236     bool ret = false;
 237
 238     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 239         excp_idx = EXCP_FIQ;
 240         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 241         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 242             cs->exception_index = excp_idx;
 243             env->exception.target_el = target_el;
 244             cc->do_interrupt(cs);
 245             ret = true;
 246         }
 247     }
 248     if (interrupt_request & CPU_INTERRUPT_HARD) {
 249         excp_idx = EXCP_IRQ;
 250         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 251         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 252             cs->exception_index = excp_idx;
 253             env->exception.target_el = target_el;
 254             cc->do_interrupt(cs);
 255             ret = true;
 256         }
 257     }
 258     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 259         excp_idx = EXCP_VIRQ;
 260         target_el = 1;
 261         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 262             cs->exception_index = excp_idx;
 263             env->exception.target_el = target_el;
 264             cc->do_interrupt(cs);
 265             ret = true;
 266         }
 267     }
 268     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 269         excp_idx = EXCP_VFIQ;
 270         target_el = 1;
 271         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 272             cs->exception_index = excp_idx;
 273             env->exception.target_el = target_el;
 274             cc->do_interrupt(cs);
 275             ret = true;
 276         }
 277     }
 278
 279     return ret;
 280 }
 281
 282 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 283 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 284 {
 285     CPUClass *cc = CPU_GET_CLASS(cs);
 286     ARMCPU *cpu = ARM_CPU(cs);
 287     CPUARMState *env = &cpu->env;
 288     bool ret = false;
 289
 290
 291     if (interrupt_request & CPU_INTERRUPT_FIQ
 292         && !(env->daif & PSTATE_F)) {
 293         cs->exception_index = EXCP_FIQ;
 294         cc->do_interrupt(cs);
 295         ret = true;
 296     }
 297     /* ARMv7-M interrupt return works by loading a magic value
 298      * into the PC.  On real hardware the load causes the
 299      * return to occur.  The qemu implementation performs the
 300      * jump normally, then does the exception return when the
 301      * CPU tries to execute code at the magic address.
 302      * This will cause the magic PC value to be pushed to
 303      * the stack if an interrupt occurred at the wrong time.
 304      * We avoid this by disabling interrupts when
 305      * pc contains a magic address.
 306      */
 307     if (interrupt_request & CPU_INTERRUPT_HARD
 308         && !(env->daif & PSTATE_I)
 309         && (env->regs[15] < 0xfffffff0)) {
 310         cs->exception_index = EXCP_IRQ;
 311         cc->do_interrupt(cs);
 312         ret = true;
 313     }
 314     return ret;
 315 }
 316 #endif
 317
 318 #ifndef CONFIG_USER_ONLY
 319 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 320 {
 321     ARMCPU *cpu = opaque;
 322     CPUARMState *env = &cpu->env;
 323     CPUState *cs = CPU(cpu);
 324     static const int mask[] = {
 325         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 326         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 327         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 328         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 329     };
 330
 331     switch (irq) {
 332     case ARM_CPU_VIRQ:
 333     case ARM_CPU_VFIQ:
 334         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 335             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 336                      __func__, irq);
 337         }
 338         /* fall through */
 339     case ARM_CPU_IRQ:
 340     case ARM_CPU_FIQ:
 341         if (level) {
 342             cpu_interrupt(cs, mask[irq]);
 343         } else {
 344             cpu_reset_interrupt(cs, mask[irq]);
 345         }
 346         break;
 347     default:
 348         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 349     }
 350 }
 351
 352 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 353 {
 354 #ifdef CONFIG_KVM
 355     ARMCPU *cpu = opaque;
 356     CPUState *cs = CPU(cpu);
 357     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 358
 359     switch (irq) {
 360     case ARM_CPU_IRQ:
 361         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 362         break;
 363     case ARM_CPU_FIQ:
 364         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 365         break;
 366     default:
 367         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 368     }
 369     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 370     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 371 #endif
 372 }
 373
 374 static bool arm_cpu_is_big_endian(CPUState *cs)
 375 {
 376     ARMCPU *cpu = ARM_CPU(cs);
 377     CPUARMState *env = &cpu->env;
 378     int cur_el;
 379
 380     cpu_synchronize_state(cs);
 381
 382     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 383     if (!is_a64(env)) {
 384         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 385     }
 386
 387     cur_el = arm_current_el(env);
 388
 389     if (cur_el == 0) {
 390         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 391     }
 392
 393     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 394 }
 395
 396 #endif
 397
 398 static inline void set_feature(CPUARMState *env, int feature)
 399 {
 400     env->features |= 1ULL << feature;
 401 }
 402
 403 static inline void unset_feature(CPUARMState *env, int feature)
 404 {
 405     env->features &= ~(1ULL << feature);
 406 }
 407
 408 static int
 409 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 410 {
 411   return print_insn_arm(pc | 1, info);
 412 }
 413
 414 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 415 {
 416     ARMCPU *ac = ARM_CPU(cpu);
 417     CPUARMState *env = &ac->env;
 418
 419     if (is_a64(env)) {
 420         /* We might not be compiled with the A64 disassembler
 421          * because it needs a C++ compiler. Leave print_insn
 422          * unset in this case to use the caller default behaviour.
 423          */
 424 #if defined(CONFIG_ARM_A64_DIS)
 425         info->print_insn = print_insn_arm_a64;
 426 #endif
 427     } else if (env->thumb) {
 428         info->print_insn = print_insn_thumb1;
 429     } else {
 430         info->print_insn = print_insn_arm;
 431     }
 432     if (env->bswap_code) {
 433 #ifdef TARGET_WORDS_BIGENDIAN
 434         info->endian = BFD_ENDIAN_LITTLE;
 435 #else
 436         info->endian = BFD_ENDIAN_BIG;
 437 #endif
 438     }
 439 }
 440
 441 #define ARM_CPUS_PER_CLUSTER 8
 442
 443 static void arm_cpu_initfn(Object *obj)
 444 {
 445     CPUState *cs = CPU(obj);
 446     ARMCPU *cpu = ARM_CPU(obj);
 447     static bool inited;
 448     uint32_t Aff1, Aff0;
 449
 450     cs->env_ptr = &cpu->env;
 451     cpu_exec_init(cs, &error_abort);
 452     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 453                                          g_free, g_free);
 454
 455     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 456      * We don't support setting cluster ID ([16..23]) (known as Aff2
 457      * in later ARM ARM versions), or any of the higher affinity level fields,
 458      * so these bits always RAZ.
 459      */
 460     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 461     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 462     cpu->mp_affinity = (Aff1 << 8) | Aff0;
 463
 464 #ifndef CONFIG_USER_ONLY
 465     /* Our inbound IRQ and FIQ lines */
 466     if (kvm_enabled()) {
 467         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 468          * the same interface as non-KVM CPUs.
 469          */
 470         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 471     } else {
 472         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 473     }
 474
 475     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 476                                                 arm_gt_ptimer_cb, cpu);
 477     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 478                                                 arm_gt_vtimer_cb, cpu);
 479     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 480                                                 arm_gt_htimer_cb, cpu);
 481     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 482                                                 arm_gt_stimer_cb, cpu);
 483     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 484                        ARRAY_SIZE(cpu->gt_timer_outputs));
 485 #endif
 486
 487     /* DTB consumers generally don't in fact care what the 'compatible'
 488      * string is, so always provide some string and trust that a hypothetical
 489      * picky DTB consumer will also provide a helpful error message.
 490      */
 491     cpu->dtb_compatible = "qemu,unknown";
 492     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 493     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 494
 495     if (tcg_enabled()) {
 496         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 497         if (!inited) {
 498             inited = true;
 499             arm_translate_init();
 500         }
 501     }
 502 }
 503
 504 static Property arm_cpu_reset_cbar_property =
 505             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 506
 507 static Property arm_cpu_reset_hivecs_property =
 508             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 509
 510 static Property arm_cpu_rvbar_property =
 511             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 512
 513 static Property arm_cpu_has_el3_property =
 514             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 515
 516 static Property arm_cpu_has_mpu_property =
 517             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 518
 519 static Property arm_cpu_pmsav7_dregion_property =
 520             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 521
 522 static void arm_cpu_post_init(Object *obj)
 523 {
 524     ARMCPU *cpu = ARM_CPU(obj);
 525
 526     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 527         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 528         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 529                                  &error_abort);
 530     }
 531
 532     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 533         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 534                                  &error_abort);
 535     }
 536
 537     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 538         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 539                                  &error_abort);
 540     }
 541
 542     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 543         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 544          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 545          */
 546         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 547                                  &error_abort);
 548     }
 549
 550     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 551         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 552                                  &error_abort);
 553         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 554             qdev_property_add_static(DEVICE(obj),
 555                                      &arm_cpu_pmsav7_dregion_property,
 556                                      &error_abort);
 557         }
 558     }
 559
 560 }
 561
 562 static void arm_cpu_finalizefn(Object *obj)
 563 {
 564     ARMCPU *cpu = ARM_CPU(obj);
 565     g_hash_table_destroy(cpu->cp_regs);
 566 }
 567
 568 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 569 {
 570     CPUState *cs = CPU(dev);
 571     ARMCPU *cpu = ARM_CPU(dev);
 572     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 573     CPUARMState *env = &cpu->env;
 574
 575     /* Some features automatically imply others: */
 576     if (arm_feature(env, ARM_FEATURE_V8)) {
 577         set_feature(env, ARM_FEATURE_V7);
 578         set_feature(env, ARM_FEATURE_ARM_DIV);
 579         set_feature(env, ARM_FEATURE_LPAE);
 580     }
 581     if (arm_feature(env, ARM_FEATURE_V7)) {
 582         set_feature(env, ARM_FEATURE_VAPA);
 583         set_feature(env, ARM_FEATURE_THUMB2);
 584         set_feature(env, ARM_FEATURE_MPIDR);
 585         if (!arm_feature(env, ARM_FEATURE_M)) {
 586             set_feature(env, ARM_FEATURE_V6K);
 587         } else {
 588             set_feature(env, ARM_FEATURE_V6);
 589         }
 590     }
 591     if (arm_feature(env, ARM_FEATURE_V6K)) {
 592         set_feature(env, ARM_FEATURE_V6);
 593         set_feature(env, ARM_FEATURE_MVFR);
 594     }
 595     if (arm_feature(env, ARM_FEATURE_V6)) {
 596         set_feature(env, ARM_FEATURE_V5);
 597         if (!arm_feature(env, ARM_FEATURE_M)) {
 598             set_feature(env, ARM_FEATURE_AUXCR);
 599         }
 600     }
 601     if (arm_feature(env, ARM_FEATURE_V5)) {
 602         set_feature(env, ARM_FEATURE_V4T);
 603     }
 604     if (arm_feature(env, ARM_FEATURE_M)) {
 605         set_feature(env, ARM_FEATURE_THUMB_DIV);
 606     }
 607     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 608         set_feature(env, ARM_FEATURE_THUMB_DIV);
 609     }
 610     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 611         set_feature(env, ARM_FEATURE_VFP3);
 612         set_feature(env, ARM_FEATURE_VFP_FP16);
 613     }
 614     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 615         set_feature(env, ARM_FEATURE_VFP);
 616     }
 617     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 618         set_feature(env, ARM_FEATURE_V7MP);
 619         set_feature(env, ARM_FEATURE_PXN);
 620     }
 621     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 622         set_feature(env, ARM_FEATURE_CBAR);
 623     }
 624     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 625         !arm_feature(env, ARM_FEATURE_M)) {
 626         set_feature(env, ARM_FEATURE_THUMB_DSP);
 627     }
 628
 629     if (cpu->reset_hivecs) {
 630             cpu->reset_sctlr |= (1 << 13);
 631     }
 632
 633     if (!cpu->has_el3) {
 634         /* If the has_el3 CPU property is disabled then we need to disable the
 635          * feature.
 636          */
 637         unset_feature(env, ARM_FEATURE_EL3);
 638
 639         /* Disable the security extension feature bits in the processor feature
 640          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 641          */
 642         cpu->id_pfr1 &= ~0xf0;
 643         cpu->id_aa64pfr0 &= ~0xf000;
 644     }
 645
 646     if (!cpu->has_mpu) {
 647         unset_feature(env, ARM_FEATURE_MPU);
 648     }
 649
 650     if (arm_feature(env, ARM_FEATURE_MPU) &&
 651         arm_feature(env, ARM_FEATURE_V7)) {
 652         uint32_t nr = cpu->pmsav7_dregion;
 653
 654         if (nr > 0xff) {
 655             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
 656             return;
 657         }
 658
 659         if (nr) {
 660             env->pmsav7.drbar = g_new0(uint32_t, nr);
 661             env->pmsav7.drsr = g_new0(uint32_t, nr);
 662             env->pmsav7.dracr = g_new0(uint32_t, nr);
 663         }
 664     }
 665
 666     register_cp_regs_for_features(cpu);
 667     arm_cpu_register_gdb_regs_for_features(cpu);
 668
 669     init_cpreg_list(cpu);
 670
 671     qemu_init_vcpu(cs);
 672     cpu_reset(cs);
 673
 674     acc->parent_realize(dev, errp);
 675 }
 676
 677 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 678 {
 679     ObjectClass *oc;
 680     char *typename;
 681     char **cpuname;
 682
 683     if (!cpu_model) {
 684         return NULL;
 685     }
 686
 687     cpuname = g_strsplit(cpu_model, ",", 1);
 688     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 689     oc = object_class_by_name(typename);
 690     g_strfreev(cpuname);
 691     g_free(typename);
 692     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 693         object_class_is_abstract(oc)) {
 694         return NULL;
 695     }
 696     return oc;
 697 }
 698
 699 /* CPU models. These are not needed for the AArch64 linux-user build. */
 700 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 701
 702 static void arm926_initfn(Object *obj)
 703 {
 704     ARMCPU *cpu = ARM_CPU(obj);
 705
 706     cpu->dtb_compatible = "arm,arm926";
 707     set_feature(&cpu->env, ARM_FEATURE_V5);
 708     set_feature(&cpu->env, ARM_FEATURE_VFP);
 709     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 710     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 711     cpu->midr = 0x41069265;
 712     cpu->reset_fpsid = 0x41011090;
 713     cpu->ctr = 0x1dd20d2;
 714     cpu->reset_sctlr = 0x00090078;
 715 }
 716
 717 static void arm946_initfn(Object *obj)
 718 {
 719     ARMCPU *cpu = ARM_CPU(obj);
 720
 721     cpu->dtb_compatible = "arm,arm946";
 722     set_feature(&cpu->env, ARM_FEATURE_V5);
 723     set_feature(&cpu->env, ARM_FEATURE_MPU);
 724     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 725     cpu->midr = 0x41059461;
 726     cpu->ctr = 0x0f004006;
 727     cpu->reset_sctlr = 0x00000078;
 728 }
 729
 730 static void arm1026_initfn(Object *obj)
 731 {
 732     ARMCPU *cpu = ARM_CPU(obj);
 733
 734     cpu->dtb_compatible = "arm,arm1026";
 735     set_feature(&cpu->env, ARM_FEATURE_V5);
 736     set_feature(&cpu->env, ARM_FEATURE_VFP);
 737     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 738     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 739     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 740     cpu->midr = 0x4106a262;
 741     cpu->reset_fpsid = 0x410110a0;
 742     cpu->ctr = 0x1dd20d2;
 743     cpu->reset_sctlr = 0x00090078;
 744     cpu->reset_auxcr = 1;
 745     {
 746         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 747         ARMCPRegInfo ifar = {
 748             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 749             .access = PL1_RW,
 750             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 751             .resetvalue = 0
 752         };
 753         define_one_arm_cp_reg(cpu, &ifar);
 754     }
 755 }
 756
 757 static void arm1136_r2_initfn(Object *obj)
 758 {
 759     ARMCPU *cpu = ARM_CPU(obj);
 760     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 761      * older core than plain "arm1136". In particular this does not
 762      * have the v6K features.
 763      * These ID register values are correct for 1136 but may be wrong
 764      * for 1136_r2 (in particular r0p2 does not actually implement most
 765      * of the ID registers).
 766      */
 767
 768     cpu->dtb_compatible = "arm,arm1136";
 769     set_feature(&cpu->env, ARM_FEATURE_V6);
 770     set_feature(&cpu->env, ARM_FEATURE_VFP);
 771     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 772     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 773     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 774     cpu->midr = 0x4107b362;
 775     cpu->reset_fpsid = 0x410120b4;
 776     cpu->mvfr0 = 0x11111111;
 777     cpu->mvfr1 = 0x00000000;
 778     cpu->ctr = 0x1dd20d2;
 779     cpu->reset_sctlr = 0x00050078;
 780     cpu->id_pfr0 = 0x111;
 781     cpu->id_pfr1 = 0x1;
 782     cpu->id_dfr0 = 0x2;
 783     cpu->id_afr0 = 0x3;
 784     cpu->id_mmfr0 = 0x01130003;
 785     cpu->id_mmfr1 = 0x10030302;
 786     cpu->id_mmfr2 = 0x01222110;
 787     cpu->id_isar0 = 0x00140011;
 788     cpu->id_isar1 = 0x12002111;
 789     cpu->id_isar2 = 0x11231111;
 790     cpu->id_isar3 = 0x01102131;
 791     cpu->id_isar4 = 0x141;
 792     cpu->reset_auxcr = 7;
 793 }
 794
 795 static void arm1136_initfn(Object *obj)
 796 {
 797     ARMCPU *cpu = ARM_CPU(obj);
 798
 799     cpu->dtb_compatible = "arm,arm1136";
 800     set_feature(&cpu->env, ARM_FEATURE_V6K);
 801     set_feature(&cpu->env, ARM_FEATURE_V6);
 802     set_feature(&cpu->env, ARM_FEATURE_VFP);
 803     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 804     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 805     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 806     cpu->midr = 0x4117b363;
 807     cpu->reset_fpsid = 0x410120b4;
 808     cpu->mvfr0 = 0x11111111;
 809     cpu->mvfr1 = 0x00000000;
 810     cpu->ctr = 0x1dd20d2;
 811     cpu->reset_sctlr = 0x00050078;
 812     cpu->id_pfr0 = 0x111;
 813     cpu->id_pfr1 = 0x1;
 814     cpu->id_dfr0 = 0x2;
 815     cpu->id_afr0 = 0x3;
 816     cpu->id_mmfr0 = 0x01130003;
 817     cpu->id_mmfr1 = 0x10030302;
 818     cpu->id_mmfr2 = 0x01222110;
 819     cpu->id_isar0 = 0x00140011;
 820     cpu->id_isar1 = 0x12002111;
 821     cpu->id_isar2 = 0x11231111;
 822     cpu->id_isar3 = 0x01102131;
 823     cpu->id_isar4 = 0x141;
 824     cpu->reset_auxcr = 7;
 825 }
 826
 827 static void arm1176_initfn(Object *obj)
 828 {
 829     ARMCPU *cpu = ARM_CPU(obj);
 830
 831     cpu->dtb_compatible = "arm,arm1176";
 832     set_feature(&cpu->env, ARM_FEATURE_V6K);
 833     set_feature(&cpu->env, ARM_FEATURE_VFP);
 834     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 835     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 836     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 837     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 838     set_feature(&cpu->env, ARM_FEATURE_EL3);
 839     cpu->midr = 0x410fb767;
 840     cpu->reset_fpsid = 0x410120b5;
 841     cpu->mvfr0 = 0x11111111;
 842     cpu->mvfr1 = 0x00000000;
 843     cpu->ctr = 0x1dd20d2;
 844     cpu->reset_sctlr = 0x00050078;
 845     cpu->id_pfr0 = 0x111;
 846     cpu->id_pfr1 = 0x11;
 847     cpu->id_dfr0 = 0x33;
 848     cpu->id_afr0 = 0;
 849     cpu->id_mmfr0 = 0x01130003;
 850     cpu->id_mmfr1 = 0x10030302;
 851     cpu->id_mmfr2 = 0x01222100;
 852     cpu->id_isar0 = 0x0140011;
 853     cpu->id_isar1 = 0x12002111;
 854     cpu->id_isar2 = 0x11231121;
 855     cpu->id_isar3 = 0x01102131;
 856     cpu->id_isar4 = 0x01141;
 857     cpu->reset_auxcr = 7;
 858 }
 859
 860 static void arm11mpcore_initfn(Object *obj)
 861 {
 862     ARMCPU *cpu = ARM_CPU(obj);
 863
 864     cpu->dtb_compatible = "arm,arm11mpcore";
 865     set_feature(&cpu->env, ARM_FEATURE_V6K);
 866     set_feature(&cpu->env, ARM_FEATURE_VFP);
 867     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 868     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 869     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 870     cpu->midr = 0x410fb022;
 871     cpu->reset_fpsid = 0x410120b4;
 872     cpu->mvfr0 = 0x11111111;
 873     cpu->mvfr1 = 0x00000000;
 874     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 875     cpu->id_pfr0 = 0x111;
 876     cpu->id_pfr1 = 0x1;
 877     cpu->id_dfr0 = 0;
 878     cpu->id_afr0 = 0x2;
 879     cpu->id_mmfr0 = 0x01100103;
 880     cpu->id_mmfr1 = 0x10020302;
 881     cpu->id_mmfr2 = 0x01222000;
 882     cpu->id_isar0 = 0x00100011;
 883     cpu->id_isar1 = 0x12002111;
 884     cpu->id_isar2 = 0x11221011;
 885     cpu->id_isar3 = 0x01102131;
 886     cpu->id_isar4 = 0x141;
 887     cpu->reset_auxcr = 1;
 888 }
 889
 890 static void cortex_m3_initfn(Object *obj)
 891 {
 892     ARMCPU *cpu = ARM_CPU(obj);
 893     set_feature(&cpu->env, ARM_FEATURE_V7);
 894     set_feature(&cpu->env, ARM_FEATURE_M);
 895     cpu->midr = 0x410fc231;
 896 }
 897
 898 static void cortex_m4_initfn(Object *obj)
 899 {
 900     ARMCPU *cpu = ARM_CPU(obj);
 901
 902     set_feature(&cpu->env, ARM_FEATURE_V7);
 903     set_feature(&cpu->env, ARM_FEATURE_M);
 904     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 905     cpu->midr = 0x410fc240; /* r0p0 */
 906 }
 907 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 908 {
 909     CPUClass *cc = CPU_CLASS(oc);
 910
 911 #ifndef CONFIG_USER_ONLY
 912     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 913 #endif
 914
 915     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 916 }
 917
 918 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 919     /* Dummy the TCM region regs for the moment */
 920     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 921       .access = PL1_RW, .type = ARM_CP_CONST },
 922     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 923       .access = PL1_RW, .type = ARM_CP_CONST },
 924     REGINFO_SENTINEL
 925 };
 926
 927 static void cortex_r5_initfn(Object *obj)
 928 {
 929     ARMCPU *cpu = ARM_CPU(obj);
 930
 931     set_feature(&cpu->env, ARM_FEATURE_V7);
 932     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 933     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 934     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 935     set_feature(&cpu->env, ARM_FEATURE_MPU);
 936     cpu->midr = 0x411fc153; /* r1p3 */
 937     cpu->id_pfr0 = 0x0131;
 938     cpu->id_pfr1 = 0x001;
 939     cpu->id_dfr0 = 0x010400;
 940     cpu->id_afr0 = 0x0;
 941     cpu->id_mmfr0 = 0x0210030;
 942     cpu->id_mmfr1 = 0x00000000;
 943     cpu->id_mmfr2 = 0x01200000;
 944     cpu->id_mmfr3 = 0x0211;
 945     cpu->id_isar0 = 0x2101111;
 946     cpu->id_isar1 = 0x13112111;
 947     cpu->id_isar2 = 0x21232141;
 948     cpu->id_isar3 = 0x01112131;
 949     cpu->id_isar4 = 0x0010142;
 950     cpu->id_isar5 = 0x0;
 951     cpu->mp_is_up = true;
 952     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 953 }
 954
 955 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 956     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 957       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 958     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 959       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 960     REGINFO_SENTINEL
 961 };
 962
 963 static void cortex_a8_initfn(Object *obj)
 964 {
 965     ARMCPU *cpu = ARM_CPU(obj);
 966
 967     cpu->dtb_compatible = "arm,cortex-a8";
 968     set_feature(&cpu->env, ARM_FEATURE_V7);
 969     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 970     set_feature(&cpu->env, ARM_FEATURE_NEON);
 971     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 972     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 973     set_feature(&cpu->env, ARM_FEATURE_EL3);
 974     cpu->midr = 0x410fc080;
 975     cpu->reset_fpsid = 0x410330c0;
 976     cpu->mvfr0 = 0x11110222;
 977     cpu->mvfr1 = 0x00011100;
 978     cpu->ctr = 0x82048004;
 979     cpu->reset_sctlr = 0x00c50078;
 980     cpu->id_pfr0 = 0x1031;
 981     cpu->id_pfr1 = 0x11;
 982     cpu->id_dfr0 = 0x400;
 983     cpu->id_afr0 = 0;
 984     cpu->id_mmfr0 = 0x31100003;
 985     cpu->id_mmfr1 = 0x20000000;
 986     cpu->id_mmfr2 = 0x01202000;
 987     cpu->id_mmfr3 = 0x11;
 988     cpu->id_isar0 = 0x00101111;
 989     cpu->id_isar1 = 0x12112111;
 990     cpu->id_isar2 = 0x21232031;
 991     cpu->id_isar3 = 0x11112131;
 992     cpu->id_isar4 = 0x00111142;
 993     cpu->dbgdidr = 0x15141000;
 994     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 995     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 996     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 997     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 998     cpu->reset_auxcr = 2;
 999     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1000 }
1001
1002 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1003     /* power_control should be set to maximum latency. Again,
1004      * default to 0 and set by private hook
1005      */
1006     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1007       .access = PL1_RW, .resetvalue = 0,
1008       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1009     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1010       .access = PL1_RW, .resetvalue = 0,
1011       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1012     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1013       .access = PL1_RW, .resetvalue = 0,
1014       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1015     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1016       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1017     /* TLB lockdown control */
1018     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1019       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1020     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1021       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1022     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1023       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1024     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1025       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1026     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1027       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1028     REGINFO_SENTINEL
1029 };
1030
1031 static void cortex_a9_initfn(Object *obj)
1032 {
1033     ARMCPU *cpu = ARM_CPU(obj);
1034
1035     cpu->dtb_compatible = "arm,cortex-a9";
1036     set_feature(&cpu->env, ARM_FEATURE_V7);
1037     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1038     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1039     set_feature(&cpu->env, ARM_FEATURE_NEON);
1040     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1041     set_feature(&cpu->env, ARM_FEATURE_EL3);
1042     /* Note that A9 supports the MP extensions even for
1043      * A9UP and single-core A9MP (which are both different
1044      * and valid configurations; we don't model A9UP).
1045      */
1046     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1047     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1048     cpu->midr = 0x410fc090;
1049     cpu->reset_fpsid = 0x41033090;
1050     cpu->mvfr0 = 0x11110222;
1051     cpu->mvfr1 = 0x01111111;
1052     cpu->ctr = 0x80038003;
1053     cpu->reset_sctlr = 0x00c50078;
1054     cpu->id_pfr0 = 0x1031;
1055     cpu->id_pfr1 = 0x11;
1056     cpu->id_dfr0 = 0x000;
1057     cpu->id_afr0 = 0;
1058     cpu->id_mmfr0 = 0x00100103;
1059     cpu->id_mmfr1 = 0x20000000;
1060     cpu->id_mmfr2 = 0x01230000;
1061     cpu->id_mmfr3 = 0x00002111;
1062     cpu->id_isar0 = 0x00101111;
1063     cpu->id_isar1 = 0x13112111;
1064     cpu->id_isar2 = 0x21232041;
1065     cpu->id_isar3 = 0x11112131;
1066     cpu->id_isar4 = 0x00111142;
1067     cpu->dbgdidr = 0x35141000;
1068     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1069     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1070     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1071     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1072 }
1073
1074 #ifndef CONFIG_USER_ONLY
1075 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1076 {
1077     /* Linux wants the number of processors from here.
1078      * Might as well set the interrupt-controller bit too.
1079      */
1080     return ((smp_cpus - 1) << 24) | (1 << 23);
1081 }
1082 #endif
1083
1084 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1085 #ifndef CONFIG_USER_ONLY
1086     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1087       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1088       .writefn = arm_cp_write_ignore, },
1089 #endif
1090     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1091       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1092     REGINFO_SENTINEL
1093 };
1094
1095 static void cortex_a15_initfn(Object *obj)
1096 {
1097     ARMCPU *cpu = ARM_CPU(obj);
1098
1099     cpu->dtb_compatible = "arm,cortex-a15";
1100     set_feature(&cpu->env, ARM_FEATURE_V7);
1101     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1102     set_feature(&cpu->env, ARM_FEATURE_NEON);
1103     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1104     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1105     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1106     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1107     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1108     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1109     set_feature(&cpu->env, ARM_FEATURE_EL3);
1110     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1111     cpu->midr = 0x412fc0f1;
1112     cpu->reset_fpsid = 0x410430f0;
1113     cpu->mvfr0 = 0x10110222;
1114     cpu->mvfr1 = 0x11111111;
1115     cpu->ctr = 0x8444c004;
1116     cpu->reset_sctlr = 0x00c50078;
1117     cpu->id_pfr0 = 0x00001131;
1118     cpu->id_pfr1 = 0x00011011;
1119     cpu->id_dfr0 = 0x02010555;
1120     cpu->id_afr0 = 0x00000000;
1121     cpu->id_mmfr0 = 0x10201105;
1122     cpu->id_mmfr1 = 0x20000000;
1123     cpu->id_mmfr2 = 0x01240000;
1124     cpu->id_mmfr3 = 0x02102211;
1125     cpu->id_isar0 = 0x02101110;
1126     cpu->id_isar1 = 0x13112111;
1127     cpu->id_isar2 = 0x21232041;
1128     cpu->id_isar3 = 0x11112131;
1129     cpu->id_isar4 = 0x10011142;
1130     cpu->dbgdidr = 0x3515f021;
1131     cpu->clidr = 0x0a200023;
1132     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1133     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1134     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1135     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1136 }
1137
1138 static void ti925t_initfn(Object *obj)
1139 {
1140     ARMCPU *cpu = ARM_CPU(obj);
1141     set_feature(&cpu->env, ARM_FEATURE_V4T);
1142     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1143     cpu->midr = ARM_CPUID_TI925T;
1144     cpu->ctr = 0x5109149;
1145     cpu->reset_sctlr = 0x00000070;
1146 }
1147
1148 static void sa1100_initfn(Object *obj)
1149 {
1150     ARMCPU *cpu = ARM_CPU(obj);
1151
1152     cpu->dtb_compatible = "intel,sa1100";
1153     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1154     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1155     cpu->midr = 0x4401A11B;
1156     cpu->reset_sctlr = 0x00000070;
1157 }
1158
1159 static void sa1110_initfn(Object *obj)
1160 {
1161     ARMCPU *cpu = ARM_CPU(obj);
1162     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1163     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1164     cpu->midr = 0x6901B119;
1165     cpu->reset_sctlr = 0x00000070;
1166 }
1167
1168 static void pxa250_initfn(Object *obj)
1169 {
1170     ARMCPU *cpu = ARM_CPU(obj);
1171
1172     cpu->dtb_compatible = "marvell,xscale";
1173     set_feature(&cpu->env, ARM_FEATURE_V5);
1174     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1175     cpu->midr = 0x69052100;
1176     cpu->ctr = 0xd172172;
1177     cpu->reset_sctlr = 0x00000078;
1178 }
1179
1180 static void pxa255_initfn(Object *obj)
1181 {
1182     ARMCPU *cpu = ARM_CPU(obj);
1183
1184     cpu->dtb_compatible = "marvell,xscale";
1185     set_feature(&cpu->env, ARM_FEATURE_V5);
1186     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1187     cpu->midr = 0x69052d00;
1188     cpu->ctr = 0xd172172;
1189     cpu->reset_sctlr = 0x00000078;
1190 }
1191
1192 static void pxa260_initfn(Object *obj)
1193 {
1194     ARMCPU *cpu = ARM_CPU(obj);
1195
1196     cpu->dtb_compatible = "marvell,xscale";
1197     set_feature(&cpu->env, ARM_FEATURE_V5);
1198     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1199     cpu->midr = 0x69052903;
1200     cpu->ctr = 0xd172172;
1201     cpu->reset_sctlr = 0x00000078;
1202 }
1203
1204 static void pxa261_initfn(Object *obj)
1205 {
1206     ARMCPU *cpu = ARM_CPU(obj);
1207
1208     cpu->dtb_compatible = "marvell,xscale";
1209     set_feature(&cpu->env, ARM_FEATURE_V5);
1210     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1211     cpu->midr = 0x69052d05;
1212     cpu->ctr = 0xd172172;
1213     cpu->reset_sctlr = 0x00000078;
1214 }
1215
1216 static void pxa262_initfn(Object *obj)
1217 {
1218     ARMCPU *cpu = ARM_CPU(obj);
1219
1220     cpu->dtb_compatible = "marvell,xscale";
1221     set_feature(&cpu->env, ARM_FEATURE_V5);
1222     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1223     cpu->midr = 0x69052d06;
1224     cpu->ctr = 0xd172172;
1225     cpu->reset_sctlr = 0x00000078;
1226 }
1227
1228 static void pxa270a0_initfn(Object *obj)
1229 {
1230     ARMCPU *cpu = ARM_CPU(obj);
1231
1232     cpu->dtb_compatible = "marvell,xscale";
1233     set_feature(&cpu->env, ARM_FEATURE_V5);
1234     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1235     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1236     cpu->midr = 0x69054110;
1237     cpu->ctr = 0xd172172;
1238     cpu->reset_sctlr = 0x00000078;
1239 }
1240
1241 static void pxa270a1_initfn(Object *obj)
1242 {
1243     ARMCPU *cpu = ARM_CPU(obj);
1244
1245     cpu->dtb_compatible = "marvell,xscale";
1246     set_feature(&cpu->env, ARM_FEATURE_V5);
1247     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1248     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1249     cpu->midr = 0x69054111;
1250     cpu->ctr = 0xd172172;
1251     cpu->reset_sctlr = 0x00000078;
1252 }
1253
1254 static void pxa270b0_initfn(Object *obj)
1255 {
1256     ARMCPU *cpu = ARM_CPU(obj);
1257
1258     cpu->dtb_compatible = "marvell,xscale";
1259     set_feature(&cpu->env, ARM_FEATURE_V5);
1260     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1261     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1262     cpu->midr = 0x69054112;
1263     cpu->ctr = 0xd172172;
1264     cpu->reset_sctlr = 0x00000078;
1265 }
1266
1267 static void pxa270b1_initfn(Object *obj)
1268 {
1269     ARMCPU *cpu = ARM_CPU(obj);
1270
1271     cpu->dtb_compatible = "marvell,xscale";
1272     set_feature(&cpu->env, ARM_FEATURE_V5);
1273     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1274     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1275     cpu->midr = 0x69054113;
1276     cpu->ctr = 0xd172172;
1277     cpu->reset_sctlr = 0x00000078;
1278 }
1279
1280 static void pxa270c0_initfn(Object *obj)
1281 {
1282     ARMCPU *cpu = ARM_CPU(obj);
1283
1284     cpu->dtb_compatible = "marvell,xscale";
1285     set_feature(&cpu->env, ARM_FEATURE_V5);
1286     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1287     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1288     cpu->midr = 0x69054114;
1289     cpu->ctr = 0xd172172;
1290     cpu->reset_sctlr = 0x00000078;
1291 }
1292
1293 static void pxa270c5_initfn(Object *obj)
1294 {
1295     ARMCPU *cpu = ARM_CPU(obj);
1296
1297     cpu->dtb_compatible = "marvell,xscale";
1298     set_feature(&cpu->env, ARM_FEATURE_V5);
1299     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1300     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1301     cpu->midr = 0x69054117;
1302     cpu->ctr = 0xd172172;
1303     cpu->reset_sctlr = 0x00000078;
1304 }
1305
1306 #ifdef CONFIG_USER_ONLY
1307 static void arm_any_initfn(Object *obj)
1308 {
1309     ARMCPU *cpu = ARM_CPU(obj);
1310     set_feature(&cpu->env, ARM_FEATURE_V8);
1311     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1312     set_feature(&cpu->env, ARM_FEATURE_NEON);
1313     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1314     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1315     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1316     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1317     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1318     set_feature(&cpu->env, ARM_FEATURE_CRC);
1319     cpu->midr = 0xffffffff;
1320 }
1321 #endif
1322
1323 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1324
1325 typedef struct ARMCPUInfo {
1326     const char *name;
1327     void (*initfn)(Object *obj);
1328     void (*class_init)(ObjectClass *oc, void *data);
1329 } ARMCPUInfo;
1330
1331 static const ARMCPUInfo arm_cpus[] = {
1332 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1333     { .name = "arm926",      .initfn = arm926_initfn },
1334     { .name = "arm946",      .initfn = arm946_initfn },
1335     { .name = "arm1026",     .initfn = arm1026_initfn },
1336     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1337      * older core than plain "arm1136". In particular this does not
1338      * have the v6K features.
1339      */
1340     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1341     { .name = "arm1136",     .initfn = arm1136_initfn },
1342     { .name = "arm1176",     .initfn = arm1176_initfn },
1343     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1344     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1345                              .class_init = arm_v7m_class_init },
1346     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1347                              .class_init = arm_v7m_class_init },
1348     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1349     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1350     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1351     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1352     { .name = "ti925t",      .initfn = ti925t_initfn },
1353     { .name = "sa1100",      .initfn = sa1100_initfn },
1354     { .name = "sa1110",      .initfn = sa1110_initfn },
1355     { .name = "pxa250",      .initfn = pxa250_initfn },
1356     { .name = "pxa255",      .initfn = pxa255_initfn },
1357     { .name = "pxa260",      .initfn = pxa260_initfn },
1358     { .name = "pxa261",      .initfn = pxa261_initfn },
1359     { .name = "pxa262",      .initfn = pxa262_initfn },
1360     /* "pxa270" is an alias for "pxa270-a0" */
1361     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1362     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1363     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1364     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1365     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1366     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1367     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1368 #ifdef CONFIG_USER_ONLY
1369     { .name = "any",         .initfn = arm_any_initfn },
1370 #endif
1371 #endif
1372     { .name = NULL }
1373 };
1374
1375 static Property arm_cpu_properties[] = {
1376     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1377     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1378     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1379     DEFINE_PROP_END_OF_LIST()
1380 };
1381
1382 #ifdef CONFIG_USER_ONLY
1383 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1384                                     int mmu_idx)
1385 {
1386     ARMCPU *cpu = ARM_CPU(cs);
1387     CPUARMState *env = &cpu->env;
1388
1389     env->exception.vaddress = address;
1390     if (rw == 2) {
1391         cs->exception_index = EXCP_PREFETCH_ABORT;
1392     } else {
1393         cs->exception_index = EXCP_DATA_ABORT;
1394     }
1395     return 1;
1396 }
1397 #endif
1398
1399 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1400 {
1401     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1402     CPUClass *cc = CPU_CLASS(acc);
1403     DeviceClass *dc = DEVICE_CLASS(oc);
1404
1405     acc->parent_realize = dc->realize;
1406     dc->realize = arm_cpu_realizefn;
1407     dc->props = arm_cpu_properties;
1408
1409     acc->parent_reset = cc->reset;
1410     cc->reset = arm_cpu_reset;
1411
1412     cc->class_by_name = arm_cpu_class_by_name;
1413     cc->has_work = arm_cpu_has_work;
1414     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1415     cc->dump_state = arm_cpu_dump_state;
1416     cc->set_pc = arm_cpu_set_pc;
1417     cc->gdb_read_register = arm_cpu_gdb_read_register;
1418     cc->gdb_write_register = arm_cpu_gdb_write_register;
1419 #ifdef CONFIG_USER_ONLY
1420     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1421 #else
1422     cc->do_interrupt = arm_cpu_do_interrupt;
1423     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1424     cc->vmsd = &vmstate_arm_cpu;
1425     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1426 #endif
1427     cc->gdb_num_core_regs = 26;
1428     cc->gdb_core_xml_file = "arm-core.xml";
1429     cc->gdb_stop_before_watchpoint = true;
1430     cc->debug_excp_handler = arm_debug_excp_handler;
1431
1432     cc->disas_set_info = arm_disas_set_info;
1433 }
1434
1435 static void cpu_register(const ARMCPUInfo *info)
1436 {
1437     TypeInfo type_info = {
1438         .parent = TYPE_ARM_CPU,
1439         .instance_size = sizeof(ARMCPU),
1440         .instance_init = info->initfn,
1441         .class_size = sizeof(ARMCPUClass),
1442         .class_init = info->class_init,
1443     };
1444
1445     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1446     type_register(&type_info);
1447     g_free((void *)type_info.name);
1448 }
1449
1450 static const TypeInfo arm_cpu_type_info = {
1451     .name = TYPE_ARM_CPU,
1452     .parent = TYPE_CPU,
1453     .instance_size = sizeof(ARMCPU),
1454     .instance_init = arm_cpu_initfn,
1455     .instance_post_init = arm_cpu_post_init,
1456     .instance_finalize = arm_cpu_finalizefn,
1457     .abstract = true,
1458     .class_size = sizeof(ARMCPUClass),
1459     .class_init = arm_cpu_class_init,
1460 };
1461
1462 static void arm_cpu_register_types(void)
1463 {
1464     const ARMCPUInfo *info = arm_cpus;
1465
1466     type_register_static(&arm_cpu_type_info);
1467
1468     while (info->name) {
1469         cpu_register(info);
1470         info++;
1471     }
1472 }
1473
1474 type_init(arm_cpu_register_types)