target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table public API */
  27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  28 {
  29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  30 }
  31
  32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  33 {
  34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  35 }
  36
  37 /* Predicates */
  38 static RISCVException fs(CPURISCVState *env, int csrno)
  39 {
  40 #if !defined(CONFIG_USER_ONLY)
  41     /* loose check condition for fcsr in vector extension */
  42     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  43         return RISCV_EXCP_NONE;
  44     }
  45     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  46         return RISCV_EXCP_ILLEGAL_INST;
  47     }
  48 #endif
  49     return RISCV_EXCP_NONE;
  50 }
  51
  52 static RISCVException vs(CPURISCVState *env, int csrno)
  53 {
  54     if (env->misa & RVV) {
  55         return RISCV_EXCP_NONE;
  56     }
  57     return RISCV_EXCP_ILLEGAL_INST;
  58 }
  59
  60 static RISCVException ctr(CPURISCVState *env, int csrno)
  61 {
  62 #if !defined(CONFIG_USER_ONLY)
  63     CPUState *cs = env_cpu(env);
  64     RISCVCPU *cpu = RISCV_CPU(cs);
  65
  66     if (!cpu->cfg.ext_counters) {
  67         /* The Counters extensions is not enabled */
  68         return RISCV_EXCP_ILLEGAL_INST;
  69     }
  70
  71     if (riscv_cpu_virt_enabled(env)) {
  72         switch (csrno) {
  73         case CSR_CYCLE:
  74             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
  75                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
  76                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  77             }
  78             break;
  79         case CSR_TIME:
  80             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
  81                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
  82                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  83             }
  84             break;
  85         case CSR_INSTRET:
  86             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
  87                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
  88                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  89             }
  90             break;
  91         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
  92             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
  93                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
  94                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  95             }
  96             break;
  97         }
  98         if (riscv_cpu_is_32bit(env)) {
  99             switch (csrno) {
 100             case CSR_CYCLEH:
 101                 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 102                     get_field(env->mcounteren, HCOUNTEREN_CY)) {
 103                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 104                 }
 105                 break;
 106             case CSR_TIMEH:
 107                 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 108                     get_field(env->mcounteren, HCOUNTEREN_TM)) {
 109                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 110                 }
 111                 break;
 112             case CSR_INSTRETH:
 113                 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 114                     get_field(env->mcounteren, HCOUNTEREN_IR)) {
 115                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 116                 }
 117                 break;
 118             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 119                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 120                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 121                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 122                 }
 123                 break;
 124             }
 125         }
 126     }
 127 #endif
 128     return RISCV_EXCP_NONE;
 129 }
 130
 131 static RISCVException ctr32(CPURISCVState *env, int csrno)
 132 {
 133     if (!riscv_cpu_is_32bit(env)) {
 134         return RISCV_EXCP_ILLEGAL_INST;
 135     }
 136
 137     return ctr(env, csrno);
 138 }
 139
 140 #if !defined(CONFIG_USER_ONLY)
 141 static RISCVException any(CPURISCVState *env, int csrno)
 142 {
 143     return RISCV_EXCP_NONE;
 144 }
 145
 146 static RISCVException any32(CPURISCVState *env, int csrno)
 147 {
 148     if (!riscv_cpu_is_32bit(env)) {
 149         return RISCV_EXCP_ILLEGAL_INST;
 150     }
 151
 152     return any(env, csrno);
 153
 154 }
 155
 156 static RISCVException smode(CPURISCVState *env, int csrno)
 157 {
 158     if (riscv_has_ext(env, RVS)) {
 159         return RISCV_EXCP_NONE;
 160     }
 161
 162     return RISCV_EXCP_ILLEGAL_INST;
 163 }
 164
 165 static RISCVException hmode(CPURISCVState *env, int csrno)
 166 {
 167     if (riscv_has_ext(env, RVS) &&
 168         riscv_has_ext(env, RVH)) {
 169         /* Hypervisor extension is supported */
 170         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 171             env->priv == PRV_M) {
 172             return RISCV_EXCP_NONE;
 173         } else {
 174             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 175         }
 176     }
 177
 178     return RISCV_EXCP_ILLEGAL_INST;
 179 }
 180
 181 static RISCVException hmode32(CPURISCVState *env, int csrno)
 182 {
 183     if (!riscv_cpu_is_32bit(env)) {
 184         if (riscv_cpu_virt_enabled(env)) {
 185             return RISCV_EXCP_ILLEGAL_INST;
 186         } else {
 187             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 188         }
 189     }
 190
 191     return hmode(env, csrno);
 192
 193 }
 194
 195 static RISCVException pmp(CPURISCVState *env, int csrno)
 196 {
 197     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
 198         return RISCV_EXCP_NONE;
 199     }
 200
 201     return RISCV_EXCP_ILLEGAL_INST;
 202 }
 203
 204 static RISCVException epmp(CPURISCVState *env, int csrno)
 205 {
 206     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
 207         return RISCV_EXCP_NONE;
 208     }
 209
 210     return RISCV_EXCP_ILLEGAL_INST;
 211 }
 212 #endif
 213
 214 /* User Floating-Point CSRs */
 215 static RISCVException read_fflags(CPURISCVState *env, int csrno,
 216                                   target_ulong *val)
 217 {
 218 #if !defined(CONFIG_USER_ONLY)
 219     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 220         return RISCV_EXCP_ILLEGAL_INST;
 221     }
 222 #endif
 223     *val = riscv_cpu_get_fflags(env);
 224     return RISCV_EXCP_NONE;
 225 }
 226
 227 static RISCVException write_fflags(CPURISCVState *env, int csrno,
 228                                    target_ulong val)
 229 {
 230 #if !defined(CONFIG_USER_ONLY)
 231     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 232         return RISCV_EXCP_ILLEGAL_INST;
 233     }
 234     env->mstatus |= MSTATUS_FS;
 235 #endif
 236     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 237     return RISCV_EXCP_NONE;
 238 }
 239
 240 static RISCVException read_frm(CPURISCVState *env, int csrno,
 241                                target_ulong *val)
 242 {
 243 #if !defined(CONFIG_USER_ONLY)
 244     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 245         return RISCV_EXCP_ILLEGAL_INST;
 246     }
 247 #endif
 248     *val = env->frm;
 249     return RISCV_EXCP_NONE;
 250 }
 251
 252 static RISCVException write_frm(CPURISCVState *env, int csrno,
 253                                 target_ulong val)
 254 {
 255 #if !defined(CONFIG_USER_ONLY)
 256     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 257         return RISCV_EXCP_ILLEGAL_INST;
 258     }
 259     env->mstatus |= MSTATUS_FS;
 260 #endif
 261     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 262     return RISCV_EXCP_NONE;
 263 }
 264
 265 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
 266                                 target_ulong *val)
 267 {
 268 #if !defined(CONFIG_USER_ONLY)
 269     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 270         return RISCV_EXCP_ILLEGAL_INST;
 271     }
 272 #endif
 273     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 274         | (env->frm << FSR_RD_SHIFT);
 275     if (vs(env, csrno) >= 0) {
 276         *val |= (env->vxrm << FSR_VXRM_SHIFT)
 277                 | (env->vxsat << FSR_VXSAT_SHIFT);
 278     }
 279     return RISCV_EXCP_NONE;
 280 }
 281
 282 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 283                                  target_ulong val)
 284 {
 285 #if !defined(CONFIG_USER_ONLY)
 286     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 287         return RISCV_EXCP_ILLEGAL_INST;
 288     }
 289     env->mstatus |= MSTATUS_FS;
 290 #endif
 291     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 292     if (vs(env, csrno) >= 0) {
 293         env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
 294         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 295     }
 296     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 297     return RISCV_EXCP_NONE;
 298 }
 299
 300 static RISCVException read_vtype(CPURISCVState *env, int csrno,
 301                                  target_ulong *val)
 302 {
 303     *val = env->vtype;
 304     return RISCV_EXCP_NONE;
 305 }
 306
 307 static RISCVException read_vl(CPURISCVState *env, int csrno,
 308                               target_ulong *val)
 309 {
 310     *val = env->vl;
 311     return RISCV_EXCP_NONE;
 312 }
 313
 314 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
 315                                 target_ulong *val)
 316 {
 317     *val = env->vxrm;
 318     return RISCV_EXCP_NONE;
 319 }
 320
 321 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
 322                                  target_ulong val)
 323 {
 324     env->vxrm = val;
 325     return RISCV_EXCP_NONE;
 326 }
 327
 328 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
 329                                  target_ulong *val)
 330 {
 331     *val = env->vxsat;
 332     return RISCV_EXCP_NONE;
 333 }
 334
 335 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
 336                                   target_ulong val)
 337 {
 338     env->vxsat = val;
 339     return RISCV_EXCP_NONE;
 340 }
 341
 342 static RISCVException read_vstart(CPURISCVState *env, int csrno,
 343                                   target_ulong *val)
 344 {
 345     *val = env->vstart;
 346     return RISCV_EXCP_NONE;
 347 }
 348
 349 static RISCVException write_vstart(CPURISCVState *env, int csrno,
 350                                    target_ulong val)
 351 {
 352     env->vstart = val;
 353     return RISCV_EXCP_NONE;
 354 }
 355
 356 /* User Timers and Counters */
 357 static RISCVException read_instret(CPURISCVState *env, int csrno,
 358                                    target_ulong *val)
 359 {
 360 #if !defined(CONFIG_USER_ONLY)
 361     if (icount_enabled()) {
 362         *val = icount_get();
 363     } else {
 364         *val = cpu_get_host_ticks();
 365     }
 366 #else
 367     *val = cpu_get_host_ticks();
 368 #endif
 369     return RISCV_EXCP_NONE;
 370 }
 371
 372 static RISCVException read_instreth(CPURISCVState *env, int csrno,
 373                                     target_ulong *val)
 374 {
 375 #if !defined(CONFIG_USER_ONLY)
 376     if (icount_enabled()) {
 377         *val = icount_get() >> 32;
 378     } else {
 379         *val = cpu_get_host_ticks() >> 32;
 380     }
 381 #else
 382     *val = cpu_get_host_ticks() >> 32;
 383 #endif
 384     return RISCV_EXCP_NONE;
 385 }
 386
 387 #if defined(CONFIG_USER_ONLY)
 388 static RISCVException read_time(CPURISCVState *env, int csrno,
 389                                 target_ulong *val)
 390 {
 391     *val = cpu_get_host_ticks();
 392     return RISCV_EXCP_NONE;
 393 }
 394
 395 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 396                                  target_ulong *val)
 397 {
 398     *val = cpu_get_host_ticks() >> 32;
 399     return RISCV_EXCP_NONE;
 400 }
 401
 402 #else /* CONFIG_USER_ONLY */
 403
 404 static RISCVException read_time(CPURISCVState *env, int csrno,
 405                                 target_ulong *val)
 406 {
 407     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 408
 409     if (!env->rdtime_fn) {
 410         return RISCV_EXCP_ILLEGAL_INST;
 411     }
 412
 413     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 414     return RISCV_EXCP_NONE;
 415 }
 416
 417 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 418                                  target_ulong *val)
 419 {
 420     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 421
 422     if (!env->rdtime_fn) {
 423         return RISCV_EXCP_ILLEGAL_INST;
 424     }
 425
 426     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 427     return RISCV_EXCP_NONE;
 428 }
 429
 430 /* Machine constants */
 431
 432 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 433 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 434 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 435
 436 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 437                                            VS_MODE_INTERRUPTS;
 438 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 439                                      VS_MODE_INTERRUPTS;
 440 static const target_ulong delegable_excps =
 441     (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
 442     (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
 443     (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
 444     (1ULL << (RISCV_EXCP_BREAKPOINT)) |
 445     (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
 446     (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
 447     (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
 448     (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
 449     (1ULL << (RISCV_EXCP_U_ECALL)) |
 450     (1ULL << (RISCV_EXCP_S_ECALL)) |
 451     (1ULL << (RISCV_EXCP_VS_ECALL)) |
 452     (1ULL << (RISCV_EXCP_M_ECALL)) |
 453     (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
 454     (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
 455     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
 456     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 457     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 458     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 459     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 460 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 461     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 462     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 463 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 464 static const target_ulong hip_writable_mask = MIP_VSSIP;
 465 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 466 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 467
 468 static const char valid_vm_1_10_32[16] = {
 469     [VM_1_10_MBARE] = 1,
 470     [VM_1_10_SV32] = 1
 471 };
 472
 473 static const char valid_vm_1_10_64[16] = {
 474     [VM_1_10_MBARE] = 1,
 475     [VM_1_10_SV39] = 1,
 476     [VM_1_10_SV48] = 1,
 477     [VM_1_10_SV57] = 1
 478 };
 479
 480 /* Machine Information Registers */
 481 static RISCVException read_zero(CPURISCVState *env, int csrno,
 482                                 target_ulong *val)
 483 {
 484     *val = 0;
 485     return RISCV_EXCP_NONE;
 486 }
 487
 488 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 489                                    target_ulong *val)
 490 {
 491     *val = env->mhartid;
 492     return RISCV_EXCP_NONE;
 493 }
 494
 495 /* Machine Trap Setup */
 496 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 497                                    target_ulong *val)
 498 {
 499     *val = env->mstatus;
 500     return RISCV_EXCP_NONE;
 501 }
 502
 503 static int validate_vm(CPURISCVState *env, target_ulong vm)
 504 {
 505     if (riscv_cpu_is_32bit(env)) {
 506         return valid_vm_1_10_32[vm & 0xf];
 507     } else {
 508         return valid_vm_1_10_64[vm & 0xf];
 509     }
 510 }
 511
 512 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 513                                     target_ulong val)
 514 {
 515     uint64_t mstatus = env->mstatus;
 516     uint64_t mask = 0;
 517     int dirty;
 518
 519     /* flush tlb on mstatus fields that affect VM */
 520     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 521             MSTATUS_MPRV | MSTATUS_SUM)) {
 522         tlb_flush(env_cpu(env));
 523     }
 524     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 525         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 526         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 527         MSTATUS_TW;
 528
 529     if (!riscv_cpu_is_32bit(env)) {
 530         /*
 531          * RV32: MPV and GVA are not in mstatus. The current plan is to
 532          * add them to mstatush. For now, we just don't support it.
 533          */
 534         mask |= MSTATUS_MPV | MSTATUS_GVA;
 535     }
 536
 537     mstatus = (mstatus & ~mask) | (val & mask);
 538
 539     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 540             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 541     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
 542     env->mstatus = mstatus;
 543
 544     return RISCV_EXCP_NONE;
 545 }
 546
 547 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
 548                                     target_ulong *val)
 549 {
 550     *val = env->mstatus >> 32;
 551     return RISCV_EXCP_NONE;
 552 }
 553
 554 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 555                                      target_ulong val)
 556 {
 557     uint64_t valh = (uint64_t)val << 32;
 558     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 559
 560     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 561         tlb_flush(env_cpu(env));
 562     }
 563
 564     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 565
 566     return RISCV_EXCP_NONE;
 567 }
 568
 569 static RISCVException read_misa(CPURISCVState *env, int csrno,
 570                                 target_ulong *val)
 571 {
 572     *val = env->misa;
 573     return RISCV_EXCP_NONE;
 574 }
 575
 576 static RISCVException write_misa(CPURISCVState *env, int csrno,
 577                                  target_ulong val)
 578 {
 579     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 580         /* drop write to misa */
 581         return RISCV_EXCP_NONE;
 582     }
 583
 584     /* 'I' or 'E' must be present */
 585     if (!(val & (RVI | RVE))) {
 586         /* It is not, drop write to misa */
 587         return RISCV_EXCP_NONE;
 588     }
 589
 590     /* 'E' excludes all other extensions */
 591     if (val & RVE) {
 592         /* when we support 'E' we can do "val = RVE;" however
 593          * for now we just drop writes if 'E' is present.
 594          */
 595         return RISCV_EXCP_NONE;
 596     }
 597
 598     /* Mask extensions that are not supported by this hart */
 599     val &= env->misa_mask;
 600
 601     /* Mask extensions that are not supported by QEMU */
 602     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 603
 604     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 605     if ((val & RVD) && !(val & RVF)) {
 606         val &= ~RVD;
 607     }
 608
 609     /* Suppress 'C' if next instruction is not aligned
 610      * TODO: this should check next_pc
 611      */
 612     if ((val & RVC) && (GETPC() & ~3) != 0) {
 613         val &= ~RVC;
 614     }
 615
 616     /* misa.MXL writes are not supported by QEMU */
 617     val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
 618
 619     /* flush translation cache */
 620     if (val != env->misa) {
 621         tb_flush(env_cpu(env));
 622     }
 623
 624     env->misa = val;
 625
 626     return RISCV_EXCP_NONE;
 627 }
 628
 629 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
 630                                    target_ulong *val)
 631 {
 632     *val = env->medeleg;
 633     return RISCV_EXCP_NONE;
 634 }
 635
 636 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
 637                                     target_ulong val)
 638 {
 639     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 640     return RISCV_EXCP_NONE;
 641 }
 642
 643 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
 644                                    target_ulong *val)
 645 {
 646     *val = env->mideleg;
 647     return RISCV_EXCP_NONE;
 648 }
 649
 650 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
 651                                     target_ulong val)
 652 {
 653     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 654     if (riscv_has_ext(env, RVH)) {
 655         env->mideleg |= VS_MODE_INTERRUPTS;
 656     }
 657     return RISCV_EXCP_NONE;
 658 }
 659
 660 static RISCVException read_mie(CPURISCVState *env, int csrno,
 661                                target_ulong *val)
 662 {
 663     *val = env->mie;
 664     return RISCV_EXCP_NONE;
 665 }
 666
 667 static RISCVException write_mie(CPURISCVState *env, int csrno,
 668                                 target_ulong val)
 669 {
 670     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 671     return RISCV_EXCP_NONE;
 672 }
 673
 674 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
 675                                  target_ulong *val)
 676 {
 677     *val = env->mtvec;
 678     return RISCV_EXCP_NONE;
 679 }
 680
 681 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 682                                   target_ulong val)
 683 {
 684     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 685     if ((val & 3) < 2) {
 686         env->mtvec = val;
 687     } else {
 688         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 689     }
 690     return RISCV_EXCP_NONE;
 691 }
 692
 693 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
 694                                       target_ulong *val)
 695 {
 696     *val = env->mcounteren;
 697     return RISCV_EXCP_NONE;
 698 }
 699
 700 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
 701                                        target_ulong val)
 702 {
 703     env->mcounteren = val;
 704     return RISCV_EXCP_NONE;
 705 }
 706
 707 /* Machine Trap Handling */
 708 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
 709                                     target_ulong *val)
 710 {
 711     *val = env->mscratch;
 712     return RISCV_EXCP_NONE;
 713 }
 714
 715 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
 716                                      target_ulong val)
 717 {
 718     env->mscratch = val;
 719     return RISCV_EXCP_NONE;
 720 }
 721
 722 static RISCVException read_mepc(CPURISCVState *env, int csrno,
 723                                      target_ulong *val)
 724 {
 725     *val = env->mepc;
 726     return RISCV_EXCP_NONE;
 727 }
 728
 729 static RISCVException write_mepc(CPURISCVState *env, int csrno,
 730                                      target_ulong val)
 731 {
 732     env->mepc = val;
 733     return RISCV_EXCP_NONE;
 734 }
 735
 736 static RISCVException read_mcause(CPURISCVState *env, int csrno,
 737                                      target_ulong *val)
 738 {
 739     *val = env->mcause;
 740     return RISCV_EXCP_NONE;
 741 }
 742
 743 static RISCVException write_mcause(CPURISCVState *env, int csrno,
 744                                      target_ulong val)
 745 {
 746     env->mcause = val;
 747     return RISCV_EXCP_NONE;
 748 }
 749
 750 static RISCVException read_mtval(CPURISCVState *env, int csrno,
 751                                  target_ulong *val)
 752 {
 753     *val = env->mtval;
 754     return RISCV_EXCP_NONE;
 755 }
 756
 757 static RISCVException write_mtval(CPURISCVState *env, int csrno,
 758                                   target_ulong val)
 759 {
 760     env->mtval = val;
 761     return RISCV_EXCP_NONE;
 762 }
 763
 764 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
 765                               target_ulong *ret_value,
 766                               target_ulong new_value, target_ulong write_mask)
 767 {
 768     RISCVCPU *cpu = env_archcpu(env);
 769     /* Allow software control of delegable interrupts not claimed by hardware */
 770     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 771     uint32_t old_mip;
 772
 773     if (mask) {
 774         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 775     } else {
 776         old_mip = env->mip;
 777     }
 778
 779     if (ret_value) {
 780         *ret_value = old_mip;
 781     }
 782
 783     return RISCV_EXCP_NONE;
 784 }
 785
 786 /* Supervisor Trap Setup */
 787 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 788                                    target_ulong *val)
 789 {
 790     target_ulong mask = (sstatus_v1_10_mask);
 791     *val = env->mstatus & mask;
 792     return RISCV_EXCP_NONE;
 793 }
 794
 795 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 796                                     target_ulong val)
 797 {
 798     target_ulong mask = (sstatus_v1_10_mask);
 799     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 800     return write_mstatus(env, CSR_MSTATUS, newval);
 801 }
 802
 803 static RISCVException read_vsie(CPURISCVState *env, int csrno,
 804                                 target_ulong *val)
 805 {
 806     /* Shift the VS bits to their S bit location in vsie */
 807     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 808     return RISCV_EXCP_NONE;
 809 }
 810
 811 static RISCVException read_sie(CPURISCVState *env, int csrno,
 812                                target_ulong *val)
 813 {
 814     if (riscv_cpu_virt_enabled(env)) {
 815         read_vsie(env, CSR_VSIE, val);
 816     } else {
 817         *val = env->mie & env->mideleg;
 818     }
 819     return RISCV_EXCP_NONE;
 820 }
 821
 822 static RISCVException write_vsie(CPURISCVState *env, int csrno,
 823                                  target_ulong val)
 824 {
 825     /* Shift the S bits to their VS bit location in mie */
 826     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 827                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 828     return write_mie(env, CSR_MIE, newval);
 829 }
 830
 831 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 832 {
 833     if (riscv_cpu_virt_enabled(env)) {
 834         write_vsie(env, CSR_VSIE, val);
 835     } else {
 836         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 837                               (val & S_MODE_INTERRUPTS);
 838         write_mie(env, CSR_MIE, newval);
 839     }
 840
 841     return RISCV_EXCP_NONE;
 842 }
 843
 844 static RISCVException read_stvec(CPURISCVState *env, int csrno,
 845                                  target_ulong *val)
 846 {
 847     *val = env->stvec;
 848     return RISCV_EXCP_NONE;
 849 }
 850
 851 static RISCVException write_stvec(CPURISCVState *env, int csrno,
 852                                   target_ulong val)
 853 {
 854     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 855     if ((val & 3) < 2) {
 856         env->stvec = val;
 857     } else {
 858         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 859     }
 860     return RISCV_EXCP_NONE;
 861 }
 862
 863 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
 864                                       target_ulong *val)
 865 {
 866     *val = env->scounteren;
 867     return RISCV_EXCP_NONE;
 868 }
 869
 870 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
 871                                        target_ulong val)
 872 {
 873     env->scounteren = val;
 874     return RISCV_EXCP_NONE;
 875 }
 876
 877 /* Supervisor Trap Handling */
 878 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
 879                                     target_ulong *val)
 880 {
 881     *val = env->sscratch;
 882     return RISCV_EXCP_NONE;
 883 }
 884
 885 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
 886                                      target_ulong val)
 887 {
 888     env->sscratch = val;
 889     return RISCV_EXCP_NONE;
 890 }
 891
 892 static RISCVException read_sepc(CPURISCVState *env, int csrno,
 893                                 target_ulong *val)
 894 {
 895     *val = env->sepc;
 896     return RISCV_EXCP_NONE;
 897 }
 898
 899 static RISCVException write_sepc(CPURISCVState *env, int csrno,
 900                                  target_ulong val)
 901 {
 902     env->sepc = val;
 903     return RISCV_EXCP_NONE;
 904 }
 905
 906 static RISCVException read_scause(CPURISCVState *env, int csrno,
 907                                   target_ulong *val)
 908 {
 909     *val = env->scause;
 910     return RISCV_EXCP_NONE;
 911 }
 912
 913 static RISCVException write_scause(CPURISCVState *env, int csrno,
 914                                    target_ulong val)
 915 {
 916     env->scause = val;
 917     return RISCV_EXCP_NONE;
 918 }
 919
 920 static RISCVException read_stval(CPURISCVState *env, int csrno,
 921                                  target_ulong *val)
 922 {
 923     *val = env->stval;
 924     return RISCV_EXCP_NONE;
 925 }
 926
 927 static RISCVException write_stval(CPURISCVState *env, int csrno,
 928                                   target_ulong val)
 929 {
 930     env->stval = val;
 931     return RISCV_EXCP_NONE;
 932 }
 933
 934 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
 935                                target_ulong *ret_value,
 936                                target_ulong new_value, target_ulong write_mask)
 937 {
 938     /* Shift the S bits to their VS bit location in mip */
 939     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
 940                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
 941     *ret_value &= VS_MODE_INTERRUPTS;
 942     /* Shift the VS bits to their S bit location in vsip */
 943     *ret_value >>= 1;
 944     return ret;
 945 }
 946
 947 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
 948                               target_ulong *ret_value,
 949                               target_ulong new_value, target_ulong write_mask)
 950 {
 951     int ret;
 952
 953     if (riscv_cpu_virt_enabled(env)) {
 954         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
 955     } else {
 956         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 957                       write_mask & env->mideleg & sip_writable_mask);
 958     }
 959
 960     *ret_value &= env->mideleg;
 961     return ret;
 962 }
 963
 964 /* Supervisor Protection and Translation */
 965 static RISCVException read_satp(CPURISCVState *env, int csrno,
 966                                 target_ulong *val)
 967 {
 968     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 969         *val = 0;
 970         return RISCV_EXCP_NONE;
 971     }
 972
 973     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 974         return RISCV_EXCP_ILLEGAL_INST;
 975     } else {
 976         *val = env->satp;
 977     }
 978
 979     return RISCV_EXCP_NONE;
 980 }
 981
 982 static RISCVException write_satp(CPURISCVState *env, int csrno,
 983                                  target_ulong val)
 984 {
 985     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 986         return RISCV_EXCP_NONE;
 987     }
 988     if (validate_vm(env, get_field(val, SATP_MODE)) &&
 989         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 990     {
 991         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 992             return RISCV_EXCP_ILLEGAL_INST;
 993         } else {
 994             if ((val ^ env->satp) & SATP_ASID) {
 995                 tlb_flush(env_cpu(env));
 996             }
 997             env->satp = val;
 998         }
 999     }
1000     return RISCV_EXCP_NONE;
1001 }
1002
1003 /* Hypervisor Extensions */
1004 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1005                                    target_ulong *val)
1006 {
1007     *val = env->hstatus;
1008     if (!riscv_cpu_is_32bit(env)) {
1009         /* We only support 64-bit VSXL */
1010         *val = set_field(*val, HSTATUS_VSXL, 2);
1011     }
1012     /* We only support little endian */
1013     *val = set_field(*val, HSTATUS_VSBE, 0);
1014     return RISCV_EXCP_NONE;
1015 }
1016
1017 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1018                                     target_ulong val)
1019 {
1020     env->hstatus = val;
1021     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
1022         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1023     }
1024     if (get_field(val, HSTATUS_VSBE) != 0) {
1025         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1026     }
1027     return RISCV_EXCP_NONE;
1028 }
1029
1030 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1031                                    target_ulong *val)
1032 {
1033     *val = env->hedeleg;
1034     return RISCV_EXCP_NONE;
1035 }
1036
1037 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1038                                     target_ulong val)
1039 {
1040     env->hedeleg = val;
1041     return RISCV_EXCP_NONE;
1042 }
1043
1044 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1045                                    target_ulong *val)
1046 {
1047     *val = env->hideleg;
1048     return RISCV_EXCP_NONE;
1049 }
1050
1051 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1052                                     target_ulong val)
1053 {
1054     env->hideleg = val;
1055     return RISCV_EXCP_NONE;
1056 }
1057
1058 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1059                                target_ulong *ret_value,
1060                                target_ulong new_value, target_ulong write_mask)
1061 {
1062     int ret = rmw_mip(env, 0, ret_value, new_value,
1063                       write_mask & hvip_writable_mask);
1064
1065     *ret_value &= hvip_writable_mask;
1066
1067     return ret;
1068 }
1069
1070 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1071                               target_ulong *ret_value,
1072                               target_ulong new_value, target_ulong write_mask)
1073 {
1074     int ret = rmw_mip(env, 0, ret_value, new_value,
1075                       write_mask & hip_writable_mask);
1076
1077     *ret_value &= hip_writable_mask;
1078
1079     return ret;
1080 }
1081
1082 static RISCVException read_hie(CPURISCVState *env, int csrno,
1083                                target_ulong *val)
1084 {
1085     *val = env->mie & VS_MODE_INTERRUPTS;
1086     return RISCV_EXCP_NONE;
1087 }
1088
1089 static RISCVException write_hie(CPURISCVState *env, int csrno,
1090                                 target_ulong val)
1091 {
1092     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1093     return write_mie(env, CSR_MIE, newval);
1094 }
1095
1096 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1097                                       target_ulong *val)
1098 {
1099     *val = env->hcounteren;
1100     return RISCV_EXCP_NONE;
1101 }
1102
1103 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1104                                        target_ulong val)
1105 {
1106     env->hcounteren = val;
1107     return RISCV_EXCP_NONE;
1108 }
1109
1110 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
1111                                  target_ulong *val)
1112 {
1113     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1114     return RISCV_EXCP_NONE;
1115 }
1116
1117 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1118                                   target_ulong val)
1119 {
1120     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1121     return RISCV_EXCP_NONE;
1122 }
1123
1124 static RISCVException read_htval(CPURISCVState *env, int csrno,
1125                                  target_ulong *val)
1126 {
1127     *val = env->htval;
1128     return RISCV_EXCP_NONE;
1129 }
1130
1131 static RISCVException write_htval(CPURISCVState *env, int csrno,
1132                                   target_ulong val)
1133 {
1134     env->htval = val;
1135     return RISCV_EXCP_NONE;
1136 }
1137
1138 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1139                                   target_ulong *val)
1140 {
1141     *val = env->htinst;
1142     return RISCV_EXCP_NONE;
1143 }
1144
1145 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1146                                    target_ulong val)
1147 {
1148     return RISCV_EXCP_NONE;
1149 }
1150
1151 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
1152                                  target_ulong *val)
1153 {
1154     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1155     return RISCV_EXCP_NONE;
1156 }
1157
1158 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1159                                   target_ulong val)
1160 {
1161     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1162     return RISCV_EXCP_NONE;
1163 }
1164
1165 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1166                                  target_ulong *val)
1167 {
1168     *val = env->hgatp;
1169     return RISCV_EXCP_NONE;
1170 }
1171
1172 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1173                                   target_ulong val)
1174 {
1175     env->hgatp = val;
1176     return RISCV_EXCP_NONE;
1177 }
1178
1179 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1180                                       target_ulong *val)
1181 {
1182     if (!env->rdtime_fn) {
1183         return RISCV_EXCP_ILLEGAL_INST;
1184     }
1185
1186     *val = env->htimedelta;
1187     return RISCV_EXCP_NONE;
1188 }
1189
1190 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1191                                        target_ulong val)
1192 {
1193     if (!env->rdtime_fn) {
1194         return RISCV_EXCP_ILLEGAL_INST;
1195     }
1196
1197     if (riscv_cpu_is_32bit(env)) {
1198         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1199     } else {
1200         env->htimedelta = val;
1201     }
1202     return RISCV_EXCP_NONE;
1203 }
1204
1205 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1206                                        target_ulong *val)
1207 {
1208     if (!env->rdtime_fn) {
1209         return RISCV_EXCP_ILLEGAL_INST;
1210     }
1211
1212     *val = env->htimedelta >> 32;
1213     return RISCV_EXCP_NONE;
1214 }
1215
1216 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1217                                         target_ulong val)
1218 {
1219     if (!env->rdtime_fn) {
1220         return RISCV_EXCP_ILLEGAL_INST;
1221     }
1222
1223     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1224     return RISCV_EXCP_NONE;
1225 }
1226
1227 /* Virtual CSR Registers */
1228 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1229                                     target_ulong *val)
1230 {
1231     *val = env->vsstatus;
1232     return RISCV_EXCP_NONE;
1233 }
1234
1235 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1236                                      target_ulong val)
1237 {
1238     uint64_t mask = (target_ulong)-1;
1239     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1240     return RISCV_EXCP_NONE;
1241 }
1242
1243 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1244 {
1245     *val = env->vstvec;
1246     return RISCV_EXCP_NONE;
1247 }
1248
1249 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1250                                    target_ulong val)
1251 {
1252     env->vstvec = val;
1253     return RISCV_EXCP_NONE;
1254 }
1255
1256 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1257                                      target_ulong *val)
1258 {
1259     *val = env->vsscratch;
1260     return RISCV_EXCP_NONE;
1261 }
1262
1263 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1264                                       target_ulong val)
1265 {
1266     env->vsscratch = val;
1267     return RISCV_EXCP_NONE;
1268 }
1269
1270 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1271                                  target_ulong *val)
1272 {
1273     *val = env->vsepc;
1274     return RISCV_EXCP_NONE;
1275 }
1276
1277 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1278                                   target_ulong val)
1279 {
1280     env->vsepc = val;
1281     return RISCV_EXCP_NONE;
1282 }
1283
1284 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1285                                    target_ulong *val)
1286 {
1287     *val = env->vscause;
1288     return RISCV_EXCP_NONE;
1289 }
1290
1291 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1292                                     target_ulong val)
1293 {
1294     env->vscause = val;
1295     return RISCV_EXCP_NONE;
1296 }
1297
1298 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1299                                   target_ulong *val)
1300 {
1301     *val = env->vstval;
1302     return RISCV_EXCP_NONE;
1303 }
1304
1305 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1306                                    target_ulong val)
1307 {
1308     env->vstval = val;
1309     return RISCV_EXCP_NONE;
1310 }
1311
1312 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1313                                  target_ulong *val)
1314 {
1315     *val = env->vsatp;
1316     return RISCV_EXCP_NONE;
1317 }
1318
1319 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1320                                   target_ulong val)
1321 {
1322     env->vsatp = val;
1323     return RISCV_EXCP_NONE;
1324 }
1325
1326 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1327                                   target_ulong *val)
1328 {
1329     *val = env->mtval2;
1330     return RISCV_EXCP_NONE;
1331 }
1332
1333 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1334                                    target_ulong val)
1335 {
1336     env->mtval2 = val;
1337     return RISCV_EXCP_NONE;
1338 }
1339
1340 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1341                                   target_ulong *val)
1342 {
1343     *val = env->mtinst;
1344     return RISCV_EXCP_NONE;
1345 }
1346
1347 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1348                                    target_ulong val)
1349 {
1350     env->mtinst = val;
1351     return RISCV_EXCP_NONE;
1352 }
1353
1354 /* Physical Memory Protection */
1355 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1356                                    target_ulong *val)
1357 {
1358     *val = mseccfg_csr_read(env);
1359     return RISCV_EXCP_NONE;
1360 }
1361
1362 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1363                          target_ulong val)
1364 {
1365     mseccfg_csr_write(env, val);
1366     return RISCV_EXCP_NONE;
1367 }
1368
1369 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1370                                   target_ulong *val)
1371 {
1372     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1373     return RISCV_EXCP_NONE;
1374 }
1375
1376 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1377                                    target_ulong val)
1378 {
1379     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1380     return RISCV_EXCP_NONE;
1381 }
1382
1383 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1384                                    target_ulong *val)
1385 {
1386     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1387     return RISCV_EXCP_NONE;
1388 }
1389
1390 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1391                                     target_ulong val)
1392 {
1393     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1394     return RISCV_EXCP_NONE;
1395 }
1396
1397 #endif
1398
1399 /*
1400  * riscv_csrrw - read and/or update control and status register
1401  *
1402  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1403  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1404  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1405  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1406  */
1407
1408 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1409                            target_ulong *ret_value,
1410                            target_ulong new_value, target_ulong write_mask)
1411 {
1412     RISCVException ret;
1413     target_ulong old_value;
1414     RISCVCPU *cpu = env_archcpu(env);
1415
1416     /* check privileges and return -1 if check fails */
1417 #if !defined(CONFIG_USER_ONLY)
1418     int effective_priv = env->priv;
1419     int read_only = get_field(csrno, 0xC00) == 3;
1420
1421     if (riscv_has_ext(env, RVH) &&
1422         env->priv == PRV_S &&
1423         !riscv_cpu_virt_enabled(env)) {
1424         /*
1425          * We are in S mode without virtualisation, therefore we are in HS Mode.
1426          * Add 1 to the effective privledge level to allow us to access the
1427          * Hypervisor CSRs.
1428          */
1429         effective_priv++;
1430     }
1431
1432     if ((write_mask && read_only) ||
1433         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1434         return RISCV_EXCP_ILLEGAL_INST;
1435     }
1436 #endif
1437
1438     /* ensure the CSR extension is enabled. */
1439     if (!cpu->cfg.ext_icsr) {
1440         return RISCV_EXCP_ILLEGAL_INST;
1441     }
1442
1443     /* check predicate */
1444     if (!csr_ops[csrno].predicate) {
1445         return RISCV_EXCP_ILLEGAL_INST;
1446     }
1447     ret = csr_ops[csrno].predicate(env, csrno);
1448     if (ret != RISCV_EXCP_NONE) {
1449         return ret;
1450     }
1451
1452     /* execute combined read/write operation if it exists */
1453     if (csr_ops[csrno].op) {
1454         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1455     }
1456
1457     /* if no accessor exists then return failure */
1458     if (!csr_ops[csrno].read) {
1459         return RISCV_EXCP_ILLEGAL_INST;
1460     }
1461     /* read old value */
1462     ret = csr_ops[csrno].read(env, csrno, &old_value);
1463     if (ret != RISCV_EXCP_NONE) {
1464         return ret;
1465     }
1466
1467     /* write value if writable and write mask set, otherwise drop writes */
1468     if (write_mask) {
1469         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1470         if (csr_ops[csrno].write) {
1471             ret = csr_ops[csrno].write(env, csrno, new_value);
1472             if (ret != RISCV_EXCP_NONE) {
1473                 return ret;
1474             }
1475         }
1476     }
1477
1478     /* return old value */
1479     if (ret_value) {
1480         *ret_value = old_value;
1481     }
1482
1483     return RISCV_EXCP_NONE;
1484 }
1485
1486 /*
1487  * Debugger support.  If not in user mode, set env->debugger before the
1488  * riscv_csrrw call and clear it after the call.
1489  */
1490 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
1491                                  target_ulong *ret_value,
1492                                  target_ulong new_value,
1493                                  target_ulong write_mask)
1494 {
1495     RISCVException ret;
1496 #if !defined(CONFIG_USER_ONLY)
1497     env->debugger = true;
1498 #endif
1499     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1500 #if !defined(CONFIG_USER_ONLY)
1501     env->debugger = false;
1502 #endif
1503     return ret;
1504 }
1505
1506 /* Control and Status Register function table */
1507 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1508     /* User Floating-Point CSRs */
1509     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1510     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1511     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1512     /* Vector CSRs */
1513     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1514     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
1515     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
1516     [CSR_VL]       = { "vl",       vs,     read_vl                    },
1517     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
1518     /* User Timers and Counters */
1519     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
1520     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
1521     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
1522     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
1523
1524     /*
1525      * In privileged mode, the monitor will have to emulate TIME CSRs only if
1526      * rdtime callback is not provided by machine/platform emulation.
1527      */
1528     [CSR_TIME]  = { "time",  ctr,   read_time  },
1529     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
1530
1531 #if !defined(CONFIG_USER_ONLY)
1532     /* Machine Timers and Counters */
1533     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
1534     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
1535     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
1536     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
1537
1538     /* Machine Information Registers */
1539     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
1540     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
1541     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
1542     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
1543
1544     /* Machine Trap Setup */
1545     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
1546     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa        },
1547     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
1548     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
1549     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
1550     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
1551     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
1552
1553     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
1554
1555     /* Machine Trap Handling */
1556     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
1557     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
1558     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
1559     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
1560     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
1561
1562     /* Supervisor Trap Setup */
1563     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus    },
1564     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
1565     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
1566     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
1567
1568     /* Supervisor Trap Handling */
1569     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
1570     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
1571     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
1572     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
1573     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
1574
1575     /* Supervisor Protection and Translation */
1576     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
1577
1578     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
1579     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
1580     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
1581     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
1582     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
1583     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
1584     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
1585     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
1586     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
1587     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
1588     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
1589     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
1590     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
1591     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
1592
1593     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
1594     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
1595     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
1596     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
1597     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
1598     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
1599     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
1600     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
1601     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
1602
1603     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
1604     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
1605
1606     /* Physical Memory Protection */
1607     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
1608     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
1609     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
1610     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
1611     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
1612     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
1613     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
1614     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
1615     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
1616     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
1617     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
1618     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
1619     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
1620     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
1621     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
1622     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
1623     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
1624     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
1625     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
1626     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
1627     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
1628
1629     /* Performance Counters */
1630     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
1631     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
1632     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
1633     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
1634     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
1635     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
1636     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
1637     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
1638     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
1639     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
1640     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
1641     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
1642     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
1643     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
1644     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
1645     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
1646     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
1647     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
1648     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
1649     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
1650     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
1651     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
1652     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
1653     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
1654     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
1655     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
1656     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
1657     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
1658     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
1659
1660     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
1661     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
1662     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
1663     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
1664     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
1665     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
1666     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
1667     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
1668     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
1669     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
1670     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
1671     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
1672     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
1673     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
1674     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
1675     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
1676     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
1677     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
1678     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
1679     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
1680     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
1681     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
1682     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
1683     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
1684     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
1685     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
1686     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
1687     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
1688     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
1689
1690     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
1691     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
1692     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
1693     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
1694     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
1695     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
1696     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
1697     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
1698     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
1699     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
1700     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
1701     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
1702     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
1703     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
1704     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
1705     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
1706     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
1707     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
1708     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
1709     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
1710     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
1711     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
1712     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
1713     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
1714     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
1715     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
1716     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
1717     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
1718     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
1719
1720     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
1721     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
1722     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
1723     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
1724     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
1725     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
1726     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
1727     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
1728     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
1729     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
1730     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
1731     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
1732     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
1733     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
1734     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
1735     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
1736     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
1737     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
1738     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
1739     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
1740     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
1741     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
1742     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
1743     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
1744     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
1745     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
1746     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
1747     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
1748     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
1749
1750     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
1751     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
1752     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
1753     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
1754     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
1755     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
1756     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
1757     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
1758     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
1759     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
1760     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
1761     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
1762     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
1763     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
1764     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
1765     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
1766     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
1767     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
1768     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
1769     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
1770     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
1771     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
1772     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
1773     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
1774     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
1775     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
1776     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
1777     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
1778     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
1779 #endif /* !CONFIG_USER_ONLY */
1780 };