hw/i2c/imx_i2c.c

   1 /*
   2  *  i.MX I2C Bus Serial Interface Emulation
   3  *
   4  *  Copyright (C) 2013 Jean-Christophe Dubois. <[email protected]>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/i2c/imx_i2c.h"
  23 #include "hw/i2c/i2c.h"
  24
  25 #ifndef DEBUG_IMX_I2C
  26 #define DEBUG_IMX_I2C 0
  27 #endif
  28
  29 #define DPRINTF(fmt, args...) \
  30     do { \
  31         if (DEBUG_IMX_I2C) { \
  32             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
  33                                              __func__, ##args); \
  34         } \
  35     } while (0)
  36
  37 static const char *imx_i2c_get_regname(unsigned offset)
  38 {
  39     switch (offset) {
  40     case IADR_ADDR:
  41         return "IADR";
  42     case IFDR_ADDR:
  43         return "IFDR";
  44     case I2CR_ADDR:
  45         return "I2CR";
  46     case I2SR_ADDR:
  47         return "I2SR";
  48     case I2DR_ADDR:
  49         return "I2DR";
  50     default:
  51         return "[?]";
  52     }
  53 }
  54
  55 static inline bool imx_i2c_is_enabled(IMXI2CState *s)
  56 {
  57     return s->i2cr & I2CR_IEN;
  58 }
  59
  60 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
  61 {
  62     return s->i2cr & I2CR_IIEN;
  63 }
  64
  65 static inline bool imx_i2c_is_master(IMXI2CState *s)
  66 {
  67     return s->i2cr & I2CR_MSTA;
  68 }
  69
  70 static void imx_i2c_reset(DeviceState *dev)
  71 {
  72     IMXI2CState *s = IMX_I2C(dev);
  73
  74     if (s->address != ADDR_RESET) {
  75         i2c_end_transfer(s->bus);
  76     }
  77
  78     s->address    = ADDR_RESET;
  79     s->iadr       = IADR_RESET;
  80     s->ifdr       = IFDR_RESET;
  81     s->i2cr       = I2CR_RESET;
  82     s->i2sr       = I2SR_RESET;
  83     s->i2dr_read  = I2DR_RESET;
  84     s->i2dr_write = I2DR_RESET;
  85 }
  86
  87 static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
  88 {
  89     /*
  90      * raise an interrupt if the device is enabled and it is configured
  91      * to generate some interrupts.
  92      */
  93     if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
  94         s->i2sr |= I2SR_IIF;
  95         qemu_irq_raise(s->irq);
  96     }
  97 }
  98
  99 static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
 100                              unsigned size)
 101 {
 102     uint16_t value;
 103     IMXI2CState *s = IMX_I2C(opaque);
 104
 105     switch (offset) {
 106     case IADR_ADDR:
 107         value = s->iadr;
 108         break;
 109     case IFDR_ADDR:
 110         value = s->ifdr;
 111         break;
 112     case I2CR_ADDR:
 113         value = s->i2cr;
 114         break;
 115     case I2SR_ADDR:
 116         value = s->i2sr;
 117         break;
 118     case I2DR_ADDR:
 119         value = s->i2dr_read;
 120
 121         if (imx_i2c_is_master(s)) {
 122             int ret = 0xff;
 123
 124             if (s->address == ADDR_RESET) {
 125                 /* something is wrong as the address is not set */
 126                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
 127                               "without specifying the slave address\n",
 128                               TYPE_IMX_I2C, __func__);
 129             } else if (s->i2cr & I2CR_MTX) {
 130                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
 131                               "but MTX is set\n", TYPE_IMX_I2C, __func__);
 132             } else {
 133                 /* get the next byte */
 134                 ret = i2c_recv(s->bus);
 135
 136                 if (ret >= 0) {
 137                     imx_i2c_raise_interrupt(s);
 138                 } else {
 139                     qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
 140                                   "for device 0x%02x\n", TYPE_IMX_I2C,
 141                                   __func__, s->address);
 142                     ret = 0xff;
 143                 }
 144             }
 145
 146             s->i2dr_read = ret;
 147         } else {
 148             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 149                           TYPE_IMX_I2C, __func__);
 150         }
 151         break;
 152     default:
 153         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 154                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
 155         value = 0;
 156         break;
 157     }
 158
 159     DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
 160             imx_i2c_get_regname(offset), offset, value);
 161
 162     return (uint64_t)value;
 163 }
 164
 165 static void imx_i2c_write(void *opaque, hwaddr offset,
 166                           uint64_t value, unsigned size)
 167 {
 168     IMXI2CState *s = IMX_I2C(opaque);
 169
 170     DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
 171             imx_i2c_get_regname(offset), offset, (int)value);
 172
 173     value &= 0xff;
 174
 175     switch (offset) {
 176     case IADR_ADDR:
 177         s->iadr = value & IADR_MASK;
 178         /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
 179         break;
 180     case IFDR_ADDR:
 181         s->ifdr = value & IFDR_MASK;
 182         break;
 183     case I2CR_ADDR:
 184         if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
 185             /* This is a soft reset. IADR is preserved during soft resets */
 186             uint16_t iadr = s->iadr;
 187             imx_i2c_reset(DEVICE(s));
 188             s->iadr = iadr;
 189         } else { /* normal write */
 190             s->i2cr = value & I2CR_MASK;
 191
 192             if (imx_i2c_is_master(s)) {
 193                 /* set the bus to busy */
 194                 s->i2sr |= I2SR_IBB;
 195             } else { /* slave mode */
 196                 /* bus is not busy anymore */
 197                 s->i2sr &= ~I2SR_IBB;
 198
 199                 /*
 200                  * if we unset the master mode then it ends the ongoing
 201                  * transfer if any
 202                  */
 203                 if (s->address != ADDR_RESET) {
 204                     i2c_end_transfer(s->bus);
 205                     s->address = ADDR_RESET;
 206                 }
 207             }
 208
 209             if (s->i2cr & I2CR_RSTA) { /* Restart */
 210                 /* if this is a restart then it ends the ongoing transfer */
 211                 if (s->address != ADDR_RESET) {
 212                     i2c_end_transfer(s->bus);
 213                     s->address = ADDR_RESET;
 214                     s->i2cr &= ~I2CR_RSTA;
 215                 }
 216             }
 217         }
 218         break;
 219     case I2SR_ADDR:
 220         /*
 221          * if the user writes 0 to IIF then lower the interrupt and
 222          * reset the bit
 223          */
 224         if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
 225             s->i2sr &= ~I2SR_IIF;
 226             qemu_irq_lower(s->irq);
 227         }
 228
 229         /*
 230          * if the user writes 0 to IAL, reset the bit
 231          */
 232         if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
 233             s->i2sr &= ~I2SR_IAL;
 234         }
 235
 236         break;
 237     case I2DR_ADDR:
 238         /* if the device is not enabled, nothing to do */
 239         if (!imx_i2c_is_enabled(s)) {
 240             break;
 241         }
 242
 243         s->i2dr_write = value & I2DR_MASK;
 244
 245         if (imx_i2c_is_master(s)) {
 246             /* If this is the first write cycle then it is the slave addr */
 247             if (s->address == ADDR_RESET) {
 248                 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
 249                                        extract32(s->i2dr_write, 0, 1))) {
 250                     /* if non zero is returned, the adress is not valid */
 251                     s->i2sr |= I2SR_RXAK;
 252                 } else {
 253                     s->address = s->i2dr_write;
 254                     s->i2sr &= ~I2SR_RXAK;
 255                     imx_i2c_raise_interrupt(s);
 256                 }
 257             } else { /* This is a normal data write */
 258                 if (i2c_send(s->bus, s->i2dr_write)) {
 259                     /* if the target return non zero then end the transfer */
 260                     s->i2sr |= I2SR_RXAK;
 261                     s->address = ADDR_RESET;
 262                     i2c_end_transfer(s->bus);
 263                 } else {
 264                     s->i2sr &= ~I2SR_RXAK;
 265                     imx_i2c_raise_interrupt(s);
 266                 }
 267             }
 268         } else {
 269             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 270                           TYPE_IMX_I2C, __func__);
 271         }
 272         break;
 273     default:
 274         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 275                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
 276         break;
 277     }
 278 }
 279
 280 static const MemoryRegionOps imx_i2c_ops = {
 281     .read = imx_i2c_read,
 282     .write = imx_i2c_write,
 283     .valid.min_access_size = 1,
 284     .valid.max_access_size = 2,
 285     .endianness = DEVICE_NATIVE_ENDIAN,
 286 };
 287
 288 static const VMStateDescription imx_i2c_vmstate = {
 289     .name = TYPE_IMX_I2C,
 290     .version_id = 1,
 291     .minimum_version_id = 1,
 292     .fields = (VMStateField[]) {
 293         VMSTATE_UINT16(address, IMXI2CState),
 294         VMSTATE_UINT16(iadr, IMXI2CState),
 295         VMSTATE_UINT16(ifdr, IMXI2CState),
 296         VMSTATE_UINT16(i2cr, IMXI2CState),
 297         VMSTATE_UINT16(i2sr, IMXI2CState),
 298         VMSTATE_UINT16(i2dr_read, IMXI2CState),
 299         VMSTATE_UINT16(i2dr_write, IMXI2CState),
 300         VMSTATE_END_OF_LIST()
 301     }
 302 };
 303
 304 static void imx_i2c_realize(DeviceState *dev, Error **errp)
 305 {
 306     IMXI2CState *s = IMX_I2C(dev);
 307
 308     memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
 309                           IMX_I2C_MEM_SIZE);
 310     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 311     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 312     s->bus = i2c_init_bus(DEVICE(dev), "i2c");
 313 }
 314
 315 static void imx_i2c_class_init(ObjectClass *klass, void *data)
 316 {
 317     DeviceClass *dc = DEVICE_CLASS(klass);
 318
 319     dc->vmsd = &imx_i2c_vmstate;
 320     dc->reset = imx_i2c_reset;
 321     dc->realize = imx_i2c_realize;
 322     dc->desc = "i.MX I2C Controller";
 323 }
 324
 325 static const TypeInfo imx_i2c_type_info = {
 326     .name = TYPE_IMX_I2C,
 327     .parent = TYPE_SYS_BUS_DEVICE,
 328     .instance_size = sizeof(IMXI2CState),
 329     .class_init = imx_i2c_class_init,
 330 };
 331
 332 static void imx_i2c_register_types(void)
 333 {
 334     type_register_static(&imx_i2c_type_info);
 335 }
 336
 337 type_init(imx_i2c_register_types)