target-xtensa/translate.c

   1 /*
   2  * Xtensa ISA:
   3  * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
   4  *
   5  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in the
  14  *       documentation and/or other materials provided with the distribution.
  15  *     * Neither the name of the Open Source and Linux Lab nor the
  16  *       names of its contributors may be used to endorse or promote products
  17  *       derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <stdio.h>
  32
  33 #include "cpu.h"
  34 #include "exec/exec-all.h"
  35 #include "disas/disas.h"
  36 #include "tcg-op.h"
  37 #include "qemu/log.h"
  38 #include "sysemu/sysemu.h"
  39 #include "exec/cpu_ldst.h"
  40
  41 #include "exec/helper-proto.h"
  42 #include "exec/helper-gen.h"
  43
  44 #include "trace-tcg.h"
  45
  46
  47 typedef struct DisasContext {
  48     const XtensaConfig *config;
  49     TranslationBlock *tb;
  50     uint32_t pc;
  51     uint32_t next_pc;
  52     int cring;
  53     int ring;
  54     uint32_t lbeg;
  55     uint32_t lend;
  56     TCGv_i32 litbase;
  57     int is_jmp;
  58     int singlestep_enabled;
  59
  60     bool sar_5bit;
  61     bool sar_m32_5bit;
  62     bool sar_m32_allocated;
  63     TCGv_i32 sar_m32;
  64
  65     uint32_t ccount_delta;
  66     unsigned window;
  67
  68     bool debug;
  69     bool icount;
  70     TCGv_i32 next_icount;
  71
  72     unsigned cpenable;
  73 } DisasContext;
  74
  75 static TCGv_ptr cpu_env;
  76 static TCGv_i32 cpu_pc;
  77 static TCGv_i32 cpu_R[16];
  78 static TCGv_i32 cpu_FR[16];
  79 static TCGv_i32 cpu_SR[256];
  80 static TCGv_i32 cpu_UR[256];
  81
  82 #include "exec/gen-icount.h"
  83
  84 typedef struct XtensaReg {
  85     const char *name;
  86     uint64_t opt_bits;
  87     enum {
  88         SR_R = 1,
  89         SR_W = 2,
  90         SR_X = 4,
  91         SR_RW = 3,
  92         SR_RWX = 7,
  93     } access;
  94 } XtensaReg;
  95
  96 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
  97         .name = (regname), \
  98         .opt_bits = XTENSA_OPTION_BIT(opt), \
  99         .access = (acc), \
 100     }
 101
 102 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
 103
 104 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
 105         .name = (regname), \
 106         .opt_bits = (opt), \
 107         .access = (acc), \
 108     }
 109
 110 #define XTENSA_REG_BITS(regname, opt) \
 111     XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
 112
 113 static const XtensaReg sregnames[256] = {
 114     [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
 115     [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
 116     [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
 117     [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
 118     [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
 119     [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
 120     [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
 121     [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
 122     [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
 123     [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
 124     [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
 125     [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
 126     [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
 127     [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
 128     [WINDOW_START] = XTENSA_REG("WINDOW_START",
 129             XTENSA_OPTION_WINDOWED_REGISTER),
 130     [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
 131     [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
 132     [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
 133     [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
 134     [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
 135     [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
 136     [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
 137     [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
 138     [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
 139     [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
 140     [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
 141     [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
 142     [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
 143     [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
 144     [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
 145     [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 146     [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 147     [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 148     [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 149     [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 150     [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 151     [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
 152     [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 153     [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 154     [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 155     [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 156     [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 157     [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 158     [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
 159     [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
 160     [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
 161             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 162     [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
 163             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 164     [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
 165             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 166     [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
 167             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 168     [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
 169             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 170     [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
 171             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 172     [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
 173     [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
 174     [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
 175     [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
 176     [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
 177     [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
 178     [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
 179     [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
 180     [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
 181     [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
 182     [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
 183     [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
 184     [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
 185     [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
 186     [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
 187             XTENSA_OPTION_TIMER_INTERRUPT),
 188     [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
 189             XTENSA_OPTION_TIMER_INTERRUPT),
 190     [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
 191     [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
 192     [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
 193     [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
 194 };
 195
 196 static const XtensaReg uregnames[256] = {
 197     [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
 198     [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
 199     [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
 200 };
 201
 202 void xtensa_translate_init(void)
 203 {
 204     static const char * const regnames[] = {
 205         "ar0", "ar1", "ar2", "ar3",
 206         "ar4", "ar5", "ar6", "ar7",
 207         "ar8", "ar9", "ar10", "ar11",
 208         "ar12", "ar13", "ar14", "ar15",
 209     };
 210     static const char * const fregnames[] = {
 211         "f0", "f1", "f2", "f3",
 212         "f4", "f5", "f6", "f7",
 213         "f8", "f9", "f10", "f11",
 214         "f12", "f13", "f14", "f15",
 215     };
 216     int i;
 217
 218     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 219     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 220             offsetof(CPUXtensaState, pc), "pc");
 221
 222     for (i = 0; i < 16; i++) {
 223         cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
 224                 offsetof(CPUXtensaState, regs[i]),
 225                 regnames[i]);
 226     }
 227
 228     for (i = 0; i < 16; i++) {
 229         cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 230                 offsetof(CPUXtensaState, fregs[i]),
 231                 fregnames[i]);
 232     }
 233
 234     for (i = 0; i < 256; ++i) {
 235         if (sregnames[i].name) {
 236             cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 237                     offsetof(CPUXtensaState, sregs[i]),
 238                     sregnames[i].name);
 239         }
 240     }
 241
 242     for (i = 0; i < 256; ++i) {
 243         if (uregnames[i].name) {
 244             cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 245                     offsetof(CPUXtensaState, uregs[i]),
 246                     uregnames[i].name);
 247         }
 248     }
 249 }
 250
 251 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
 252 {
 253     return xtensa_option_bits_enabled(dc->config, opt);
 254 }
 255
 256 static inline bool option_enabled(DisasContext *dc, int opt)
 257 {
 258     return xtensa_option_enabled(dc->config, opt);
 259 }
 260
 261 static void init_litbase(DisasContext *dc)
 262 {
 263     if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
 264         dc->litbase = tcg_temp_local_new_i32();
 265         tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
 266     }
 267 }
 268
 269 static void reset_litbase(DisasContext *dc)
 270 {
 271     if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
 272         tcg_temp_free(dc->litbase);
 273     }
 274 }
 275
 276 static void init_sar_tracker(DisasContext *dc)
 277 {
 278     dc->sar_5bit = false;
 279     dc->sar_m32_5bit = false;
 280     dc->sar_m32_allocated = false;
 281 }
 282
 283 static void reset_sar_tracker(DisasContext *dc)
 284 {
 285     if (dc->sar_m32_allocated) {
 286         tcg_temp_free(dc->sar_m32);
 287     }
 288 }
 289
 290 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
 291 {
 292     tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
 293     if (dc->sar_m32_5bit) {
 294         tcg_gen_discard_i32(dc->sar_m32);
 295     }
 296     dc->sar_5bit = true;
 297     dc->sar_m32_5bit = false;
 298 }
 299
 300 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
 301 {
 302     TCGv_i32 tmp = tcg_const_i32(32);
 303     if (!dc->sar_m32_allocated) {
 304         dc->sar_m32 = tcg_temp_local_new_i32();
 305         dc->sar_m32_allocated = true;
 306     }
 307     tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
 308     tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
 309     dc->sar_5bit = false;
 310     dc->sar_m32_5bit = true;
 311     tcg_temp_free(tmp);
 312 }
 313
 314 static void gen_advance_ccount(DisasContext *dc)
 315 {
 316     if (dc->ccount_delta > 0) {
 317         TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
 318         gen_helper_advance_ccount(cpu_env, tmp);
 319         tcg_temp_free(tmp);
 320     }
 321     dc->ccount_delta = 0;
 322 }
 323
 324 static void gen_exception(DisasContext *dc, int excp)
 325 {
 326     TCGv_i32 tmp = tcg_const_i32(excp);
 327     gen_advance_ccount(dc);
 328     gen_helper_exception(cpu_env, tmp);
 329     tcg_temp_free(tmp);
 330 }
 331
 332 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
 333 {
 334     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 335     TCGv_i32 tcause = tcg_const_i32(cause);
 336     gen_advance_ccount(dc);
 337     gen_helper_exception_cause(cpu_env, tpc, tcause);
 338     tcg_temp_free(tpc);
 339     tcg_temp_free(tcause);
 340     if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
 341             cause == SYSCALL_CAUSE) {
 342         dc->is_jmp = DISAS_UPDATE;
 343     }
 344 }
 345
 346 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
 347         TCGv_i32 vaddr)
 348 {
 349     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 350     TCGv_i32 tcause = tcg_const_i32(cause);
 351     gen_advance_ccount(dc);
 352     gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
 353     tcg_temp_free(tpc);
 354     tcg_temp_free(tcause);
 355 }
 356
 357 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
 358 {
 359     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 360     TCGv_i32 tcause = tcg_const_i32(cause);
 361     gen_advance_ccount(dc);
 362     gen_helper_debug_exception(cpu_env, tpc, tcause);
 363     tcg_temp_free(tpc);
 364     tcg_temp_free(tcause);
 365     if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
 366         dc->is_jmp = DISAS_UPDATE;
 367     }
 368 }
 369
 370 static bool gen_check_privilege(DisasContext *dc)
 371 {
 372     if (dc->cring) {
 373         gen_exception_cause(dc, PRIVILEGED_CAUSE);
 374         dc->is_jmp = DISAS_UPDATE;
 375         return false;
 376     }
 377     return true;
 378 }
 379
 380 static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
 381 {
 382     if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
 383             !(dc->cpenable & (1 << cp))) {
 384         gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
 385         dc->is_jmp = DISAS_UPDATE;
 386         return false;
 387     }
 388     return true;
 389 }
 390
 391 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
 392 {
 393     tcg_gen_mov_i32(cpu_pc, dest);
 394     gen_advance_ccount(dc);
 395     if (dc->icount) {
 396         tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
 397     }
 398     if (dc->singlestep_enabled) {
 399         gen_exception(dc, EXCP_DEBUG);
 400     } else {
 401         if (slot >= 0) {
 402             tcg_gen_goto_tb(slot);
 403             tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
 404         } else {
 405             tcg_gen_exit_tb(0);
 406         }
 407     }
 408     dc->is_jmp = DISAS_UPDATE;
 409 }
 410
 411 static void gen_jump(DisasContext *dc, TCGv dest)
 412 {
 413     gen_jump_slot(dc, dest, -1);
 414 }
 415
 416 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
 417 {
 418     TCGv_i32 tmp = tcg_const_i32(dest);
 419     if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
 420         slot = -1;
 421     }
 422     gen_jump_slot(dc, tmp, slot);
 423     tcg_temp_free(tmp);
 424 }
 425
 426 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
 427         int slot)
 428 {
 429     TCGv_i32 tcallinc = tcg_const_i32(callinc);
 430
 431     tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
 432             tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
 433     tcg_temp_free(tcallinc);
 434     tcg_gen_movi_i32(cpu_R[callinc << 2],
 435             (callinc << 30) | (dc->next_pc & 0x3fffffff));
 436     gen_jump_slot(dc, dest, slot);
 437 }
 438
 439 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
 440 {
 441     gen_callw_slot(dc, callinc, dest, -1);
 442 }
 443
 444 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
 445 {
 446     TCGv_i32 tmp = tcg_const_i32(dest);
 447     if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
 448         slot = -1;
 449     }
 450     gen_callw_slot(dc, callinc, tmp, slot);
 451     tcg_temp_free(tmp);
 452 }
 453
 454 static bool gen_check_loop_end(DisasContext *dc, int slot)
 455 {
 456     if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
 457             !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
 458             dc->next_pc == dc->lend) {
 459         int label = gen_new_label();
 460
 461         gen_advance_ccount(dc);
 462         tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
 463         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
 464         gen_jumpi(dc, dc->lbeg, slot);
 465         gen_set_label(label);
 466         gen_jumpi(dc, dc->next_pc, -1);
 467         return true;
 468     }
 469     return false;
 470 }
 471
 472 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
 473 {
 474     if (!gen_check_loop_end(dc, slot)) {
 475         gen_jumpi(dc, dc->next_pc, slot);
 476     }
 477 }
 478
 479 static void gen_brcond(DisasContext *dc, TCGCond cond,
 480         TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
 481 {
 482     int label = gen_new_label();
 483
 484     gen_advance_ccount(dc);
 485     tcg_gen_brcond_i32(cond, t0, t1, label);
 486     gen_jumpi_check_loop_end(dc, 0);
 487     gen_set_label(label);
 488     gen_jumpi(dc, dc->pc + offset, 1);
 489 }
 490
 491 static void gen_brcondi(DisasContext *dc, TCGCond cond,
 492         TCGv_i32 t0, uint32_t t1, uint32_t offset)
 493 {
 494     TCGv_i32 tmp = tcg_const_i32(t1);
 495     gen_brcond(dc, cond, t0, tmp, offset);
 496     tcg_temp_free(tmp);
 497 }
 498
 499 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
 500 {
 501     if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
 502         if (sregnames[sr].name) {
 503             qemu_log("SR %s is not configured\n", sregnames[sr].name);
 504         } else {
 505             qemu_log("SR %d is not implemented\n", sr);
 506         }
 507         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
 508         return false;
 509     } else if (!(sregnames[sr].access & access)) {
 510         static const char * const access_text[] = {
 511             [SR_R] = "rsr",
 512             [SR_W] = "wsr",
 513             [SR_X] = "xsr",
 514         };
 515         assert(access < ARRAY_SIZE(access_text) && access_text[access]);
 516         qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
 517                 access_text[access]);
 518         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
 519         return false;
 520     }
 521     return true;
 522 }
 523
 524 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 525 {
 526     gen_advance_ccount(dc);
 527     tcg_gen_mov_i32(d, cpu_SR[sr]);
 528 }
 529
 530 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 531 {
 532     tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
 533     tcg_gen_or_i32(d, d, cpu_SR[sr]);
 534     tcg_gen_andi_i32(d, d, 0xfffffffc);
 535 }
 536
 537 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 538 {
 539     static void (* const rsr_handler[256])(DisasContext *dc,
 540             TCGv_i32 d, uint32_t sr) = {
 541         [CCOUNT] = gen_rsr_ccount,
 542         [PTEVADDR] = gen_rsr_ptevaddr,
 543     };
 544
 545     if (rsr_handler[sr]) {
 546         rsr_handler[sr](dc, d, sr);
 547     } else {
 548         tcg_gen_mov_i32(d, cpu_SR[sr]);
 549     }
 550 }
 551
 552 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 553 {
 554     gen_helper_wsr_lbeg(cpu_env, s);
 555     gen_jumpi_check_loop_end(dc, 0);
 556 }
 557
 558 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 559 {
 560     gen_helper_wsr_lend(cpu_env, s);
 561     gen_jumpi_check_loop_end(dc, 0);
 562 }
 563
 564 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 565 {
 566     tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
 567     if (dc->sar_m32_5bit) {
 568         tcg_gen_discard_i32(dc->sar_m32);
 569     }
 570     dc->sar_5bit = false;
 571     dc->sar_m32_5bit = false;
 572 }
 573
 574 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 575 {
 576     tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
 577 }
 578
 579 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 580 {
 581     tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
 582     /* This can change tb->flags, so exit tb */
 583     gen_jumpi_check_loop_end(dc, -1);
 584 }
 585
 586 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 587 {
 588     tcg_gen_ext8s_i32(cpu_SR[sr], s);
 589 }
 590
 591 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 592 {
 593     gen_helper_wsr_windowbase(cpu_env, v);
 594     /* This can change tb->flags, so exit tb */
 595     gen_jumpi_check_loop_end(dc, -1);
 596 }
 597
 598 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 599 {
 600     tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
 601     /* This can change tb->flags, so exit tb */
 602     gen_jumpi_check_loop_end(dc, -1);
 603 }
 604
 605 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 606 {
 607     tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
 608 }
 609
 610 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 611 {
 612     gen_helper_wsr_rasid(cpu_env, v);
 613     /* This can change tb->flags, so exit tb */
 614     gen_jumpi_check_loop_end(dc, -1);
 615 }
 616
 617 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 618 {
 619     tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
 620 }
 621
 622 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 623 {
 624     gen_helper_wsr_ibreakenable(cpu_env, v);
 625     gen_jumpi_check_loop_end(dc, 0);
 626 }
 627
 628 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 629 {
 630     tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
 631 }
 632
 633 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 634 {
 635     unsigned id = sr - IBREAKA;
 636
 637     if (id < dc->config->nibreak) {
 638         TCGv_i32 tmp = tcg_const_i32(id);
 639         gen_helper_wsr_ibreaka(cpu_env, tmp, v);
 640         tcg_temp_free(tmp);
 641         gen_jumpi_check_loop_end(dc, 0);
 642     }
 643 }
 644
 645 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 646 {
 647     unsigned id = sr - DBREAKA;
 648
 649     if (id < dc->config->ndbreak) {
 650         TCGv_i32 tmp = tcg_const_i32(id);
 651         gen_helper_wsr_dbreaka(cpu_env, tmp, v);
 652         tcg_temp_free(tmp);
 653     }
 654 }
 655
 656 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 657 {
 658     unsigned id = sr - DBREAKC;
 659
 660     if (id < dc->config->ndbreak) {
 661         TCGv_i32 tmp = tcg_const_i32(id);
 662         gen_helper_wsr_dbreakc(cpu_env, tmp, v);
 663         tcg_temp_free(tmp);
 664     }
 665 }
 666
 667 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 668 {
 669     tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
 670     /* This can change tb->flags, so exit tb */
 671     gen_jumpi_check_loop_end(dc, -1);
 672 }
 673
 674 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 675 {
 676     tcg_gen_andi_i32(cpu_SR[sr], v,
 677             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
 678     gen_helper_check_interrupts(cpu_env);
 679     gen_jumpi_check_loop_end(dc, 0);
 680 }
 681
 682 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 683 {
 684     TCGv_i32 tmp = tcg_temp_new_i32();
 685
 686     tcg_gen_andi_i32(tmp, v,
 687             dc->config->inttype_mask[INTTYPE_EDGE] |
 688             dc->config->inttype_mask[INTTYPE_NMI] |
 689             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
 690     tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
 691     tcg_temp_free(tmp);
 692     gen_helper_check_interrupts(cpu_env);
 693 }
 694
 695 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 696 {
 697     tcg_gen_mov_i32(cpu_SR[sr], v);
 698     gen_helper_check_interrupts(cpu_env);
 699     gen_jumpi_check_loop_end(dc, 0);
 700 }
 701
 702 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 703 {
 704     uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
 705         PS_UM | PS_EXCM | PS_INTLEVEL;
 706
 707     if (option_enabled(dc, XTENSA_OPTION_MMU)) {
 708         mask |= PS_RING;
 709     }
 710     tcg_gen_andi_i32(cpu_SR[sr], v, mask);
 711     gen_helper_check_interrupts(cpu_env);
 712     /* This can change mmu index and tb->flags, so exit tb */
 713     gen_jumpi_check_loop_end(dc, -1);
 714 }
 715
 716 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 717 {
 718     if (dc->icount) {
 719         tcg_gen_mov_i32(dc->next_icount, v);
 720     } else {
 721         tcg_gen_mov_i32(cpu_SR[sr], v);
 722     }
 723 }
 724
 725 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 726 {
 727     tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
 728     /* This can change tb->flags, so exit tb */
 729     gen_jumpi_check_loop_end(dc, -1);
 730 }
 731
 732 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 733 {
 734     uint32_t id = sr - CCOMPARE;
 735     if (id < dc->config->nccompare) {
 736         uint32_t int_bit = 1 << dc->config->timerint[id];
 737         gen_advance_ccount(dc);
 738         tcg_gen_mov_i32(cpu_SR[sr], v);
 739         tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
 740         gen_helper_check_interrupts(cpu_env);
 741     }
 742 }
 743
 744 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 745 {
 746     static void (* const wsr_handler[256])(DisasContext *dc,
 747             uint32_t sr, TCGv_i32 v) = {
 748         [LBEG] = gen_wsr_lbeg,
 749         [LEND] = gen_wsr_lend,
 750         [SAR] = gen_wsr_sar,
 751         [BR] = gen_wsr_br,
 752         [LITBASE] = gen_wsr_litbase,
 753         [ACCHI] = gen_wsr_acchi,
 754         [WINDOW_BASE] = gen_wsr_windowbase,
 755         [WINDOW_START] = gen_wsr_windowstart,
 756         [PTEVADDR] = gen_wsr_ptevaddr,
 757         [RASID] = gen_wsr_rasid,
 758         [ITLBCFG] = gen_wsr_tlbcfg,
 759         [DTLBCFG] = gen_wsr_tlbcfg,
 760         [IBREAKENABLE] = gen_wsr_ibreakenable,
 761         [ATOMCTL] = gen_wsr_atomctl,
 762         [IBREAKA] = gen_wsr_ibreaka,
 763         [IBREAKA + 1] = gen_wsr_ibreaka,
 764         [DBREAKA] = gen_wsr_dbreaka,
 765         [DBREAKA + 1] = gen_wsr_dbreaka,
 766         [DBREAKC] = gen_wsr_dbreakc,
 767         [DBREAKC + 1] = gen_wsr_dbreakc,
 768         [CPENABLE] = gen_wsr_cpenable,
 769         [INTSET] = gen_wsr_intset,
 770         [INTCLEAR] = gen_wsr_intclear,
 771         [INTENABLE] = gen_wsr_intenable,
 772         [PS] = gen_wsr_ps,
 773         [ICOUNT] = gen_wsr_icount,
 774         [ICOUNTLEVEL] = gen_wsr_icountlevel,
 775         [CCOMPARE] = gen_wsr_ccompare,
 776         [CCOMPARE + 1] = gen_wsr_ccompare,
 777         [CCOMPARE + 2] = gen_wsr_ccompare,
 778     };
 779
 780     if (wsr_handler[sr]) {
 781         wsr_handler[sr](dc, sr, s);
 782     } else {
 783         tcg_gen_mov_i32(cpu_SR[sr], s);
 784     }
 785 }
 786
 787 static void gen_wur(uint32_t ur, TCGv_i32 s)
 788 {
 789     switch (ur) {
 790     case FCR:
 791         gen_helper_wur_fcr(cpu_env, s);
 792         break;
 793
 794     case FSR:
 795         tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
 796         break;
 797
 798     default:
 799         tcg_gen_mov_i32(cpu_UR[ur], s);
 800         break;
 801     }
 802 }
 803
 804 static void gen_load_store_alignment(DisasContext *dc, int shift,
 805         TCGv_i32 addr, bool no_hw_alignment)
 806 {
 807     if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
 808         tcg_gen_andi_i32(addr, addr, ~0 << shift);
 809     } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
 810             no_hw_alignment) {
 811         int label = gen_new_label();
 812         TCGv_i32 tmp = tcg_temp_new_i32();
 813         tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
 814         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
 815         gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
 816         gen_set_label(label);
 817         tcg_temp_free(tmp);
 818     }
 819 }
 820
 821 static void gen_waiti(DisasContext *dc, uint32_t imm4)
 822 {
 823     TCGv_i32 pc = tcg_const_i32(dc->next_pc);
 824     TCGv_i32 intlevel = tcg_const_i32(imm4);
 825     gen_advance_ccount(dc);
 826     gen_helper_waiti(cpu_env, pc, intlevel);
 827     tcg_temp_free(pc);
 828     tcg_temp_free(intlevel);
 829 }
 830
 831 static bool gen_window_check1(DisasContext *dc, unsigned r1)
 832 {
 833     if (r1 / 4 > dc->window) {
 834         TCGv_i32 pc = tcg_const_i32(dc->pc);
 835         TCGv_i32 w = tcg_const_i32(r1 / 4);
 836
 837         gen_advance_ccount(dc);
 838         gen_helper_window_check(cpu_env, pc, w);
 839         dc->is_jmp = DISAS_UPDATE;
 840         return false;
 841     }
 842     return true;
 843 }
 844
 845 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
 846 {
 847     return gen_window_check1(dc, r1 > r2 ? r1 : r2);
 848 }
 849
 850 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
 851         unsigned r3)
 852 {
 853     return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
 854 }
 855
 856 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
 857 {
 858     TCGv_i32 m = tcg_temp_new_i32();
 859
 860     if (hi) {
 861         (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
 862     } else {
 863         (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
 864     }
 865     return m;
 866 }
 867
 868 static inline unsigned xtensa_op0_insn_len(unsigned op0)
 869 {
 870     return op0 >= 8 ? 2 : 3;
 871 }
 872
 873 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
 874 {
 875 #define HAS_OPTION_BITS(opt) do { \
 876         if (!option_bits_enabled(dc, opt)) { \
 877             qemu_log("Option is not enabled %s:%d\n", \
 878                     __FILE__, __LINE__); \
 879             goto invalid_opcode; \
 880         } \
 881     } while (0)
 882
 883 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
 884
 885 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
 886 #define RESERVED() do { \
 887         qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
 888                 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
 889         goto invalid_opcode; \
 890     } while (0)
 891
 892
 893 #ifdef TARGET_WORDS_BIGENDIAN
 894 #define OP0 (((b0) & 0xf0) >> 4)
 895 #define OP1 (((b2) & 0xf0) >> 4)
 896 #define OP2 ((b2) & 0xf)
 897 #define RRR_R ((b1) & 0xf)
 898 #define RRR_S (((b1) & 0xf0) >> 4)
 899 #define RRR_T ((b0) & 0xf)
 900 #else
 901 #define OP0 (((b0) & 0xf))
 902 #define OP1 (((b2) & 0xf))
 903 #define OP2 (((b2) & 0xf0) >> 4)
 904 #define RRR_R (((b1) & 0xf0) >> 4)
 905 #define RRR_S (((b1) & 0xf))
 906 #define RRR_T (((b0) & 0xf0) >> 4)
 907 #endif
 908 #define RRR_X ((RRR_R & 0x4) >> 2)
 909 #define RRR_Y ((RRR_T & 0x4) >> 2)
 910 #define RRR_W (RRR_R & 0x3)
 911
 912 #define RRRN_R RRR_R
 913 #define RRRN_S RRR_S
 914 #define RRRN_T RRR_T
 915
 916 #define RRI4_R RRR_R
 917 #define RRI4_S RRR_S
 918 #define RRI4_T RRR_T
 919 #ifdef TARGET_WORDS_BIGENDIAN
 920 #define RRI4_IMM4 ((b2) & 0xf)
 921 #else
 922 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
 923 #endif
 924
 925 #define RRI8_R RRR_R
 926 #define RRI8_S RRR_S
 927 #define RRI8_T RRR_T
 928 #define RRI8_IMM8 (b2)
 929 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
 930
 931 #ifdef TARGET_WORDS_BIGENDIAN
 932 #define RI16_IMM16 (((b1) << 8) | (b2))
 933 #else
 934 #define RI16_IMM16 (((b2) << 8) | (b1))
 935 #endif
 936
 937 #ifdef TARGET_WORDS_BIGENDIAN
 938 #define CALL_N (((b0) & 0xc) >> 2)
 939 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
 940 #else
 941 #define CALL_N (((b0) & 0x30) >> 4)
 942 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
 943 #endif
 944 #define CALL_OFFSET_SE \
 945     (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
 946
 947 #define CALLX_N CALL_N
 948 #ifdef TARGET_WORDS_BIGENDIAN
 949 #define CALLX_M ((b0) & 0x3)
 950 #else
 951 #define CALLX_M (((b0) & 0xc0) >> 6)
 952 #endif
 953 #define CALLX_S RRR_S
 954
 955 #define BRI12_M CALLX_M
 956 #define BRI12_S RRR_S
 957 #ifdef TARGET_WORDS_BIGENDIAN
 958 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
 959 #else
 960 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
 961 #endif
 962 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
 963
 964 #define BRI8_M BRI12_M
 965 #define BRI8_R RRI8_R
 966 #define BRI8_S RRI8_S
 967 #define BRI8_IMM8 RRI8_IMM8
 968 #define BRI8_IMM8_SE RRI8_IMM8_SE
 969
 970 #define RSR_SR (b1)
 971
 972     uint8_t b0 = cpu_ldub_code(env, dc->pc);
 973     uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
 974     uint8_t b2 = 0;
 975     unsigned len = xtensa_op0_insn_len(OP0);
 976
 977     static const uint32_t B4CONST[] = {
 978         0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 979     };
 980
 981     static const uint32_t B4CONSTU[] = {
 982         32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 983     };
 984
 985     switch (len) {
 986     case 2:
 987         HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
 988         break;
 989
 990     case 3:
 991         b2 = cpu_ldub_code(env, dc->pc + 2);
 992         break;
 993
 994     default:
 995         RESERVED();
 996     }
 997     dc->next_pc = dc->pc + len;
 998
 999     switch (OP0) {
1000     case 0: /*QRST*/
1001         switch (OP1) {
1002         case 0: /*RST0*/
1003             switch (OP2) {
1004             case 0: /*ST0*/
1005                 if ((RRR_R & 0xc) == 0x8) {
1006                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1007                 }
1008
1009                 switch (RRR_R) {
1010                 case 0: /*SNM0*/
1011                     switch (CALLX_M) {
1012                     case 0: /*ILL*/
1013                         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1014                         break;
1015
1016                     case 1: /*reserved*/
1017                         RESERVED();
1018                         break;
1019
1020                     case 2: /*JR*/
1021                         switch (CALLX_N) {
1022                         case 0: /*RET*/
1023                         case 2: /*JX*/
1024                             if (gen_window_check1(dc, CALLX_S)) {
1025                                 gen_jump(dc, cpu_R[CALLX_S]);
1026                             }
1027                             break;
1028
1029                         case 1: /*RETWw*/
1030                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1031                             {
1032                                 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1033                                 gen_advance_ccount(dc);
1034                                 gen_helper_retw(tmp, cpu_env, tmp);
1035                                 gen_jump(dc, tmp);
1036                                 tcg_temp_free(tmp);
1037                             }
1038                             break;
1039
1040                         case 3: /*reserved*/
1041                             RESERVED();
1042                             break;
1043                         }
1044                         break;
1045
1046                     case 3: /*CALLX*/
1047                         if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1048                             break;
1049                         }
1050                         switch (CALLX_N) {
1051                         case 0: /*CALLX0*/
1052                             {
1053                                 TCGv_i32 tmp = tcg_temp_new_i32();
1054                                 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1055                                 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1056                                 gen_jump(dc, tmp);
1057                                 tcg_temp_free(tmp);
1058                             }
1059                             break;
1060
1061                         case 1: /*CALLX4w*/
1062                         case 2: /*CALLX8w*/
1063                         case 3: /*CALLX12w*/
1064                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1065                             {
1066                                 TCGv_i32 tmp = tcg_temp_new_i32();
1067
1068                                 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1069                                 gen_callw(dc, CALLX_N, tmp);
1070                                 tcg_temp_free(tmp);
1071                             }
1072                             break;
1073                         }
1074                         break;
1075                     }
1076                     break;
1077
1078                 case 1: /*MOVSPw*/
1079                     HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1080                     if (gen_window_check2(dc, RRR_T, RRR_S)) {
1081                         TCGv_i32 pc = tcg_const_i32(dc->pc);
1082                         gen_advance_ccount(dc);
1083                         gen_helper_movsp(cpu_env, pc);
1084                         tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1085                         tcg_temp_free(pc);
1086                     }
1087                     break;
1088
1089                 case 2: /*SYNC*/
1090                     switch (RRR_T) {
1091                     case 0: /*ISYNC*/
1092                         break;
1093
1094                     case 1: /*RSYNC*/
1095                         break;
1096
1097                     case 2: /*ESYNC*/
1098                         break;
1099
1100                     case 3: /*DSYNC*/
1101                         break;
1102
1103                     case 8: /*EXCW*/
1104                         HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1105                         break;
1106
1107                     case 12: /*MEMW*/
1108                         break;
1109
1110                     case 13: /*EXTW*/
1111                         break;
1112
1113                     case 15: /*NOP*/
1114                         break;
1115
1116                     default: /*reserved*/
1117                         RESERVED();
1118                         break;
1119                     }
1120                     break;
1121
1122                 case 3: /*RFEIx*/
1123                     switch (RRR_T) {
1124                     case 0: /*RFETx*/
1125                         HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1126                         switch (RRR_S) {
1127                         case 0: /*RFEx*/
1128                             if (gen_check_privilege(dc)) {
1129                                 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1130                                 gen_helper_check_interrupts(cpu_env);
1131                                 gen_jump(dc, cpu_SR[EPC1]);
1132                             }
1133                             break;
1134
1135                         case 1: /*RFUEx*/
1136                             RESERVED();
1137                             break;
1138
1139                         case 2: /*RFDEx*/
1140                             if (gen_check_privilege(dc)) {
1141                                 gen_jump(dc, cpu_SR[
1142                                          dc->config->ndepc ? DEPC : EPC1]);
1143                             }
1144                             break;
1145
1146                         case 4: /*RFWOw*/
1147                         case 5: /*RFWUw*/
1148                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1149                             if (gen_check_privilege(dc)) {
1150                                 TCGv_i32 tmp = tcg_const_i32(1);
1151
1152                                 tcg_gen_andi_i32(
1153                                         cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1154                                 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1155
1156                                 if (RRR_S == 4) {
1157                                     tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1158                                             cpu_SR[WINDOW_START], tmp);
1159                                 } else {
1160                                     tcg_gen_or_i32(cpu_SR[WINDOW_START],
1161                                             cpu_SR[WINDOW_START], tmp);
1162                                 }
1163
1164                                 gen_helper_restore_owb(cpu_env);
1165                                 gen_helper_check_interrupts(cpu_env);
1166                                 gen_jump(dc, cpu_SR[EPC1]);
1167
1168                                 tcg_temp_free(tmp);
1169                             }
1170                             break;
1171
1172                         default: /*reserved*/
1173                             RESERVED();
1174                             break;
1175                         }
1176                         break;
1177
1178                     case 1: /*RFIx*/
1179                         HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1180                         if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1181                             if (gen_check_privilege(dc)) {
1182                                 tcg_gen_mov_i32(cpu_SR[PS],
1183                                                 cpu_SR[EPS2 + RRR_S - 2]);
1184                                 gen_helper_check_interrupts(cpu_env);
1185                                 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1186                             }
1187                         } else {
1188                             qemu_log("RFI %d is illegal\n", RRR_S);
1189                             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1190                         }
1191                         break;
1192
1193                     case 2: /*RFME*/
1194                         TBD();
1195                         break;
1196
1197                     default: /*reserved*/
1198                         RESERVED();
1199                         break;
1200
1201                     }
1202                     break;
1203
1204                 case 4: /*BREAKx*/
1205                     HAS_OPTION(XTENSA_OPTION_DEBUG);
1206                     if (dc->debug) {
1207                         gen_debug_exception(dc, DEBUGCAUSE_BI);
1208                     }
1209                     break;
1210
1211                 case 5: /*SYSCALLx*/
1212                     HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1213                     switch (RRR_S) {
1214                     case 0: /*SYSCALLx*/
1215                         gen_exception_cause(dc, SYSCALL_CAUSE);
1216                         break;
1217
1218                     case 1: /*SIMCALL*/
1219                         if (semihosting_enabled) {
1220                             if (gen_check_privilege(dc)) {
1221                                 gen_helper_simcall(cpu_env);
1222                             }
1223                         } else {
1224                             qemu_log("SIMCALL but semihosting is disabled\n");
1225                             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1226                         }
1227                         break;
1228
1229                     default:
1230                         RESERVED();
1231                         break;
1232                     }
1233                     break;
1234
1235                 case 6: /*RSILx*/
1236                     HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1237                     if (gen_check_privilege(dc) &&
1238                         gen_window_check1(dc, RRR_T)) {
1239                         tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1240                         tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1241                         tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1242                         gen_helper_check_interrupts(cpu_env);
1243                         gen_jumpi_check_loop_end(dc, 0);
1244                     }
1245                     break;
1246
1247                 case 7: /*WAITIx*/
1248                     HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1249                     if (gen_check_privilege(dc)) {
1250                         gen_waiti(dc, RRR_S);
1251                     }
1252                     break;
1253
1254                 case 8: /*ANY4p*/
1255                 case 9: /*ALL4p*/
1256                 case 10: /*ANY8p*/
1257                 case 11: /*ALL8p*/
1258                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1259                     {
1260                         const unsigned shift = (RRR_R & 2) ? 8 : 4;
1261                         TCGv_i32 mask = tcg_const_i32(
1262                                 ((1 << shift) - 1) << RRR_S);
1263                         TCGv_i32 tmp = tcg_temp_new_i32();
1264
1265                         tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1266                         if (RRR_R & 1) { /*ALL*/
1267                             tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1268                         } else { /*ANY*/
1269                             tcg_gen_add_i32(tmp, tmp, mask);
1270                         }
1271                         tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1272                         tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1273                                 tmp, RRR_T, 1);
1274                         tcg_temp_free(mask);
1275                         tcg_temp_free(tmp);
1276                     }
1277                     break;
1278
1279                 default: /*reserved*/
1280                     RESERVED();
1281                     break;
1282
1283                 }
1284                 break;
1285
1286             case 1: /*AND*/
1287                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1288                     tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1289                 }
1290                 break;
1291
1292             case 2: /*OR*/
1293                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1294                     tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1295                 }
1296                 break;
1297
1298             case 3: /*XOR*/
1299                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1300                     tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1301                 }
1302                 break;
1303
1304             case 4: /*ST1*/
1305                 switch (RRR_R) {
1306                 case 0: /*SSR*/
1307                     if (gen_window_check1(dc, RRR_S)) {
1308                         gen_right_shift_sar(dc, cpu_R[RRR_S]);
1309                     }
1310                     break;
1311
1312                 case 1: /*SSL*/
1313                     if (gen_window_check1(dc, RRR_S)) {
1314                         gen_left_shift_sar(dc, cpu_R[RRR_S]);
1315                     }
1316                     break;
1317
1318                 case 2: /*SSA8L*/
1319                     if (gen_window_check1(dc, RRR_S)) {
1320                         TCGv_i32 tmp = tcg_temp_new_i32();
1321                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1322                         gen_right_shift_sar(dc, tmp);
1323                         tcg_temp_free(tmp);
1324                     }
1325                     break;
1326
1327                 case 3: /*SSA8B*/
1328                     if (gen_window_check1(dc, RRR_S)) {
1329                         TCGv_i32 tmp = tcg_temp_new_i32();
1330                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1331                         gen_left_shift_sar(dc, tmp);
1332                         tcg_temp_free(tmp);
1333                     }
1334                     break;
1335
1336                 case 4: /*SSAI*/
1337                     {
1338                         TCGv_i32 tmp = tcg_const_i32(
1339                                 RRR_S | ((RRR_T & 1) << 4));
1340                         gen_right_shift_sar(dc, tmp);
1341                         tcg_temp_free(tmp);
1342                     }
1343                     break;
1344
1345                 case 6: /*RER*/
1346                     TBD();
1347                     break;
1348
1349                 case 7: /*WER*/
1350                     TBD();
1351                     break;
1352
1353                 case 8: /*ROTWw*/
1354                     HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1355                     if (gen_check_privilege(dc)) {
1356                         TCGv_i32 tmp = tcg_const_i32(
1357                                 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1358                         gen_helper_rotw(cpu_env, tmp);
1359                         tcg_temp_free(tmp);
1360                         /* This can change tb->flags, so exit tb */
1361                         gen_jumpi_check_loop_end(dc, -1);
1362                     }
1363                     break;
1364
1365                 case 14: /*NSAu*/
1366                     HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1367                     if (gen_window_check2(dc, RRR_S, RRR_T)) {
1368                         gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1369                     }
1370                     break;
1371
1372                 case 15: /*NSAUu*/
1373                     HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1374                     if (gen_window_check2(dc, RRR_S, RRR_T)) {
1375                         gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1376                     }
1377                     break;
1378
1379                 default: /*reserved*/
1380                     RESERVED();
1381                     break;
1382                 }
1383                 break;
1384
1385             case 5: /*TLB*/
1386                 HAS_OPTION_BITS(
1387                         XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1388                         XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1389                         XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1390                 if (gen_check_privilege(dc) &&
1391                     gen_window_check2(dc, RRR_S, RRR_T)) {
1392                     TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1393
1394                     switch (RRR_R & 7) {
1395                     case 3: /*RITLB0*/ /*RDTLB0*/
1396                         gen_helper_rtlb0(cpu_R[RRR_T],
1397                                 cpu_env, cpu_R[RRR_S], dtlb);
1398                         break;
1399
1400                     case 4: /*IITLB*/ /*IDTLB*/
1401                         gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1402                         /* This could change memory mapping, so exit tb */
1403                         gen_jumpi_check_loop_end(dc, -1);
1404                         break;
1405
1406                     case 5: /*PITLB*/ /*PDTLB*/
1407                         tcg_gen_movi_i32(cpu_pc, dc->pc);
1408                         gen_helper_ptlb(cpu_R[RRR_T],
1409                                 cpu_env, cpu_R[RRR_S], dtlb);
1410                         break;
1411
1412                     case 6: /*WITLB*/ /*WDTLB*/
1413                         gen_helper_wtlb(
1414                                 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1415                         /* This could change memory mapping, so exit tb */
1416                         gen_jumpi_check_loop_end(dc, -1);
1417                         break;
1418
1419                     case 7: /*RITLB1*/ /*RDTLB1*/
1420                         gen_helper_rtlb1(cpu_R[RRR_T],
1421                                 cpu_env, cpu_R[RRR_S], dtlb);
1422                         break;
1423
1424                     default:
1425                         tcg_temp_free(dtlb);
1426                         RESERVED();
1427                         break;
1428                     }
1429                     tcg_temp_free(dtlb);
1430                 }
1431                 break;
1432
1433             case 6: /*RT0*/
1434                 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1435                     break;
1436                 }
1437                 switch (RRR_S) {
1438                 case 0: /*NEG*/
1439                     tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1440                     break;
1441
1442                 case 1: /*ABS*/
1443                     {
1444                         TCGv_i32 zero = tcg_const_i32(0);
1445                         TCGv_i32 neg = tcg_temp_new_i32();
1446
1447                         tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1448                         tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1449                                 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1450                         tcg_temp_free(neg);
1451                         tcg_temp_free(zero);
1452                     }
1453                     break;
1454
1455                 default: /*reserved*/
1456                     RESERVED();
1457                     break;
1458                 }
1459                 break;
1460
1461             case 7: /*reserved*/
1462                 RESERVED();
1463                 break;
1464
1465             case 8: /*ADD*/
1466                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1467                     tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1468                 }
1469                 break;
1470
1471             case 9: /*ADD**/
1472             case 10:
1473             case 11:
1474                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1475                     TCGv_i32 tmp = tcg_temp_new_i32();
1476                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1477                     tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1478                     tcg_temp_free(tmp);
1479                 }
1480                 break;
1481
1482             case 12: /*SUB*/
1483                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1484                     tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1485                 }
1486                 break;
1487
1488             case 13: /*SUB**/
1489             case 14:
1490             case 15:
1491                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1492                     TCGv_i32 tmp = tcg_temp_new_i32();
1493                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1494                     tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1495                     tcg_temp_free(tmp);
1496                 }
1497                 break;
1498             }
1499             break;
1500
1501         case 1: /*RST1*/
1502             switch (OP2) {
1503             case 0: /*SLLI*/
1504             case 1:
1505                 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1506                     tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1507                                      32 - (RRR_T | ((OP2 & 1) << 4)));
1508                 }
1509                 break;
1510
1511             case 2: /*SRAI*/
1512             case 3:
1513                 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1514                     tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1515                                      RRR_S | ((OP2 & 1) << 4));
1516                 }
1517                 break;
1518
1519             case 4: /*SRLI*/
1520                 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1521                     tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1522                 }
1523                 break;
1524
1525             case 6: /*XSR*/
1526                 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1527                     (RSR_SR < 64 || gen_check_privilege(dc)) &&
1528                     gen_window_check1(dc, RRR_T)) {
1529                     TCGv_i32 tmp = tcg_temp_new_i32();
1530
1531                     tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1532                     gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1533                     gen_wsr(dc, RSR_SR, tmp);
1534                     tcg_temp_free(tmp);
1535                 }
1536                 break;
1537
1538                 /*
1539                  * Note: 64 bit ops are used here solely because SAR values
1540                  * have range 0..63
1541                  */
1542 #define gen_shift_reg(cmd, reg) do { \
1543                     TCGv_i64 tmp = tcg_temp_new_i64(); \
1544                     tcg_gen_extu_i32_i64(tmp, reg); \
1545                     tcg_gen_##cmd##_i64(v, v, tmp); \
1546                     tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1547                     tcg_temp_free_i64(v); \
1548                     tcg_temp_free_i64(tmp); \
1549                 } while (0)
1550
1551 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1552
1553             case 8: /*SRC*/
1554                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1555                     TCGv_i64 v = tcg_temp_new_i64();
1556                     tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1557                     gen_shift(shr);
1558                 }
1559                 break;
1560
1561             case 9: /*SRL*/
1562                 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1563                     break;
1564                 }
1565                 if (dc->sar_5bit) {
1566                     tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1567                 } else {
1568                     TCGv_i64 v = tcg_temp_new_i64();
1569                     tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1570                     gen_shift(shr);
1571                 }
1572                 break;
1573
1574             case 10: /*SLL*/
1575                 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1576                     break;
1577                 }
1578                 if (dc->sar_m32_5bit) {
1579                     tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1580                 } else {
1581                     TCGv_i64 v = tcg_temp_new_i64();
1582                     TCGv_i32 s = tcg_const_i32(32);
1583                     tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1584                     tcg_gen_andi_i32(s, s, 0x3f);
1585                     tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1586                     gen_shift_reg(shl, s);
1587                     tcg_temp_free(s);
1588                 }
1589                 break;
1590
1591             case 11: /*SRA*/
1592                 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1593                     break;
1594                 }
1595                 if (dc->sar_5bit) {
1596                     tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1597                 } else {
1598                     TCGv_i64 v = tcg_temp_new_i64();
1599                     tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1600                     gen_shift(sar);
1601                 }
1602                 break;
1603 #undef gen_shift
1604 #undef gen_shift_reg
1605
1606             case 12: /*MUL16U*/
1607                 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1608                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1609                     TCGv_i32 v1 = tcg_temp_new_i32();
1610                     TCGv_i32 v2 = tcg_temp_new_i32();
1611                     tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1612                     tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1613                     tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1614                     tcg_temp_free(v2);
1615                     tcg_temp_free(v1);
1616                 }
1617                 break;
1618
1619             case 13: /*MUL16S*/
1620                 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1621                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1622                     TCGv_i32 v1 = tcg_temp_new_i32();
1623                     TCGv_i32 v2 = tcg_temp_new_i32();
1624                     tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1625                     tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1626                     tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1627                     tcg_temp_free(v2);
1628                     tcg_temp_free(v1);
1629                 }
1630                 break;
1631
1632             default: /*reserved*/
1633                 RESERVED();
1634                 break;
1635             }
1636             break;
1637
1638         case 2: /*RST2*/
1639             if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1640                 break;
1641             }
1642
1643             if (OP2 >= 12) {
1644                 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1645                 int label = gen_new_label();
1646                 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1647                 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1648                 gen_set_label(label);
1649             }
1650
1651             switch (OP2) {
1652 #define BOOLEAN_LOGIC(fn, r, s, t) \
1653                 do { \
1654                     HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1655                     TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1656                     TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1657                     \
1658                     tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1659                     tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1660                     tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1661                     tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1662                     tcg_temp_free(tmp1); \
1663                     tcg_temp_free(tmp2); \
1664                 } while (0)
1665
1666             case 0: /*ANDBp*/
1667                 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1668                 break;
1669
1670             case 1: /*ANDBCp*/
1671                 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1672                 break;
1673
1674             case 2: /*ORBp*/
1675                 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1676                 break;
1677
1678             case 3: /*ORBCp*/
1679                 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1680                 break;
1681
1682             case 4: /*XORBp*/
1683                 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1684                 break;
1685
1686 #undef BOOLEAN_LOGIC
1687
1688             case 8: /*MULLi*/
1689                 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1690                 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1691                 break;
1692
1693             case 10: /*MULUHi*/
1694             case 11: /*MULSHi*/
1695                 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1696                 {
1697                     TCGv lo = tcg_temp_new();
1698
1699                     if (OP2 == 10) {
1700                         tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1701                                           cpu_R[RRR_S], cpu_R[RRR_T]);
1702                     } else {
1703                         tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1704                                           cpu_R[RRR_S], cpu_R[RRR_T]);
1705                     }
1706                     tcg_temp_free(lo);
1707                 }
1708                 break;
1709
1710             case 12: /*QUOUi*/
1711                 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1712                 break;
1713
1714             case 13: /*QUOSi*/
1715             case 15: /*REMSi*/
1716                 {
1717                     int label1 = gen_new_label();
1718                     int label2 = gen_new_label();
1719
1720                     tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1721                             label1);
1722                     tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1723                             label1);
1724                     tcg_gen_movi_i32(cpu_R[RRR_R],
1725                             OP2 == 13 ? 0x80000000 : 0);
1726                     tcg_gen_br(label2);
1727                     gen_set_label(label1);
1728                     if (OP2 == 13) {
1729                         tcg_gen_div_i32(cpu_R[RRR_R],
1730                                 cpu_R[RRR_S], cpu_R[RRR_T]);
1731                     } else {
1732                         tcg_gen_rem_i32(cpu_R[RRR_R],
1733                                 cpu_R[RRR_S], cpu_R[RRR_T]);
1734                     }
1735                     gen_set_label(label2);
1736                 }
1737                 break;
1738
1739             case 14: /*REMUi*/
1740                 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1741                 break;
1742
1743             default: /*reserved*/
1744                 RESERVED();
1745                 break;
1746             }
1747             break;
1748
1749         case 3: /*RST3*/
1750             switch (OP2) {
1751             case 0: /*RSR*/
1752                 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1753                     (RSR_SR < 64 || gen_check_privilege(dc)) &&
1754                     gen_window_check1(dc, RRR_T)) {
1755                     gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1756                 }
1757                 break;
1758
1759             case 1: /*WSR*/
1760                 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1761                     (RSR_SR < 64 || gen_check_privilege(dc)) &&
1762                     gen_window_check1(dc, RRR_T)) {
1763                     gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1764                 }
1765                 break;
1766
1767             case 2: /*SEXTu*/
1768                 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1769                 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1770                     int shift = 24 - RRR_T;
1771
1772                     if (shift == 24) {
1773                         tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1774                     } else if (shift == 16) {
1775                         tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1776                     } else {
1777                         TCGv_i32 tmp = tcg_temp_new_i32();
1778                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1779                         tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1780                         tcg_temp_free(tmp);
1781                     }
1782                 }
1783                 break;
1784
1785             case 3: /*CLAMPSu*/
1786                 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1787                 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1788                     TCGv_i32 tmp1 = tcg_temp_new_i32();
1789                     TCGv_i32 tmp2 = tcg_temp_new_i32();
1790                     TCGv_i32 zero = tcg_const_i32(0);
1791
1792                     tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1793                     tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1794                     tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1795
1796                     tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1797                     tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1798
1799                     tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1800                             cpu_R[RRR_S], tmp1);
1801                     tcg_temp_free(tmp1);
1802                     tcg_temp_free(tmp2);
1803                     tcg_temp_free(zero);
1804                 }
1805                 break;
1806
1807             case 4: /*MINu*/
1808             case 5: /*MAXu*/
1809             case 6: /*MINUu*/
1810             case 7: /*MAXUu*/
1811                 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1812                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1813                     static const TCGCond cond[] = {
1814                         TCG_COND_LE,
1815                         TCG_COND_GE,
1816                         TCG_COND_LEU,
1817                         TCG_COND_GEU
1818                     };
1819                     tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1820                             cpu_R[RRR_S], cpu_R[RRR_T],
1821                             cpu_R[RRR_S], cpu_R[RRR_T]);
1822                 }
1823                 break;
1824
1825             case 8: /*MOVEQZ*/
1826             case 9: /*MOVNEZ*/
1827             case 10: /*MOVLTZ*/
1828             case 11: /*MOVGEZ*/
1829                 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1830                     static const TCGCond cond[] = {
1831                         TCG_COND_EQ,
1832                         TCG_COND_NE,
1833                         TCG_COND_LT,
1834                         TCG_COND_GE,
1835                     };
1836                     TCGv_i32 zero = tcg_const_i32(0);
1837
1838                     tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1839                             cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1840                     tcg_temp_free(zero);
1841                 }
1842                 break;
1843
1844             case 12: /*MOVFp*/
1845             case 13: /*MOVTp*/
1846                 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1847                 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1848                     TCGv_i32 zero = tcg_const_i32(0);
1849                     TCGv_i32 tmp = tcg_temp_new_i32();
1850
1851                     tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1852                     tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1853                             cpu_R[RRR_R], tmp, zero,
1854                             cpu_R[RRR_S], cpu_R[RRR_R]);
1855
1856                     tcg_temp_free(tmp);
1857                     tcg_temp_free(zero);
1858                 }
1859                 break;
1860
1861             case 14: /*RUR*/
1862                 if (gen_window_check1(dc, RRR_R)) {
1863                     int st = (RRR_S << 4) + RRR_T;
1864                     if (uregnames[st].name) {
1865                         tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1866                     } else {
1867                         qemu_log("RUR %d not implemented, ", st);
1868                         TBD();
1869                     }
1870                 }
1871                 break;
1872
1873             case 15: /*WUR*/
1874                 if (gen_window_check1(dc, RRR_T)) {
1875                     if (uregnames[RSR_SR].name) {
1876                         gen_wur(RSR_SR, cpu_R[RRR_T]);
1877                     } else {
1878                         qemu_log("WUR %d not implemented, ", RSR_SR);
1879                         TBD();
1880                     }
1881                 }
1882                 break;
1883
1884             }
1885             break;
1886
1887         case 4: /*EXTUI*/
1888         case 5:
1889             if (gen_window_check2(dc, RRR_R, RRR_T)) {
1890                 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1891                 int maskimm = (1 << (OP2 + 1)) - 1;
1892
1893                 TCGv_i32 tmp = tcg_temp_new_i32();
1894                 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1895                 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1896                 tcg_temp_free(tmp);
1897             }
1898             break;
1899
1900         case 6: /*CUST0*/
1901             RESERVED();
1902             break;
1903
1904         case 7: /*CUST1*/
1905             RESERVED();
1906             break;
1907
1908         case 8: /*LSCXp*/
1909             switch (OP2) {
1910             case 0: /*LSXf*/
1911             case 1: /*LSXUf*/
1912             case 4: /*SSXf*/
1913             case 5: /*SSXUf*/
1914                 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1915                 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1916                     gen_check_cpenable(dc, 0)) {
1917                     TCGv_i32 addr = tcg_temp_new_i32();
1918                     tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1919                     gen_load_store_alignment(dc, 2, addr, false);
1920                     if (OP2 & 0x4) {
1921                         tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1922                     } else {
1923                         tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1924                     }
1925                     if (OP2 & 0x1) {
1926                         tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1927                     }
1928                     tcg_temp_free(addr);
1929                 }
1930                 break;
1931
1932             default: /*reserved*/
1933                 RESERVED();
1934                 break;
1935             }
1936             break;
1937
1938         case 9: /*LSC4*/
1939             if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1940                 break;
1941             }
1942             switch (OP2) {
1943             case 0: /*L32E*/
1944                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1945                 if (gen_check_privilege(dc)) {
1946                     TCGv_i32 addr = tcg_temp_new_i32();
1947                     tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1948                             (0xffffffc0 | (RRR_R << 2)));
1949                     tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1950                     tcg_temp_free(addr);
1951                 }
1952                 break;
1953
1954             case 4: /*S32E*/
1955                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1956                 if (gen_check_privilege(dc)) {
1957                     TCGv_i32 addr = tcg_temp_new_i32();
1958                     tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1959                             (0xffffffc0 | (RRR_R << 2)));
1960                     tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1961                     tcg_temp_free(addr);
1962                 }
1963                 break;
1964
1965             default:
1966                 RESERVED();
1967                 break;
1968             }
1969             break;
1970
1971         case 10: /*FP0*/
1972             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1973             switch (OP2) {
1974             case 0: /*ADD.Sf*/
1975                 if (gen_check_cpenable(dc, 0)) {
1976                     gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1977                                      cpu_FR[RRR_S], cpu_FR[RRR_T]);
1978                 }
1979                 break;
1980
1981             case 1: /*SUB.Sf*/
1982                 if (gen_check_cpenable(dc, 0)) {
1983                     gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1984                                      cpu_FR[RRR_S], cpu_FR[RRR_T]);
1985                 }
1986                 break;
1987
1988             case 2: /*MUL.Sf*/
1989                 if (gen_check_cpenable(dc, 0)) {
1990                     gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1991                                      cpu_FR[RRR_S], cpu_FR[RRR_T]);
1992                 }
1993                 break;
1994
1995             case 4: /*MADD.Sf*/
1996                 if (gen_check_cpenable(dc, 0)) {
1997                     gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1998                                       cpu_FR[RRR_R], cpu_FR[RRR_S],
1999                                       cpu_FR[RRR_T]);
2000                 }
2001                 break;
2002
2003             case 5: /*MSUB.Sf*/
2004                 if (gen_check_cpenable(dc, 0)) {
2005                     gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2006                                       cpu_FR[RRR_R], cpu_FR[RRR_S],
2007                                       cpu_FR[RRR_T]);
2008                 }
2009                 break;
2010
2011             case 8: /*ROUND.Sf*/
2012             case 9: /*TRUNC.Sf*/
2013             case 10: /*FLOOR.Sf*/
2014             case 11: /*CEIL.Sf*/
2015             case 14: /*UTRUNC.Sf*/
2016                 if (gen_window_check1(dc, RRR_R) &&
2017                     gen_check_cpenable(dc, 0)) {
2018                     static const unsigned rounding_mode_const[] = {
2019                         float_round_nearest_even,
2020                         float_round_to_zero,
2021                         float_round_down,
2022                         float_round_up,
2023                         [6] = float_round_to_zero,
2024                     };
2025                     TCGv_i32 rounding_mode = tcg_const_i32(
2026                             rounding_mode_const[OP2 & 7]);
2027                     TCGv_i32 scale = tcg_const_i32(RRR_T);
2028
2029                     if (OP2 == 14) {
2030                         gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2031                                 rounding_mode, scale);
2032                     } else {
2033                         gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2034                                 rounding_mode, scale);
2035                     }
2036
2037                     tcg_temp_free(rounding_mode);
2038                     tcg_temp_free(scale);
2039                 }
2040                 break;
2041
2042             case 12: /*FLOAT.Sf*/
2043             case 13: /*UFLOAT.Sf*/
2044                 if (gen_window_check1(dc, RRR_S) &&
2045                     gen_check_cpenable(dc, 0)) {
2046                     TCGv_i32 scale = tcg_const_i32(-RRR_T);
2047
2048                     if (OP2 == 13) {
2049                         gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2050                                 cpu_R[RRR_S], scale);
2051                     } else {
2052                         gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2053                                 cpu_R[RRR_S], scale);
2054                     }
2055                     tcg_temp_free(scale);
2056                 }
2057                 break;
2058
2059             case 15: /*FP1OP*/
2060                 switch (RRR_T) {
2061                 case 0: /*MOV.Sf*/
2062                     if (gen_check_cpenable(dc, 0)) {
2063                         tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2064                     }
2065                     break;
2066
2067                 case 1: /*ABS.Sf*/
2068                     if (gen_check_cpenable(dc, 0)) {
2069                         gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2070                     }
2071                     break;
2072
2073                 case 4: /*RFRf*/
2074                     if (gen_window_check1(dc, RRR_R) &&
2075                         gen_check_cpenable(dc, 0)) {
2076                         tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2077                     }
2078                     break;
2079
2080                 case 5: /*WFRf*/
2081                     if (gen_window_check1(dc, RRR_S) &&
2082                         gen_check_cpenable(dc, 0)) {
2083                         tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2084                     }
2085                     break;
2086
2087                 case 6: /*NEG.Sf*/
2088                     if (gen_check_cpenable(dc, 0)) {
2089                         gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2090                     }
2091                     break;
2092
2093                 default: /*reserved*/
2094                     RESERVED();
2095                     break;
2096                 }
2097                 break;
2098
2099             default: /*reserved*/
2100                 RESERVED();
2101                 break;
2102             }
2103             break;
2104
2105         case 11: /*FP1*/
2106             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2107
2108 #define gen_compare(rel, br, a, b) \
2109     do { \
2110         if (gen_check_cpenable(dc, 0)) { \
2111             TCGv_i32 bit = tcg_const_i32(1 << br); \
2112             \
2113             gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2114             tcg_temp_free(bit); \
2115         } \
2116     } while (0)
2117
2118             switch (OP2) {
2119             case 1: /*UN.Sf*/
2120                 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2121                 break;
2122
2123             case 2: /*OEQ.Sf*/
2124                 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2125                 break;
2126
2127             case 3: /*UEQ.Sf*/
2128                 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2129                 break;
2130
2131             case 4: /*OLT.Sf*/
2132                 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2133                 break;
2134
2135             case 5: /*ULT.Sf*/
2136                 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2137                 break;
2138
2139             case 6: /*OLE.Sf*/
2140                 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2141                 break;
2142
2143             case 7: /*ULE.Sf*/
2144                 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2145                 break;
2146
2147 #undef gen_compare
2148
2149             case 8: /*MOVEQZ.Sf*/
2150             case 9: /*MOVNEZ.Sf*/
2151             case 10: /*MOVLTZ.Sf*/
2152             case 11: /*MOVGEZ.Sf*/
2153                 if (gen_window_check1(dc, RRR_T) &&
2154                     gen_check_cpenable(dc, 0)) {
2155                     static const TCGCond cond[] = {
2156                         TCG_COND_EQ,
2157                         TCG_COND_NE,
2158                         TCG_COND_LT,
2159                         TCG_COND_GE,
2160                     };
2161                     TCGv_i32 zero = tcg_const_i32(0);
2162
2163                     tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2164                             cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2165                     tcg_temp_free(zero);
2166                 }
2167                 break;
2168
2169             case 12: /*MOVF.Sf*/
2170             case 13: /*MOVT.Sf*/
2171                 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2172                 if (gen_check_cpenable(dc, 0)) {
2173                     TCGv_i32 zero = tcg_const_i32(0);
2174                     TCGv_i32 tmp = tcg_temp_new_i32();
2175
2176                     tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2177                     tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2178                             cpu_FR[RRR_R], tmp, zero,
2179                             cpu_FR[RRR_S], cpu_FR[RRR_R]);
2180
2181                     tcg_temp_free(tmp);
2182                     tcg_temp_free(zero);
2183                 }
2184                 break;
2185
2186             default: /*reserved*/
2187                 RESERVED();
2188                 break;
2189             }
2190             break;
2191
2192         default: /*reserved*/
2193             RESERVED();
2194             break;
2195         }
2196         break;
2197
2198     case 1: /*L32R*/
2199         if (gen_window_check1(dc, RRR_T)) {
2200             TCGv_i32 tmp = tcg_const_i32(
2201                     ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2202                      0 : ((dc->pc + 3) & ~3)) +
2203                     (0xfffc0000 | (RI16_IMM16 << 2)));
2204
2205             if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2206                 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2207             }
2208             tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2209             tcg_temp_free(tmp);
2210         }
2211         break;
2212
2213     case 2: /*LSAI*/
2214 #define gen_load_store(type, shift) do { \
2215             if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2216                 TCGv_i32 addr = tcg_temp_new_i32(); \
2217                 \
2218                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2219                 if (shift) { \
2220                     gen_load_store_alignment(dc, shift, addr, false); \
2221                 } \
2222                 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2223                 tcg_temp_free(addr); \
2224             } \
2225         } while (0)
2226
2227         switch (RRI8_R) {
2228         case 0: /*L8UI*/
2229             gen_load_store(ld8u, 0);
2230             break;
2231
2232         case 1: /*L16UI*/
2233             gen_load_store(ld16u, 1);
2234             break;
2235
2236         case 2: /*L32I*/
2237             gen_load_store(ld32u, 2);
2238             break;
2239
2240         case 4: /*S8I*/
2241             gen_load_store(st8, 0);
2242             break;
2243
2244         case 5: /*S16I*/
2245             gen_load_store(st16, 1);
2246             break;
2247
2248         case 6: /*S32I*/
2249             gen_load_store(st32, 2);
2250             break;
2251
2252 #define gen_dcache_hit_test(w, shift) do { \
2253             if (gen_window_check1(dc, RRI##w##_S)) { \
2254                 TCGv_i32 addr = tcg_temp_new_i32(); \
2255                 TCGv_i32 res = tcg_temp_new_i32(); \
2256                 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2257                                  RRI##w##_IMM##w << shift); \
2258                 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2259                 tcg_temp_free(addr); \
2260                 tcg_temp_free(res); \
2261             } \
2262         } while (0)
2263
2264 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2265 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2266
2267         case 7: /*CACHEc*/
2268             if (RRI8_T < 8) {
2269                 HAS_OPTION(XTENSA_OPTION_DCACHE);
2270             }
2271
2272             switch (RRI8_T) {
2273             case 0: /*DPFRc*/
2274                 gen_window_check1(dc, RRI8_S);
2275                 break;
2276
2277             case 1: /*DPFWc*/
2278                 gen_window_check1(dc, RRI8_S);
2279                 break;
2280
2281             case 2: /*DPFROc*/
2282                 gen_window_check1(dc, RRI8_S);
2283                 break;
2284
2285             case 3: /*DPFWOc*/
2286                 gen_window_check1(dc, RRI8_S);
2287                 break;
2288
2289             case 4: /*DHWBc*/
2290                 gen_dcache_hit_test8();
2291                 break;
2292
2293             case 5: /*DHWBIc*/
2294                 gen_dcache_hit_test8();
2295                 break;
2296
2297             case 6: /*DHIc*/
2298                 if (gen_check_privilege(dc)) {
2299                     gen_dcache_hit_test8();
2300                 }
2301                 break;
2302
2303             case 7: /*DIIc*/
2304                 if (gen_check_privilege(dc)) {
2305                     gen_window_check1(dc, RRI8_S);
2306                 }
2307                 break;
2308
2309             case 8: /*DCEc*/
2310                 switch (OP1) {
2311                 case 0: /*DPFLl*/
2312                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2313                     if (gen_check_privilege(dc)) {
2314                         gen_dcache_hit_test4();
2315                     }
2316                     break;
2317
2318                 case 2: /*DHUl*/
2319                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2320                     if (gen_check_privilege(dc)) {
2321                         gen_dcache_hit_test4();
2322                     }
2323                     break;
2324
2325                 case 3: /*DIUl*/
2326                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2327                     if (gen_check_privilege(dc)) {
2328                         gen_window_check1(dc, RRI4_S);
2329                     }
2330                     break;
2331
2332                 case 4: /*DIWBc*/
2333                     HAS_OPTION(XTENSA_OPTION_DCACHE);
2334                     if (gen_check_privilege(dc)) {
2335                         gen_window_check1(dc, RRI4_S);
2336                     }
2337                     break;
2338
2339                 case 5: /*DIWBIc*/
2340                     HAS_OPTION(XTENSA_OPTION_DCACHE);
2341                     if (gen_check_privilege(dc)) {
2342                         gen_window_check1(dc, RRI4_S);
2343                     }
2344                     break;
2345
2346                 default: /*reserved*/
2347                     RESERVED();
2348                     break;
2349
2350                 }
2351                 break;
2352
2353 #undef gen_dcache_hit_test
2354 #undef gen_dcache_hit_test4
2355 #undef gen_dcache_hit_test8
2356
2357 #define gen_icache_hit_test(w, shift) do { \
2358             if (gen_window_check1(dc, RRI##w##_S)) { \
2359                 TCGv_i32 addr = tcg_temp_new_i32(); \
2360                 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2361                 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2362                                  RRI##w##_IMM##w << shift); \
2363                 gen_helper_itlb_hit_test(cpu_env, addr); \
2364                 tcg_temp_free(addr); \
2365             }\
2366         } while (0)
2367
2368 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2369 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2370
2371             case 12: /*IPFc*/
2372                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2373                 gen_window_check1(dc, RRI8_S);
2374                 break;
2375
2376             case 13: /*ICEc*/
2377                 switch (OP1) {
2378                 case 0: /*IPFLl*/
2379                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2380                     if (gen_check_privilege(dc)) {
2381                         gen_icache_hit_test4();
2382                     }
2383                     break;
2384
2385                 case 2: /*IHUl*/
2386                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2387                     if (gen_check_privilege(dc)) {
2388                         gen_icache_hit_test4();
2389                     }
2390                     break;
2391
2392                 case 3: /*IIUl*/
2393                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2394                     if (gen_check_privilege(dc)) {
2395                         gen_window_check1(dc, RRI4_S);
2396                     }
2397                     break;
2398
2399                 default: /*reserved*/
2400                     RESERVED();
2401                     break;
2402                 }
2403                 break;
2404
2405             case 14: /*IHIc*/
2406                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2407                 gen_icache_hit_test8();
2408                 break;
2409
2410             case 15: /*IIIc*/
2411                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2412                 if (gen_check_privilege(dc)) {
2413                     gen_window_check1(dc, RRI8_S);
2414                 }
2415                 break;
2416
2417             default: /*reserved*/
2418                 RESERVED();
2419                 break;
2420             }
2421             break;
2422
2423 #undef gen_icache_hit_test
2424 #undef gen_icache_hit_test4
2425 #undef gen_icache_hit_test8
2426
2427         case 9: /*L16SI*/
2428             gen_load_store(ld16s, 1);
2429             break;
2430 #undef gen_load_store
2431
2432         case 10: /*MOVI*/
2433             if (gen_window_check1(dc, RRI8_T)) {
2434                 tcg_gen_movi_i32(cpu_R[RRI8_T],
2435                                  RRI8_IMM8 | (RRI8_S << 8) |
2436                                  ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2437             }
2438             break;
2439
2440 #define gen_load_store_no_hw_align(type) do { \
2441             if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2442                 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2443                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2444                 gen_load_store_alignment(dc, 2, addr, true); \
2445                 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2446                 tcg_temp_free(addr); \
2447             } \
2448         } while (0)
2449
2450         case 11: /*L32AIy*/
2451             HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2452             gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2453             break;
2454
2455         case 12: /*ADDI*/
2456             if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2457                 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2458             }
2459             break;
2460
2461         case 13: /*ADDMI*/
2462             if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2463                 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2464                                  RRI8_IMM8_SE << 8);
2465             }
2466             break;
2467
2468         case 14: /*S32C1Iy*/
2469             HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2470             if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2471                 int label = gen_new_label();
2472                 TCGv_i32 tmp = tcg_temp_local_new_i32();
2473                 TCGv_i32 addr = tcg_temp_local_new_i32();
2474                 TCGv_i32 tpc;
2475
2476                 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2477                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2478                 gen_load_store_alignment(dc, 2, addr, true);
2479
2480                 gen_advance_ccount(dc);
2481                 tpc = tcg_const_i32(dc->pc);
2482                 gen_helper_check_atomctl(cpu_env, tpc, addr);
2483                 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2484                 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2485                         cpu_SR[SCOMPARE1], label);
2486
2487                 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2488
2489                 gen_set_label(label);
2490                 tcg_temp_free(tpc);
2491                 tcg_temp_free(addr);
2492                 tcg_temp_free(tmp);
2493             }
2494             break;
2495
2496         case 15: /*S32RIy*/
2497             HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2498             gen_load_store_no_hw_align(st32); /*TODO release?*/
2499             break;
2500 #undef gen_load_store_no_hw_align
2501
2502         default: /*reserved*/
2503             RESERVED();
2504             break;
2505         }
2506         break;
2507
2508     case 3: /*LSCIp*/
2509         switch (RRI8_R) {
2510         case 0: /*LSIf*/
2511         case 4: /*SSIf*/
2512         case 8: /*LSIUf*/
2513         case 12: /*SSIUf*/
2514             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2515             if (gen_window_check1(dc, RRI8_S) &&
2516                 gen_check_cpenable(dc, 0)) {
2517                 TCGv_i32 addr = tcg_temp_new_i32();
2518                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2519                 gen_load_store_alignment(dc, 2, addr, false);
2520                 if (RRI8_R & 0x4) {
2521                     tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2522                 } else {
2523                     tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2524                 }
2525                 if (RRI8_R & 0x8) {
2526                     tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2527                 }
2528                 tcg_temp_free(addr);
2529             }
2530             break;
2531
2532         default: /*reserved*/
2533             RESERVED();
2534             break;
2535         }
2536         break;
2537
2538     case 4: /*MAC16d*/
2539         HAS_OPTION(XTENSA_OPTION_MAC16);
2540         {
2541             enum {
2542                 MAC16_UMUL = 0x0,
2543                 MAC16_MUL  = 0x4,
2544                 MAC16_MULA = 0x8,
2545                 MAC16_MULS = 0xc,
2546                 MAC16_NONE = 0xf,
2547             } op = OP1 & 0xc;
2548             bool is_m1_sr = (OP2 & 0x3) == 2;
2549             bool is_m2_sr = (OP2 & 0xc) == 0;
2550             uint32_t ld_offset = 0;
2551
2552             if (OP2 > 9) {
2553                 RESERVED();
2554             }
2555
2556             switch (OP2 & 2) {
2557             case 0: /*MACI?/MACC?*/
2558                 is_m1_sr = true;
2559                 ld_offset = (OP2 & 1) ? -4 : 4;
2560
2561                 if (OP2 >= 8) { /*MACI/MACC*/
2562                     if (OP1 == 0) { /*LDINC/LDDEC*/
2563                         op = MAC16_NONE;
2564                     } else {
2565                         RESERVED();
2566                     }
2567                 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2568                     RESERVED();
2569                 }
2570                 break;
2571
2572             case 2: /*MACD?/MACA?*/
2573                 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2574                     RESERVED();
2575                 }
2576                 break;
2577             }
2578
2579             if (op != MAC16_NONE) {
2580                 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2581                     break;
2582                 }
2583                 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2584                     break;
2585                 }
2586             }
2587
2588             if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2589                 break;
2590             }
2591
2592             {
2593                 TCGv_i32 vaddr = tcg_temp_new_i32();
2594                 TCGv_i32 mem32 = tcg_temp_new_i32();
2595
2596                 if (ld_offset) {
2597                     tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2598                     gen_load_store_alignment(dc, 2, vaddr, false);
2599                     tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2600                 }
2601                 if (op != MAC16_NONE) {
2602                     TCGv_i32 m1 = gen_mac16_m(
2603                             is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2604                             OP1 & 1, op == MAC16_UMUL);
2605                     TCGv_i32 m2 = gen_mac16_m(
2606                             is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2607                             OP1 & 2, op == MAC16_UMUL);
2608
2609                     if (op == MAC16_MUL || op == MAC16_UMUL) {
2610                         tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2611                         if (op == MAC16_UMUL) {
2612                             tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2613                         } else {
2614                             tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2615                         }
2616                     } else {
2617                         TCGv_i32 lo = tcg_temp_new_i32();
2618                         TCGv_i32 hi = tcg_temp_new_i32();
2619
2620                         tcg_gen_mul_i32(lo, m1, m2);
2621                         tcg_gen_sari_i32(hi, lo, 31);
2622                         if (op == MAC16_MULA) {
2623                             tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2624                                              cpu_SR[ACCLO], cpu_SR[ACCHI],
2625                                              lo, hi);
2626                         } else {
2627                             tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2628                                              cpu_SR[ACCLO], cpu_SR[ACCHI],
2629                                              lo, hi);
2630                         }
2631                         tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2632
2633                         tcg_temp_free_i32(lo);
2634                         tcg_temp_free_i32(hi);
2635                     }
2636                     tcg_temp_free(m1);
2637                     tcg_temp_free(m2);
2638                 }
2639                 if (ld_offset) {
2640                     tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2641                     tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2642                 }
2643                 tcg_temp_free(vaddr);
2644                 tcg_temp_free(mem32);
2645             }
2646         }
2647         break;
2648
2649     case 5: /*CALLN*/
2650         switch (CALL_N) {
2651         case 0: /*CALL0*/
2652             tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2653             gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2654             break;
2655
2656         case 1: /*CALL4w*/
2657         case 2: /*CALL8w*/
2658         case 3: /*CALL12w*/
2659             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2660             if (gen_window_check1(dc, CALL_N << 2)) {
2661                 gen_callwi(dc, CALL_N,
2662                            (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2663             }
2664             break;
2665         }
2666         break;
2667
2668     case 6: /*SI*/
2669         switch (CALL_N) {
2670         case 0: /*J*/
2671             gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2672             break;
2673
2674         case 1: /*BZ*/
2675             if (gen_window_check1(dc, BRI12_S)) {
2676                 static const TCGCond cond[] = {
2677                     TCG_COND_EQ, /*BEQZ*/
2678                     TCG_COND_NE, /*BNEZ*/
2679                     TCG_COND_LT, /*BLTZ*/
2680                     TCG_COND_GE, /*BGEZ*/
2681                 };
2682
2683                 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2684                         4 + BRI12_IMM12_SE);
2685             }
2686             break;
2687
2688         case 2: /*BI0*/
2689             if (gen_window_check1(dc, BRI8_S)) {
2690                 static const TCGCond cond[] = {
2691                     TCG_COND_EQ, /*BEQI*/
2692                     TCG_COND_NE, /*BNEI*/
2693                     TCG_COND_LT, /*BLTI*/
2694                     TCG_COND_GE, /*BGEI*/
2695                 };
2696
2697                 gen_brcondi(dc, cond[BRI8_M & 3],
2698                         cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2699             }
2700             break;
2701
2702         case 3: /*BI1*/
2703             switch (BRI8_M) {
2704             case 0: /*ENTRYw*/
2705                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2706                 {
2707                     TCGv_i32 pc = tcg_const_i32(dc->pc);
2708                     TCGv_i32 s = tcg_const_i32(BRI12_S);
2709                     TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2710                     gen_advance_ccount(dc);
2711                     gen_helper_entry(cpu_env, pc, s, imm);
2712                     tcg_temp_free(imm);
2713                     tcg_temp_free(s);
2714                     tcg_temp_free(pc);
2715                     /* This can change tb->flags, so exit tb */
2716                     gen_jumpi_check_loop_end(dc, -1);
2717                 }
2718                 break;
2719
2720             case 1: /*B1*/
2721                 switch (BRI8_R) {
2722                 case 0: /*BFp*/
2723                 case 1: /*BTp*/
2724                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2725                     {
2726                         TCGv_i32 tmp = tcg_temp_new_i32();
2727                         tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2728                         gen_brcondi(dc,
2729                                 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2730                                 tmp, 0, 4 + RRI8_IMM8_SE);
2731                         tcg_temp_free(tmp);
2732                     }
2733                     break;
2734
2735                 case 8: /*LOOP*/
2736                 case 9: /*LOOPNEZ*/
2737                 case 10: /*LOOPGTZ*/
2738                     HAS_OPTION(XTENSA_OPTION_LOOP);
2739                     if (gen_window_check1(dc, RRI8_S)) {
2740                         uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2741                         TCGv_i32 tmp = tcg_const_i32(lend);
2742
2743                         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2744                         tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2745                         gen_helper_wsr_lend(cpu_env, tmp);
2746                         tcg_temp_free(tmp);
2747
2748                         if (BRI8_R > 8) {
2749                             int label = gen_new_label();
2750                             tcg_gen_brcondi_i32(
2751                                     BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2752                                     cpu_R[RRI8_S], 0, label);
2753                             gen_jumpi(dc, lend, 1);
2754                             gen_set_label(label);
2755                         }
2756
2757                         gen_jumpi(dc, dc->next_pc, 0);
2758                     }
2759                     break;
2760
2761                 default: /*reserved*/
2762                     RESERVED();
2763                     break;
2764
2765                 }
2766                 break;
2767
2768             case 2: /*BLTUI*/
2769             case 3: /*BGEUI*/
2770                 if (gen_window_check1(dc, BRI8_S)) {
2771                     gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2772                                 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2773                                 4 + BRI8_IMM8_SE);
2774                 }
2775                 break;
2776             }
2777             break;
2778
2779         }
2780         break;
2781
2782     case 7: /*B*/
2783         {
2784             TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2785
2786             switch (RRI8_R & 7) {
2787             case 0: /*BNONE*/ /*BANY*/
2788                 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2789                     TCGv_i32 tmp = tcg_temp_new_i32();
2790                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2791                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2792                     tcg_temp_free(tmp);
2793                 }
2794                 break;
2795
2796             case 1: /*BEQ*/ /*BNE*/
2797             case 2: /*BLT*/ /*BGE*/
2798             case 3: /*BLTU*/ /*BGEU*/
2799                 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2800                     static const TCGCond cond[] = {
2801                         [1] = TCG_COND_EQ,
2802                         [2] = TCG_COND_LT,
2803                         [3] = TCG_COND_LTU,
2804                         [9] = TCG_COND_NE,
2805                         [10] = TCG_COND_GE,
2806                         [11] = TCG_COND_GEU,
2807                     };
2808                     gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2809                             4 + RRI8_IMM8_SE);
2810                 }
2811                 break;
2812
2813             case 4: /*BALL*/ /*BNALL*/
2814                 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2815                     TCGv_i32 tmp = tcg_temp_new_i32();
2816                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2817                     gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2818                             4 + RRI8_IMM8_SE);
2819                     tcg_temp_free(tmp);
2820                 }
2821                 break;
2822
2823             case 5: /*BBC*/ /*BBS*/
2824                 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2825 #ifdef TARGET_WORDS_BIGENDIAN
2826                     TCGv_i32 bit = tcg_const_i32(0x80000000);
2827 #else
2828                     TCGv_i32 bit = tcg_const_i32(0x00000001);
2829 #endif
2830                     TCGv_i32 tmp = tcg_temp_new_i32();
2831                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2832 #ifdef TARGET_WORDS_BIGENDIAN
2833                     tcg_gen_shr_i32(bit, bit, tmp);
2834 #else
2835                     tcg_gen_shl_i32(bit, bit, tmp);
2836 #endif
2837                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2838                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2839                     tcg_temp_free(tmp);
2840                     tcg_temp_free(bit);
2841                 }
2842                 break;
2843
2844             case 6: /*BBCI*/ /*BBSI*/
2845             case 7:
2846                 if (gen_window_check1(dc, RRI8_S)) {
2847                     TCGv_i32 tmp = tcg_temp_new_i32();
2848                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2849 #ifdef TARGET_WORDS_BIGENDIAN
2850                             0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2851 #else
2852                             0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2853 #endif
2854                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2855                     tcg_temp_free(tmp);
2856                 }
2857                 break;
2858
2859             }
2860         }
2861         break;
2862
2863 #define gen_narrow_load_store(type) do { \
2864             if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2865                 TCGv_i32 addr = tcg_temp_new_i32(); \
2866                 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2867                 gen_load_store_alignment(dc, 2, addr, false); \
2868                 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2869                 tcg_temp_free(addr); \
2870             } \
2871         } while (0)
2872
2873     case 8: /*L32I.Nn*/
2874         gen_narrow_load_store(ld32u);
2875         break;
2876
2877     case 9: /*S32I.Nn*/
2878         gen_narrow_load_store(st32);
2879         break;
2880 #undef gen_narrow_load_store
2881
2882     case 10: /*ADD.Nn*/
2883         if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2884             tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2885         }
2886         break;
2887
2888     case 11: /*ADDI.Nn*/
2889         if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2890             tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2891                              RRRN_T ? RRRN_T : -1);
2892         }
2893         break;
2894
2895     case 12: /*ST2n*/
2896         if (!gen_window_check1(dc, RRRN_S)) {
2897             break;
2898         }
2899         if (RRRN_T < 8) { /*MOVI.Nn*/
2900             tcg_gen_movi_i32(cpu_R[RRRN_S],
2901                     RRRN_R | (RRRN_T << 4) |
2902                     ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2903         } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2904             TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2905
2906             gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2907                     4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2908         }
2909         break;
2910
2911     case 13: /*ST3n*/
2912         switch (RRRN_R) {
2913         case 0: /*MOV.Nn*/
2914             if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2915                 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2916             }
2917             break;
2918
2919         case 15: /*S3*/
2920             switch (RRRN_T) {
2921             case 0: /*RET.Nn*/
2922                 gen_jump(dc, cpu_R[0]);
2923                 break;
2924
2925             case 1: /*RETW.Nn*/
2926                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2927                 {
2928                     TCGv_i32 tmp = tcg_const_i32(dc->pc);
2929                     gen_advance_ccount(dc);
2930                     gen_helper_retw(tmp, cpu_env, tmp);
2931                     gen_jump(dc, tmp);
2932                     tcg_temp_free(tmp);
2933                 }
2934                 break;
2935
2936             case 2: /*BREAK.Nn*/
2937                 HAS_OPTION(XTENSA_OPTION_DEBUG);
2938                 if (dc->debug) {
2939                     gen_debug_exception(dc, DEBUGCAUSE_BN);
2940                 }
2941                 break;
2942
2943             case 3: /*NOP.Nn*/
2944                 break;
2945
2946             case 6: /*ILL.Nn*/
2947                 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2948                 break;
2949
2950             default: /*reserved*/
2951                 RESERVED();
2952                 break;
2953             }
2954             break;
2955
2956         default: /*reserved*/
2957             RESERVED();
2958             break;
2959         }
2960         break;
2961
2962     default: /*reserved*/
2963         RESERVED();
2964         break;
2965     }
2966
2967     if (dc->is_jmp == DISAS_NEXT) {
2968         gen_check_loop_end(dc, 0);
2969     }
2970     dc->pc = dc->next_pc;
2971
2972     return;
2973
2974 invalid_opcode:
2975     qemu_log("INVALID(pc = %08x)\n", dc->pc);
2976     gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2977 #undef HAS_OPTION
2978 }
2979
2980 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
2981 {
2982     uint8_t b0 = cpu_ldub_code(env, dc->pc);
2983     return xtensa_op0_insn_len(OP0);
2984 }
2985
2986 static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2987 {
2988     CPUState *cs = CPU(xtensa_env_get_cpu(env));
2989     CPUBreakpoint *bp;
2990
2991     if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
2992         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
2993             if (bp->pc == dc->pc) {
2994                 tcg_gen_movi_i32(cpu_pc, dc->pc);
2995                 gen_exception(dc, EXCP_DEBUG);
2996                 dc->is_jmp = DISAS_UPDATE;
2997              }
2998         }
2999     }
3000 }
3001
3002 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
3003 {
3004     unsigned i;
3005
3006     for (i = 0; i < dc->config->nibreak; ++i) {
3007         if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3008                 env->sregs[IBREAKA + i] == dc->pc) {
3009             gen_debug_exception(dc, DEBUGCAUSE_IB);
3010             break;
3011         }
3012     }
3013 }
3014
3015 static inline
3016 void gen_intermediate_code_internal(XtensaCPU *cpu,
3017                                     TranslationBlock *tb, bool search_pc)
3018 {
3019     CPUState *cs = CPU(cpu);
3020     CPUXtensaState *env = &cpu->env;
3021     DisasContext dc;
3022     int insn_count = 0;
3023     int j, lj = -1;
3024     uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3025     int max_insns = tb->cflags & CF_COUNT_MASK;
3026     uint32_t pc_start = tb->pc;
3027     uint32_t next_page_start =
3028         (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3029
3030     if (max_insns == 0) {
3031         max_insns = CF_COUNT_MASK;
3032     }
3033
3034     dc.config = env->config;
3035     dc.singlestep_enabled = cs->singlestep_enabled;
3036     dc.tb = tb;
3037     dc.pc = pc_start;
3038     dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3039     dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3040     dc.lbeg = env->sregs[LBEG];
3041     dc.lend = env->sregs[LEND];
3042     dc.is_jmp = DISAS_NEXT;
3043     dc.ccount_delta = 0;
3044     dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3045     dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3046     dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3047         XTENSA_TBFLAG_CPENABLE_SHIFT;
3048     dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3049                  XTENSA_TBFLAG_WINDOW_SHIFT);
3050
3051     init_litbase(&dc);
3052     init_sar_tracker(&dc);
3053     if (dc.icount) {
3054         dc.next_icount = tcg_temp_local_new_i32();
3055     }
3056
3057     gen_tb_start();
3058
3059     if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3060         tcg_gen_movi_i32(cpu_pc, dc.pc);
3061         gen_exception(&dc, EXCP_DEBUG);
3062     }
3063
3064     do {
3065         check_breakpoint(env, &dc);
3066
3067         if (search_pc) {
3068             j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3069             if (lj < j) {
3070                 lj++;
3071                 while (lj < j) {
3072                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
3073                 }
3074             }
3075             tcg_ctx.gen_opc_pc[lj] = dc.pc;
3076             tcg_ctx.gen_opc_instr_start[lj] = 1;
3077             tcg_ctx.gen_opc_icount[lj] = insn_count;
3078         }
3079
3080         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3081             tcg_gen_debug_insn_start(dc.pc);
3082         }
3083
3084         ++dc.ccount_delta;
3085
3086         if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3087             gen_io_start();
3088         }
3089
3090         if (dc.icount) {
3091             int label = gen_new_label();
3092
3093             tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3094             tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3095             tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3096             if (dc.debug) {
3097                 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3098             }
3099             gen_set_label(label);
3100         }
3101
3102         if (dc.debug) {
3103             gen_ibreak_check(env, &dc);
3104         }
3105
3106         disas_xtensa_insn(env, &dc);
3107         ++insn_count;
3108         if (dc.icount) {
3109             tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3110         }
3111         if (cs->singlestep_enabled) {
3112             tcg_gen_movi_i32(cpu_pc, dc.pc);
3113             gen_exception(&dc, EXCP_DEBUG);
3114             break;
3115         }
3116     } while (dc.is_jmp == DISAS_NEXT &&
3117             insn_count < max_insns &&
3118             dc.pc < next_page_start &&
3119             dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3120             tcg_ctx.gen_opc_ptr < gen_opc_end);
3121
3122     reset_litbase(&dc);
3123     reset_sar_tracker(&dc);
3124     if (dc.icount) {
3125         tcg_temp_free(dc.next_icount);
3126     }
3127
3128     if (tb->cflags & CF_LAST_IO) {
3129         gen_io_end();
3130     }
3131
3132     if (dc.is_jmp == DISAS_NEXT) {
3133         gen_jumpi(&dc, dc.pc, 0);
3134     }
3135     gen_tb_end(tb, insn_count);
3136     *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3137
3138 #ifdef DEBUG_DISAS
3139     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3140         qemu_log("----------------\n");
3141         qemu_log("IN: %s\n", lookup_symbol(pc_start));
3142         log_target_disas(env, pc_start, dc.pc - pc_start, 0);
3143         qemu_log("\n");
3144     }
3145 #endif
3146     if (search_pc) {
3147         j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3148         memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
3149                 (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
3150     } else {
3151         tb->size = dc.pc - pc_start;
3152         tb->icount = insn_count;
3153     }
3154 }
3155
3156 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3157 {
3158     gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
3159 }
3160
3161 void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
3162 {
3163     gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
3164 }
3165
3166 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3167                            fprintf_function cpu_fprintf, int flags)
3168 {
3169     XtensaCPU *cpu = XTENSA_CPU(cs);
3170     CPUXtensaState *env = &cpu->env;
3171     int i, j;
3172
3173     cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3174
3175     for (i = j = 0; i < 256; ++i) {
3176         if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3177             cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3178                     (j++ % 4) == 3 ? '\n' : ' ');
3179         }
3180     }
3181
3182     cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3183
3184     for (i = j = 0; i < 256; ++i) {
3185         if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3186             cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3187                     (j++ % 4) == 3 ? '\n' : ' ');
3188         }
3189     }
3190
3191     cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3192
3193     for (i = 0; i < 16; ++i) {
3194         cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3195                 (i % 4) == 3 ? '\n' : ' ');
3196     }
3197
3198     cpu_fprintf(f, "\n");
3199
3200     for (i = 0; i < env->config->nareg; ++i) {
3201         cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3202                 (i % 4) == 3 ? '\n' : ' ');
3203     }
3204
3205     if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3206         cpu_fprintf(f, "\n");
3207
3208         for (i = 0; i < 16; ++i) {
3209             cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3210                     float32_val(env->fregs[i]),
3211                     *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3212         }
3213     }
3214 }
3215
3216 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
3217 {
3218     env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3219 }