target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "sysemu/kvm.h"
  23 #include "sysemu/cpus.h"
  24 #include "kvm_i386.h"
  25
  26 #include "qemu/error-report.h"
  27 #include "qemu/option.h"
  28 #include "qemu/config-file.h"
  29 #include "qapi/qmp/qerror.h"
  30
  31 #include "qapi-types.h"
  32 #include "qapi-visit.h"
  33 #include "qapi/visitor.h"
  34 #include "sysemu/arch_init.h"
  35
  36 #include "hw/hw.h"
  37 #if defined(CONFIG_KVM)
  38 #include <linux/kvm_para.h>
  39 #endif
  40
  41 #include "sysemu/sysemu.h"
  42 #include "hw/qdev-properties.h"
  43 #ifndef CONFIG_USER_ONLY
  44 #include "exec/address-spaces.h"
  45 #include "hw/xen/xen.h"
  46 #include "hw/i386/apic_internal.h"
  47 #endif
  48
  49
  50 /* Cache topology CPUID constants: */
  51
  52 /* CPUID Leaf 2 Descriptors */
  53
  54 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  55 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  56 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  57
  58
  59 /* CPUID Leaf 4 constants: */
  60
  61 /* EAX: */
  62 #define CPUID_4_TYPE_DCACHE  1
  63 #define CPUID_4_TYPE_ICACHE  2
  64 #define CPUID_4_TYPE_UNIFIED 3
  65
  66 #define CPUID_4_LEVEL(l)          ((l) << 5)
  67
  68 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  69 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  70
  71 /* EDX: */
  72 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  73 #define CPUID_4_INCLUSIVE       (1 << 1)
  74 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  75
  76 #define ASSOC_FULL 0xFF
  77
  78 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  79 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  80                           a ==   2 ? 0x2 : \
  81                           a ==   4 ? 0x4 : \
  82                           a ==   8 ? 0x6 : \
  83                           a ==  16 ? 0x8 : \
  84                           a ==  32 ? 0xA : \
  85                           a ==  48 ? 0xB : \
  86                           a ==  64 ? 0xC : \
  87                           a ==  96 ? 0xD : \
  88                           a == 128 ? 0xE : \
  89                           a == ASSOC_FULL ? 0xF : \
  90                           0 /* invalid value */)
  91
  92
  93 /* Definitions of the hardcoded cache entries we expose: */
  94
  95 /* L1 data cache: */
  96 #define L1D_LINE_SIZE         64
  97 #define L1D_ASSOCIATIVITY      8
  98 #define L1D_SETS              64
  99 #define L1D_PARTITIONS         1
 100 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 101 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 102 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 103 #define L1D_LINES_PER_TAG      1
 104 #define L1D_SIZE_KB_AMD       64
 105 #define L1D_ASSOCIATIVITY_AMD  2
 106
 107 /* L1 instruction cache: */
 108 #define L1I_LINE_SIZE         64
 109 #define L1I_ASSOCIATIVITY      8
 110 #define L1I_SETS              64
 111 #define L1I_PARTITIONS         1
 112 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 113 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 114 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 115 #define L1I_LINES_PER_TAG      1
 116 #define L1I_SIZE_KB_AMD       64
 117 #define L1I_ASSOCIATIVITY_AMD  2
 118
 119 /* Level 2 unified cache: */
 120 #define L2_LINE_SIZE          64
 121 #define L2_ASSOCIATIVITY      16
 122 #define L2_SETS             4096
 123 #define L2_PARTITIONS          1
 124 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 125 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 126 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 127 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 128 #define L2_LINES_PER_TAG       1
 129 #define L2_SIZE_KB_AMD       512
 130
 131 /* No L3 cache: */
 132 #define L3_SIZE_KB             0 /* disabled */
 133 #define L3_ASSOCIATIVITY       0 /* disabled */
 134 #define L3_LINES_PER_TAG       0 /* disabled */
 135 #define L3_LINE_SIZE           0 /* disabled */
 136
 137 /* TLB definitions: */
 138
 139 #define L1_DTLB_2M_ASSOC       1
 140 #define L1_DTLB_2M_ENTRIES   255
 141 #define L1_DTLB_4K_ASSOC       1
 142 #define L1_DTLB_4K_ENTRIES   255
 143
 144 #define L1_ITLB_2M_ASSOC       1
 145 #define L1_ITLB_2M_ENTRIES   255
 146 #define L1_ITLB_4K_ASSOC       1
 147 #define L1_ITLB_4K_ENTRIES   255
 148
 149 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 150 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 151 #define L2_DTLB_4K_ASSOC       4
 152 #define L2_DTLB_4K_ENTRIES   512
 153
 154 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 155 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 156 #define L2_ITLB_4K_ASSOC       4
 157 #define L2_ITLB_4K_ENTRIES   512
 158
 159
 160
 161 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 162                                      uint32_t vendor2, uint32_t vendor3)
 163 {
 164     int i;
 165     for (i = 0; i < 4; i++) {
 166         dst[i] = vendor1 >> (8 * i);
 167         dst[i + 4] = vendor2 >> (8 * i);
 168         dst[i + 8] = vendor3 >> (8 * i);
 169     }
 170     dst[CPUID_VENDOR_SZ] = '\0';
 171 }
 172
 173 /* feature flags taken from "Intel Processor Identification and the CPUID
 174  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 175  * between feature naming conventions, aliases may be added.
 176  */
 177 static const char *feature_name[] = {
 178     "fpu", "vme", "de", "pse",
 179     "tsc", "msr", "pae", "mce",
 180     "cx8", "apic", NULL, "sep",
 181     "mtrr", "pge", "mca", "cmov",
 182     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 183     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 184     "fxsr", "sse", "sse2", "ss",
 185     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 186 };
 187 static const char *ext_feature_name[] = {
 188     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 189     "ds_cpl", "vmx", "smx", "est",
 190     "tm2", "ssse3", "cid", NULL,
 191     "fma", "cx16", "xtpr", "pdcm",
 192     NULL, "pcid", "dca", "sse4.1|sse4_1",
 193     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 194     "tsc-deadline", "aes", "xsave", "osxsave",
 195     "avx", "f16c", "rdrand", "hypervisor",
 196 };
 197 /* Feature names that are already defined on feature_name[] but are set on
 198  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 199  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 200  * if and only if CPU vendor is AMD.
 201  */
 202 static const char *ext2_feature_name[] = {
 203     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 204     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 205     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 206     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 207     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 208     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 209     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 210     NULL, "lm|i64", "3dnowext", "3dnow",
 211 };
 212 static const char *ext3_feature_name[] = {
 213     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 214     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 215     "3dnowprefetch", "osvw", "ibs", "xop",
 216     "skinit", "wdt", NULL, "lwp",
 217     "fma4", "tce", NULL, "nodeid_msr",
 218     NULL, "tbm", "topoext", "perfctr_core",
 219     "perfctr_nb", NULL, NULL, NULL,
 220     NULL, NULL, NULL, NULL,
 221 };
 222
 223 static const char *ext4_feature_name[] = {
 224     NULL, NULL, "xstore", "xstore-en",
 225     NULL, NULL, "xcrypt", "xcrypt-en",
 226     "ace2", "ace2-en", "phe", "phe-en",
 227     "pmm", "pmm-en", NULL, NULL,
 228     NULL, NULL, NULL, NULL,
 229     NULL, NULL, NULL, NULL,
 230     NULL, NULL, NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232 };
 233
 234 static const char *kvm_feature_name[] = {
 235     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 236     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 237     NULL, NULL, NULL, NULL,
 238     NULL, NULL, NULL, NULL,
 239     NULL, NULL, NULL, NULL,
 240     NULL, NULL, NULL, NULL,
 241     "kvmclock-stable-bit", NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243 };
 244
 245 static const char *svm_feature_name[] = {
 246     "npt", "lbrv", "svm_lock", "nrip_save",
 247     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 248     NULL, NULL, "pause_filter", NULL,
 249     "pfthreshold", NULL, NULL, NULL,
 250     NULL, NULL, NULL, NULL,
 251     NULL, NULL, NULL, NULL,
 252     NULL, NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254 };
 255
 256 static const char *cpuid_7_0_ebx_feature_name[] = {
 257     "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
 258     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
 259     "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
 260     "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
 261 };
 262
 263 static const char *cpuid_7_0_ecx_feature_name[] = {
 264     NULL, NULL, NULL, "pku",
 265     "ospke", NULL, NULL, NULL,
 266     NULL, NULL, NULL, NULL,
 267     NULL, NULL, NULL, NULL,
 268     NULL, NULL, NULL, NULL,
 269     NULL, NULL, NULL, NULL,
 270     NULL, NULL, NULL, NULL,
 271     NULL, NULL, NULL, NULL,
 272 };
 273
 274 static const char *cpuid_apm_edx_feature_name[] = {
 275     NULL, NULL, NULL, NULL,
 276     NULL, NULL, NULL, NULL,
 277     "invtsc", NULL, NULL, NULL,
 278     NULL, NULL, NULL, NULL,
 279     NULL, NULL, NULL, NULL,
 280     NULL, NULL, NULL, NULL,
 281     NULL, NULL, NULL, NULL,
 282     NULL, NULL, NULL, NULL,
 283 };
 284
 285 static const char *cpuid_xsave_feature_name[] = {
 286     "xsaveopt", "xsavec", "xgetbv1", "xsaves",
 287     NULL, NULL, NULL, NULL,
 288     NULL, NULL, NULL, NULL,
 289     NULL, NULL, NULL, NULL,
 290     NULL, NULL, NULL, NULL,
 291     NULL, NULL, NULL, NULL,
 292     NULL, NULL, NULL, NULL,
 293     NULL, NULL, NULL, NULL,
 294 };
 295
 296 static const char *cpuid_6_feature_name[] = {
 297     NULL, NULL, "arat", NULL,
 298     NULL, NULL, NULL, NULL,
 299     NULL, NULL, NULL, NULL,
 300     NULL, NULL, NULL, NULL,
 301     NULL, NULL, NULL, NULL,
 302     NULL, NULL, NULL, NULL,
 303     NULL, NULL, NULL, NULL,
 304     NULL, NULL, NULL, NULL,
 305 };
 306
 307 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 308 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 309           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 310 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 311           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 312           CPUID_PSE36 | CPUID_FXSR)
 313 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 314 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 315           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 316           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 317           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 318
 319 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 320           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 321           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 322           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 323           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
 324           /* partly implemented:
 325           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 326           /* missing:
 327           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 328 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 329           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 330           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 331           CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */   \
 332           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 333           /* missing:
 334           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 335           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 336           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 337           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
 338           CPUID_EXT_F16C, CPUID_EXT_RDRAND */
 339
 340 #ifdef TARGET_X86_64
 341 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
 342 #else
 343 #define TCG_EXT2_X86_64_FEATURES 0
 344 #endif
 345
 346 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 347           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 348           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
 349           TCG_EXT2_X86_64_FEATURES)
 350 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 351           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 352 #define TCG_EXT4_FEATURES 0
 353 #define TCG_SVM_FEATURES 0
 354 #define TCG_KVM_FEATURES 0
 355 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
 356           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
 357           CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
 358           CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE)
 359           /* missing:
 360           CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 361           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 362           CPUID_7_0_EBX_RDSEED */
 363 #define TCG_7_0_ECX_FEATURES 0
 364 #define TCG_APM_FEATURES 0
 365 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 366 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
 367           /* missing:
 368           CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
 369
 370 typedef struct FeatureWordInfo {
 371     const char **feat_names;
 372     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 373     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 374     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 375     int cpuid_reg;        /* output register (R_* constant) */
 376     uint32_t tcg_features; /* Feature flags supported by TCG */
 377     uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
 378 } FeatureWordInfo;
 379
 380 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 381     [FEAT_1_EDX] = {
 382         .feat_names = feature_name,
 383         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 384         .tcg_features = TCG_FEATURES,
 385     },
 386     [FEAT_1_ECX] = {
 387         .feat_names = ext_feature_name,
 388         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 389         .tcg_features = TCG_EXT_FEATURES,
 390     },
 391     [FEAT_8000_0001_EDX] = {
 392         .feat_names = ext2_feature_name,
 393         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 394         .tcg_features = TCG_EXT2_FEATURES,
 395     },
 396     [FEAT_8000_0001_ECX] = {
 397         .feat_names = ext3_feature_name,
 398         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 399         .tcg_features = TCG_EXT3_FEATURES,
 400     },
 401     [FEAT_C000_0001_EDX] = {
 402         .feat_names = ext4_feature_name,
 403         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 404         .tcg_features = TCG_EXT4_FEATURES,
 405     },
 406     [FEAT_KVM] = {
 407         .feat_names = kvm_feature_name,
 408         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 409         .tcg_features = TCG_KVM_FEATURES,
 410     },
 411     [FEAT_SVM] = {
 412         .feat_names = svm_feature_name,
 413         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 414         .tcg_features = TCG_SVM_FEATURES,
 415     },
 416     [FEAT_7_0_EBX] = {
 417         .feat_names = cpuid_7_0_ebx_feature_name,
 418         .cpuid_eax = 7,
 419         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 420         .cpuid_reg = R_EBX,
 421         .tcg_features = TCG_7_0_EBX_FEATURES,
 422     },
 423     [FEAT_7_0_ECX] = {
 424         .feat_names = cpuid_7_0_ecx_feature_name,
 425         .cpuid_eax = 7,
 426         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 427         .cpuid_reg = R_ECX,
 428         .tcg_features = TCG_7_0_ECX_FEATURES,
 429     },
 430     [FEAT_8000_0007_EDX] = {
 431         .feat_names = cpuid_apm_edx_feature_name,
 432         .cpuid_eax = 0x80000007,
 433         .cpuid_reg = R_EDX,
 434         .tcg_features = TCG_APM_FEATURES,
 435         .unmigratable_flags = CPUID_APM_INVTSC,
 436     },
 437     [FEAT_XSAVE] = {
 438         .feat_names = cpuid_xsave_feature_name,
 439         .cpuid_eax = 0xd,
 440         .cpuid_needs_ecx = true, .cpuid_ecx = 1,
 441         .cpuid_reg = R_EAX,
 442         .tcg_features = TCG_XSAVE_FEATURES,
 443     },
 444     [FEAT_6_EAX] = {
 445         .feat_names = cpuid_6_feature_name,
 446         .cpuid_eax = 6, .cpuid_reg = R_EAX,
 447         .tcg_features = TCG_6_EAX_FEATURES,
 448     },
 449 };
 450
 451 typedef struct X86RegisterInfo32 {
 452     /* Name of register */
 453     const char *name;
 454     /* QAPI enum value register */
 455     X86CPURegister32 qapi_enum;
 456 } X86RegisterInfo32;
 457
 458 #define REGISTER(reg) \
 459     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 460 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 461     REGISTER(EAX),
 462     REGISTER(ECX),
 463     REGISTER(EDX),
 464     REGISTER(EBX),
 465     REGISTER(ESP),
 466     REGISTER(EBP),
 467     REGISTER(ESI),
 468     REGISTER(EDI),
 469 };
 470 #undef REGISTER
 471
 472 const ExtSaveArea x86_ext_save_areas[] = {
 473     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 474             .offset = 0x240, .size = 0x100 },
 475     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 476             .offset = 0x3c0, .size = 0x40  },
 477     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 478             .offset = 0x400, .size = 0x40  },
 479     [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 480             .offset = 0x440, .size = 0x40 },
 481     [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 482             .offset = 0x480, .size = 0x200 },
 483     [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 484             .offset = 0x680, .size = 0x400 },
 485     [9] = { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
 486             .offset = 0xA80, .size = 0x8 },
 487 };
 488
 489 const char *get_register_name_32(unsigned int reg)
 490 {
 491     if (reg >= CPU_NB_REGS32) {
 492         return NULL;
 493     }
 494     return x86_reg_info_32[reg].name;
 495 }
 496
 497 /*
 498  * Returns the set of feature flags that are supported and migratable by
 499  * QEMU, for a given FeatureWord.
 500  */
 501 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
 502 {
 503     FeatureWordInfo *wi = &feature_word_info[w];
 504     uint32_t r = 0;
 505     int i;
 506
 507     for (i = 0; i < 32; i++) {
 508         uint32_t f = 1U << i;
 509         /* If the feature name is unknown, it is not supported by QEMU yet */
 510         if (!wi->feat_names[i]) {
 511             continue;
 512         }
 513         /* Skip features known to QEMU, but explicitly marked as unmigratable */
 514         if (wi->unmigratable_flags & f) {
 515             continue;
 516         }
 517         r |= f;
 518     }
 519     return r;
 520 }
 521
 522 void host_cpuid(uint32_t function, uint32_t count,
 523                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 524 {
 525     uint32_t vec[4];
 526
 527 #ifdef __x86_64__
 528     asm volatile("cpuid"
 529                  : "=a"(vec[0]), "=b"(vec[1]),
 530                    "=c"(vec[2]), "=d"(vec[3])
 531                  : "0"(function), "c"(count) : "cc");
 532 #elif defined(__i386__)
 533     asm volatile("pusha \n\t"
 534                  "cpuid \n\t"
 535                  "mov %%eax, 0(%2) \n\t"
 536                  "mov %%ebx, 4(%2) \n\t"
 537                  "mov %%ecx, 8(%2) \n\t"
 538                  "mov %%edx, 12(%2) \n\t"
 539                  "popa"
 540                  : : "a"(function), "c"(count), "S"(vec)
 541                  : "memory", "cc");
 542 #else
 543     abort();
 544 #endif
 545
 546     if (eax)
 547         *eax = vec[0];
 548     if (ebx)
 549         *ebx = vec[1];
 550     if (ecx)
 551         *ecx = vec[2];
 552     if (edx)
 553         *edx = vec[3];
 554 }
 555
 556 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 557
 558 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 559  * a substring.  ex if !NULL points to the first char after a substring,
 560  * otherwise the string is assumed to sized by a terminating nul.
 561  * Return lexical ordering of *s1:*s2.
 562  */
 563 static int sstrcmp(const char *s1, const char *e1,
 564                    const char *s2, const char *e2)
 565 {
 566     for (;;) {
 567         if (!*s1 || !*s2 || *s1 != *s2)
 568             return (*s1 - *s2);
 569         ++s1, ++s2;
 570         if (s1 == e1 && s2 == e2)
 571             return (0);
 572         else if (s1 == e1)
 573             return (*s2);
 574         else if (s2 == e2)
 575             return (*s1);
 576     }
 577 }
 578
 579 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 580  * '|' delimited (possibly empty) strings in which case search for a match
 581  * within the alternatives proceeds left to right.  Return 0 for success,
 582  * non-zero otherwise.
 583  */
 584 static int altcmp(const char *s, const char *e, const char *altstr)
 585 {
 586     const char *p, *q;
 587
 588     for (q = p = altstr; ; ) {
 589         while (*p && *p != '|')
 590             ++p;
 591         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 592             return (0);
 593         if (!*p)
 594             return (1);
 595         else
 596             q = ++p;
 597     }
 598 }
 599
 600 /* search featureset for flag *[s..e), if found set corresponding bit in
 601  * *pval and return true, otherwise return false
 602  */
 603 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 604                            const char **featureset)
 605 {
 606     uint32_t mask;
 607     const char **ppc;
 608     bool found = false;
 609
 610     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 611         if (*ppc && !altcmp(s, e, *ppc)) {
 612             *pval |= mask;
 613             found = true;
 614         }
 615     }
 616     return found;
 617 }
 618
 619 static void add_flagname_to_bitmaps(const char *flagname,
 620                                     FeatureWordArray words,
 621                                     Error **errp)
 622 {
 623     FeatureWord w;
 624     for (w = 0; w < FEATURE_WORDS; w++) {
 625         FeatureWordInfo *wi = &feature_word_info[w];
 626         if (wi->feat_names &&
 627             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 628             break;
 629         }
 630     }
 631     if (w == FEATURE_WORDS) {
 632         error_setg(errp, "CPU feature %s not found", flagname);
 633     }
 634 }
 635
 636 /* CPU class name definitions: */
 637
 638 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 639 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 640
 641 /* Return type name for a given CPU model name
 642  * Caller is responsible for freeing the returned string.
 643  */
 644 static char *x86_cpu_type_name(const char *model_name)
 645 {
 646     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
 647 }
 648
 649 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
 650 {
 651     ObjectClass *oc;
 652     char *typename;
 653
 654     if (cpu_model == NULL) {
 655         return NULL;
 656     }
 657
 658     typename = x86_cpu_type_name(cpu_model);
 659     oc = object_class_by_name(typename);
 660     g_free(typename);
 661     return oc;
 662 }
 663
 664 struct X86CPUDefinition {
 665     const char *name;
 666     uint32_t level;
 667     uint32_t xlevel;
 668     uint32_t xlevel2;
 669     /* vendor is zero-terminated, 12 character ASCII string */
 670     char vendor[CPUID_VENDOR_SZ + 1];
 671     int family;
 672     int model;
 673     int stepping;
 674     FeatureWordArray features;
 675     char model_id[48];
 676 };
 677
 678 static X86CPUDefinition builtin_x86_defs[] = {
 679     {
 680         .name = "qemu64",
 681         .level = 0xd,
 682         .vendor = CPUID_VENDOR_AMD,
 683         .family = 6,
 684         .model = 6,
 685         .stepping = 3,
 686         .features[FEAT_1_EDX] =
 687             PPRO_FEATURES |
 688             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 689             CPUID_PSE36,
 690         .features[FEAT_1_ECX] =
 691             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 692         .features[FEAT_8000_0001_EDX] =
 693             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 694         .features[FEAT_8000_0001_ECX] =
 695             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
 696         .xlevel = 0x8000000A,
 697     },
 698     {
 699         .name = "phenom",
 700         .level = 5,
 701         .vendor = CPUID_VENDOR_AMD,
 702         .family = 16,
 703         .model = 2,
 704         .stepping = 3,
 705         /* Missing: CPUID_HT */
 706         .features[FEAT_1_EDX] =
 707             PPRO_FEATURES |
 708             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 709             CPUID_PSE36 | CPUID_VME,
 710         .features[FEAT_1_ECX] =
 711             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 712             CPUID_EXT_POPCNT,
 713         .features[FEAT_8000_0001_EDX] =
 714             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 715             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 716             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 717         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 718                     CPUID_EXT3_CR8LEG,
 719                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 720                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 721         .features[FEAT_8000_0001_ECX] =
 722             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 723             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 724         /* Missing: CPUID_SVM_LBRV */
 725         .features[FEAT_SVM] =
 726             CPUID_SVM_NPT,
 727         .xlevel = 0x8000001A,
 728         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 729     },
 730     {
 731         .name = "core2duo",
 732         .level = 10,
 733         .vendor = CPUID_VENDOR_INTEL,
 734         .family = 6,
 735         .model = 15,
 736         .stepping = 11,
 737         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 738         .features[FEAT_1_EDX] =
 739             PPRO_FEATURES |
 740             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 741             CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
 742         /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
 743          * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
 744         .features[FEAT_1_ECX] =
 745             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 746             CPUID_EXT_CX16,
 747         .features[FEAT_8000_0001_EDX] =
 748             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 749         .features[FEAT_8000_0001_ECX] =
 750             CPUID_EXT3_LAHF_LM,
 751         .xlevel = 0x80000008,
 752         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 753     },
 754     {
 755         .name = "kvm64",
 756         .level = 0xd,
 757         .vendor = CPUID_VENDOR_INTEL,
 758         .family = 15,
 759         .model = 6,
 760         .stepping = 1,
 761         /* Missing: CPUID_HT */
 762         .features[FEAT_1_EDX] =
 763             PPRO_FEATURES | CPUID_VME |
 764             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 765             CPUID_PSE36,
 766         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 767         .features[FEAT_1_ECX] =
 768             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 769         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 770         .features[FEAT_8000_0001_EDX] =
 771             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 772         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 773                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 774                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 775                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 776         .features[FEAT_8000_0001_ECX] =
 777             0,
 778         .xlevel = 0x80000008,
 779         .model_id = "Common KVM processor"
 780     },
 781     {
 782         .name = "qemu32",
 783         .level = 4,
 784         .vendor = CPUID_VENDOR_INTEL,
 785         .family = 6,
 786         .model = 6,
 787         .stepping = 3,
 788         .features[FEAT_1_EDX] =
 789             PPRO_FEATURES,
 790         .features[FEAT_1_ECX] =
 791             CPUID_EXT_SSE3,
 792         .xlevel = 0x80000004,
 793     },
 794     {
 795         .name = "kvm32",
 796         .level = 5,
 797         .vendor = CPUID_VENDOR_INTEL,
 798         .family = 15,
 799         .model = 6,
 800         .stepping = 1,
 801         .features[FEAT_1_EDX] =
 802             PPRO_FEATURES | CPUID_VME |
 803             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 804         .features[FEAT_1_ECX] =
 805             CPUID_EXT_SSE3,
 806         .features[FEAT_8000_0001_ECX] =
 807             0,
 808         .xlevel = 0x80000008,
 809         .model_id = "Common 32-bit KVM processor"
 810     },
 811     {
 812         .name = "coreduo",
 813         .level = 10,
 814         .vendor = CPUID_VENDOR_INTEL,
 815         .family = 6,
 816         .model = 14,
 817         .stepping = 8,
 818         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 819         .features[FEAT_1_EDX] =
 820             PPRO_FEATURES | CPUID_VME |
 821             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
 822             CPUID_SS,
 823         /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
 824          * CPUID_EXT_PDCM, CPUID_EXT_VMX */
 825         .features[FEAT_1_ECX] =
 826             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
 827         .features[FEAT_8000_0001_EDX] =
 828             CPUID_EXT2_NX,
 829         .xlevel = 0x80000008,
 830         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 831     },
 832     {
 833         .name = "486",
 834         .level = 1,
 835         .vendor = CPUID_VENDOR_INTEL,
 836         .family = 4,
 837         .model = 8,
 838         .stepping = 0,
 839         .features[FEAT_1_EDX] =
 840             I486_FEATURES,
 841         .xlevel = 0,
 842     },
 843     {
 844         .name = "pentium",
 845         .level = 1,
 846         .vendor = CPUID_VENDOR_INTEL,
 847         .family = 5,
 848         .model = 4,
 849         .stepping = 3,
 850         .features[FEAT_1_EDX] =
 851             PENTIUM_FEATURES,
 852         .xlevel = 0,
 853     },
 854     {
 855         .name = "pentium2",
 856         .level = 2,
 857         .vendor = CPUID_VENDOR_INTEL,
 858         .family = 6,
 859         .model = 5,
 860         .stepping = 2,
 861         .features[FEAT_1_EDX] =
 862             PENTIUM2_FEATURES,
 863         .xlevel = 0,
 864     },
 865     {
 866         .name = "pentium3",
 867         .level = 3,
 868         .vendor = CPUID_VENDOR_INTEL,
 869         .family = 6,
 870         .model = 7,
 871         .stepping = 3,
 872         .features[FEAT_1_EDX] =
 873             PENTIUM3_FEATURES,
 874         .xlevel = 0,
 875     },
 876     {
 877         .name = "athlon",
 878         .level = 2,
 879         .vendor = CPUID_VENDOR_AMD,
 880         .family = 6,
 881         .model = 2,
 882         .stepping = 3,
 883         .features[FEAT_1_EDX] =
 884             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 885             CPUID_MCA,
 886         .features[FEAT_8000_0001_EDX] =
 887             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 888         .xlevel = 0x80000008,
 889     },
 890     {
 891         .name = "n270",
 892         .level = 10,
 893         .vendor = CPUID_VENDOR_INTEL,
 894         .family = 6,
 895         .model = 28,
 896         .stepping = 2,
 897         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 898         .features[FEAT_1_EDX] =
 899             PPRO_FEATURES |
 900             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
 901             CPUID_ACPI | CPUID_SS,
 902             /* Some CPUs got no CPUID_SEP */
 903         /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
 904          * CPUID_EXT_XTPR */
 905         .features[FEAT_1_ECX] =
 906             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 907             CPUID_EXT_MOVBE,
 908         .features[FEAT_8000_0001_EDX] =
 909             CPUID_EXT2_NX,
 910         .features[FEAT_8000_0001_ECX] =
 911             CPUID_EXT3_LAHF_LM,
 912         .xlevel = 0x80000008,
 913         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 914     },
 915     {
 916         .name = "Conroe",
 917         .level = 10,
 918         .vendor = CPUID_VENDOR_INTEL,
 919         .family = 6,
 920         .model = 15,
 921         .stepping = 3,
 922         .features[FEAT_1_EDX] =
 923             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 924             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 925             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 926             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 927             CPUID_DE | CPUID_FP87,
 928         .features[FEAT_1_ECX] =
 929             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 930         .features[FEAT_8000_0001_EDX] =
 931             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 932         .features[FEAT_8000_0001_ECX] =
 933             CPUID_EXT3_LAHF_LM,
 934         .xlevel = 0x80000008,
 935         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 936     },
 937     {
 938         .name = "Penryn",
 939         .level = 10,
 940         .vendor = CPUID_VENDOR_INTEL,
 941         .family = 6,
 942         .model = 23,
 943         .stepping = 3,
 944         .features[FEAT_1_EDX] =
 945             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 946             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 947             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 948             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 949             CPUID_DE | CPUID_FP87,
 950         .features[FEAT_1_ECX] =
 951             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 952             CPUID_EXT_SSE3,
 953         .features[FEAT_8000_0001_EDX] =
 954             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 955         .features[FEAT_8000_0001_ECX] =
 956             CPUID_EXT3_LAHF_LM,
 957         .xlevel = 0x80000008,
 958         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 959     },
 960     {
 961         .name = "Nehalem",
 962         .level = 11,
 963         .vendor = CPUID_VENDOR_INTEL,
 964         .family = 6,
 965         .model = 26,
 966         .stepping = 3,
 967         .features[FEAT_1_EDX] =
 968             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 969             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 970             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 971             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 972             CPUID_DE | CPUID_FP87,
 973         .features[FEAT_1_ECX] =
 974             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 975             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 976         .features[FEAT_8000_0001_EDX] =
 977             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 978         .features[FEAT_8000_0001_ECX] =
 979             CPUID_EXT3_LAHF_LM,
 980         .xlevel = 0x80000008,
 981         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 982     },
 983     {
 984         .name = "Westmere",
 985         .level = 11,
 986         .vendor = CPUID_VENDOR_INTEL,
 987         .family = 6,
 988         .model = 44,
 989         .stepping = 1,
 990         .features[FEAT_1_EDX] =
 991             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 992             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 993             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 994             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 995             CPUID_DE | CPUID_FP87,
 996         .features[FEAT_1_ECX] =
 997             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 998             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 999             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1000         .features[FEAT_8000_0001_EDX] =
1001             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1002         .features[FEAT_8000_0001_ECX] =
1003             CPUID_EXT3_LAHF_LM,
1004         .features[FEAT_6_EAX] =
1005             CPUID_6_EAX_ARAT,
1006         .xlevel = 0x80000008,
1007         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1008     },
1009     {
1010         .name = "SandyBridge",
1011         .level = 0xd,
1012         .vendor = CPUID_VENDOR_INTEL,
1013         .family = 6,
1014         .model = 42,
1015         .stepping = 1,
1016         .features[FEAT_1_EDX] =
1017             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1018             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1019             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1020             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1021             CPUID_DE | CPUID_FP87,
1022         .features[FEAT_1_ECX] =
1023             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1024             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1025             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1026             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1027             CPUID_EXT_SSE3,
1028         .features[FEAT_8000_0001_EDX] =
1029             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1030             CPUID_EXT2_SYSCALL,
1031         .features[FEAT_8000_0001_ECX] =
1032             CPUID_EXT3_LAHF_LM,
1033         .features[FEAT_XSAVE] =
1034             CPUID_XSAVE_XSAVEOPT,
1035         .features[FEAT_6_EAX] =
1036             CPUID_6_EAX_ARAT,
1037         .xlevel = 0x80000008,
1038         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1039     },
1040     {
1041         .name = "IvyBridge",
1042         .level = 0xd,
1043         .vendor = CPUID_VENDOR_INTEL,
1044         .family = 6,
1045         .model = 58,
1046         .stepping = 9,
1047         .features[FEAT_1_EDX] =
1048             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1049             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1050             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1051             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1052             CPUID_DE | CPUID_FP87,
1053         .features[FEAT_1_ECX] =
1054             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1055             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1056             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1057             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1058             CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1059         .features[FEAT_7_0_EBX] =
1060             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1061             CPUID_7_0_EBX_ERMS,
1062         .features[FEAT_8000_0001_EDX] =
1063             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1064             CPUID_EXT2_SYSCALL,
1065         .features[FEAT_8000_0001_ECX] =
1066             CPUID_EXT3_LAHF_LM,
1067         .features[FEAT_XSAVE] =
1068             CPUID_XSAVE_XSAVEOPT,
1069         .features[FEAT_6_EAX] =
1070             CPUID_6_EAX_ARAT,
1071         .xlevel = 0x80000008,
1072         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1073     },
1074     {
1075         .name = "Haswell-noTSX",
1076         .level = 0xd,
1077         .vendor = CPUID_VENDOR_INTEL,
1078         .family = 6,
1079         .model = 60,
1080         .stepping = 1,
1081         .features[FEAT_1_EDX] =
1082             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1083             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1084             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1085             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1086             CPUID_DE | CPUID_FP87,
1087         .features[FEAT_1_ECX] =
1088             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1089             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1090             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1091             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1092             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1093             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1094         .features[FEAT_8000_0001_EDX] =
1095             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1096             CPUID_EXT2_SYSCALL,
1097         .features[FEAT_8000_0001_ECX] =
1098             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1099         .features[FEAT_7_0_EBX] =
1100             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1101             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1102             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1103         .features[FEAT_XSAVE] =
1104             CPUID_XSAVE_XSAVEOPT,
1105         .features[FEAT_6_EAX] =
1106             CPUID_6_EAX_ARAT,
1107         .xlevel = 0x80000008,
1108         .model_id = "Intel Core Processor (Haswell, no TSX)",
1109     },    {
1110         .name = "Haswell",
1111         .level = 0xd,
1112         .vendor = CPUID_VENDOR_INTEL,
1113         .family = 6,
1114         .model = 60,
1115         .stepping = 1,
1116         .features[FEAT_1_EDX] =
1117             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1118             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1119             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1120             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1121             CPUID_DE | CPUID_FP87,
1122         .features[FEAT_1_ECX] =
1123             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1124             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1125             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1126             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1127             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1128             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1129         .features[FEAT_8000_0001_EDX] =
1130             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1131             CPUID_EXT2_SYSCALL,
1132         .features[FEAT_8000_0001_ECX] =
1133             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1134         .features[FEAT_7_0_EBX] =
1135             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1136             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1137             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1138             CPUID_7_0_EBX_RTM,
1139         .features[FEAT_XSAVE] =
1140             CPUID_XSAVE_XSAVEOPT,
1141         .features[FEAT_6_EAX] =
1142             CPUID_6_EAX_ARAT,
1143         .xlevel = 0x80000008,
1144         .model_id = "Intel Core Processor (Haswell)",
1145     },
1146     {
1147         .name = "Broadwell-noTSX",
1148         .level = 0xd,
1149         .vendor = CPUID_VENDOR_INTEL,
1150         .family = 6,
1151         .model = 61,
1152         .stepping = 2,
1153         .features[FEAT_1_EDX] =
1154             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1155             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1156             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1157             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1158             CPUID_DE | CPUID_FP87,
1159         .features[FEAT_1_ECX] =
1160             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1161             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1162             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1163             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1164             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1165             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1166         .features[FEAT_8000_0001_EDX] =
1167             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1168             CPUID_EXT2_SYSCALL,
1169         .features[FEAT_8000_0001_ECX] =
1170             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1171         .features[FEAT_7_0_EBX] =
1172             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1173             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1174             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1175             CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1176             CPUID_7_0_EBX_SMAP,
1177         .features[FEAT_XSAVE] =
1178             CPUID_XSAVE_XSAVEOPT,
1179         .features[FEAT_6_EAX] =
1180             CPUID_6_EAX_ARAT,
1181         .xlevel = 0x80000008,
1182         .model_id = "Intel Core Processor (Broadwell, no TSX)",
1183     },
1184     {
1185         .name = "Broadwell",
1186         .level = 0xd,
1187         .vendor = CPUID_VENDOR_INTEL,
1188         .family = 6,
1189         .model = 61,
1190         .stepping = 2,
1191         .features[FEAT_1_EDX] =
1192             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1193             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1194             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1195             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1196             CPUID_DE | CPUID_FP87,
1197         .features[FEAT_1_ECX] =
1198             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1199             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1200             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1201             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1202             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1203             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1204         .features[FEAT_8000_0001_EDX] =
1205             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1206             CPUID_EXT2_SYSCALL,
1207         .features[FEAT_8000_0001_ECX] =
1208             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1209         .features[FEAT_7_0_EBX] =
1210             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1211             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1212             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1213             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1214             CPUID_7_0_EBX_SMAP,
1215         .features[FEAT_XSAVE] =
1216             CPUID_XSAVE_XSAVEOPT,
1217         .features[FEAT_6_EAX] =
1218             CPUID_6_EAX_ARAT,
1219         .xlevel = 0x80000008,
1220         .model_id = "Intel Core Processor (Broadwell)",
1221     },
1222     {
1223         .name = "Opteron_G1",
1224         .level = 5,
1225         .vendor = CPUID_VENDOR_AMD,
1226         .family = 15,
1227         .model = 6,
1228         .stepping = 1,
1229         .features[FEAT_1_EDX] =
1230             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1231             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1232             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1233             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1234             CPUID_DE | CPUID_FP87,
1235         .features[FEAT_1_ECX] =
1236             CPUID_EXT_SSE3,
1237         .features[FEAT_8000_0001_EDX] =
1238             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1239             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1240             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1241             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1242             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1243             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1244         .xlevel = 0x80000008,
1245         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1246     },
1247     {
1248         .name = "Opteron_G2",
1249         .level = 5,
1250         .vendor = CPUID_VENDOR_AMD,
1251         .family = 15,
1252         .model = 6,
1253         .stepping = 1,
1254         .features[FEAT_1_EDX] =
1255             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1256             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1257             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1258             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1259             CPUID_DE | CPUID_FP87,
1260         .features[FEAT_1_ECX] =
1261             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1262         /* Missing: CPUID_EXT2_RDTSCP */
1263         .features[FEAT_8000_0001_EDX] =
1264             CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1265             CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1266             CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1267             CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1268             CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1269             CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1270             CPUID_EXT2_DE | CPUID_EXT2_FPU,
1271         .features[FEAT_8000_0001_ECX] =
1272             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1273         .xlevel = 0x80000008,
1274         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1275     },
1276     {
1277         .name = "Opteron_G3",
1278         .level = 5,
1279         .vendor = CPUID_VENDOR_AMD,
1280         .family = 15,
1281         .model = 6,
1282         .stepping = 1,
1283         .features[FEAT_1_EDX] =
1284             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1285             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1286             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1287             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1288             CPUID_DE | CPUID_FP87,
1289         .features[FEAT_1_ECX] =
1290             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1291             CPUID_EXT_SSE3,
1292         /* Missing: CPUID_EXT2_RDTSCP */
1293         .features[FEAT_8000_0001_EDX] =
1294             CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1295             CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1296             CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1297             CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1298             CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1299             CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1300             CPUID_EXT2_DE | CPUID_EXT2_FPU,
1301         .features[FEAT_8000_0001_ECX] =
1302             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1303             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1304         .xlevel = 0x80000008,
1305         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1306     },
1307     {
1308         .name = "Opteron_G4",
1309         .level = 0xd,
1310         .vendor = CPUID_VENDOR_AMD,
1311         .family = 21,
1312         .model = 1,
1313         .stepping = 2,
1314         .features[FEAT_1_EDX] =
1315             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1316             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1317             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1318             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1319             CPUID_DE | CPUID_FP87,
1320         .features[FEAT_1_ECX] =
1321             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1322             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1323             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1324             CPUID_EXT_SSE3,
1325         /* Missing: CPUID_EXT2_RDTSCP */
1326         .features[FEAT_8000_0001_EDX] =
1327             CPUID_EXT2_LM |
1328             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1329             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1330             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1331             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1332             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1333             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1334         .features[FEAT_8000_0001_ECX] =
1335             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1336             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1337             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1338             CPUID_EXT3_LAHF_LM,
1339         /* no xsaveopt! */
1340         .xlevel = 0x8000001A,
1341         .model_id = "AMD Opteron 62xx class CPU",
1342     },
1343     {
1344         .name = "Opteron_G5",
1345         .level = 0xd,
1346         .vendor = CPUID_VENDOR_AMD,
1347         .family = 21,
1348         .model = 2,
1349         .stepping = 0,
1350         .features[FEAT_1_EDX] =
1351             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1352             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1353             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1354             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1355             CPUID_DE | CPUID_FP87,
1356         .features[FEAT_1_ECX] =
1357             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1358             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1359             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1360             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1361         /* Missing: CPUID_EXT2_RDTSCP */
1362         .features[FEAT_8000_0001_EDX] =
1363             CPUID_EXT2_LM |
1364             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1365             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1366             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1367             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1368             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1369             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1370         .features[FEAT_8000_0001_ECX] =
1371             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1372             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1373             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1374             CPUID_EXT3_LAHF_LM,
1375         /* no xsaveopt! */
1376         .xlevel = 0x8000001A,
1377         .model_id = "AMD Opteron 63xx class CPU",
1378     },
1379 };
1380
1381 typedef struct PropValue {
1382     const char *prop, *value;
1383 } PropValue;
1384
1385 /* KVM-specific features that are automatically added/removed
1386  * from all CPU models when KVM is enabled.
1387  */
1388 static PropValue kvm_default_props[] = {
1389     { "kvmclock", "on" },
1390     { "kvm-nopiodelay", "on" },
1391     { "kvm-asyncpf", "on" },
1392     { "kvm-steal-time", "on" },
1393     { "kvm-pv-eoi", "on" },
1394     { "kvmclock-stable-bit", "on" },
1395     { "x2apic", "on" },
1396     { "acpi", "off" },
1397     { "monitor", "off" },
1398     { "svm", "off" },
1399     { NULL, NULL },
1400 };
1401
1402 void x86_cpu_change_kvm_default(const char *prop, const char *value)
1403 {
1404     PropValue *pv;
1405     for (pv = kvm_default_props; pv->prop; pv++) {
1406         if (!strcmp(pv->prop, prop)) {
1407             pv->value = value;
1408             break;
1409         }
1410     }
1411
1412     /* It is valid to call this function only for properties that
1413      * are already present in the kvm_default_props table.
1414      */
1415     assert(pv->prop);
1416 }
1417
1418 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1419                                                    bool migratable_only);
1420
1421 #ifdef CONFIG_KVM
1422
1423 static int cpu_x86_fill_model_id(char *str)
1424 {
1425     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1426     int i;
1427
1428     for (i = 0; i < 3; i++) {
1429         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1430         memcpy(str + i * 16 +  0, &eax, 4);
1431         memcpy(str + i * 16 +  4, &ebx, 4);
1432         memcpy(str + i * 16 +  8, &ecx, 4);
1433         memcpy(str + i * 16 + 12, &edx, 4);
1434     }
1435     return 0;
1436 }
1437
1438 static X86CPUDefinition host_cpudef;
1439
1440 static Property host_x86_cpu_properties[] = {
1441     DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1442     DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
1443     DEFINE_PROP_END_OF_LIST()
1444 };
1445
1446 /* class_init for the "host" CPU model
1447  *
1448  * This function may be called before KVM is initialized.
1449  */
1450 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1451 {
1452     DeviceClass *dc = DEVICE_CLASS(oc);
1453     X86CPUClass *xcc = X86_CPU_CLASS(oc);
1454     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1455
1456     xcc->kvm_required = true;
1457
1458     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1459     x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1460
1461     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1462     host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1463     host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1464     host_cpudef.stepping = eax & 0x0F;
1465
1466     cpu_x86_fill_model_id(host_cpudef.model_id);
1467
1468     xcc->cpu_def = &host_cpudef;
1469
1470     /* level, xlevel, xlevel2, and the feature words are initialized on
1471      * instance_init, because they require KVM to be initialized.
1472      */
1473
1474     dc->props = host_x86_cpu_properties;
1475     /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1476     dc->cannot_destroy_with_object_finalize_yet = true;
1477 }
1478
1479 static void host_x86_cpu_initfn(Object *obj)
1480 {
1481     X86CPU *cpu = X86_CPU(obj);
1482     CPUX86State *env = &cpu->env;
1483     KVMState *s = kvm_state;
1484
1485     assert(kvm_enabled());
1486
1487     /* We can't fill the features array here because we don't know yet if
1488      * "migratable" is true or false.
1489      */
1490     cpu->host_features = true;
1491
1492     env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1493     env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1494     env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1495
1496     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1497 }
1498
1499 static const TypeInfo host_x86_cpu_type_info = {
1500     .name = X86_CPU_TYPE_NAME("host"),
1501     .parent = TYPE_X86_CPU,
1502     .instance_init = host_x86_cpu_initfn,
1503     .class_init = host_x86_cpu_class_init,
1504 };
1505
1506 #endif
1507
1508 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1509 {
1510     FeatureWordInfo *f = &feature_word_info[w];
1511     int i;
1512
1513     for (i = 0; i < 32; ++i) {
1514         if ((1UL << i) & mask) {
1515             const char *reg = get_register_name_32(f->cpuid_reg);
1516             assert(reg);
1517             fprintf(stderr, "warning: %s doesn't support requested feature: "
1518                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1519                 kvm_enabled() ? "host" : "TCG",
1520                 f->cpuid_eax, reg,
1521                 f->feat_names[i] ? "." : "",
1522                 f->feat_names[i] ? f->feat_names[i] : "", i);
1523         }
1524     }
1525 }
1526
1527 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1528                                          const char *name, void *opaque,
1529                                          Error **errp)
1530 {
1531     X86CPU *cpu = X86_CPU(obj);
1532     CPUX86State *env = &cpu->env;
1533     int64_t value;
1534
1535     value = (env->cpuid_version >> 8) & 0xf;
1536     if (value == 0xf) {
1537         value += (env->cpuid_version >> 20) & 0xff;
1538     }
1539     visit_type_int(v, name, &value, errp);
1540 }
1541
1542 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1543                                          const char *name, void *opaque,
1544                                          Error **errp)
1545 {
1546     X86CPU *cpu = X86_CPU(obj);
1547     CPUX86State *env = &cpu->env;
1548     const int64_t min = 0;
1549     const int64_t max = 0xff + 0xf;
1550     Error *local_err = NULL;
1551     int64_t value;
1552
1553     visit_type_int(v, name, &value, &local_err);
1554     if (local_err) {
1555         error_propagate(errp, local_err);
1556         return;
1557     }
1558     if (value < min || value > max) {
1559         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1560                    name ? name : "null", value, min, max);
1561         return;
1562     }
1563
1564     env->cpuid_version &= ~0xff00f00;
1565     if (value > 0x0f) {
1566         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1567     } else {
1568         env->cpuid_version |= value << 8;
1569     }
1570 }
1571
1572 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1573                                         const char *name, void *opaque,
1574                                         Error **errp)
1575 {
1576     X86CPU *cpu = X86_CPU(obj);
1577     CPUX86State *env = &cpu->env;
1578     int64_t value;
1579
1580     value = (env->cpuid_version >> 4) & 0xf;
1581     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1582     visit_type_int(v, name, &value, errp);
1583 }
1584
1585 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1586                                         const char *name, void *opaque,
1587                                         Error **errp)
1588 {
1589     X86CPU *cpu = X86_CPU(obj);
1590     CPUX86State *env = &cpu->env;
1591     const int64_t min = 0;
1592     const int64_t max = 0xff;
1593     Error *local_err = NULL;
1594     int64_t value;
1595
1596     visit_type_int(v, name, &value, &local_err);
1597     if (local_err) {
1598         error_propagate(errp, local_err);
1599         return;
1600     }
1601     if (value < min || value > max) {
1602         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1603                    name ? name : "null", value, min, max);
1604         return;
1605     }
1606
1607     env->cpuid_version &= ~0xf00f0;
1608     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1609 }
1610
1611 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1612                                            const char *name, void *opaque,
1613                                            Error **errp)
1614 {
1615     X86CPU *cpu = X86_CPU(obj);
1616     CPUX86State *env = &cpu->env;
1617     int64_t value;
1618
1619     value = env->cpuid_version & 0xf;
1620     visit_type_int(v, name, &value, errp);
1621 }
1622
1623 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1624                                            const char *name, void *opaque,
1625                                            Error **errp)
1626 {
1627     X86CPU *cpu = X86_CPU(obj);
1628     CPUX86State *env = &cpu->env;
1629     const int64_t min = 0;
1630     const int64_t max = 0xf;
1631     Error *local_err = NULL;
1632     int64_t value;
1633
1634     visit_type_int(v, name, &value, &local_err);
1635     if (local_err) {
1636         error_propagate(errp, local_err);
1637         return;
1638     }
1639     if (value < min || value > max) {
1640         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1641                    name ? name : "null", value, min, max);
1642         return;
1643     }
1644
1645     env->cpuid_version &= ~0xf;
1646     env->cpuid_version |= value & 0xf;
1647 }
1648
1649 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1650 {
1651     X86CPU *cpu = X86_CPU(obj);
1652     CPUX86State *env = &cpu->env;
1653     char *value;
1654
1655     value = g_malloc(CPUID_VENDOR_SZ + 1);
1656     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1657                              env->cpuid_vendor3);
1658     return value;
1659 }
1660
1661 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1662                                  Error **errp)
1663 {
1664     X86CPU *cpu = X86_CPU(obj);
1665     CPUX86State *env = &cpu->env;
1666     int i;
1667
1668     if (strlen(value) != CPUID_VENDOR_SZ) {
1669         error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1670         return;
1671     }
1672
1673     env->cpuid_vendor1 = 0;
1674     env->cpuid_vendor2 = 0;
1675     env->cpuid_vendor3 = 0;
1676     for (i = 0; i < 4; i++) {
1677         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1678         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1679         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1680     }
1681 }
1682
1683 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1684 {
1685     X86CPU *cpu = X86_CPU(obj);
1686     CPUX86State *env = &cpu->env;
1687     char *value;
1688     int i;
1689
1690     value = g_malloc(48 + 1);
1691     for (i = 0; i < 48; i++) {
1692         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1693     }
1694     value[48] = '\0';
1695     return value;
1696 }
1697
1698 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1699                                    Error **errp)
1700 {
1701     X86CPU *cpu = X86_CPU(obj);
1702     CPUX86State *env = &cpu->env;
1703     int c, len, i;
1704
1705     if (model_id == NULL) {
1706         model_id = "";
1707     }
1708     len = strlen(model_id);
1709     memset(env->cpuid_model, 0, 48);
1710     for (i = 0; i < 48; i++) {
1711         if (i >= len) {
1712             c = '\0';
1713         } else {
1714             c = (uint8_t)model_id[i];
1715         }
1716         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1717     }
1718 }
1719
1720 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1721                                    void *opaque, Error **errp)
1722 {
1723     X86CPU *cpu = X86_CPU(obj);
1724     int64_t value;
1725
1726     value = cpu->env.tsc_khz * 1000;
1727     visit_type_int(v, name, &value, errp);
1728 }
1729
1730 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1731                                    void *opaque, Error **errp)
1732 {
1733     X86CPU *cpu = X86_CPU(obj);
1734     const int64_t min = 0;
1735     const int64_t max = INT64_MAX;
1736     Error *local_err = NULL;
1737     int64_t value;
1738
1739     visit_type_int(v, name, &value, &local_err);
1740     if (local_err) {
1741         error_propagate(errp, local_err);
1742         return;
1743     }
1744     if (value < min || value > max) {
1745         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1746                    name ? name : "null", value, min, max);
1747         return;
1748     }
1749
1750     cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
1751 }
1752
1753 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1754                                   void *opaque, Error **errp)
1755 {
1756     X86CPU *cpu = X86_CPU(obj);
1757     int64_t value = cpu->apic_id;
1758
1759     visit_type_int(v, name, &value, errp);
1760 }
1761
1762 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1763                                   void *opaque, Error **errp)
1764 {
1765     X86CPU *cpu = X86_CPU(obj);
1766     DeviceState *dev = DEVICE(obj);
1767     const int64_t min = 0;
1768     const int64_t max = UINT32_MAX;
1769     Error *error = NULL;
1770     int64_t value;
1771
1772     if (dev->realized) {
1773         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1774                    "it was realized", name, object_get_typename(obj));
1775         return;
1776     }
1777
1778     visit_type_int(v, name, &value, &error);
1779     if (error) {
1780         error_propagate(errp, error);
1781         return;
1782     }
1783     if (value < min || value > max) {
1784         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1785                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1786                    object_get_typename(obj), name, value, min, max);
1787         return;
1788     }
1789
1790     if ((value != cpu->apic_id) && cpu_exists(value)) {
1791         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1792         return;
1793     }
1794     cpu->apic_id = value;
1795 }
1796
1797 /* Generic getter for "feature-words" and "filtered-features" properties */
1798 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1799                                       const char *name, void *opaque,
1800                                       Error **errp)
1801 {
1802     uint32_t *array = (uint32_t *)opaque;
1803     FeatureWord w;
1804     Error *err = NULL;
1805     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1806     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1807     X86CPUFeatureWordInfoList *list = NULL;
1808
1809     for (w = 0; w < FEATURE_WORDS; w++) {
1810         FeatureWordInfo *wi = &feature_word_info[w];
1811         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1812         qwi->cpuid_input_eax = wi->cpuid_eax;
1813         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1814         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1815         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1816         qwi->features = array[w];
1817
1818         /* List will be in reverse order, but order shouldn't matter */
1819         list_entries[w].next = list;
1820         list_entries[w].value = &word_infos[w];
1821         list = &list_entries[w];
1822     }
1823
1824     visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, &err);
1825     error_propagate(errp, err);
1826 }
1827
1828 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1829                                  void *opaque, Error **errp)
1830 {
1831     X86CPU *cpu = X86_CPU(obj);
1832     int64_t value = cpu->hyperv_spinlock_attempts;
1833
1834     visit_type_int(v, name, &value, errp);
1835 }
1836
1837 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1838                                  void *opaque, Error **errp)
1839 {
1840     const int64_t min = 0xFFF;
1841     const int64_t max = UINT_MAX;
1842     X86CPU *cpu = X86_CPU(obj);
1843     Error *err = NULL;
1844     int64_t value;
1845
1846     visit_type_int(v, name, &value, &err);
1847     if (err) {
1848         error_propagate(errp, err);
1849         return;
1850     }
1851
1852     if (value < min || value > max) {
1853         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1854                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1855                    object_get_typename(obj), name ? name : "null",
1856                    value, min, max);
1857         return;
1858     }
1859     cpu->hyperv_spinlock_attempts = value;
1860 }
1861
1862 static PropertyInfo qdev_prop_spinlocks = {
1863     .name  = "int",
1864     .get   = x86_get_hv_spinlocks,
1865     .set   = x86_set_hv_spinlocks,
1866 };
1867
1868 /* Convert all '_' in a feature string option name to '-', to make feature
1869  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1870  */
1871 static inline void feat2prop(char *s)
1872 {
1873     while ((s = strchr(s, '_'))) {
1874         *s = '-';
1875     }
1876 }
1877
1878 /* Parse "+feature,-feature,feature=foo" CPU feature string
1879  */
1880 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1881                                      Error **errp)
1882 {
1883     X86CPU *cpu = X86_CPU(cs);
1884     char *featurestr; /* Single 'key=value" string being parsed */
1885     FeatureWord w;
1886     /* Features to be added */
1887     FeatureWordArray plus_features = { 0 };
1888     /* Features to be removed */
1889     FeatureWordArray minus_features = { 0 };
1890     uint32_t numvalue;
1891     CPUX86State *env = &cpu->env;
1892     Error *local_err = NULL;
1893
1894     featurestr = features ? strtok(features, ",") : NULL;
1895
1896     while (featurestr) {
1897         char *val;
1898         if (featurestr[0] == '+') {
1899             add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
1900         } else if (featurestr[0] == '-') {
1901             add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
1902         } else if ((val = strchr(featurestr, '='))) {
1903             *val = 0; val++;
1904             feat2prop(featurestr);
1905             if (!strcmp(featurestr, "xlevel")) {
1906                 char *err;
1907                 char num[32];
1908
1909                 numvalue = strtoul(val, &err, 0);
1910                 if (!*val || *err) {
1911                     error_setg(errp, "bad numerical value %s", val);
1912                     return;
1913                 }
1914                 if (numvalue < 0x80000000) {
1915                     error_report("xlevel value shall always be >= 0x80000000"
1916                                  ", fixup will be removed in future versions");
1917                     numvalue += 0x80000000;
1918                 }
1919                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1920                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1921             } else if (!strcmp(featurestr, "tsc-freq")) {
1922                 int64_t tsc_freq;
1923                 char *err;
1924                 char num[32];
1925
1926                 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1927                                                QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
1928                 if (tsc_freq < 0 || *err) {
1929                     error_setg(errp, "bad numerical value %s", val);
1930                     return;
1931                 }
1932                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1933                 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1934                                       &local_err);
1935             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1936                 char *err;
1937                 const int min = 0xFFF;
1938                 char num[32];
1939                 numvalue = strtoul(val, &err, 0);
1940                 if (!*val || *err) {
1941                     error_setg(errp, "bad numerical value %s", val);
1942                     return;
1943                 }
1944                 if (numvalue < min) {
1945                     error_report("hv-spinlocks value shall always be >= 0x%x"
1946                                  ", fixup will be removed in future versions",
1947                                  min);
1948                     numvalue = min;
1949                 }
1950                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1951                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1952             } else {
1953                 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1954             }
1955         } else {
1956             feat2prop(featurestr);
1957             object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1958         }
1959         if (local_err) {
1960             error_propagate(errp, local_err);
1961             return;
1962         }
1963         featurestr = strtok(NULL, ",");
1964     }
1965
1966     if (cpu->host_features) {
1967         for (w = 0; w < FEATURE_WORDS; w++) {
1968             env->features[w] =
1969                 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1970         }
1971     }
1972
1973     for (w = 0; w < FEATURE_WORDS; w++) {
1974         env->features[w] |= plus_features[w];
1975         env->features[w] &= ~minus_features[w];
1976     }
1977 }
1978
1979 /* Print all cpuid feature names in featureset
1980  */
1981 static void listflags(FILE *f, fprintf_function print, const char **featureset)
1982 {
1983     int bit;
1984     bool first = true;
1985
1986     for (bit = 0; bit < 32; bit++) {
1987         if (featureset[bit]) {
1988             print(f, "%s%s", first ? "" : " ", featureset[bit]);
1989             first = false;
1990         }
1991     }
1992 }
1993
1994 /* generate CPU information. */
1995 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1996 {
1997     X86CPUDefinition *def;
1998     char buf[256];
1999     int i;
2000
2001     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2002         def = &builtin_x86_defs[i];
2003         snprintf(buf, sizeof(buf), "%s", def->name);
2004         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
2005     }
2006 #ifdef CONFIG_KVM
2007     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
2008                    "KVM processor with all supported host features "
2009                    "(only available in KVM mode)");
2010 #endif
2011
2012     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
2013     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2014         FeatureWordInfo *fw = &feature_word_info[i];
2015
2016         (*cpu_fprintf)(f, "  ");
2017         listflags(f, cpu_fprintf, fw->feat_names);
2018         (*cpu_fprintf)(f, "\n");
2019     }
2020 }
2021
2022 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2023 {
2024     CpuDefinitionInfoList *cpu_list = NULL;
2025     X86CPUDefinition *def;
2026     int i;
2027
2028     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2029         CpuDefinitionInfoList *entry;
2030         CpuDefinitionInfo *info;
2031
2032         def = &builtin_x86_defs[i];
2033         info = g_malloc0(sizeof(*info));
2034         info->name = g_strdup(def->name);
2035
2036         entry = g_malloc0(sizeof(*entry));
2037         entry->value = info;
2038         entry->next = cpu_list;
2039         cpu_list = entry;
2040     }
2041
2042     return cpu_list;
2043 }
2044
2045 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2046                                                    bool migratable_only)
2047 {
2048     FeatureWordInfo *wi = &feature_word_info[w];
2049     uint32_t r;
2050
2051     if (kvm_enabled()) {
2052         r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2053                                                     wi->cpuid_ecx,
2054                                                     wi->cpuid_reg);
2055     } else if (tcg_enabled()) {
2056         r = wi->tcg_features;
2057     } else {
2058         return ~0;
2059     }
2060     if (migratable_only) {
2061         r &= x86_cpu_get_migratable_flags(w);
2062     }
2063     return r;
2064 }
2065
2066 /*
2067  * Filters CPU feature words based on host availability of each feature.
2068  *
2069  * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2070  */
2071 static int x86_cpu_filter_features(X86CPU *cpu)
2072 {
2073     CPUX86State *env = &cpu->env;
2074     FeatureWord w;
2075     int rv = 0;
2076
2077     for (w = 0; w < FEATURE_WORDS; w++) {
2078         uint32_t host_feat =
2079             x86_cpu_get_supported_feature_word(w, cpu->migratable);
2080         uint32_t requested_features = env->features[w];
2081         env->features[w] &= host_feat;
2082         cpu->filtered_features[w] = requested_features & ~env->features[w];
2083         if (cpu->filtered_features[w]) {
2084             if (cpu->check_cpuid || cpu->enforce_cpuid) {
2085                 report_unavailable_features(w, cpu->filtered_features[w]);
2086             }
2087             rv = 1;
2088         }
2089     }
2090
2091     return rv;
2092 }
2093
2094 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2095 {
2096     PropValue *pv;
2097     for (pv = props; pv->prop; pv++) {
2098         if (!pv->value) {
2099             continue;
2100         }
2101         object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2102                               &error_abort);
2103     }
2104 }
2105
2106 /* Load data from X86CPUDefinition
2107  */
2108 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2109 {
2110     CPUX86State *env = &cpu->env;
2111     const char *vendor;
2112     char host_vendor[CPUID_VENDOR_SZ + 1];
2113     FeatureWord w;
2114
2115     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2116     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2117     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2118     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2119     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
2120     object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2121     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2122     for (w = 0; w < FEATURE_WORDS; w++) {
2123         env->features[w] = def->features[w];
2124     }
2125
2126     /* Special cases not set in the X86CPUDefinition structs: */
2127     if (kvm_enabled()) {
2128         x86_cpu_apply_props(cpu, kvm_default_props);
2129     }
2130
2131     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2132
2133     /* sysenter isn't supported in compatibility mode on AMD,
2134      * syscall isn't supported in compatibility mode on Intel.
2135      * Normally we advertise the actual CPU vendor, but you can
2136      * override this using the 'vendor' property if you want to use
2137      * KVM's sysenter/syscall emulation in compatibility mode and
2138      * when doing cross vendor migration
2139      */
2140     vendor = def->vendor;
2141     if (kvm_enabled()) {
2142         uint32_t  ebx = 0, ecx = 0, edx = 0;
2143         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2144         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2145         vendor = host_vendor;
2146     }
2147
2148     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2149
2150 }
2151
2152 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
2153 {
2154     X86CPU *cpu = NULL;
2155     X86CPUClass *xcc;
2156     ObjectClass *oc;
2157     gchar **model_pieces;
2158     char *name, *features;
2159     Error *error = NULL;
2160
2161     model_pieces = g_strsplit(cpu_model, ",", 2);
2162     if (!model_pieces[0]) {
2163         error_setg(&error, "Invalid/empty CPU model name");
2164         goto out;
2165     }
2166     name = model_pieces[0];
2167     features = model_pieces[1];
2168
2169     oc = x86_cpu_class_by_name(name);
2170     if (oc == NULL) {
2171         error_setg(&error, "Unable to find CPU definition: %s", name);
2172         goto out;
2173     }
2174     xcc = X86_CPU_CLASS(oc);
2175
2176     if (xcc->kvm_required && !kvm_enabled()) {
2177         error_setg(&error, "CPU model '%s' requires KVM", name);
2178         goto out;
2179     }
2180
2181     cpu = X86_CPU(object_new(object_class_get_name(oc)));
2182
2183     x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2184     if (error) {
2185         goto out;
2186     }
2187
2188 out:
2189     if (error != NULL) {
2190         error_propagate(errp, error);
2191         if (cpu) {
2192             object_unref(OBJECT(cpu));
2193             cpu = NULL;
2194         }
2195     }
2196     g_strfreev(model_pieces);
2197     return cpu;
2198 }
2199
2200 X86CPU *cpu_x86_init(const char *cpu_model)
2201 {
2202     Error *error = NULL;
2203     X86CPU *cpu;
2204
2205     cpu = cpu_x86_create(cpu_model, &error);
2206     if (error) {
2207         goto out;
2208     }
2209
2210     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2211
2212 out:
2213     if (error) {
2214         error_report_err(error);
2215         if (cpu != NULL) {
2216             object_unref(OBJECT(cpu));
2217             cpu = NULL;
2218         }
2219     }
2220     return cpu;
2221 }
2222
2223 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2224 {
2225     X86CPUDefinition *cpudef = data;
2226     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2227
2228     xcc->cpu_def = cpudef;
2229 }
2230
2231 static void x86_register_cpudef_type(X86CPUDefinition *def)
2232 {
2233     char *typename = x86_cpu_type_name(def->name);
2234     TypeInfo ti = {
2235         .name = typename,
2236         .parent = TYPE_X86_CPU,
2237         .class_init = x86_cpu_cpudef_class_init,
2238         .class_data = def,
2239     };
2240
2241     type_register(&ti);
2242     g_free(typename);
2243 }
2244
2245 #if !defined(CONFIG_USER_ONLY)
2246
2247 void cpu_clear_apic_feature(CPUX86State *env)
2248 {
2249     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2250 }
2251
2252 #endif /* !CONFIG_USER_ONLY */
2253
2254 /* Initialize list of CPU models, filling some non-static fields if necessary
2255  */
2256 void x86_cpudef_setup(void)
2257 {
2258     int i, j;
2259     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2260
2261     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2262         X86CPUDefinition *def = &builtin_x86_defs[i];
2263
2264         /* Look for specific "cpudef" models that */
2265         /* have the QEMU version in .model_id */
2266         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2267             if (strcmp(model_with_versions[j], def->name) == 0) {
2268                 pstrcpy(def->model_id, sizeof(def->model_id),
2269                         "QEMU Virtual CPU version ");
2270                 pstrcat(def->model_id, sizeof(def->model_id),
2271                         qemu_hw_version());
2272                 break;
2273             }
2274         }
2275     }
2276 }
2277
2278 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2279                    uint32_t *eax, uint32_t *ebx,
2280                    uint32_t *ecx, uint32_t *edx)
2281 {
2282     X86CPU *cpu = x86_env_get_cpu(env);
2283     CPUState *cs = CPU(cpu);
2284
2285     /* test if maximum index reached */
2286     if (index & 0x80000000) {
2287         if (index > env->cpuid_xlevel) {
2288             if (env->cpuid_xlevel2 > 0) {
2289                 /* Handle the Centaur's CPUID instruction. */
2290                 if (index > env->cpuid_xlevel2) {
2291                     index = env->cpuid_xlevel2;
2292                 } else if (index < 0xC0000000) {
2293                     index = env->cpuid_xlevel;
2294                 }
2295             } else {
2296                 /* Intel documentation states that invalid EAX input will
2297                  * return the same information as EAX=cpuid_level
2298                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2299                  */
2300                 index =  env->cpuid_level;
2301             }
2302         }
2303     } else {
2304         if (index > env->cpuid_level)
2305             index = env->cpuid_level;
2306     }
2307
2308     switch(index) {
2309     case 0:
2310         *eax = env->cpuid_level;
2311         *ebx = env->cpuid_vendor1;
2312         *edx = env->cpuid_vendor2;
2313         *ecx = env->cpuid_vendor3;
2314         break;
2315     case 1:
2316         *eax = env->cpuid_version;
2317         *ebx = (cpu->apic_id << 24) |
2318                8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2319         *ecx = env->features[FEAT_1_ECX];
2320         if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2321             *ecx |= CPUID_EXT_OSXSAVE;
2322         }
2323         *edx = env->features[FEAT_1_EDX];
2324         if (cs->nr_cores * cs->nr_threads > 1) {
2325             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2326             *edx |= CPUID_HT;
2327         }
2328         break;
2329     case 2:
2330         /* cache info: needed for Pentium Pro compatibility */
2331         if (cpu->cache_info_passthrough) {
2332             host_cpuid(index, 0, eax, ebx, ecx, edx);
2333             break;
2334         }
2335         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2336         *ebx = 0;
2337         *ecx = 0;
2338         *edx = (L1D_DESCRIPTOR << 16) | \
2339                (L1I_DESCRIPTOR <<  8) | \
2340                (L2_DESCRIPTOR);
2341         break;
2342     case 4:
2343         /* cache info: needed for Core compatibility */
2344         if (cpu->cache_info_passthrough) {
2345             host_cpuid(index, count, eax, ebx, ecx, edx);
2346             *eax &= ~0xFC000000;
2347         } else {
2348             *eax = 0;
2349             switch (count) {
2350             case 0: /* L1 dcache info */
2351                 *eax |= CPUID_4_TYPE_DCACHE | \
2352                         CPUID_4_LEVEL(1) | \
2353                         CPUID_4_SELF_INIT_LEVEL;
2354                 *ebx = (L1D_LINE_SIZE - 1) | \
2355                        ((L1D_PARTITIONS - 1) << 12) | \
2356                        ((L1D_ASSOCIATIVITY - 1) << 22);
2357                 *ecx = L1D_SETS - 1;
2358                 *edx = CPUID_4_NO_INVD_SHARING;
2359                 break;
2360             case 1: /* L1 icache info */
2361                 *eax |= CPUID_4_TYPE_ICACHE | \
2362                         CPUID_4_LEVEL(1) | \
2363                         CPUID_4_SELF_INIT_LEVEL;
2364                 *ebx = (L1I_LINE_SIZE - 1) | \
2365                        ((L1I_PARTITIONS - 1) << 12) | \
2366                        ((L1I_ASSOCIATIVITY - 1) << 22);
2367                 *ecx = L1I_SETS - 1;
2368                 *edx = CPUID_4_NO_INVD_SHARING;
2369                 break;
2370             case 2: /* L2 cache info */
2371                 *eax |= CPUID_4_TYPE_UNIFIED | \
2372                         CPUID_4_LEVEL(2) | \
2373                         CPUID_4_SELF_INIT_LEVEL;
2374                 if (cs->nr_threads > 1) {
2375                     *eax |= (cs->nr_threads - 1) << 14;
2376                 }
2377                 *ebx = (L2_LINE_SIZE - 1) | \
2378                        ((L2_PARTITIONS - 1) << 12) | \
2379                        ((L2_ASSOCIATIVITY - 1) << 22);
2380                 *ecx = L2_SETS - 1;
2381                 *edx = CPUID_4_NO_INVD_SHARING;
2382                 break;
2383             default: /* end of info */
2384                 *eax = 0;
2385                 *ebx = 0;
2386                 *ecx = 0;
2387                 *edx = 0;
2388                 break;
2389             }
2390         }
2391
2392         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2393         if ((*eax & 31) && cs->nr_cores > 1) {
2394             *eax |= (cs->nr_cores - 1) << 26;
2395         }
2396         break;
2397     case 5:
2398         /* mwait info: needed for Core compatibility */
2399         *eax = 0; /* Smallest monitor-line size in bytes */
2400         *ebx = 0; /* Largest monitor-line size in bytes */
2401         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2402         *edx = 0;
2403         break;
2404     case 6:
2405         /* Thermal and Power Leaf */
2406         *eax = env->features[FEAT_6_EAX];
2407         *ebx = 0;
2408         *ecx = 0;
2409         *edx = 0;
2410         break;
2411     case 7:
2412         /* Structured Extended Feature Flags Enumeration Leaf */
2413         if (count == 0) {
2414             *eax = 0; /* Maximum ECX value for sub-leaves */
2415             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2416             *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
2417             *edx = 0; /* Reserved */
2418         } else {
2419             *eax = 0;
2420             *ebx = 0;
2421             *ecx = 0;
2422             *edx = 0;
2423         }
2424         break;
2425     case 9:
2426         /* Direct Cache Access Information Leaf */
2427         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2428         *ebx = 0;
2429         *ecx = 0;
2430         *edx = 0;
2431         break;
2432     case 0xA:
2433         /* Architectural Performance Monitoring Leaf */
2434         if (kvm_enabled() && cpu->enable_pmu) {
2435             KVMState *s = cs->kvm_state;
2436
2437             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2438             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2439             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2440             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2441         } else {
2442             *eax = 0;
2443             *ebx = 0;
2444             *ecx = 0;
2445             *edx = 0;
2446         }
2447         break;
2448     case 0xD: {
2449         KVMState *s = cs->kvm_state;
2450         uint64_t ena_mask;
2451         int i;
2452
2453         /* Processor Extended State */
2454         *eax = 0;
2455         *ebx = 0;
2456         *ecx = 0;
2457         *edx = 0;
2458         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2459             break;
2460         }
2461         if (kvm_enabled()) {
2462             ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2463             ena_mask <<= 32;
2464             ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2465         } else {
2466             ena_mask = -1;
2467         }
2468
2469         if (count == 0) {
2470             *ecx = 0x240;
2471             for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2472                 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2473                 if ((env->features[esa->feature] & esa->bits) == esa->bits
2474                     && ((ena_mask >> i) & 1) != 0) {
2475                     if (i < 32) {
2476                         *eax |= 1u << i;
2477                     } else {
2478                         *edx |= 1u << (i - 32);
2479                     }
2480                     *ecx = MAX(*ecx, esa->offset + esa->size);
2481                 }
2482             }
2483             *eax |= ena_mask & (XSTATE_FP | XSTATE_SSE);
2484             *ebx = *ecx;
2485         } else if (count == 1) {
2486             *eax = env->features[FEAT_XSAVE];
2487         } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2488             const ExtSaveArea *esa = &x86_ext_save_areas[count];
2489             if ((env->features[esa->feature] & esa->bits) == esa->bits
2490                 && ((ena_mask >> count) & 1) != 0) {
2491                 *eax = esa->size;
2492                 *ebx = esa->offset;
2493             }
2494         }
2495         break;
2496     }
2497     case 0x80000000:
2498         *eax = env->cpuid_xlevel;
2499         *ebx = env->cpuid_vendor1;
2500         *edx = env->cpuid_vendor2;
2501         *ecx = env->cpuid_vendor3;
2502         break;
2503     case 0x80000001:
2504         *eax = env->cpuid_version;
2505         *ebx = 0;
2506         *ecx = env->features[FEAT_8000_0001_ECX];
2507         *edx = env->features[FEAT_8000_0001_EDX];
2508
2509         /* The Linux kernel checks for the CMPLegacy bit and
2510          * discards multiple thread information if it is set.
2511          * So dont set it here for Intel to make Linux guests happy.
2512          */
2513         if (cs->nr_cores * cs->nr_threads > 1) {
2514             if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2515                 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2516                 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2517                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2518             }
2519         }
2520         break;
2521     case 0x80000002:
2522     case 0x80000003:
2523     case 0x80000004:
2524         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2525         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2526         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2527         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2528         break;
2529     case 0x80000005:
2530         /* cache info (L1 cache) */
2531         if (cpu->cache_info_passthrough) {
2532             host_cpuid(index, 0, eax, ebx, ecx, edx);
2533             break;
2534         }
2535         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2536                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2537         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2538                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2539         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2540                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2541         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2542                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2543         break;
2544     case 0x80000006:
2545         /* cache info (L2 cache) */
2546         if (cpu->cache_info_passthrough) {
2547             host_cpuid(index, 0, eax, ebx, ecx, edx);
2548             break;
2549         }
2550         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2551                (L2_DTLB_2M_ENTRIES << 16) | \
2552                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2553                (L2_ITLB_2M_ENTRIES);
2554         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2555                (L2_DTLB_4K_ENTRIES << 16) | \
2556                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2557                (L2_ITLB_4K_ENTRIES);
2558         *ecx = (L2_SIZE_KB_AMD << 16) | \
2559                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2560                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2561         *edx = ((L3_SIZE_KB/512) << 18) | \
2562                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2563                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2564         break;
2565     case 0x80000007:
2566         *eax = 0;
2567         *ebx = 0;
2568         *ecx = 0;
2569         *edx = env->features[FEAT_8000_0007_EDX];
2570         break;
2571     case 0x80000008:
2572         /* virtual & phys address size in low 2 bytes. */
2573 /* XXX: This value must match the one used in the MMU code. */
2574         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2575             /* 64 bit processor */
2576 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2577             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2578         } else {
2579             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2580                 *eax = 0x00000024; /* 36 bits physical */
2581             } else {
2582                 *eax = 0x00000020; /* 32 bits physical */
2583             }
2584         }
2585         *ebx = 0;
2586         *ecx = 0;
2587         *edx = 0;
2588         if (cs->nr_cores * cs->nr_threads > 1) {
2589             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2590         }
2591         break;
2592     case 0x8000000A:
2593         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2594             *eax = 0x00000001; /* SVM Revision */
2595             *ebx = 0x00000010; /* nr of ASIDs */
2596             *ecx = 0;
2597             *edx = env->features[FEAT_SVM]; /* optional features */
2598         } else {
2599             *eax = 0;
2600             *ebx = 0;
2601             *ecx = 0;
2602             *edx = 0;
2603         }
2604         break;
2605     case 0xC0000000:
2606         *eax = env->cpuid_xlevel2;
2607         *ebx = 0;
2608         *ecx = 0;
2609         *edx = 0;
2610         break;
2611     case 0xC0000001:
2612         /* Support for VIA CPU's CPUID instruction */
2613         *eax = env->cpuid_version;
2614         *ebx = 0;
2615         *ecx = 0;
2616         *edx = env->features[FEAT_C000_0001_EDX];
2617         break;
2618     case 0xC0000002:
2619     case 0xC0000003:
2620     case 0xC0000004:
2621         /* Reserved for the future, and now filled with zero */
2622         *eax = 0;
2623         *ebx = 0;
2624         *ecx = 0;
2625         *edx = 0;
2626         break;
2627     default:
2628         /* reserved values: zero */
2629         *eax = 0;
2630         *ebx = 0;
2631         *ecx = 0;
2632         *edx = 0;
2633         break;
2634     }
2635 }
2636
2637 /* CPUClass::reset() */
2638 static void x86_cpu_reset(CPUState *s)
2639 {
2640     X86CPU *cpu = X86_CPU(s);
2641     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2642     CPUX86State *env = &cpu->env;
2643     target_ulong cr4;
2644     uint64_t xcr0;
2645     int i;
2646
2647     xcc->parent_reset(s);
2648
2649     memset(env, 0, offsetof(CPUX86State, cpuid_level));
2650
2651     tlb_flush(s, 1);
2652
2653     env->old_exception = -1;
2654
2655     /* init to reset state */
2656
2657 #ifdef CONFIG_SOFTMMU
2658     env->hflags |= HF_SOFTMMU_MASK;
2659 #endif
2660     env->hflags2 |= HF2_GIF_MASK;
2661
2662     cpu_x86_update_cr0(env, 0x60000010);
2663     env->a20_mask = ~0x0;
2664     env->smbase = 0x30000;
2665
2666     env->idt.limit = 0xffff;
2667     env->gdt.limit = 0xffff;
2668     env->ldt.limit = 0xffff;
2669     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2670     env->tr.limit = 0xffff;
2671     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2672
2673     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2674                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2675                            DESC_R_MASK | DESC_A_MASK);
2676     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2677                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2678                            DESC_A_MASK);
2679     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2680                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2681                            DESC_A_MASK);
2682     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2683                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2684                            DESC_A_MASK);
2685     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2686                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2687                            DESC_A_MASK);
2688     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2689                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2690                            DESC_A_MASK);
2691
2692     env->eip = 0xfff0;
2693     env->regs[R_EDX] = env->cpuid_version;
2694
2695     env->eflags = 0x2;
2696
2697     /* FPU init */
2698     for (i = 0; i < 8; i++) {
2699         env->fptags[i] = 1;
2700     }
2701     cpu_set_fpuc(env, 0x37f);
2702
2703     env->mxcsr = 0x1f80;
2704     /* All units are in INIT state.  */
2705     env->xstate_bv = 0;
2706
2707     env->pat = 0x0007040600070406ULL;
2708     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2709
2710     memset(env->dr, 0, sizeof(env->dr));
2711     env->dr[6] = DR6_FIXED_1;
2712     env->dr[7] = DR7_FIXED_1;
2713     cpu_breakpoint_remove_all(s, BP_CPU);
2714     cpu_watchpoint_remove_all(s, BP_CPU);
2715
2716     cr4 = 0;
2717     xcr0 = XSTATE_FP;
2718
2719 #ifdef CONFIG_USER_ONLY
2720     /* Enable all the features for user-mode.  */
2721     if (env->features[FEAT_1_EDX] & CPUID_SSE) {
2722         xcr0 |= XSTATE_SSE;
2723     }
2724     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_MPX) {
2725         xcr0 |= XSTATE_BNDREGS | XSTATE_BNDCSR;
2726     }
2727     if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2728         cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2729     }
2730     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2731         cr4 |= CR4_FSGSBASE_MASK;
2732     }
2733 #endif
2734
2735     env->xcr0 = xcr0;
2736     cpu_x86_update_cr4(env, cr4);
2737
2738     /*
2739      * SDM 11.11.5 requires:
2740      *  - IA32_MTRR_DEF_TYPE MSR.E = 0
2741      *  - IA32_MTRR_PHYSMASKn.V = 0
2742      * All other bits are undefined.  For simplification, zero it all.
2743      */
2744     env->mtrr_deftype = 0;
2745     memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2746     memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2747
2748 #if !defined(CONFIG_USER_ONLY)
2749     /* We hard-wire the BSP to the first CPU. */
2750     apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2751
2752     s->halted = !cpu_is_bsp(cpu);
2753
2754     if (kvm_enabled()) {
2755         kvm_arch_reset_vcpu(cpu);
2756     }
2757 #endif
2758 }
2759
2760 #ifndef CONFIG_USER_ONLY
2761 bool cpu_is_bsp(X86CPU *cpu)
2762 {
2763     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2764 }
2765
2766 /* TODO: remove me, when reset over QOM tree is implemented */
2767 static void x86_cpu_machine_reset_cb(void *opaque)
2768 {
2769     X86CPU *cpu = opaque;
2770     cpu_reset(CPU(cpu));
2771 }
2772 #endif
2773
2774 static void mce_init(X86CPU *cpu)
2775 {
2776     CPUX86State *cenv = &cpu->env;
2777     unsigned int bank;
2778
2779     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2780         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2781             (CPUID_MCE | CPUID_MCA)) {
2782         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2783         cenv->mcg_ctl = ~(uint64_t)0;
2784         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2785             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2786         }
2787     }
2788 }
2789
2790 #ifndef CONFIG_USER_ONLY
2791 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2792 {
2793     APICCommonState *apic;
2794     const char *apic_type = "apic";
2795
2796     if (kvm_apic_in_kernel()) {
2797         apic_type = "kvm-apic";
2798     } else if (xen_enabled()) {
2799         apic_type = "xen-apic";
2800     }
2801
2802     cpu->apic_state = DEVICE(object_new(apic_type));
2803
2804     object_property_add_child(OBJECT(cpu), "apic",
2805                               OBJECT(cpu->apic_state), NULL);
2806     qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
2807     /* TODO: convert to link<> */
2808     apic = APIC_COMMON(cpu->apic_state);
2809     apic->cpu = cpu;
2810     apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
2811 }
2812
2813 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2814 {
2815     APICCommonState *apic;
2816     static bool apic_mmio_map_once;
2817
2818     if (cpu->apic_state == NULL) {
2819         return;
2820     }
2821     object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2822                              errp);
2823
2824     /* Map APIC MMIO area */
2825     apic = APIC_COMMON(cpu->apic_state);
2826     if (!apic_mmio_map_once) {
2827         memory_region_add_subregion_overlap(get_system_memory(),
2828                                             apic->apicbase &
2829                                             MSR_IA32_APICBASE_BASE,
2830                                             &apic->io_memory,
2831                                             0x1000);
2832         apic_mmio_map_once = true;
2833      }
2834 }
2835
2836 static void x86_cpu_machine_done(Notifier *n, void *unused)
2837 {
2838     X86CPU *cpu = container_of(n, X86CPU, machine_done);
2839     MemoryRegion *smram =
2840         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2841
2842     if (smram) {
2843         cpu->smram = g_new(MemoryRegion, 1);
2844         memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2845                                  smram, 0, 1ull << 32);
2846         memory_region_set_enabled(cpu->smram, false);
2847         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2848     }
2849 }
2850 #else
2851 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2852 {
2853 }
2854 #endif
2855
2856
2857 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2858                            (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2859                            (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2860 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2861                          (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2862                          (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2863 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2864 {
2865     CPUState *cs = CPU(dev);
2866     X86CPU *cpu = X86_CPU(dev);
2867     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2868     CPUX86State *env = &cpu->env;
2869     Error *local_err = NULL;
2870     static bool ht_warned;
2871
2872     if (cpu->apic_id < 0) {
2873         error_setg(errp, "apic-id property was not initialized properly");
2874         return;
2875     }
2876
2877     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2878         env->cpuid_level = 7;
2879     }
2880
2881     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2882      * CPUID[1].EDX.
2883      */
2884     if (IS_AMD_CPU(env)) {
2885         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2886         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2887            & CPUID_EXT2_AMD_ALIASES);
2888     }
2889
2890
2891     if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2892         error_setg(&local_err,
2893                    kvm_enabled() ?
2894                        "Host doesn't support requested features" :
2895                        "TCG doesn't support requested features");
2896         goto out;
2897     }
2898
2899 #ifndef CONFIG_USER_ONLY
2900     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2901
2902     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2903         x86_cpu_apic_create(cpu, &local_err);
2904         if (local_err != NULL) {
2905             goto out;
2906         }
2907     }
2908 #endif
2909
2910     mce_init(cpu);
2911
2912 #ifndef CONFIG_USER_ONLY
2913     if (tcg_enabled()) {
2914         AddressSpace *newas = g_new(AddressSpace, 1);
2915
2916         cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2917         cpu->cpu_as_root = g_new(MemoryRegion, 1);
2918
2919         /* Outer container... */
2920         memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2921         memory_region_set_enabled(cpu->cpu_as_root, true);
2922
2923         /* ... with two regions inside: normal system memory with low
2924          * priority, and...
2925          */
2926         memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2927                                  get_system_memory(), 0, ~0ull);
2928         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2929         memory_region_set_enabled(cpu->cpu_as_mem, true);
2930         address_space_init(newas, cpu->cpu_as_root, "CPU");
2931         cs->num_ases = 1;
2932         cpu_address_space_init(cs, newas, 0);
2933
2934         /* ... SMRAM with higher priority, linked from /machine/smram.  */
2935         cpu->machine_done.notify = x86_cpu_machine_done;
2936         qemu_add_machine_init_done_notifier(&cpu->machine_done);
2937     }
2938 #endif
2939
2940     qemu_init_vcpu(cs);
2941
2942     /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2943      * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2944      * based on inputs (sockets,cores,threads), it is still better to gives
2945      * users a warning.
2946      *
2947      * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2948      * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2949      */
2950     if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2951         error_report("AMD CPU doesn't support hyperthreading. Please configure"
2952                      " -smp options properly.");
2953         ht_warned = true;
2954     }
2955
2956     x86_cpu_apic_realize(cpu, &local_err);
2957     if (local_err != NULL) {
2958         goto out;
2959     }
2960     cpu_reset(cs);
2961
2962     xcc->parent_realize(dev, &local_err);
2963
2964 out:
2965     if (local_err != NULL) {
2966         error_propagate(errp, local_err);
2967         return;
2968     }
2969 }
2970
2971 typedef struct BitProperty {
2972     uint32_t *ptr;
2973     uint32_t mask;
2974 } BitProperty;
2975
2976 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
2977                                  void *opaque, Error **errp)
2978 {
2979     BitProperty *fp = opaque;
2980     bool value = (*fp->ptr & fp->mask) == fp->mask;
2981     visit_type_bool(v, name, &value, errp);
2982 }
2983
2984 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
2985                                  void *opaque, Error **errp)
2986 {
2987     DeviceState *dev = DEVICE(obj);
2988     BitProperty *fp = opaque;
2989     Error *local_err = NULL;
2990     bool value;
2991
2992     if (dev->realized) {
2993         qdev_prop_set_after_realize(dev, name, errp);
2994         return;
2995     }
2996
2997     visit_type_bool(v, name, &value, &local_err);
2998     if (local_err) {
2999         error_propagate(errp, local_err);
3000         return;
3001     }
3002
3003     if (value) {
3004         *fp->ptr |= fp->mask;
3005     } else {
3006         *fp->ptr &= ~fp->mask;
3007     }
3008 }
3009
3010 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3011                                      void *opaque)
3012 {
3013     BitProperty *prop = opaque;
3014     g_free(prop);
3015 }
3016
3017 /* Register a boolean property to get/set a single bit in a uint32_t field.
3018  *
3019  * The same property name can be registered multiple times to make it affect
3020  * multiple bits in the same FeatureWord. In that case, the getter will return
3021  * true only if all bits are set.
3022  */
3023 static void x86_cpu_register_bit_prop(X86CPU *cpu,
3024                                       const char *prop_name,
3025                                       uint32_t *field,
3026                                       int bitnr)
3027 {
3028     BitProperty *fp;
3029     ObjectProperty *op;
3030     uint32_t mask = (1UL << bitnr);
3031
3032     op = object_property_find(OBJECT(cpu), prop_name, NULL);
3033     if (op) {
3034         fp = op->opaque;
3035         assert(fp->ptr == field);
3036         fp->mask |= mask;
3037     } else {
3038         fp = g_new0(BitProperty, 1);
3039         fp->ptr = field;
3040         fp->mask = mask;
3041         object_property_add(OBJECT(cpu), prop_name, "bool",
3042                             x86_cpu_get_bit_prop,
3043                             x86_cpu_set_bit_prop,
3044                             x86_cpu_release_bit_prop, fp, &error_abort);
3045     }
3046 }
3047
3048 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3049                                                FeatureWord w,
3050                                                int bitnr)
3051 {
3052     Object *obj = OBJECT(cpu);
3053     int i;
3054     char **names;
3055     FeatureWordInfo *fi = &feature_word_info[w];
3056
3057     if (!fi->feat_names) {
3058         return;
3059     }
3060     if (!fi->feat_names[bitnr]) {
3061         return;
3062     }
3063
3064     names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3065
3066     feat2prop(names[0]);
3067     x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3068
3069     for (i = 1; names[i]; i++) {
3070         feat2prop(names[i]);
3071         object_property_add_alias(obj, names[i], obj, names[0],
3072                                   &error_abort);
3073     }
3074
3075     g_strfreev(names);
3076 }
3077
3078 static void x86_cpu_initfn(Object *obj)
3079 {
3080     CPUState *cs = CPU(obj);
3081     X86CPU *cpu = X86_CPU(obj);
3082     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3083     CPUX86State *env = &cpu->env;
3084     FeatureWord w;
3085     static int inited;
3086
3087     cs->env_ptr = env;
3088     cpu_exec_init(cs, &error_abort);
3089
3090     object_property_add(obj, "family", "int",
3091                         x86_cpuid_version_get_family,
3092                         x86_cpuid_version_set_family, NULL, NULL, NULL);
3093     object_property_add(obj, "model", "int",
3094                         x86_cpuid_version_get_model,
3095                         x86_cpuid_version_set_model, NULL, NULL, NULL);
3096     object_property_add(obj, "stepping", "int",
3097                         x86_cpuid_version_get_stepping,
3098                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3099     object_property_add_str(obj, "vendor",
3100                             x86_cpuid_get_vendor,
3101                             x86_cpuid_set_vendor, NULL);
3102     object_property_add_str(obj, "model-id",
3103                             x86_cpuid_get_model_id,
3104                             x86_cpuid_set_model_id, NULL);
3105     object_property_add(obj, "tsc-frequency", "int",
3106                         x86_cpuid_get_tsc_freq,
3107                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3108     object_property_add(obj, "apic-id", "int",
3109                         x86_cpuid_get_apic_id,
3110                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
3111     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3112                         x86_cpu_get_feature_words,
3113                         NULL, NULL, (void *)env->features, NULL);
3114     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3115                         x86_cpu_get_feature_words,
3116                         NULL, NULL, (void *)cpu->filtered_features, NULL);
3117
3118     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3119
3120 #ifndef CONFIG_USER_ONLY
3121     /* Any code creating new X86CPU objects have to set apic-id explicitly */
3122     cpu->apic_id = -1;
3123 #endif
3124
3125     for (w = 0; w < FEATURE_WORDS; w++) {
3126         int bitnr;
3127
3128         for (bitnr = 0; bitnr < 32; bitnr++) {
3129             x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3130         }
3131     }
3132
3133     x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3134
3135     /* init various static tables used in TCG mode */
3136     if (tcg_enabled() && !inited) {
3137         inited = 1;
3138         tcg_x86_init();
3139     }
3140 }
3141
3142 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3143 {
3144     X86CPU *cpu = X86_CPU(cs);
3145
3146     return cpu->apic_id;
3147 }
3148
3149 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3150 {
3151     X86CPU *cpu = X86_CPU(cs);
3152
3153     return cpu->env.cr[0] & CR0_PG_MASK;
3154 }
3155
3156 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3157 {
3158     X86CPU *cpu = X86_CPU(cs);
3159
3160     cpu->env.eip = value;
3161 }
3162
3163 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3164 {
3165     X86CPU *cpu = X86_CPU(cs);
3166
3167     cpu->env.eip = tb->pc - tb->cs_base;
3168 }
3169
3170 static bool x86_cpu_has_work(CPUState *cs)
3171 {
3172     X86CPU *cpu = X86_CPU(cs);
3173     CPUX86State *env = &cpu->env;
3174
3175     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3176                                       CPU_INTERRUPT_POLL)) &&
3177             (env->eflags & IF_MASK)) ||
3178            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3179                                      CPU_INTERRUPT_INIT |
3180                                      CPU_INTERRUPT_SIPI |
3181                                      CPU_INTERRUPT_MCE)) ||
3182            ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3183             !(env->hflags & HF_SMM_MASK));
3184 }
3185
3186 static Property x86_cpu_properties[] = {
3187     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3188     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
3189     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3190     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3191     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3192     DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
3193     DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
3194     DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
3195     DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
3196     DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
3197     DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
3198     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
3199     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3200     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3201     DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3202     DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
3203     DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
3204     DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
3205     DEFINE_PROP_END_OF_LIST()
3206 };
3207
3208 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3209 {
3210     X86CPUClass *xcc = X86_CPU_CLASS(oc);
3211     CPUClass *cc = CPU_CLASS(oc);
3212     DeviceClass *dc = DEVICE_CLASS(oc);
3213
3214     xcc->parent_realize = dc->realize;
3215     dc->realize = x86_cpu_realizefn;
3216     dc->props = x86_cpu_properties;
3217
3218     xcc->parent_reset = cc->reset;
3219     cc->reset = x86_cpu_reset;
3220     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3221
3222     cc->class_by_name = x86_cpu_class_by_name;
3223     cc->parse_features = x86_cpu_parse_featurestr;
3224     cc->has_work = x86_cpu_has_work;
3225     cc->do_interrupt = x86_cpu_do_interrupt;
3226     cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3227     cc->dump_state = x86_cpu_dump_state;
3228     cc->set_pc = x86_cpu_set_pc;
3229     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3230     cc->gdb_read_register = x86_cpu_gdb_read_register;
3231     cc->gdb_write_register = x86_cpu_gdb_write_register;
3232     cc->get_arch_id = x86_cpu_get_arch_id;
3233     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3234 #ifdef CONFIG_USER_ONLY
3235     cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3236 #else
3237     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3238     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3239     cc->write_elf64_note = x86_cpu_write_elf64_note;
3240     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3241     cc->write_elf32_note = x86_cpu_write_elf32_note;
3242     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3243     cc->vmsd = &vmstate_x86_cpu;
3244 #endif
3245     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3246 #ifndef CONFIG_USER_ONLY
3247     cc->debug_excp_handler = breakpoint_handler;
3248 #endif
3249     cc->cpu_exec_enter = x86_cpu_exec_enter;
3250     cc->cpu_exec_exit = x86_cpu_exec_exit;
3251
3252     /*
3253      * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3254      * object in cpus -> dangling pointer after final object_unref().
3255      */
3256     dc->cannot_destroy_with_object_finalize_yet = true;
3257 }
3258
3259 static const TypeInfo x86_cpu_type_info = {
3260     .name = TYPE_X86_CPU,
3261     .parent = TYPE_CPU,
3262     .instance_size = sizeof(X86CPU),
3263     .instance_init = x86_cpu_initfn,
3264     .abstract = true,
3265     .class_size = sizeof(X86CPUClass),
3266     .class_init = x86_cpu_common_class_init,
3267 };
3268
3269 static void x86_cpu_register_types(void)
3270 {
3271     int i;
3272
3273     type_register_static(&x86_cpu_type_info);
3274     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3275         x86_register_cpudef_type(&builtin_x86_defs[i]);
3276     }
3277 #ifdef CONFIG_KVM
3278     type_register_static(&host_x86_cpu_type_info);
3279 #endif
3280 }
3281
3282 type_init(x86_cpu_register_types)