target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "kvm_i386.h"
  28
  29 #include "qemu/error-report.h"
  30 #include "qemu/option.h"
  31 #include "qemu/config-file.h"
  32 #include "qapi/qmp/qerror.h"
  33
  34 #include "qapi-types.h"
  35 #include "qapi-visit.h"
  36 #include "qapi/visitor.h"
  37 #include "sysemu/arch_init.h"
  38
  39 #include "hw/hw.h"
  40 #if defined(CONFIG_KVM)
  41 #include <linux/kvm_para.h>
  42 #endif
  43
  44 #include "sysemu/sysemu.h"
  45 #include "hw/qdev-properties.h"
  46 #ifndef CONFIG_USER_ONLY
  47 #include "exec/address-spaces.h"
  48 #include "hw/xen/xen.h"
  49 #include "hw/i386/apic_internal.h"
  50 #endif
  51
  52
  53 /* Cache topology CPUID constants: */
  54
  55 /* CPUID Leaf 2 Descriptors */
  56
  57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  59 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  60
  61
  62 /* CPUID Leaf 4 constants: */
  63
  64 /* EAX: */
  65 #define CPUID_4_TYPE_DCACHE  1
  66 #define CPUID_4_TYPE_ICACHE  2
  67 #define CPUID_4_TYPE_UNIFIED 3
  68
  69 #define CPUID_4_LEVEL(l)          ((l) << 5)
  70
  71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  72 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  73
  74 /* EDX: */
  75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  76 #define CPUID_4_INCLUSIVE       (1 << 1)
  77 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  78
  79 #define ASSOC_FULL 0xFF
  80
  81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  82 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  83                           a ==   2 ? 0x2 : \
  84                           a ==   4 ? 0x4 : \
  85                           a ==   8 ? 0x6 : \
  86                           a ==  16 ? 0x8 : \
  87                           a ==  32 ? 0xA : \
  88                           a ==  48 ? 0xB : \
  89                           a ==  64 ? 0xC : \
  90                           a ==  96 ? 0xD : \
  91                           a == 128 ? 0xE : \
  92                           a == ASSOC_FULL ? 0xF : \
  93                           0 /* invalid value */)
  94
  95
  96 /* Definitions of the hardcoded cache entries we expose: */
  97
  98 /* L1 data cache: */
  99 #define L1D_LINE_SIZE         64
 100 #define L1D_ASSOCIATIVITY      8
 101 #define L1D_SETS              64
 102 #define L1D_PARTITIONS         1
 103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 106 #define L1D_LINES_PER_TAG      1
 107 #define L1D_SIZE_KB_AMD       64
 108 #define L1D_ASSOCIATIVITY_AMD  2
 109
 110 /* L1 instruction cache: */
 111 #define L1I_LINE_SIZE         64
 112 #define L1I_ASSOCIATIVITY      8
 113 #define L1I_SETS              64
 114 #define L1I_PARTITIONS         1
 115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 118 #define L1I_LINES_PER_TAG      1
 119 #define L1I_SIZE_KB_AMD       64
 120 #define L1I_ASSOCIATIVITY_AMD  2
 121
 122 /* Level 2 unified cache: */
 123 #define L2_LINE_SIZE          64
 124 #define L2_ASSOCIATIVITY      16
 125 #define L2_SETS             4096
 126 #define L2_PARTITIONS          1
 127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 131 #define L2_LINES_PER_TAG       1
 132 #define L2_SIZE_KB_AMD       512
 133
 134 /* No L3 cache: */
 135 #define L3_SIZE_KB             0 /* disabled */
 136 #define L3_ASSOCIATIVITY       0 /* disabled */
 137 #define L3_LINES_PER_TAG       0 /* disabled */
 138 #define L3_LINE_SIZE           0 /* disabled */
 139
 140 /* TLB definitions: */
 141
 142 #define L1_DTLB_2M_ASSOC       1
 143 #define L1_DTLB_2M_ENTRIES   255
 144 #define L1_DTLB_4K_ASSOC       1
 145 #define L1_DTLB_4K_ENTRIES   255
 146
 147 #define L1_ITLB_2M_ASSOC       1
 148 #define L1_ITLB_2M_ENTRIES   255
 149 #define L1_ITLB_4K_ASSOC       1
 150 #define L1_ITLB_4K_ENTRIES   255
 151
 152 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 153 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 154 #define L2_DTLB_4K_ASSOC       4
 155 #define L2_DTLB_4K_ENTRIES   512
 156
 157 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 158 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 159 #define L2_ITLB_4K_ASSOC       4
 160 #define L2_ITLB_4K_ENTRIES   512
 161
 162
 163
 164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 165                                      uint32_t vendor2, uint32_t vendor3)
 166 {
 167     int i;
 168     for (i = 0; i < 4; i++) {
 169         dst[i] = vendor1 >> (8 * i);
 170         dst[i + 4] = vendor2 >> (8 * i);
 171         dst[i + 8] = vendor3 >> (8 * i);
 172     }
 173     dst[CPUID_VENDOR_SZ] = '\0';
 174 }
 175
 176 /* feature flags taken from "Intel Processor Identification and the CPUID
 177  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 178  * between feature naming conventions, aliases may be added.
 179  */
 180 static const char *feature_name[] = {
 181     "fpu", "vme", "de", "pse",
 182     "tsc", "msr", "pae", "mce",
 183     "cx8", "apic", NULL, "sep",
 184     "mtrr", "pge", "mca", "cmov",
 185     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 186     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 187     "fxsr", "sse", "sse2", "ss",
 188     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 189 };
 190 static const char *ext_feature_name[] = {
 191     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 192     "ds_cpl", "vmx", "smx", "est",
 193     "tm2", "ssse3", "cid", NULL,
 194     "fma", "cx16", "xtpr", "pdcm",
 195     NULL, "pcid", "dca", "sse4.1|sse4_1",
 196     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 197     "tsc-deadline", "aes", "xsave", "osxsave",
 198     "avx", "f16c", "rdrand", "hypervisor",
 199 };
 200 /* Feature names that are already defined on feature_name[] but are set on
 201  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 202  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 203  * if and only if CPU vendor is AMD.
 204  */
 205 static const char *ext2_feature_name[] = {
 206     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 207     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 208     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 209     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 210     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 211     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 212     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 213     NULL, "lm|i64", "3dnowext", "3dnow",
 214 };
 215 static const char *ext3_feature_name[] = {
 216     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 217     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 218     "3dnowprefetch", "osvw", "ibs", "xop",
 219     "skinit", "wdt", NULL, "lwp",
 220     "fma4", "tce", NULL, "nodeid_msr",
 221     NULL, "tbm", "topoext", "perfctr_core",
 222     "perfctr_nb", NULL, NULL, NULL,
 223     NULL, NULL, NULL, NULL,
 224 };
 225
 226 static const char *ext4_feature_name[] = {
 227     NULL, NULL, "xstore", "xstore-en",
 228     NULL, NULL, "xcrypt", "xcrypt-en",
 229     "ace2", "ace2-en", "phe", "phe-en",
 230     "pmm", "pmm-en", NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232     NULL, NULL, NULL, NULL,
 233     NULL, NULL, NULL, NULL,
 234     NULL, NULL, NULL, NULL,
 235 };
 236
 237 static const char *kvm_feature_name[] = {
 238     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 239     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 240     NULL, NULL, NULL, NULL,
 241     NULL, NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243     NULL, NULL, NULL, NULL,
 244     "kvmclock-stable-bit", NULL, NULL, NULL,
 245     NULL, NULL, NULL, NULL,
 246 };
 247
 248 static const char *svm_feature_name[] = {
 249     "npt", "lbrv", "svm_lock", "nrip_save",
 250     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 251     NULL, NULL, "pause_filter", NULL,
 252     "pfthreshold", NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254     NULL, NULL, NULL, NULL,
 255     NULL, NULL, NULL, NULL,
 256     NULL, NULL, NULL, NULL,
 257 };
 258
 259 static const char *cpuid_7_0_ebx_feature_name[] = {
 260     "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
 261     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
 262     "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
 263     "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
 264 };
 265
 266 static const char *cpuid_apm_edx_feature_name[] = {
 267     NULL, NULL, NULL, NULL,
 268     NULL, NULL, NULL, NULL,
 269     "invtsc", NULL, NULL, NULL,
 270     NULL, NULL, NULL, NULL,
 271     NULL, NULL, NULL, NULL,
 272     NULL, NULL, NULL, NULL,
 273     NULL, NULL, NULL, NULL,
 274     NULL, NULL, NULL, NULL,
 275 };
 276
 277 static const char *cpuid_xsave_feature_name[] = {
 278     "xsaveopt", "xsavec", "xgetbv1", "xsaves",
 279     NULL, NULL, NULL, NULL,
 280     NULL, NULL, NULL, NULL,
 281     NULL, NULL, NULL, NULL,
 282     NULL, NULL, NULL, NULL,
 283     NULL, NULL, NULL, NULL,
 284     NULL, NULL, NULL, NULL,
 285     NULL, NULL, NULL, NULL,
 286 };
 287
 288 static const char *cpuid_6_feature_name[] = {
 289     NULL, NULL, "arat", NULL,
 290     NULL, NULL, NULL, NULL,
 291     NULL, NULL, NULL, NULL,
 292     NULL, NULL, NULL, NULL,
 293     NULL, NULL, NULL, NULL,
 294     NULL, NULL, NULL, NULL,
 295     NULL, NULL, NULL, NULL,
 296     NULL, NULL, NULL, NULL,
 297 };
 298
 299 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 300 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 301           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 302 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 303           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 304           CPUID_PSE36 | CPUID_FXSR)
 305 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 306 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 307           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 308           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 309           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 310
 311 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 312           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 313           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 314           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 315           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
 316           /* partly implemented:
 317           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 318           /* missing:
 319           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 320 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 321           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 322           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 323           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 324           /* missing:
 325           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 326           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 327           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 328           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 329           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 330           CPUID_EXT_RDRAND */
 331
 332 #ifdef TARGET_X86_64
 333 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
 334 #else
 335 #define TCG_EXT2_X86_64_FEATURES 0
 336 #endif
 337
 338 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 339           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 340           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
 341           TCG_EXT2_X86_64_FEATURES)
 342 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 343           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 344 #define TCG_EXT4_FEATURES 0
 345 #define TCG_SVM_FEATURES 0
 346 #define TCG_KVM_FEATURES 0
 347 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
 348           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
 349           CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
 350           CPUID_7_0_EBX_CLWB)
 351           /* missing:
 352           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 353           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 354           CPUID_7_0_EBX_RDSEED */
 355 #define TCG_APM_FEATURES 0
 356 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 357
 358
 359 typedef struct FeatureWordInfo {
 360     const char **feat_names;
 361     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 362     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 363     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 364     int cpuid_reg;        /* output register (R_* constant) */
 365     uint32_t tcg_features; /* Feature flags supported by TCG */
 366     uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
 367 } FeatureWordInfo;
 368
 369 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 370     [FEAT_1_EDX] = {
 371         .feat_names = feature_name,
 372         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 373         .tcg_features = TCG_FEATURES,
 374     },
 375     [FEAT_1_ECX] = {
 376         .feat_names = ext_feature_name,
 377         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 378         .tcg_features = TCG_EXT_FEATURES,
 379     },
 380     [FEAT_8000_0001_EDX] = {
 381         .feat_names = ext2_feature_name,
 382         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 383         .tcg_features = TCG_EXT2_FEATURES,
 384     },
 385     [FEAT_8000_0001_ECX] = {
 386         .feat_names = ext3_feature_name,
 387         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 388         .tcg_features = TCG_EXT3_FEATURES,
 389     },
 390     [FEAT_C000_0001_EDX] = {
 391         .feat_names = ext4_feature_name,
 392         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 393         .tcg_features = TCG_EXT4_FEATURES,
 394     },
 395     [FEAT_KVM] = {
 396         .feat_names = kvm_feature_name,
 397         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 398         .tcg_features = TCG_KVM_FEATURES,
 399     },
 400     [FEAT_SVM] = {
 401         .feat_names = svm_feature_name,
 402         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 403         .tcg_features = TCG_SVM_FEATURES,
 404     },
 405     [FEAT_7_0_EBX] = {
 406         .feat_names = cpuid_7_0_ebx_feature_name,
 407         .cpuid_eax = 7,
 408         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 409         .cpuid_reg = R_EBX,
 410         .tcg_features = TCG_7_0_EBX_FEATURES,
 411     },
 412     [FEAT_8000_0007_EDX] = {
 413         .feat_names = cpuid_apm_edx_feature_name,
 414         .cpuid_eax = 0x80000007,
 415         .cpuid_reg = R_EDX,
 416         .tcg_features = TCG_APM_FEATURES,
 417         .unmigratable_flags = CPUID_APM_INVTSC,
 418     },
 419     [FEAT_XSAVE] = {
 420         .feat_names = cpuid_xsave_feature_name,
 421         .cpuid_eax = 0xd,
 422         .cpuid_needs_ecx = true, .cpuid_ecx = 1,
 423         .cpuid_reg = R_EAX,
 424         .tcg_features = 0,
 425     },
 426     [FEAT_6_EAX] = {
 427         .feat_names = cpuid_6_feature_name,
 428         .cpuid_eax = 6, .cpuid_reg = R_EAX,
 429         .tcg_features = TCG_6_EAX_FEATURES,
 430     },
 431 };
 432
 433 typedef struct X86RegisterInfo32 {
 434     /* Name of register */
 435     const char *name;
 436     /* QAPI enum value register */
 437     X86CPURegister32 qapi_enum;
 438 } X86RegisterInfo32;
 439
 440 #define REGISTER(reg) \
 441     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 442 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 443     REGISTER(EAX),
 444     REGISTER(ECX),
 445     REGISTER(EDX),
 446     REGISTER(EBX),
 447     REGISTER(ESP),
 448     REGISTER(EBP),
 449     REGISTER(ESI),
 450     REGISTER(EDI),
 451 };
 452 #undef REGISTER
 453
 454 typedef struct ExtSaveArea {
 455     uint32_t feature, bits;
 456     uint32_t offset, size;
 457 } ExtSaveArea;
 458
 459 static const ExtSaveArea ext_save_areas[] = {
 460     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 461             .offset = 0x240, .size = 0x100 },
 462     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 463             .offset = 0x3c0, .size = 0x40  },
 464     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 465             .offset = 0x400, .size = 0x40  },
 466     [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 467             .offset = 0x440, .size = 0x40 },
 468     [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 469             .offset = 0x480, .size = 0x200 },
 470     [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
 471             .offset = 0x680, .size = 0x400 },
 472 };
 473
 474 const char *get_register_name_32(unsigned int reg)
 475 {
 476     if (reg >= CPU_NB_REGS32) {
 477         return NULL;
 478     }
 479     return x86_reg_info_32[reg].name;
 480 }
 481
 482 /*
 483  * Returns the set of feature flags that are supported and migratable by
 484  * QEMU, for a given FeatureWord.
 485  */
 486 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
 487 {
 488     FeatureWordInfo *wi = &feature_word_info[w];
 489     uint32_t r = 0;
 490     int i;
 491
 492     for (i = 0; i < 32; i++) {
 493         uint32_t f = 1U << i;
 494         /* If the feature name is unknown, it is not supported by QEMU yet */
 495         if (!wi->feat_names[i]) {
 496             continue;
 497         }
 498         /* Skip features known to QEMU, but explicitly marked as unmigratable */
 499         if (wi->unmigratable_flags & f) {
 500             continue;
 501         }
 502         r |= f;
 503     }
 504     return r;
 505 }
 506
 507 void host_cpuid(uint32_t function, uint32_t count,
 508                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 509 {
 510     uint32_t vec[4];
 511
 512 #ifdef __x86_64__
 513     asm volatile("cpuid"
 514                  : "=a"(vec[0]), "=b"(vec[1]),
 515                    "=c"(vec[2]), "=d"(vec[3])
 516                  : "0"(function), "c"(count) : "cc");
 517 #elif defined(__i386__)
 518     asm volatile("pusha \n\t"
 519                  "cpuid \n\t"
 520                  "mov %%eax, 0(%2) \n\t"
 521                  "mov %%ebx, 4(%2) \n\t"
 522                  "mov %%ecx, 8(%2) \n\t"
 523                  "mov %%edx, 12(%2) \n\t"
 524                  "popa"
 525                  : : "a"(function), "c"(count), "S"(vec)
 526                  : "memory", "cc");
 527 #else
 528     abort();
 529 #endif
 530
 531     if (eax)
 532         *eax = vec[0];
 533     if (ebx)
 534         *ebx = vec[1];
 535     if (ecx)
 536         *ecx = vec[2];
 537     if (edx)
 538         *edx = vec[3];
 539 }
 540
 541 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 542
 543 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 544  * a substring.  ex if !NULL points to the first char after a substring,
 545  * otherwise the string is assumed to sized by a terminating nul.
 546  * Return lexical ordering of *s1:*s2.
 547  */
 548 static int sstrcmp(const char *s1, const char *e1,
 549                    const char *s2, const char *e2)
 550 {
 551     for (;;) {
 552         if (!*s1 || !*s2 || *s1 != *s2)
 553             return (*s1 - *s2);
 554         ++s1, ++s2;
 555         if (s1 == e1 && s2 == e2)
 556             return (0);
 557         else if (s1 == e1)
 558             return (*s2);
 559         else if (s2 == e2)
 560             return (*s1);
 561     }
 562 }
 563
 564 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 565  * '|' delimited (possibly empty) strings in which case search for a match
 566  * within the alternatives proceeds left to right.  Return 0 for success,
 567  * non-zero otherwise.
 568  */
 569 static int altcmp(const char *s, const char *e, const char *altstr)
 570 {
 571     const char *p, *q;
 572
 573     for (q = p = altstr; ; ) {
 574         while (*p && *p != '|')
 575             ++p;
 576         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 577             return (0);
 578         if (!*p)
 579             return (1);
 580         else
 581             q = ++p;
 582     }
 583 }
 584
 585 /* search featureset for flag *[s..e), if found set corresponding bit in
 586  * *pval and return true, otherwise return false
 587  */
 588 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 589                            const char **featureset)
 590 {
 591     uint32_t mask;
 592     const char **ppc;
 593     bool found = false;
 594
 595     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 596         if (*ppc && !altcmp(s, e, *ppc)) {
 597             *pval |= mask;
 598             found = true;
 599         }
 600     }
 601     return found;
 602 }
 603
 604 static void add_flagname_to_bitmaps(const char *flagname,
 605                                     FeatureWordArray words,
 606                                     Error **errp)
 607 {
 608     FeatureWord w;
 609     for (w = 0; w < FEATURE_WORDS; w++) {
 610         FeatureWordInfo *wi = &feature_word_info[w];
 611         if (wi->feat_names &&
 612             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 613             break;
 614         }
 615     }
 616     if (w == FEATURE_WORDS) {
 617         error_setg(errp, "CPU feature %s not found", flagname);
 618     }
 619 }
 620
 621 /* CPU class name definitions: */
 622
 623 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 624 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 625
 626 /* Return type name for a given CPU model name
 627  * Caller is responsible for freeing the returned string.
 628  */
 629 static char *x86_cpu_type_name(const char *model_name)
 630 {
 631     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
 632 }
 633
 634 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
 635 {
 636     ObjectClass *oc;
 637     char *typename;
 638
 639     if (cpu_model == NULL) {
 640         return NULL;
 641     }
 642
 643     typename = x86_cpu_type_name(cpu_model);
 644     oc = object_class_by_name(typename);
 645     g_free(typename);
 646     return oc;
 647 }
 648
 649 struct X86CPUDefinition {
 650     const char *name;
 651     uint32_t level;
 652     uint32_t xlevel;
 653     uint32_t xlevel2;
 654     /* vendor is zero-terminated, 12 character ASCII string */
 655     char vendor[CPUID_VENDOR_SZ + 1];
 656     int family;
 657     int model;
 658     int stepping;
 659     FeatureWordArray features;
 660     char model_id[48];
 661 };
 662
 663 static X86CPUDefinition builtin_x86_defs[] = {
 664     {
 665         .name = "qemu64",
 666         .level = 0xd,
 667         .vendor = CPUID_VENDOR_AMD,
 668         .family = 6,
 669         .model = 6,
 670         .stepping = 3,
 671         .features[FEAT_1_EDX] =
 672             PPRO_FEATURES |
 673             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 674             CPUID_PSE36,
 675         .features[FEAT_1_ECX] =
 676             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 677         .features[FEAT_8000_0001_EDX] =
 678             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 679         .features[FEAT_8000_0001_ECX] =
 680             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
 681         .xlevel = 0x8000000A,
 682     },
 683     {
 684         .name = "phenom",
 685         .level = 5,
 686         .vendor = CPUID_VENDOR_AMD,
 687         .family = 16,
 688         .model = 2,
 689         .stepping = 3,
 690         /* Missing: CPUID_HT */
 691         .features[FEAT_1_EDX] =
 692             PPRO_FEATURES |
 693             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 694             CPUID_PSE36 | CPUID_VME,
 695         .features[FEAT_1_ECX] =
 696             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 697             CPUID_EXT_POPCNT,
 698         .features[FEAT_8000_0001_EDX] =
 699             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 700             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 701             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 702         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 703                     CPUID_EXT3_CR8LEG,
 704                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 705                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 706         .features[FEAT_8000_0001_ECX] =
 707             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 708             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 709         /* Missing: CPUID_SVM_LBRV */
 710         .features[FEAT_SVM] =
 711             CPUID_SVM_NPT,
 712         .xlevel = 0x8000001A,
 713         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 714     },
 715     {
 716         .name = "core2duo",
 717         .level = 10,
 718         .vendor = CPUID_VENDOR_INTEL,
 719         .family = 6,
 720         .model = 15,
 721         .stepping = 11,
 722         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 723         .features[FEAT_1_EDX] =
 724             PPRO_FEATURES |
 725             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 726             CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
 727         /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
 728          * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
 729         .features[FEAT_1_ECX] =
 730             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 731             CPUID_EXT_CX16,
 732         .features[FEAT_8000_0001_EDX] =
 733             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 734         .features[FEAT_8000_0001_ECX] =
 735             CPUID_EXT3_LAHF_LM,
 736         .xlevel = 0x80000008,
 737         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 738     },
 739     {
 740         .name = "kvm64",
 741         .level = 0xd,
 742         .vendor = CPUID_VENDOR_INTEL,
 743         .family = 15,
 744         .model = 6,
 745         .stepping = 1,
 746         /* Missing: CPUID_HT */
 747         .features[FEAT_1_EDX] =
 748             PPRO_FEATURES | CPUID_VME |
 749             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 750             CPUID_PSE36,
 751         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 752         .features[FEAT_1_ECX] =
 753             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 754         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 755         .features[FEAT_8000_0001_EDX] =
 756             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 757         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 758                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 759                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 760                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 761         .features[FEAT_8000_0001_ECX] =
 762             0,
 763         .xlevel = 0x80000008,
 764         .model_id = "Common KVM processor"
 765     },
 766     {
 767         .name = "qemu32",
 768         .level = 4,
 769         .vendor = CPUID_VENDOR_INTEL,
 770         .family = 6,
 771         .model = 6,
 772         .stepping = 3,
 773         .features[FEAT_1_EDX] =
 774             PPRO_FEATURES,
 775         .features[FEAT_1_ECX] =
 776             CPUID_EXT_SSE3,
 777         .xlevel = 0x80000004,
 778     },
 779     {
 780         .name = "kvm32",
 781         .level = 5,
 782         .vendor = CPUID_VENDOR_INTEL,
 783         .family = 15,
 784         .model = 6,
 785         .stepping = 1,
 786         .features[FEAT_1_EDX] =
 787             PPRO_FEATURES | CPUID_VME |
 788             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 789         .features[FEAT_1_ECX] =
 790             CPUID_EXT_SSE3,
 791         .features[FEAT_8000_0001_ECX] =
 792             0,
 793         .xlevel = 0x80000008,
 794         .model_id = "Common 32-bit KVM processor"
 795     },
 796     {
 797         .name = "coreduo",
 798         .level = 10,
 799         .vendor = CPUID_VENDOR_INTEL,
 800         .family = 6,
 801         .model = 14,
 802         .stepping = 8,
 803         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 804         .features[FEAT_1_EDX] =
 805             PPRO_FEATURES | CPUID_VME |
 806             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
 807             CPUID_SS,
 808         /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
 809          * CPUID_EXT_PDCM, CPUID_EXT_VMX */
 810         .features[FEAT_1_ECX] =
 811             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
 812         .features[FEAT_8000_0001_EDX] =
 813             CPUID_EXT2_NX,
 814         .xlevel = 0x80000008,
 815         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 816     },
 817     {
 818         .name = "486",
 819         .level = 1,
 820         .vendor = CPUID_VENDOR_INTEL,
 821         .family = 4,
 822         .model = 8,
 823         .stepping = 0,
 824         .features[FEAT_1_EDX] =
 825             I486_FEATURES,
 826         .xlevel = 0,
 827     },
 828     {
 829         .name = "pentium",
 830         .level = 1,
 831         .vendor = CPUID_VENDOR_INTEL,
 832         .family = 5,
 833         .model = 4,
 834         .stepping = 3,
 835         .features[FEAT_1_EDX] =
 836             PENTIUM_FEATURES,
 837         .xlevel = 0,
 838     },
 839     {
 840         .name = "pentium2",
 841         .level = 2,
 842         .vendor = CPUID_VENDOR_INTEL,
 843         .family = 6,
 844         .model = 5,
 845         .stepping = 2,
 846         .features[FEAT_1_EDX] =
 847             PENTIUM2_FEATURES,
 848         .xlevel = 0,
 849     },
 850     {
 851         .name = "pentium3",
 852         .level = 3,
 853         .vendor = CPUID_VENDOR_INTEL,
 854         .family = 6,
 855         .model = 7,
 856         .stepping = 3,
 857         .features[FEAT_1_EDX] =
 858             PENTIUM3_FEATURES,
 859         .xlevel = 0,
 860     },
 861     {
 862         .name = "athlon",
 863         .level = 2,
 864         .vendor = CPUID_VENDOR_AMD,
 865         .family = 6,
 866         .model = 2,
 867         .stepping = 3,
 868         .features[FEAT_1_EDX] =
 869             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 870             CPUID_MCA,
 871         .features[FEAT_8000_0001_EDX] =
 872             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 873         .xlevel = 0x80000008,
 874     },
 875     {
 876         .name = "n270",
 877         .level = 10,
 878         .vendor = CPUID_VENDOR_INTEL,
 879         .family = 6,
 880         .model = 28,
 881         .stepping = 2,
 882         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
 883         .features[FEAT_1_EDX] =
 884             PPRO_FEATURES |
 885             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
 886             CPUID_ACPI | CPUID_SS,
 887             /* Some CPUs got no CPUID_SEP */
 888         /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
 889          * CPUID_EXT_XTPR */
 890         .features[FEAT_1_ECX] =
 891             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 892             CPUID_EXT_MOVBE,
 893         .features[FEAT_8000_0001_EDX] =
 894             CPUID_EXT2_NX,
 895         .features[FEAT_8000_0001_ECX] =
 896             CPUID_EXT3_LAHF_LM,
 897         .xlevel = 0x80000008,
 898         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 899     },
 900     {
 901         .name = "Conroe",
 902         .level = 10,
 903         .vendor = CPUID_VENDOR_INTEL,
 904         .family = 6,
 905         .model = 15,
 906         .stepping = 3,
 907         .features[FEAT_1_EDX] =
 908             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 909             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 910             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 911             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 912             CPUID_DE | CPUID_FP87,
 913         .features[FEAT_1_ECX] =
 914             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 915         .features[FEAT_8000_0001_EDX] =
 916             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 917         .features[FEAT_8000_0001_ECX] =
 918             CPUID_EXT3_LAHF_LM,
 919         .xlevel = 0x80000008,
 920         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 921     },
 922     {
 923         .name = "Penryn",
 924         .level = 10,
 925         .vendor = CPUID_VENDOR_INTEL,
 926         .family = 6,
 927         .model = 23,
 928         .stepping = 3,
 929         .features[FEAT_1_EDX] =
 930             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 931             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 932             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 933             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 934             CPUID_DE | CPUID_FP87,
 935         .features[FEAT_1_ECX] =
 936             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 937             CPUID_EXT_SSE3,
 938         .features[FEAT_8000_0001_EDX] =
 939             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 940         .features[FEAT_8000_0001_ECX] =
 941             CPUID_EXT3_LAHF_LM,
 942         .xlevel = 0x80000008,
 943         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 944     },
 945     {
 946         .name = "Nehalem",
 947         .level = 11,
 948         .vendor = CPUID_VENDOR_INTEL,
 949         .family = 6,
 950         .model = 26,
 951         .stepping = 3,
 952         .features[FEAT_1_EDX] =
 953             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 954             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 955             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 956             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 957             CPUID_DE | CPUID_FP87,
 958         .features[FEAT_1_ECX] =
 959             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 960             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 961         .features[FEAT_8000_0001_EDX] =
 962             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 963         .features[FEAT_8000_0001_ECX] =
 964             CPUID_EXT3_LAHF_LM,
 965         .xlevel = 0x80000008,
 966         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 967     },
 968     {
 969         .name = "Westmere",
 970         .level = 11,
 971         .vendor = CPUID_VENDOR_INTEL,
 972         .family = 6,
 973         .model = 44,
 974         .stepping = 1,
 975         .features[FEAT_1_EDX] =
 976             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 977             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 978             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 979             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 980             CPUID_DE | CPUID_FP87,
 981         .features[FEAT_1_ECX] =
 982             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 983             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 984             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 985         .features[FEAT_8000_0001_EDX] =
 986             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 987         .features[FEAT_8000_0001_ECX] =
 988             CPUID_EXT3_LAHF_LM,
 989         .features[FEAT_6_EAX] =
 990             CPUID_6_EAX_ARAT,
 991         .xlevel = 0x80000008,
 992         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 993     },
 994     {
 995         .name = "SandyBridge",
 996         .level = 0xd,
 997         .vendor = CPUID_VENDOR_INTEL,
 998         .family = 6,
 999         .model = 42,
1000         .stepping = 1,
1001         .features[FEAT_1_EDX] =
1002             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1003             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1004             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1005             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1006             CPUID_DE | CPUID_FP87,
1007         .features[FEAT_1_ECX] =
1008             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1009             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1010             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1011             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1012             CPUID_EXT_SSE3,
1013         .features[FEAT_8000_0001_EDX] =
1014             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1015             CPUID_EXT2_SYSCALL,
1016         .features[FEAT_8000_0001_ECX] =
1017             CPUID_EXT3_LAHF_LM,
1018         .features[FEAT_XSAVE] =
1019             CPUID_XSAVE_XSAVEOPT,
1020         .features[FEAT_6_EAX] =
1021             CPUID_6_EAX_ARAT,
1022         .xlevel = 0x80000008,
1023         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1024     },
1025     {
1026         .name = "IvyBridge",
1027         .level = 0xd,
1028         .vendor = CPUID_VENDOR_INTEL,
1029         .family = 6,
1030         .model = 58,
1031         .stepping = 9,
1032         .features[FEAT_1_EDX] =
1033             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1034             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037             CPUID_DE | CPUID_FP87,
1038         .features[FEAT_1_ECX] =
1039             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1040             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1041             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1042             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1043             CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1044         .features[FEAT_7_0_EBX] =
1045             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1046             CPUID_7_0_EBX_ERMS,
1047         .features[FEAT_8000_0001_EDX] =
1048             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1049             CPUID_EXT2_SYSCALL,
1050         .features[FEAT_8000_0001_ECX] =
1051             CPUID_EXT3_LAHF_LM,
1052         .features[FEAT_XSAVE] =
1053             CPUID_XSAVE_XSAVEOPT,
1054         .features[FEAT_6_EAX] =
1055             CPUID_6_EAX_ARAT,
1056         .xlevel = 0x80000008,
1057         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1058     },
1059     {
1060         .name = "Haswell-noTSX",
1061         .level = 0xd,
1062         .vendor = CPUID_VENDOR_INTEL,
1063         .family = 6,
1064         .model = 60,
1065         .stepping = 1,
1066         .features[FEAT_1_EDX] =
1067             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071             CPUID_DE | CPUID_FP87,
1072         .features[FEAT_1_ECX] =
1073             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1074             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1075             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1076             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1077             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1078             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1079         .features[FEAT_8000_0001_EDX] =
1080             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1081             CPUID_EXT2_SYSCALL,
1082         .features[FEAT_8000_0001_ECX] =
1083             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1084         .features[FEAT_7_0_EBX] =
1085             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1086             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1087             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1088         .features[FEAT_XSAVE] =
1089             CPUID_XSAVE_XSAVEOPT,
1090         .features[FEAT_6_EAX] =
1091             CPUID_6_EAX_ARAT,
1092         .xlevel = 0x80000008,
1093         .model_id = "Intel Core Processor (Haswell, no TSX)",
1094     },    {
1095         .name = "Haswell",
1096         .level = 0xd,
1097         .vendor = CPUID_VENDOR_INTEL,
1098         .family = 6,
1099         .model = 60,
1100         .stepping = 1,
1101         .features[FEAT_1_EDX] =
1102             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1103             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1104             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1105             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1106             CPUID_DE | CPUID_FP87,
1107         .features[FEAT_1_ECX] =
1108             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1109             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1110             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1111             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1112             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1113             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1114         .features[FEAT_8000_0001_EDX] =
1115             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1116             CPUID_EXT2_SYSCALL,
1117         .features[FEAT_8000_0001_ECX] =
1118             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1119         .features[FEAT_7_0_EBX] =
1120             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1121             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1122             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1123             CPUID_7_0_EBX_RTM,
1124         .features[FEAT_XSAVE] =
1125             CPUID_XSAVE_XSAVEOPT,
1126         .features[FEAT_6_EAX] =
1127             CPUID_6_EAX_ARAT,
1128         .xlevel = 0x80000008,
1129         .model_id = "Intel Core Processor (Haswell)",
1130     },
1131     {
1132         .name = "Broadwell-noTSX",
1133         .level = 0xd,
1134         .vendor = CPUID_VENDOR_INTEL,
1135         .family = 6,
1136         .model = 61,
1137         .stepping = 2,
1138         .features[FEAT_1_EDX] =
1139             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1140             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1141             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1142             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1143             CPUID_DE | CPUID_FP87,
1144         .features[FEAT_1_ECX] =
1145             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1146             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1147             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1148             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1149             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1150             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1151         .features[FEAT_8000_0001_EDX] =
1152             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1153             CPUID_EXT2_SYSCALL,
1154         .features[FEAT_8000_0001_ECX] =
1155             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1156         .features[FEAT_7_0_EBX] =
1157             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1158             CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1159             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1160             CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1161             CPUID_7_0_EBX_SMAP,
1162         .features[FEAT_XSAVE] =
1163             CPUID_XSAVE_XSAVEOPT,
1164         .features[FEAT_6_EAX] =
1165             CPUID_6_EAX_ARAT,
1166         .xlevel = 0x80000008,
1167         .model_id = "Intel Core Processor (Broadwell, no TSX)",
1168     },
1169     {
1170         .name = "Broadwell",
1171         .level = 0xd,
1172         .vendor = CPUID_VENDOR_INTEL,
1173         .family = 6,
1174         .model = 61,
1175         .stepping = 2,
1176         .features[FEAT_1_EDX] =
1177             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1178             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1179             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1180             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1181             CPUID_DE | CPUID_FP87,
1182         .features[FEAT_1_ECX] =
1183             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1184             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1185             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1186             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1187             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1188             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1189         .features[FEAT_8000_0001_EDX] =
1190             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1191             CPUID_EXT2_SYSCALL,
1192         .features[FEAT_8000_0001_ECX] =
1193             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1194         .features[FEAT_7_0_EBX] =
1195             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1196             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1197             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1198             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1199             CPUID_7_0_EBX_SMAP,
1200         .features[FEAT_XSAVE] =
1201             CPUID_XSAVE_XSAVEOPT,
1202         .features[FEAT_6_EAX] =
1203             CPUID_6_EAX_ARAT,
1204         .xlevel = 0x80000008,
1205         .model_id = "Intel Core Processor (Broadwell)",
1206     },
1207     {
1208         .name = "Opteron_G1",
1209         .level = 5,
1210         .vendor = CPUID_VENDOR_AMD,
1211         .family = 15,
1212         .model = 6,
1213         .stepping = 1,
1214         .features[FEAT_1_EDX] =
1215             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1216             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1217             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1218             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1219             CPUID_DE | CPUID_FP87,
1220         .features[FEAT_1_ECX] =
1221             CPUID_EXT_SSE3,
1222         .features[FEAT_8000_0001_EDX] =
1223             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1224             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1225             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1226             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1227             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1228             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1229         .xlevel = 0x80000008,
1230         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1231     },
1232     {
1233         .name = "Opteron_G2",
1234         .level = 5,
1235         .vendor = CPUID_VENDOR_AMD,
1236         .family = 15,
1237         .model = 6,
1238         .stepping = 1,
1239         .features[FEAT_1_EDX] =
1240             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1241             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1242             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1243             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1244             CPUID_DE | CPUID_FP87,
1245         .features[FEAT_1_ECX] =
1246             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1247         /* Missing: CPUID_EXT2_RDTSCP */
1248         .features[FEAT_8000_0001_EDX] =
1249             CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1250             CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1251             CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1252             CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1253             CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1254             CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1255             CPUID_EXT2_DE | CPUID_EXT2_FPU,
1256         .features[FEAT_8000_0001_ECX] =
1257             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1258         .xlevel = 0x80000008,
1259         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1260     },
1261     {
1262         .name = "Opteron_G3",
1263         .level = 5,
1264         .vendor = CPUID_VENDOR_AMD,
1265         .family = 15,
1266         .model = 6,
1267         .stepping = 1,
1268         .features[FEAT_1_EDX] =
1269             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1270             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1271             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1272             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1273             CPUID_DE | CPUID_FP87,
1274         .features[FEAT_1_ECX] =
1275             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1276             CPUID_EXT_SSE3,
1277         /* Missing: CPUID_EXT2_RDTSCP */
1278         .features[FEAT_8000_0001_EDX] =
1279             CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1280             CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1281             CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1282             CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1283             CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1284             CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1285             CPUID_EXT2_DE | CPUID_EXT2_FPU,
1286         .features[FEAT_8000_0001_ECX] =
1287             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1288             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1289         .xlevel = 0x80000008,
1290         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1291     },
1292     {
1293         .name = "Opteron_G4",
1294         .level = 0xd,
1295         .vendor = CPUID_VENDOR_AMD,
1296         .family = 21,
1297         .model = 1,
1298         .stepping = 2,
1299         .features[FEAT_1_EDX] =
1300             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1301             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1302             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1303             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1304             CPUID_DE | CPUID_FP87,
1305         .features[FEAT_1_ECX] =
1306             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1307             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1308             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1309             CPUID_EXT_SSE3,
1310         /* Missing: CPUID_EXT2_RDTSCP */
1311         .features[FEAT_8000_0001_EDX] =
1312             CPUID_EXT2_LM |
1313             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1314             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1315             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1316             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1317             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1318             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1319         .features[FEAT_8000_0001_ECX] =
1320             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1321             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1322             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1323             CPUID_EXT3_LAHF_LM,
1324         /* no xsaveopt! */
1325         .xlevel = 0x8000001A,
1326         .model_id = "AMD Opteron 62xx class CPU",
1327     },
1328     {
1329         .name = "Opteron_G5",
1330         .level = 0xd,
1331         .vendor = CPUID_VENDOR_AMD,
1332         .family = 21,
1333         .model = 2,
1334         .stepping = 0,
1335         .features[FEAT_1_EDX] =
1336             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1337             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1338             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1339             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1340             CPUID_DE | CPUID_FP87,
1341         .features[FEAT_1_ECX] =
1342             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1343             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1344             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1345             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1346         /* Missing: CPUID_EXT2_RDTSCP */
1347         .features[FEAT_8000_0001_EDX] =
1348             CPUID_EXT2_LM |
1349             CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1350             CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1351             CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1352             CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1353             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1354             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1355         .features[FEAT_8000_0001_ECX] =
1356             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1357             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1358             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1359             CPUID_EXT3_LAHF_LM,
1360         /* no xsaveopt! */
1361         .xlevel = 0x8000001A,
1362         .model_id = "AMD Opteron 63xx class CPU",
1363     },
1364 };
1365
1366 typedef struct PropValue {
1367     const char *prop, *value;
1368 } PropValue;
1369
1370 /* KVM-specific features that are automatically added/removed
1371  * from all CPU models when KVM is enabled.
1372  */
1373 static PropValue kvm_default_props[] = {
1374     { "kvmclock", "on" },
1375     { "kvm-nopiodelay", "on" },
1376     { "kvm-asyncpf", "on" },
1377     { "kvm-steal-time", "on" },
1378     { "kvm-pv-eoi", "on" },
1379     { "kvmclock-stable-bit", "on" },
1380     { "x2apic", "on" },
1381     { "acpi", "off" },
1382     { "monitor", "off" },
1383     { "svm", "off" },
1384     { NULL, NULL },
1385 };
1386
1387 void x86_cpu_change_kvm_default(const char *prop, const char *value)
1388 {
1389     PropValue *pv;
1390     for (pv = kvm_default_props; pv->prop; pv++) {
1391         if (!strcmp(pv->prop, prop)) {
1392             pv->value = value;
1393             break;
1394         }
1395     }
1396
1397     /* It is valid to call this function only for properties that
1398      * are already present in the kvm_default_props table.
1399      */
1400     assert(pv->prop);
1401 }
1402
1403 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1404                                                    bool migratable_only);
1405
1406 #ifdef CONFIG_KVM
1407
1408 static int cpu_x86_fill_model_id(char *str)
1409 {
1410     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1411     int i;
1412
1413     for (i = 0; i < 3; i++) {
1414         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1415         memcpy(str + i * 16 +  0, &eax, 4);
1416         memcpy(str + i * 16 +  4, &ebx, 4);
1417         memcpy(str + i * 16 +  8, &ecx, 4);
1418         memcpy(str + i * 16 + 12, &edx, 4);
1419     }
1420     return 0;
1421 }
1422
1423 static X86CPUDefinition host_cpudef;
1424
1425 static Property host_x86_cpu_properties[] = {
1426     DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1427     DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
1428     DEFINE_PROP_END_OF_LIST()
1429 };
1430
1431 /* class_init for the "host" CPU model
1432  *
1433  * This function may be called before KVM is initialized.
1434  */
1435 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1436 {
1437     DeviceClass *dc = DEVICE_CLASS(oc);
1438     X86CPUClass *xcc = X86_CPU_CLASS(oc);
1439     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1440
1441     xcc->kvm_required = true;
1442
1443     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1444     x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1445
1446     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1447     host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1448     host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1449     host_cpudef.stepping = eax & 0x0F;
1450
1451     cpu_x86_fill_model_id(host_cpudef.model_id);
1452
1453     xcc->cpu_def = &host_cpudef;
1454
1455     /* level, xlevel, xlevel2, and the feature words are initialized on
1456      * instance_init, because they require KVM to be initialized.
1457      */
1458
1459     dc->props = host_x86_cpu_properties;
1460     /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1461     dc->cannot_destroy_with_object_finalize_yet = true;
1462 }
1463
1464 static void host_x86_cpu_initfn(Object *obj)
1465 {
1466     X86CPU *cpu = X86_CPU(obj);
1467     CPUX86State *env = &cpu->env;
1468     KVMState *s = kvm_state;
1469
1470     assert(kvm_enabled());
1471
1472     /* We can't fill the features array here because we don't know yet if
1473      * "migratable" is true or false.
1474      */
1475     cpu->host_features = true;
1476
1477     env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1478     env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1479     env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1480
1481     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1482 }
1483
1484 static const TypeInfo host_x86_cpu_type_info = {
1485     .name = X86_CPU_TYPE_NAME("host"),
1486     .parent = TYPE_X86_CPU,
1487     .instance_init = host_x86_cpu_initfn,
1488     .class_init = host_x86_cpu_class_init,
1489 };
1490
1491 #endif
1492
1493 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1494 {
1495     FeatureWordInfo *f = &feature_word_info[w];
1496     int i;
1497
1498     for (i = 0; i < 32; ++i) {
1499         if ((1UL << i) & mask) {
1500             const char *reg = get_register_name_32(f->cpuid_reg);
1501             assert(reg);
1502             fprintf(stderr, "warning: %s doesn't support requested feature: "
1503                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1504                 kvm_enabled() ? "host" : "TCG",
1505                 f->cpuid_eax, reg,
1506                 f->feat_names[i] ? "." : "",
1507                 f->feat_names[i] ? f->feat_names[i] : "", i);
1508         }
1509     }
1510 }
1511
1512 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1513                                          const char *name, Error **errp)
1514 {
1515     X86CPU *cpu = X86_CPU(obj);
1516     CPUX86State *env = &cpu->env;
1517     int64_t value;
1518
1519     value = (env->cpuid_version >> 8) & 0xf;
1520     if (value == 0xf) {
1521         value += (env->cpuid_version >> 20) & 0xff;
1522     }
1523     visit_type_int(v, &value, name, errp);
1524 }
1525
1526 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1527                                          const char *name, Error **errp)
1528 {
1529     X86CPU *cpu = X86_CPU(obj);
1530     CPUX86State *env = &cpu->env;
1531     const int64_t min = 0;
1532     const int64_t max = 0xff + 0xf;
1533     Error *local_err = NULL;
1534     int64_t value;
1535
1536     visit_type_int(v, &value, name, &local_err);
1537     if (local_err) {
1538         error_propagate(errp, local_err);
1539         return;
1540     }
1541     if (value < min || value > max) {
1542         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1543                    name ? name : "null", value, min, max);
1544         return;
1545     }
1546
1547     env->cpuid_version &= ~0xff00f00;
1548     if (value > 0x0f) {
1549         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1550     } else {
1551         env->cpuid_version |= value << 8;
1552     }
1553 }
1554
1555 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1556                                         const char *name, Error **errp)
1557 {
1558     X86CPU *cpu = X86_CPU(obj);
1559     CPUX86State *env = &cpu->env;
1560     int64_t value;
1561
1562     value = (env->cpuid_version >> 4) & 0xf;
1563     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1564     visit_type_int(v, &value, name, errp);
1565 }
1566
1567 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1568                                         const char *name, Error **errp)
1569 {
1570     X86CPU *cpu = X86_CPU(obj);
1571     CPUX86State *env = &cpu->env;
1572     const int64_t min = 0;
1573     const int64_t max = 0xff;
1574     Error *local_err = NULL;
1575     int64_t value;
1576
1577     visit_type_int(v, &value, name, &local_err);
1578     if (local_err) {
1579         error_propagate(errp, local_err);
1580         return;
1581     }
1582     if (value < min || value > max) {
1583         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1584                    name ? name : "null", value, min, max);
1585         return;
1586     }
1587
1588     env->cpuid_version &= ~0xf00f0;
1589     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1590 }
1591
1592 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1593                                            void *opaque, const char *name,
1594                                            Error **errp)
1595 {
1596     X86CPU *cpu = X86_CPU(obj);
1597     CPUX86State *env = &cpu->env;
1598     int64_t value;
1599
1600     value = env->cpuid_version & 0xf;
1601     visit_type_int(v, &value, name, errp);
1602 }
1603
1604 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1605                                            void *opaque, const char *name,
1606                                            Error **errp)
1607 {
1608     X86CPU *cpu = X86_CPU(obj);
1609     CPUX86State *env = &cpu->env;
1610     const int64_t min = 0;
1611     const int64_t max = 0xf;
1612     Error *local_err = NULL;
1613     int64_t value;
1614
1615     visit_type_int(v, &value, name, &local_err);
1616     if (local_err) {
1617         error_propagate(errp, local_err);
1618         return;
1619     }
1620     if (value < min || value > max) {
1621         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1622                    name ? name : "null", value, min, max);
1623         return;
1624     }
1625
1626     env->cpuid_version &= ~0xf;
1627     env->cpuid_version |= value & 0xf;
1628 }
1629
1630 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1631 {
1632     X86CPU *cpu = X86_CPU(obj);
1633     CPUX86State *env = &cpu->env;
1634     char *value;
1635
1636     value = g_malloc(CPUID_VENDOR_SZ + 1);
1637     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1638                              env->cpuid_vendor3);
1639     return value;
1640 }
1641
1642 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1643                                  Error **errp)
1644 {
1645     X86CPU *cpu = X86_CPU(obj);
1646     CPUX86State *env = &cpu->env;
1647     int i;
1648
1649     if (strlen(value) != CPUID_VENDOR_SZ) {
1650         error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1651         return;
1652     }
1653
1654     env->cpuid_vendor1 = 0;
1655     env->cpuid_vendor2 = 0;
1656     env->cpuid_vendor3 = 0;
1657     for (i = 0; i < 4; i++) {
1658         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1659         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1660         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1661     }
1662 }
1663
1664 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1665 {
1666     X86CPU *cpu = X86_CPU(obj);
1667     CPUX86State *env = &cpu->env;
1668     char *value;
1669     int i;
1670
1671     value = g_malloc(48 + 1);
1672     for (i = 0; i < 48; i++) {
1673         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1674     }
1675     value[48] = '\0';
1676     return value;
1677 }
1678
1679 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1680                                    Error **errp)
1681 {
1682     X86CPU *cpu = X86_CPU(obj);
1683     CPUX86State *env = &cpu->env;
1684     int c, len, i;
1685
1686     if (model_id == NULL) {
1687         model_id = "";
1688     }
1689     len = strlen(model_id);
1690     memset(env->cpuid_model, 0, 48);
1691     for (i = 0; i < 48; i++) {
1692         if (i >= len) {
1693             c = '\0';
1694         } else {
1695             c = (uint8_t)model_id[i];
1696         }
1697         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1698     }
1699 }
1700
1701 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1702                                    const char *name, Error **errp)
1703 {
1704     X86CPU *cpu = X86_CPU(obj);
1705     int64_t value;
1706
1707     value = cpu->env.tsc_khz * 1000;
1708     visit_type_int(v, &value, name, errp);
1709 }
1710
1711 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1712                                    const char *name, Error **errp)
1713 {
1714     X86CPU *cpu = X86_CPU(obj);
1715     const int64_t min = 0;
1716     const int64_t max = INT64_MAX;
1717     Error *local_err = NULL;
1718     int64_t value;
1719
1720     visit_type_int(v, &value, name, &local_err);
1721     if (local_err) {
1722         error_propagate(errp, local_err);
1723         return;
1724     }
1725     if (value < min || value > max) {
1726         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1727                    name ? name : "null", value, min, max);
1728         return;
1729     }
1730
1731     cpu->env.tsc_khz = value / 1000;
1732 }
1733
1734 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1735                                   const char *name, Error **errp)
1736 {
1737     X86CPU *cpu = X86_CPU(obj);
1738     int64_t value = cpu->apic_id;
1739
1740     visit_type_int(v, &value, name, errp);
1741 }
1742
1743 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1744                                   const char *name, Error **errp)
1745 {
1746     X86CPU *cpu = X86_CPU(obj);
1747     DeviceState *dev = DEVICE(obj);
1748     const int64_t min = 0;
1749     const int64_t max = UINT32_MAX;
1750     Error *error = NULL;
1751     int64_t value;
1752
1753     if (dev->realized) {
1754         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1755                    "it was realized", name, object_get_typename(obj));
1756         return;
1757     }
1758
1759     visit_type_int(v, &value, name, &error);
1760     if (error) {
1761         error_propagate(errp, error);
1762         return;
1763     }
1764     if (value < min || value > max) {
1765         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1766                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1767                    object_get_typename(obj), name, value, min, max);
1768         return;
1769     }
1770
1771     if ((value != cpu->apic_id) && cpu_exists(value)) {
1772         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1773         return;
1774     }
1775     cpu->apic_id = value;
1776 }
1777
1778 /* Generic getter for "feature-words" and "filtered-features" properties */
1779 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1780                                       const char *name, Error **errp)
1781 {
1782     uint32_t *array = (uint32_t *)opaque;
1783     FeatureWord w;
1784     Error *err = NULL;
1785     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1786     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1787     X86CPUFeatureWordInfoList *list = NULL;
1788
1789     for (w = 0; w < FEATURE_WORDS; w++) {
1790         FeatureWordInfo *wi = &feature_word_info[w];
1791         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1792         qwi->cpuid_input_eax = wi->cpuid_eax;
1793         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1794         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1795         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1796         qwi->features = array[w];
1797
1798         /* List will be in reverse order, but order shouldn't matter */
1799         list_entries[w].next = list;
1800         list_entries[w].value = &word_infos[w];
1801         list = &list_entries[w];
1802     }
1803
1804     visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1805     error_propagate(errp, err);
1806 }
1807
1808 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1809                                  const char *name, Error **errp)
1810 {
1811     X86CPU *cpu = X86_CPU(obj);
1812     int64_t value = cpu->hyperv_spinlock_attempts;
1813
1814     visit_type_int(v, &value, name, errp);
1815 }
1816
1817 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1818                                  const char *name, Error **errp)
1819 {
1820     const int64_t min = 0xFFF;
1821     const int64_t max = UINT_MAX;
1822     X86CPU *cpu = X86_CPU(obj);
1823     Error *err = NULL;
1824     int64_t value;
1825
1826     visit_type_int(v, &value, name, &err);
1827     if (err) {
1828         error_propagate(errp, err);
1829         return;
1830     }
1831
1832     if (value < min || value > max) {
1833         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1834                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1835                    object_get_typename(obj), name ? name : "null",
1836                    value, min, max);
1837         return;
1838     }
1839     cpu->hyperv_spinlock_attempts = value;
1840 }
1841
1842 static PropertyInfo qdev_prop_spinlocks = {
1843     .name  = "int",
1844     .get   = x86_get_hv_spinlocks,
1845     .set   = x86_set_hv_spinlocks,
1846 };
1847
1848 /* Convert all '_' in a feature string option name to '-', to make feature
1849  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1850  */
1851 static inline void feat2prop(char *s)
1852 {
1853     while ((s = strchr(s, '_'))) {
1854         *s = '-';
1855     }
1856 }
1857
1858 /* Parse "+feature,-feature,feature=foo" CPU feature string
1859  */
1860 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1861                                      Error **errp)
1862 {
1863     X86CPU *cpu = X86_CPU(cs);
1864     char *featurestr; /* Single 'key=value" string being parsed */
1865     FeatureWord w;
1866     /* Features to be added */
1867     FeatureWordArray plus_features = { 0 };
1868     /* Features to be removed */
1869     FeatureWordArray minus_features = { 0 };
1870     uint32_t numvalue;
1871     CPUX86State *env = &cpu->env;
1872     Error *local_err = NULL;
1873
1874     featurestr = features ? strtok(features, ",") : NULL;
1875
1876     while (featurestr) {
1877         char *val;
1878         if (featurestr[0] == '+') {
1879             add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
1880         } else if (featurestr[0] == '-') {
1881             add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
1882         } else if ((val = strchr(featurestr, '='))) {
1883             *val = 0; val++;
1884             feat2prop(featurestr);
1885             if (!strcmp(featurestr, "xlevel")) {
1886                 char *err;
1887                 char num[32];
1888
1889                 numvalue = strtoul(val, &err, 0);
1890                 if (!*val || *err) {
1891                     error_setg(errp, "bad numerical value %s", val);
1892                     return;
1893                 }
1894                 if (numvalue < 0x80000000) {
1895                     error_report("xlevel value shall always be >= 0x80000000"
1896                                  ", fixup will be removed in future versions");
1897                     numvalue += 0x80000000;
1898                 }
1899                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1900                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1901             } else if (!strcmp(featurestr, "tsc-freq")) {
1902                 int64_t tsc_freq;
1903                 char *err;
1904                 char num[32];
1905
1906                 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1907                                                QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
1908                 if (tsc_freq < 0 || *err) {
1909                     error_setg(errp, "bad numerical value %s", val);
1910                     return;
1911                 }
1912                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1913                 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1914                                       &local_err);
1915             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1916                 char *err;
1917                 const int min = 0xFFF;
1918                 char num[32];
1919                 numvalue = strtoul(val, &err, 0);
1920                 if (!*val || *err) {
1921                     error_setg(errp, "bad numerical value %s", val);
1922                     return;
1923                 }
1924                 if (numvalue < min) {
1925                     error_report("hv-spinlocks value shall always be >= 0x%x"
1926                                  ", fixup will be removed in future versions",
1927                                  min);
1928                     numvalue = min;
1929                 }
1930                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1931                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1932             } else {
1933                 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1934             }
1935         } else {
1936             feat2prop(featurestr);
1937             object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1938         }
1939         if (local_err) {
1940             error_propagate(errp, local_err);
1941             return;
1942         }
1943         featurestr = strtok(NULL, ",");
1944     }
1945
1946     if (cpu->host_features) {
1947         for (w = 0; w < FEATURE_WORDS; w++) {
1948             env->features[w] =
1949                 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1950         }
1951     }
1952
1953     for (w = 0; w < FEATURE_WORDS; w++) {
1954         env->features[w] |= plus_features[w];
1955         env->features[w] &= ~minus_features[w];
1956     }
1957 }
1958
1959 /* Print all cpuid feature names in featureset
1960  */
1961 static void listflags(FILE *f, fprintf_function print, const char **featureset)
1962 {
1963     int bit;
1964     bool first = true;
1965
1966     for (bit = 0; bit < 32; bit++) {
1967         if (featureset[bit]) {
1968             print(f, "%s%s", first ? "" : " ", featureset[bit]);
1969             first = false;
1970         }
1971     }
1972 }
1973
1974 /* generate CPU information. */
1975 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1976 {
1977     X86CPUDefinition *def;
1978     char buf[256];
1979     int i;
1980
1981     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1982         def = &builtin_x86_defs[i];
1983         snprintf(buf, sizeof(buf), "%s", def->name);
1984         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1985     }
1986 #ifdef CONFIG_KVM
1987     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1988                    "KVM processor with all supported host features "
1989                    "(only available in KVM mode)");
1990 #endif
1991
1992     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1993     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1994         FeatureWordInfo *fw = &feature_word_info[i];
1995
1996         (*cpu_fprintf)(f, "  ");
1997         listflags(f, cpu_fprintf, fw->feat_names);
1998         (*cpu_fprintf)(f, "\n");
1999     }
2000 }
2001
2002 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2003 {
2004     CpuDefinitionInfoList *cpu_list = NULL;
2005     X86CPUDefinition *def;
2006     int i;
2007
2008     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2009         CpuDefinitionInfoList *entry;
2010         CpuDefinitionInfo *info;
2011
2012         def = &builtin_x86_defs[i];
2013         info = g_malloc0(sizeof(*info));
2014         info->name = g_strdup(def->name);
2015
2016         entry = g_malloc0(sizeof(*entry));
2017         entry->value = info;
2018         entry->next = cpu_list;
2019         cpu_list = entry;
2020     }
2021
2022     return cpu_list;
2023 }
2024
2025 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2026                                                    bool migratable_only)
2027 {
2028     FeatureWordInfo *wi = &feature_word_info[w];
2029     uint32_t r;
2030
2031     if (kvm_enabled()) {
2032         r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2033                                                     wi->cpuid_ecx,
2034                                                     wi->cpuid_reg);
2035     } else if (tcg_enabled()) {
2036         r = wi->tcg_features;
2037     } else {
2038         return ~0;
2039     }
2040     if (migratable_only) {
2041         r &= x86_cpu_get_migratable_flags(w);
2042     }
2043     return r;
2044 }
2045
2046 /*
2047  * Filters CPU feature words based on host availability of each feature.
2048  *
2049  * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2050  */
2051 static int x86_cpu_filter_features(X86CPU *cpu)
2052 {
2053     CPUX86State *env = &cpu->env;
2054     FeatureWord w;
2055     int rv = 0;
2056
2057     for (w = 0; w < FEATURE_WORDS; w++) {
2058         uint32_t host_feat =
2059             x86_cpu_get_supported_feature_word(w, cpu->migratable);
2060         uint32_t requested_features = env->features[w];
2061         env->features[w] &= host_feat;
2062         cpu->filtered_features[w] = requested_features & ~env->features[w];
2063         if (cpu->filtered_features[w]) {
2064             if (cpu->check_cpuid || cpu->enforce_cpuid) {
2065                 report_unavailable_features(w, cpu->filtered_features[w]);
2066             }
2067             rv = 1;
2068         }
2069     }
2070
2071     return rv;
2072 }
2073
2074 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2075 {
2076     PropValue *pv;
2077     for (pv = props; pv->prop; pv++) {
2078         if (!pv->value) {
2079             continue;
2080         }
2081         object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2082                               &error_abort);
2083     }
2084 }
2085
2086 /* Load data from X86CPUDefinition
2087  */
2088 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2089 {
2090     CPUX86State *env = &cpu->env;
2091     const char *vendor;
2092     char host_vendor[CPUID_VENDOR_SZ + 1];
2093     FeatureWord w;
2094
2095     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2096     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2097     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2098     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2099     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
2100     object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2101     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2102     for (w = 0; w < FEATURE_WORDS; w++) {
2103         env->features[w] = def->features[w];
2104     }
2105
2106     /* Special cases not set in the X86CPUDefinition structs: */
2107     if (kvm_enabled()) {
2108         x86_cpu_apply_props(cpu, kvm_default_props);
2109     }
2110
2111     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2112
2113     /* sysenter isn't supported in compatibility mode on AMD,
2114      * syscall isn't supported in compatibility mode on Intel.
2115      * Normally we advertise the actual CPU vendor, but you can
2116      * override this using the 'vendor' property if you want to use
2117      * KVM's sysenter/syscall emulation in compatibility mode and
2118      * when doing cross vendor migration
2119      */
2120     vendor = def->vendor;
2121     if (kvm_enabled()) {
2122         uint32_t  ebx = 0, ecx = 0, edx = 0;
2123         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2124         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2125         vendor = host_vendor;
2126     }
2127
2128     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2129
2130 }
2131
2132 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
2133 {
2134     X86CPU *cpu = NULL;
2135     X86CPUClass *xcc;
2136     ObjectClass *oc;
2137     gchar **model_pieces;
2138     char *name, *features;
2139     Error *error = NULL;
2140
2141     model_pieces = g_strsplit(cpu_model, ",", 2);
2142     if (!model_pieces[0]) {
2143         error_setg(&error, "Invalid/empty CPU model name");
2144         goto out;
2145     }
2146     name = model_pieces[0];
2147     features = model_pieces[1];
2148
2149     oc = x86_cpu_class_by_name(name);
2150     if (oc == NULL) {
2151         error_setg(&error, "Unable to find CPU definition: %s", name);
2152         goto out;
2153     }
2154     xcc = X86_CPU_CLASS(oc);
2155
2156     if (xcc->kvm_required && !kvm_enabled()) {
2157         error_setg(&error, "CPU model '%s' requires KVM", name);
2158         goto out;
2159     }
2160
2161     cpu = X86_CPU(object_new(object_class_get_name(oc)));
2162
2163     x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2164     if (error) {
2165         goto out;
2166     }
2167
2168 out:
2169     if (error != NULL) {
2170         error_propagate(errp, error);
2171         if (cpu) {
2172             object_unref(OBJECT(cpu));
2173             cpu = NULL;
2174         }
2175     }
2176     g_strfreev(model_pieces);
2177     return cpu;
2178 }
2179
2180 X86CPU *cpu_x86_init(const char *cpu_model)
2181 {
2182     Error *error = NULL;
2183     X86CPU *cpu;
2184
2185     cpu = cpu_x86_create(cpu_model, &error);
2186     if (error) {
2187         goto out;
2188     }
2189
2190     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2191
2192 out:
2193     if (error) {
2194         error_report_err(error);
2195         if (cpu != NULL) {
2196             object_unref(OBJECT(cpu));
2197             cpu = NULL;
2198         }
2199     }
2200     return cpu;
2201 }
2202
2203 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2204 {
2205     X86CPUDefinition *cpudef = data;
2206     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2207
2208     xcc->cpu_def = cpudef;
2209 }
2210
2211 static void x86_register_cpudef_type(X86CPUDefinition *def)
2212 {
2213     char *typename = x86_cpu_type_name(def->name);
2214     TypeInfo ti = {
2215         .name = typename,
2216         .parent = TYPE_X86_CPU,
2217         .class_init = x86_cpu_cpudef_class_init,
2218         .class_data = def,
2219     };
2220
2221     type_register(&ti);
2222     g_free(typename);
2223 }
2224
2225 #if !defined(CONFIG_USER_ONLY)
2226
2227 void cpu_clear_apic_feature(CPUX86State *env)
2228 {
2229     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2230 }
2231
2232 #endif /* !CONFIG_USER_ONLY */
2233
2234 /* Initialize list of CPU models, filling some non-static fields if necessary
2235  */
2236 void x86_cpudef_setup(void)
2237 {
2238     int i, j;
2239     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2240
2241     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2242         X86CPUDefinition *def = &builtin_x86_defs[i];
2243
2244         /* Look for specific "cpudef" models that */
2245         /* have the QEMU version in .model_id */
2246         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2247             if (strcmp(model_with_versions[j], def->name) == 0) {
2248                 pstrcpy(def->model_id, sizeof(def->model_id),
2249                         "QEMU Virtual CPU version ");
2250                 pstrcat(def->model_id, sizeof(def->model_id),
2251                         qemu_hw_version());
2252                 break;
2253             }
2254         }
2255     }
2256 }
2257
2258 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2259                    uint32_t *eax, uint32_t *ebx,
2260                    uint32_t *ecx, uint32_t *edx)
2261 {
2262     X86CPU *cpu = x86_env_get_cpu(env);
2263     CPUState *cs = CPU(cpu);
2264
2265     /* test if maximum index reached */
2266     if (index & 0x80000000) {
2267         if (index > env->cpuid_xlevel) {
2268             if (env->cpuid_xlevel2 > 0) {
2269                 /* Handle the Centaur's CPUID instruction. */
2270                 if (index > env->cpuid_xlevel2) {
2271                     index = env->cpuid_xlevel2;
2272                 } else if (index < 0xC0000000) {
2273                     index = env->cpuid_xlevel;
2274                 }
2275             } else {
2276                 /* Intel documentation states that invalid EAX input will
2277                  * return the same information as EAX=cpuid_level
2278                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2279                  */
2280                 index =  env->cpuid_level;
2281             }
2282         }
2283     } else {
2284         if (index > env->cpuid_level)
2285             index = env->cpuid_level;
2286     }
2287
2288     switch(index) {
2289     case 0:
2290         *eax = env->cpuid_level;
2291         *ebx = env->cpuid_vendor1;
2292         *edx = env->cpuid_vendor2;
2293         *ecx = env->cpuid_vendor3;
2294         break;
2295     case 1:
2296         *eax = env->cpuid_version;
2297         *ebx = (cpu->apic_id << 24) |
2298                8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2299         *ecx = env->features[FEAT_1_ECX];
2300         *edx = env->features[FEAT_1_EDX];
2301         if (cs->nr_cores * cs->nr_threads > 1) {
2302             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2303             *edx |= 1 << 28;    /* HTT bit */
2304         }
2305         break;
2306     case 2:
2307         /* cache info: needed for Pentium Pro compatibility */
2308         if (cpu->cache_info_passthrough) {
2309             host_cpuid(index, 0, eax, ebx, ecx, edx);
2310             break;
2311         }
2312         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2313         *ebx = 0;
2314         *ecx = 0;
2315         *edx = (L1D_DESCRIPTOR << 16) | \
2316                (L1I_DESCRIPTOR <<  8) | \
2317                (L2_DESCRIPTOR);
2318         break;
2319     case 4:
2320         /* cache info: needed for Core compatibility */
2321         if (cpu->cache_info_passthrough) {
2322             host_cpuid(index, count, eax, ebx, ecx, edx);
2323             *eax &= ~0xFC000000;
2324         } else {
2325             *eax = 0;
2326             switch (count) {
2327             case 0: /* L1 dcache info */
2328                 *eax |= CPUID_4_TYPE_DCACHE | \
2329                         CPUID_4_LEVEL(1) | \
2330                         CPUID_4_SELF_INIT_LEVEL;
2331                 *ebx = (L1D_LINE_SIZE - 1) | \
2332                        ((L1D_PARTITIONS - 1) << 12) | \
2333                        ((L1D_ASSOCIATIVITY - 1) << 22);
2334                 *ecx = L1D_SETS - 1;
2335                 *edx = CPUID_4_NO_INVD_SHARING;
2336                 break;
2337             case 1: /* L1 icache info */
2338                 *eax |= CPUID_4_TYPE_ICACHE | \
2339                         CPUID_4_LEVEL(1) | \
2340                         CPUID_4_SELF_INIT_LEVEL;
2341                 *ebx = (L1I_LINE_SIZE - 1) | \
2342                        ((L1I_PARTITIONS - 1) << 12) | \
2343                        ((L1I_ASSOCIATIVITY - 1) << 22);
2344                 *ecx = L1I_SETS - 1;
2345                 *edx = CPUID_4_NO_INVD_SHARING;
2346                 break;
2347             case 2: /* L2 cache info */
2348                 *eax |= CPUID_4_TYPE_UNIFIED | \
2349                         CPUID_4_LEVEL(2) | \
2350                         CPUID_4_SELF_INIT_LEVEL;
2351                 if (cs->nr_threads > 1) {
2352                     *eax |= (cs->nr_threads - 1) << 14;
2353                 }
2354                 *ebx = (L2_LINE_SIZE - 1) | \
2355                        ((L2_PARTITIONS - 1) << 12) | \
2356                        ((L2_ASSOCIATIVITY - 1) << 22);
2357                 *ecx = L2_SETS - 1;
2358                 *edx = CPUID_4_NO_INVD_SHARING;
2359                 break;
2360             default: /* end of info */
2361                 *eax = 0;
2362                 *ebx = 0;
2363                 *ecx = 0;
2364                 *edx = 0;
2365                 break;
2366             }
2367         }
2368
2369         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2370         if ((*eax & 31) && cs->nr_cores > 1) {
2371             *eax |= (cs->nr_cores - 1) << 26;
2372         }
2373         break;
2374     case 5:
2375         /* mwait info: needed for Core compatibility */
2376         *eax = 0; /* Smallest monitor-line size in bytes */
2377         *ebx = 0; /* Largest monitor-line size in bytes */
2378         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2379         *edx = 0;
2380         break;
2381     case 6:
2382         /* Thermal and Power Leaf */
2383         *eax = env->features[FEAT_6_EAX];
2384         *ebx = 0;
2385         *ecx = 0;
2386         *edx = 0;
2387         break;
2388     case 7:
2389         /* Structured Extended Feature Flags Enumeration Leaf */
2390         if (count == 0) {
2391             *eax = 0; /* Maximum ECX value for sub-leaves */
2392             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2393             *ecx = 0; /* Reserved */
2394             *edx = 0; /* Reserved */
2395         } else {
2396             *eax = 0;
2397             *ebx = 0;
2398             *ecx = 0;
2399             *edx = 0;
2400         }
2401         break;
2402     case 9:
2403         /* Direct Cache Access Information Leaf */
2404         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2405         *ebx = 0;
2406         *ecx = 0;
2407         *edx = 0;
2408         break;
2409     case 0xA:
2410         /* Architectural Performance Monitoring Leaf */
2411         if (kvm_enabled() && cpu->enable_pmu) {
2412             KVMState *s = cs->kvm_state;
2413
2414             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2415             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2416             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2417             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2418         } else {
2419             *eax = 0;
2420             *ebx = 0;
2421             *ecx = 0;
2422             *edx = 0;
2423         }
2424         break;
2425     case 0xD: {
2426         KVMState *s = cs->kvm_state;
2427         uint64_t kvm_mask;
2428         int i;
2429
2430         /* Processor Extended State */
2431         *eax = 0;
2432         *ebx = 0;
2433         *ecx = 0;
2434         *edx = 0;
2435         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2436             break;
2437         }
2438         kvm_mask =
2439             kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2440             ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2441
2442         if (count == 0) {
2443             *ecx = 0x240;
2444             for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2445                 const ExtSaveArea *esa = &ext_save_areas[i];
2446                 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2447                     (kvm_mask & (1 << i)) != 0) {
2448                     if (i < 32) {
2449                         *eax |= 1 << i;
2450                     } else {
2451                         *edx |= 1 << (i - 32);
2452                     }
2453                     *ecx = MAX(*ecx, esa->offset + esa->size);
2454                 }
2455             }
2456             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2457             *ebx = *ecx;
2458         } else if (count == 1) {
2459             *eax = env->features[FEAT_XSAVE];
2460         } else if (count < ARRAY_SIZE(ext_save_areas)) {
2461             const ExtSaveArea *esa = &ext_save_areas[count];
2462             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2463                 (kvm_mask & (1 << count)) != 0) {
2464                 *eax = esa->size;
2465                 *ebx = esa->offset;
2466             }
2467         }
2468         break;
2469     }
2470     case 0x80000000:
2471         *eax = env->cpuid_xlevel;
2472         *ebx = env->cpuid_vendor1;
2473         *edx = env->cpuid_vendor2;
2474         *ecx = env->cpuid_vendor3;
2475         break;
2476     case 0x80000001:
2477         *eax = env->cpuid_version;
2478         *ebx = 0;
2479         *ecx = env->features[FEAT_8000_0001_ECX];
2480         *edx = env->features[FEAT_8000_0001_EDX];
2481
2482         /* The Linux kernel checks for the CMPLegacy bit and
2483          * discards multiple thread information if it is set.
2484          * So dont set it here for Intel to make Linux guests happy.
2485          */
2486         if (cs->nr_cores * cs->nr_threads > 1) {
2487             if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2488                 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2489                 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2490                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2491             }
2492         }
2493         break;
2494     case 0x80000002:
2495     case 0x80000003:
2496     case 0x80000004:
2497         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2498         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2499         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2500         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2501         break;
2502     case 0x80000005:
2503         /* cache info (L1 cache) */
2504         if (cpu->cache_info_passthrough) {
2505             host_cpuid(index, 0, eax, ebx, ecx, edx);
2506             break;
2507         }
2508         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2509                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2510         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2511                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2512         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2513                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2514         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2515                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2516         break;
2517     case 0x80000006:
2518         /* cache info (L2 cache) */
2519         if (cpu->cache_info_passthrough) {
2520             host_cpuid(index, 0, eax, ebx, ecx, edx);
2521             break;
2522         }
2523         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2524                (L2_DTLB_2M_ENTRIES << 16) | \
2525                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2526                (L2_ITLB_2M_ENTRIES);
2527         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2528                (L2_DTLB_4K_ENTRIES << 16) | \
2529                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2530                (L2_ITLB_4K_ENTRIES);
2531         *ecx = (L2_SIZE_KB_AMD << 16) | \
2532                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2533                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2534         *edx = ((L3_SIZE_KB/512) << 18) | \
2535                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2536                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2537         break;
2538     case 0x80000007:
2539         *eax = 0;
2540         *ebx = 0;
2541         *ecx = 0;
2542         *edx = env->features[FEAT_8000_0007_EDX];
2543         break;
2544     case 0x80000008:
2545         /* virtual & phys address size in low 2 bytes. */
2546 /* XXX: This value must match the one used in the MMU code. */
2547         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2548             /* 64 bit processor */
2549 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2550             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2551         } else {
2552             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2553                 *eax = 0x00000024; /* 36 bits physical */
2554             } else {
2555                 *eax = 0x00000020; /* 32 bits physical */
2556             }
2557         }
2558         *ebx = 0;
2559         *ecx = 0;
2560         *edx = 0;
2561         if (cs->nr_cores * cs->nr_threads > 1) {
2562             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2563         }
2564         break;
2565     case 0x8000000A:
2566         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2567             *eax = 0x00000001; /* SVM Revision */
2568             *ebx = 0x00000010; /* nr of ASIDs */
2569             *ecx = 0;
2570             *edx = env->features[FEAT_SVM]; /* optional features */
2571         } else {
2572             *eax = 0;
2573             *ebx = 0;
2574             *ecx = 0;
2575             *edx = 0;
2576         }
2577         break;
2578     case 0xC0000000:
2579         *eax = env->cpuid_xlevel2;
2580         *ebx = 0;
2581         *ecx = 0;
2582         *edx = 0;
2583         break;
2584     case 0xC0000001:
2585         /* Support for VIA CPU's CPUID instruction */
2586         *eax = env->cpuid_version;
2587         *ebx = 0;
2588         *ecx = 0;
2589         *edx = env->features[FEAT_C000_0001_EDX];
2590         break;
2591     case 0xC0000002:
2592     case 0xC0000003:
2593     case 0xC0000004:
2594         /* Reserved for the future, and now filled with zero */
2595         *eax = 0;
2596         *ebx = 0;
2597         *ecx = 0;
2598         *edx = 0;
2599         break;
2600     default:
2601         /* reserved values: zero */
2602         *eax = 0;
2603         *ebx = 0;
2604         *ecx = 0;
2605         *edx = 0;
2606         break;
2607     }
2608 }
2609
2610 /* CPUClass::reset() */
2611 static void x86_cpu_reset(CPUState *s)
2612 {
2613     X86CPU *cpu = X86_CPU(s);
2614     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2615     CPUX86State *env = &cpu->env;
2616     int i;
2617
2618     xcc->parent_reset(s);
2619
2620     memset(env, 0, offsetof(CPUX86State, cpuid_level));
2621
2622     tlb_flush(s, 1);
2623
2624     env->old_exception = -1;
2625
2626     /* init to reset state */
2627
2628 #ifdef CONFIG_SOFTMMU
2629     env->hflags |= HF_SOFTMMU_MASK;
2630 #endif
2631     env->hflags2 |= HF2_GIF_MASK;
2632
2633     cpu_x86_update_cr0(env, 0x60000010);
2634     env->a20_mask = ~0x0;
2635     env->smbase = 0x30000;
2636
2637     env->idt.limit = 0xffff;
2638     env->gdt.limit = 0xffff;
2639     env->ldt.limit = 0xffff;
2640     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2641     env->tr.limit = 0xffff;
2642     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2643
2644     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2645                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2646                            DESC_R_MASK | DESC_A_MASK);
2647     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2648                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2649                            DESC_A_MASK);
2650     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2651                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2652                            DESC_A_MASK);
2653     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2654                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2655                            DESC_A_MASK);
2656     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2657                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2658                            DESC_A_MASK);
2659     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2660                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2661                            DESC_A_MASK);
2662
2663     env->eip = 0xfff0;
2664     env->regs[R_EDX] = env->cpuid_version;
2665
2666     env->eflags = 0x2;
2667
2668     /* FPU init */
2669     for (i = 0; i < 8; i++) {
2670         env->fptags[i] = 1;
2671     }
2672     cpu_set_fpuc(env, 0x37f);
2673
2674     env->mxcsr = 0x1f80;
2675     env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2676
2677     env->pat = 0x0007040600070406ULL;
2678     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2679
2680     memset(env->dr, 0, sizeof(env->dr));
2681     env->dr[6] = DR6_FIXED_1;
2682     env->dr[7] = DR7_FIXED_1;
2683     cpu_breakpoint_remove_all(s, BP_CPU);
2684     cpu_watchpoint_remove_all(s, BP_CPU);
2685
2686     env->xcr0 = 1;
2687
2688     /*
2689      * SDM 11.11.5 requires:
2690      *  - IA32_MTRR_DEF_TYPE MSR.E = 0
2691      *  - IA32_MTRR_PHYSMASKn.V = 0
2692      * All other bits are undefined.  For simplification, zero it all.
2693      */
2694     env->mtrr_deftype = 0;
2695     memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2696     memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2697
2698 #if !defined(CONFIG_USER_ONLY)
2699     /* We hard-wire the BSP to the first CPU. */
2700     apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2701
2702     s->halted = !cpu_is_bsp(cpu);
2703
2704     if (kvm_enabled()) {
2705         kvm_arch_reset_vcpu(cpu);
2706     }
2707 #endif
2708 }
2709
2710 #ifndef CONFIG_USER_ONLY
2711 bool cpu_is_bsp(X86CPU *cpu)
2712 {
2713     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2714 }
2715
2716 /* TODO: remove me, when reset over QOM tree is implemented */
2717 static void x86_cpu_machine_reset_cb(void *opaque)
2718 {
2719     X86CPU *cpu = opaque;
2720     cpu_reset(CPU(cpu));
2721 }
2722 #endif
2723
2724 static void mce_init(X86CPU *cpu)
2725 {
2726     CPUX86State *cenv = &cpu->env;
2727     unsigned int bank;
2728
2729     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2730         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2731             (CPUID_MCE | CPUID_MCA)) {
2732         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2733         cenv->mcg_ctl = ~(uint64_t)0;
2734         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2735             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2736         }
2737     }
2738 }
2739
2740 #ifndef CONFIG_USER_ONLY
2741 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2742 {
2743     APICCommonState *apic;
2744     const char *apic_type = "apic";
2745
2746     if (kvm_apic_in_kernel()) {
2747         apic_type = "kvm-apic";
2748     } else if (xen_enabled()) {
2749         apic_type = "xen-apic";
2750     }
2751
2752     cpu->apic_state = DEVICE(object_new(apic_type));
2753
2754     object_property_add_child(OBJECT(cpu), "apic",
2755                               OBJECT(cpu->apic_state), NULL);
2756     qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
2757     /* TODO: convert to link<> */
2758     apic = APIC_COMMON(cpu->apic_state);
2759     apic->cpu = cpu;
2760     apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
2761 }
2762
2763 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2764 {
2765     APICCommonState *apic;
2766     static bool apic_mmio_map_once;
2767
2768     if (cpu->apic_state == NULL) {
2769         return;
2770     }
2771     object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2772                              errp);
2773
2774     /* Map APIC MMIO area */
2775     apic = APIC_COMMON(cpu->apic_state);
2776     if (!apic_mmio_map_once) {
2777         memory_region_add_subregion_overlap(get_system_memory(),
2778                                             apic->apicbase &
2779                                             MSR_IA32_APICBASE_BASE,
2780                                             &apic->io_memory,
2781                                             0x1000);
2782         apic_mmio_map_once = true;
2783      }
2784 }
2785
2786 static void x86_cpu_machine_done(Notifier *n, void *unused)
2787 {
2788     X86CPU *cpu = container_of(n, X86CPU, machine_done);
2789     MemoryRegion *smram =
2790         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2791
2792     if (smram) {
2793         cpu->smram = g_new(MemoryRegion, 1);
2794         memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2795                                  smram, 0, 1ull << 32);
2796         memory_region_set_enabled(cpu->smram, false);
2797         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2798     }
2799 }
2800 #else
2801 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2802 {
2803 }
2804 #endif
2805
2806
2807 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2808                            (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2809                            (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2810 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2811                          (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2812                          (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2813 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2814 {
2815     CPUState *cs = CPU(dev);
2816     X86CPU *cpu = X86_CPU(dev);
2817     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2818     CPUX86State *env = &cpu->env;
2819     Error *local_err = NULL;
2820     static bool ht_warned;
2821
2822     if (cpu->apic_id < 0) {
2823         error_setg(errp, "apic-id property was not initialized properly");
2824         return;
2825     }
2826
2827     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2828         env->cpuid_level = 7;
2829     }
2830
2831     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2832      * CPUID[1].EDX.
2833      */
2834     if (IS_AMD_CPU(env)) {
2835         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2836         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2837            & CPUID_EXT2_AMD_ALIASES);
2838     }
2839
2840
2841     if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2842         error_setg(&local_err,
2843                    kvm_enabled() ?
2844                        "Host doesn't support requested features" :
2845                        "TCG doesn't support requested features");
2846         goto out;
2847     }
2848
2849 #ifndef CONFIG_USER_ONLY
2850     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2851
2852     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2853         x86_cpu_apic_create(cpu, &local_err);
2854         if (local_err != NULL) {
2855             goto out;
2856         }
2857     }
2858 #endif
2859
2860     mce_init(cpu);
2861
2862 #ifndef CONFIG_USER_ONLY
2863     if (tcg_enabled()) {
2864         AddressSpace *newas = g_new(AddressSpace, 1);
2865
2866         cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2867         cpu->cpu_as_root = g_new(MemoryRegion, 1);
2868
2869         /* Outer container... */
2870         memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2871         memory_region_set_enabled(cpu->cpu_as_root, true);
2872
2873         /* ... with two regions inside: normal system memory with low
2874          * priority, and...
2875          */
2876         memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2877                                  get_system_memory(), 0, ~0ull);
2878         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2879         memory_region_set_enabled(cpu->cpu_as_mem, true);
2880         address_space_init(newas, cpu->cpu_as_root, "CPU");
2881         cs->num_ases = 1;
2882         cpu_address_space_init(cs, newas, 0);
2883
2884         /* ... SMRAM with higher priority, linked from /machine/smram.  */
2885         cpu->machine_done.notify = x86_cpu_machine_done;
2886         qemu_add_machine_init_done_notifier(&cpu->machine_done);
2887     }
2888 #endif
2889
2890     qemu_init_vcpu(cs);
2891
2892     /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2893      * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2894      * based on inputs (sockets,cores,threads), it is still better to gives
2895      * users a warning.
2896      *
2897      * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2898      * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2899      */
2900     if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2901         error_report("AMD CPU doesn't support hyperthreading. Please configure"
2902                      " -smp options properly.");
2903         ht_warned = true;
2904     }
2905
2906     x86_cpu_apic_realize(cpu, &local_err);
2907     if (local_err != NULL) {
2908         goto out;
2909     }
2910     cpu_reset(cs);
2911
2912     xcc->parent_realize(dev, &local_err);
2913
2914 out:
2915     if (local_err != NULL) {
2916         error_propagate(errp, local_err);
2917         return;
2918     }
2919 }
2920
2921 typedef struct BitProperty {
2922     uint32_t *ptr;
2923     uint32_t mask;
2924 } BitProperty;
2925
2926 static void x86_cpu_get_bit_prop(Object *obj,
2927                                  struct Visitor *v,
2928                                  void *opaque,
2929                                  const char *name,
2930                                  Error **errp)
2931 {
2932     BitProperty *fp = opaque;
2933     bool value = (*fp->ptr & fp->mask) == fp->mask;
2934     visit_type_bool(v, &value, name, errp);
2935 }
2936
2937 static void x86_cpu_set_bit_prop(Object *obj,
2938                                  struct Visitor *v,
2939                                  void *opaque,
2940                                  const char *name,
2941                                  Error **errp)
2942 {
2943     DeviceState *dev = DEVICE(obj);
2944     BitProperty *fp = opaque;
2945     Error *local_err = NULL;
2946     bool value;
2947
2948     if (dev->realized) {
2949         qdev_prop_set_after_realize(dev, name, errp);
2950         return;
2951     }
2952
2953     visit_type_bool(v, &value, name, &local_err);
2954     if (local_err) {
2955         error_propagate(errp, local_err);
2956         return;
2957     }
2958
2959     if (value) {
2960         *fp->ptr |= fp->mask;
2961     } else {
2962         *fp->ptr &= ~fp->mask;
2963     }
2964 }
2965
2966 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2967                                      void *opaque)
2968 {
2969     BitProperty *prop = opaque;
2970     g_free(prop);
2971 }
2972
2973 /* Register a boolean property to get/set a single bit in a uint32_t field.
2974  *
2975  * The same property name can be registered multiple times to make it affect
2976  * multiple bits in the same FeatureWord. In that case, the getter will return
2977  * true only if all bits are set.
2978  */
2979 static void x86_cpu_register_bit_prop(X86CPU *cpu,
2980                                       const char *prop_name,
2981                                       uint32_t *field,
2982                                       int bitnr)
2983 {
2984     BitProperty *fp;
2985     ObjectProperty *op;
2986     uint32_t mask = (1UL << bitnr);
2987
2988     op = object_property_find(OBJECT(cpu), prop_name, NULL);
2989     if (op) {
2990         fp = op->opaque;
2991         assert(fp->ptr == field);
2992         fp->mask |= mask;
2993     } else {
2994         fp = g_new0(BitProperty, 1);
2995         fp->ptr = field;
2996         fp->mask = mask;
2997         object_property_add(OBJECT(cpu), prop_name, "bool",
2998                             x86_cpu_get_bit_prop,
2999                             x86_cpu_set_bit_prop,
3000                             x86_cpu_release_bit_prop, fp, &error_abort);
3001     }
3002 }
3003
3004 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3005                                                FeatureWord w,
3006                                                int bitnr)
3007 {
3008     Object *obj = OBJECT(cpu);
3009     int i;
3010     char **names;
3011     FeatureWordInfo *fi = &feature_word_info[w];
3012
3013     if (!fi->feat_names) {
3014         return;
3015     }
3016     if (!fi->feat_names[bitnr]) {
3017         return;
3018     }
3019
3020     names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3021
3022     feat2prop(names[0]);
3023     x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3024
3025     for (i = 1; names[i]; i++) {
3026         feat2prop(names[i]);
3027         object_property_add_alias(obj, names[i], obj, names[0],
3028                                   &error_abort);
3029     }
3030
3031     g_strfreev(names);
3032 }
3033
3034 static void x86_cpu_initfn(Object *obj)
3035 {
3036     CPUState *cs = CPU(obj);
3037     X86CPU *cpu = X86_CPU(obj);
3038     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3039     CPUX86State *env = &cpu->env;
3040     FeatureWord w;
3041     static int inited;
3042
3043     cs->env_ptr = env;
3044     cpu_exec_init(cs, &error_abort);
3045
3046     object_property_add(obj, "family", "int",
3047                         x86_cpuid_version_get_family,
3048                         x86_cpuid_version_set_family, NULL, NULL, NULL);
3049     object_property_add(obj, "model", "int",
3050                         x86_cpuid_version_get_model,
3051                         x86_cpuid_version_set_model, NULL, NULL, NULL);
3052     object_property_add(obj, "stepping", "int",
3053                         x86_cpuid_version_get_stepping,
3054                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3055     object_property_add_str(obj, "vendor",
3056                             x86_cpuid_get_vendor,
3057                             x86_cpuid_set_vendor, NULL);
3058     object_property_add_str(obj, "model-id",
3059                             x86_cpuid_get_model_id,
3060                             x86_cpuid_set_model_id, NULL);
3061     object_property_add(obj, "tsc-frequency", "int",
3062                         x86_cpuid_get_tsc_freq,
3063                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3064     object_property_add(obj, "apic-id", "int",
3065                         x86_cpuid_get_apic_id,
3066                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
3067     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3068                         x86_cpu_get_feature_words,
3069                         NULL, NULL, (void *)env->features, NULL);
3070     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3071                         x86_cpu_get_feature_words,
3072                         NULL, NULL, (void *)cpu->filtered_features, NULL);
3073
3074     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3075
3076 #ifndef CONFIG_USER_ONLY
3077     /* Any code creating new X86CPU objects have to set apic-id explicitly */
3078     cpu->apic_id = -1;
3079 #endif
3080
3081     for (w = 0; w < FEATURE_WORDS; w++) {
3082         int bitnr;
3083
3084         for (bitnr = 0; bitnr < 32; bitnr++) {
3085             x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3086         }
3087     }
3088
3089     x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3090
3091     /* init various static tables used in TCG mode */
3092     if (tcg_enabled() && !inited) {
3093         inited = 1;
3094         optimize_flags_init();
3095     }
3096 }
3097
3098 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3099 {
3100     X86CPU *cpu = X86_CPU(cs);
3101
3102     return cpu->apic_id;
3103 }
3104
3105 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3106 {
3107     X86CPU *cpu = X86_CPU(cs);
3108
3109     return cpu->env.cr[0] & CR0_PG_MASK;
3110 }
3111
3112 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3113 {
3114     X86CPU *cpu = X86_CPU(cs);
3115
3116     cpu->env.eip = value;
3117 }
3118
3119 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3120 {
3121     X86CPU *cpu = X86_CPU(cs);
3122
3123     cpu->env.eip = tb->pc - tb->cs_base;
3124 }
3125
3126 static bool x86_cpu_has_work(CPUState *cs)
3127 {
3128     X86CPU *cpu = X86_CPU(cs);
3129     CPUX86State *env = &cpu->env;
3130
3131     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3132                                       CPU_INTERRUPT_POLL)) &&
3133             (env->eflags & IF_MASK)) ||
3134            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3135                                      CPU_INTERRUPT_INIT |
3136                                      CPU_INTERRUPT_SIPI |
3137                                      CPU_INTERRUPT_MCE)) ||
3138            ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3139             !(env->hflags & HF_SMM_MASK));
3140 }
3141
3142 static Property x86_cpu_properties[] = {
3143     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3144     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
3145     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3146     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3147     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3148     DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
3149     DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
3150     DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
3151     DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
3152     DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
3153     DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
3154     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
3155     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3156     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3157     DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3158     DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
3159     DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
3160     DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
3161     DEFINE_PROP_END_OF_LIST()
3162 };
3163
3164 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3165 {
3166     X86CPUClass *xcc = X86_CPU_CLASS(oc);
3167     CPUClass *cc = CPU_CLASS(oc);
3168     DeviceClass *dc = DEVICE_CLASS(oc);
3169
3170     xcc->parent_realize = dc->realize;
3171     dc->realize = x86_cpu_realizefn;
3172     dc->props = x86_cpu_properties;
3173
3174     xcc->parent_reset = cc->reset;
3175     cc->reset = x86_cpu_reset;
3176     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3177
3178     cc->class_by_name = x86_cpu_class_by_name;
3179     cc->parse_features = x86_cpu_parse_featurestr;
3180     cc->has_work = x86_cpu_has_work;
3181     cc->do_interrupt = x86_cpu_do_interrupt;
3182     cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3183     cc->dump_state = x86_cpu_dump_state;
3184     cc->set_pc = x86_cpu_set_pc;
3185     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3186     cc->gdb_read_register = x86_cpu_gdb_read_register;
3187     cc->gdb_write_register = x86_cpu_gdb_write_register;
3188     cc->get_arch_id = x86_cpu_get_arch_id;
3189     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3190 #ifdef CONFIG_USER_ONLY
3191     cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3192 #else
3193     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3194     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3195     cc->write_elf64_note = x86_cpu_write_elf64_note;
3196     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3197     cc->write_elf32_note = x86_cpu_write_elf32_note;
3198     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3199     cc->vmsd = &vmstate_x86_cpu;
3200 #endif
3201     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3202 #ifndef CONFIG_USER_ONLY
3203     cc->debug_excp_handler = breakpoint_handler;
3204 #endif
3205     cc->cpu_exec_enter = x86_cpu_exec_enter;
3206     cc->cpu_exec_exit = x86_cpu_exec_exit;
3207
3208     /*
3209      * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3210      * object in cpus -> dangling pointer after final object_unref().
3211      */
3212     dc->cannot_destroy_with_object_finalize_yet = true;
3213 }
3214
3215 static const TypeInfo x86_cpu_type_info = {
3216     .name = TYPE_X86_CPU,
3217     .parent = TYPE_CPU,
3218     .instance_size = sizeof(X86CPU),
3219     .instance_init = x86_cpu_initfn,
3220     .abstract = true,
3221     .class_size = sizeof(X86CPUClass),
3222     .class_init = x86_cpu_common_class_init,
3223 };
3224
3225 static void x86_cpu_register_types(void)
3226 {
3227     int i;
3228
3229     type_register_static(&x86_cpu_type_info);
3230     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3231         x86_register_cpudef_type(&builtin_x86_defs[i]);
3232     }
3233 #ifdef CONFIG_KVM
3234     type_register_static(&host_x86_cpu_type_info);
3235 #endif
3236 }
3237
3238 type_init(x86_cpu_register_types)