tci.c

   1 /*
   2  * Tiny Code Interpreter for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "config.h"
  21
  22 /* Defining NDEBUG disables assertions (which makes the code faster). */
  23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
  24 # define NDEBUG
  25 #endif
  26
  27 #include "qemu-common.h"
  28 #include "exec/exec-all.h"           /* MAX_OPC_PARAM_IARGS */
  29 #include "tcg-op.h"
  30
  31 /* Marker for missing code. */
  32 #define TODO() \
  33     do { \
  34         fprintf(stderr, "TODO %s:%u: %s()\n", \
  35                 __FILE__, __LINE__, __func__); \
  36         tcg_abort(); \
  37     } while (0)
  38
  39 #if MAX_OPC_PARAM_IARGS != 5
  40 # error Fix needed, number of supported input arguments changed!
  41 #endif
  42 #if TCG_TARGET_REG_BITS == 32
  43 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
  44                                     tcg_target_ulong, tcg_target_ulong,
  45                                     tcg_target_ulong, tcg_target_ulong,
  46                                     tcg_target_ulong, tcg_target_ulong,
  47                                     tcg_target_ulong, tcg_target_ulong);
  48 #else
  49 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
  50                                     tcg_target_ulong, tcg_target_ulong,
  51                                     tcg_target_ulong);
  52 #endif
  53
  54 /* TCI can optionally use a global register variable for env. */
  55 #if !defined(AREG0)
  56 CPUArchState *env;
  57 #endif
  58
  59 /* Targets which don't use GETPC also don't need tci_tb_ptr
  60    which makes them a little faster. */
  61 #if defined(GETPC)
  62 uintptr_t tci_tb_ptr;
  63 #endif
  64
  65 static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
  66
  67 static tcg_target_ulong tci_read_reg(TCGReg index)
  68 {
  69     assert(index < ARRAY_SIZE(tci_reg));
  70     return tci_reg[index];
  71 }
  72
  73 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
  74 static int8_t tci_read_reg8s(TCGReg index)
  75 {
  76     return (int8_t)tci_read_reg(index);
  77 }
  78 #endif
  79
  80 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
  81 static int16_t tci_read_reg16s(TCGReg index)
  82 {
  83     return (int16_t)tci_read_reg(index);
  84 }
  85 #endif
  86
  87 #if TCG_TARGET_REG_BITS == 64
  88 static int32_t tci_read_reg32s(TCGReg index)
  89 {
  90     return (int32_t)tci_read_reg(index);
  91 }
  92 #endif
  93
  94 static uint8_t tci_read_reg8(TCGReg index)
  95 {
  96     return (uint8_t)tci_read_reg(index);
  97 }
  98
  99 static uint16_t tci_read_reg16(TCGReg index)
 100 {
 101     return (uint16_t)tci_read_reg(index);
 102 }
 103
 104 static uint32_t tci_read_reg32(TCGReg index)
 105 {
 106     return (uint32_t)tci_read_reg(index);
 107 }
 108
 109 #if TCG_TARGET_REG_BITS == 64
 110 static uint64_t tci_read_reg64(TCGReg index)
 111 {
 112     return tci_read_reg(index);
 113 }
 114 #endif
 115
 116 static void tci_write_reg(TCGReg index, tcg_target_ulong value)
 117 {
 118     assert(index < ARRAY_SIZE(tci_reg));
 119     assert(index != TCG_AREG0);
 120     tci_reg[index] = value;
 121 }
 122
 123 static void tci_write_reg8s(TCGReg index, int8_t value)
 124 {
 125     tci_write_reg(index, value);
 126 }
 127
 128 static void tci_write_reg16s(TCGReg index, int16_t value)
 129 {
 130     tci_write_reg(index, value);
 131 }
 132
 133 #if TCG_TARGET_REG_BITS == 64
 134 static void tci_write_reg32s(TCGReg index, int32_t value)
 135 {
 136     tci_write_reg(index, value);
 137 }
 138 #endif
 139
 140 static void tci_write_reg8(TCGReg index, uint8_t value)
 141 {
 142     tci_write_reg(index, value);
 143 }
 144
 145 static void tci_write_reg16(TCGReg index, uint16_t value)
 146 {
 147     tci_write_reg(index, value);
 148 }
 149
 150 static void tci_write_reg32(TCGReg index, uint32_t value)
 151 {
 152     tci_write_reg(index, value);
 153 }
 154
 155 #if TCG_TARGET_REG_BITS == 32
 156 static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
 157                             uint64_t value)
 158 {
 159     tci_write_reg(low_index, value);
 160     tci_write_reg(high_index, value >> 32);
 161 }
 162 #elif TCG_TARGET_REG_BITS == 64
 163 static void tci_write_reg64(TCGReg index, uint64_t value)
 164 {
 165     tci_write_reg(index, value);
 166 }
 167 #endif
 168
 169 #if TCG_TARGET_REG_BITS == 32
 170 /* Create a 64 bit value from two 32 bit values. */
 171 static uint64_t tci_uint64(uint32_t high, uint32_t low)
 172 {
 173     return ((uint64_t)high << 32) + low;
 174 }
 175 #endif
 176
 177 /* Read constant (native size) from bytecode. */
 178 static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
 179 {
 180     tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
 181     *tb_ptr += sizeof(value);
 182     return value;
 183 }
 184
 185 /* Read constant (32 bit) from bytecode. */
 186 static uint32_t tci_read_i32(uint8_t **tb_ptr)
 187 {
 188     uint32_t value = *(uint32_t *)(*tb_ptr);
 189     *tb_ptr += sizeof(value);
 190     return value;
 191 }
 192
 193 #if TCG_TARGET_REG_BITS == 64
 194 /* Read constant (64 bit) from bytecode. */
 195 static uint64_t tci_read_i64(uint8_t **tb_ptr)
 196 {
 197     uint64_t value = *(uint64_t *)(*tb_ptr);
 198     *tb_ptr += sizeof(value);
 199     return value;
 200 }
 201 #endif
 202
 203 /* Read indexed register (native size) from bytecode. */
 204 static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
 205 {
 206     tcg_target_ulong value = tci_read_reg(**tb_ptr);
 207     *tb_ptr += 1;
 208     return value;
 209 }
 210
 211 /* Read indexed register (8 bit) from bytecode. */
 212 static uint8_t tci_read_r8(uint8_t **tb_ptr)
 213 {
 214     uint8_t value = tci_read_reg8(**tb_ptr);
 215     *tb_ptr += 1;
 216     return value;
 217 }
 218
 219 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
 220 /* Read indexed register (8 bit signed) from bytecode. */
 221 static int8_t tci_read_r8s(uint8_t **tb_ptr)
 222 {
 223     int8_t value = tci_read_reg8s(**tb_ptr);
 224     *tb_ptr += 1;
 225     return value;
 226 }
 227 #endif
 228
 229 /* Read indexed register (16 bit) from bytecode. */
 230 static uint16_t tci_read_r16(uint8_t **tb_ptr)
 231 {
 232     uint16_t value = tci_read_reg16(**tb_ptr);
 233     *tb_ptr += 1;
 234     return value;
 235 }
 236
 237 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
 238 /* Read indexed register (16 bit signed) from bytecode. */
 239 static int16_t tci_read_r16s(uint8_t **tb_ptr)
 240 {
 241     int16_t value = tci_read_reg16s(**tb_ptr);
 242     *tb_ptr += 1;
 243     return value;
 244 }
 245 #endif
 246
 247 /* Read indexed register (32 bit) from bytecode. */
 248 static uint32_t tci_read_r32(uint8_t **tb_ptr)
 249 {
 250     uint32_t value = tci_read_reg32(**tb_ptr);
 251     *tb_ptr += 1;
 252     return value;
 253 }
 254
 255 #if TCG_TARGET_REG_BITS == 32
 256 /* Read two indexed registers (2 * 32 bit) from bytecode. */
 257 static uint64_t tci_read_r64(uint8_t **tb_ptr)
 258 {
 259     uint32_t low = tci_read_r32(tb_ptr);
 260     return tci_uint64(tci_read_r32(tb_ptr), low);
 261 }
 262 #elif TCG_TARGET_REG_BITS == 64
 263 /* Read indexed register (32 bit signed) from bytecode. */
 264 static int32_t tci_read_r32s(uint8_t **tb_ptr)
 265 {
 266     int32_t value = tci_read_reg32s(**tb_ptr);
 267     *tb_ptr += 1;
 268     return value;
 269 }
 270
 271 /* Read indexed register (64 bit) from bytecode. */
 272 static uint64_t tci_read_r64(uint8_t **tb_ptr)
 273 {
 274     uint64_t value = tci_read_reg64(**tb_ptr);
 275     *tb_ptr += 1;
 276     return value;
 277 }
 278 #endif
 279
 280 /* Read indexed register(s) with target address from bytecode. */
 281 static target_ulong tci_read_ulong(uint8_t **tb_ptr)
 282 {
 283     target_ulong taddr = tci_read_r(tb_ptr);
 284 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
 285     taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
 286 #endif
 287     return taddr;
 288 }
 289
 290 /* Read indexed register or constant (native size) from bytecode. */
 291 static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
 292 {
 293     tcg_target_ulong value;
 294     TCGReg r = **tb_ptr;
 295     *tb_ptr += 1;
 296     if (r == TCG_CONST) {
 297         value = tci_read_i(tb_ptr);
 298     } else {
 299         value = tci_read_reg(r);
 300     }
 301     return value;
 302 }
 303
 304 /* Read indexed register or constant (32 bit) from bytecode. */
 305 static uint32_t tci_read_ri32(uint8_t **tb_ptr)
 306 {
 307     uint32_t value;
 308     TCGReg r = **tb_ptr;
 309     *tb_ptr += 1;
 310     if (r == TCG_CONST) {
 311         value = tci_read_i32(tb_ptr);
 312     } else {
 313         value = tci_read_reg32(r);
 314     }
 315     return value;
 316 }
 317
 318 #if TCG_TARGET_REG_BITS == 32
 319 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
 320 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
 321 {
 322     uint32_t low = tci_read_ri32(tb_ptr);
 323     return tci_uint64(tci_read_ri32(tb_ptr), low);
 324 }
 325 #elif TCG_TARGET_REG_BITS == 64
 326 /* Read indexed register or constant (64 bit) from bytecode. */
 327 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
 328 {
 329     uint64_t value;
 330     TCGReg r = **tb_ptr;
 331     *tb_ptr += 1;
 332     if (r == TCG_CONST) {
 333         value = tci_read_i64(tb_ptr);
 334     } else {
 335         value = tci_read_reg64(r);
 336     }
 337     return value;
 338 }
 339 #endif
 340
 341 static tcg_target_ulong tci_read_label(uint8_t **tb_ptr)
 342 {
 343     tcg_target_ulong label = tci_read_i(tb_ptr);
 344     assert(label != 0);
 345     return label;
 346 }
 347
 348 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
 349 {
 350     bool result = false;
 351     int32_t i0 = u0;
 352     int32_t i1 = u1;
 353     switch (condition) {
 354     case TCG_COND_EQ:
 355         result = (u0 == u1);
 356         break;
 357     case TCG_COND_NE:
 358         result = (u0 != u1);
 359         break;
 360     case TCG_COND_LT:
 361         result = (i0 < i1);
 362         break;
 363     case TCG_COND_GE:
 364         result = (i0 >= i1);
 365         break;
 366     case TCG_COND_LE:
 367         result = (i0 <= i1);
 368         break;
 369     case TCG_COND_GT:
 370         result = (i0 > i1);
 371         break;
 372     case TCG_COND_LTU:
 373         result = (u0 < u1);
 374         break;
 375     case TCG_COND_GEU:
 376         result = (u0 >= u1);
 377         break;
 378     case TCG_COND_LEU:
 379         result = (u0 <= u1);
 380         break;
 381     case TCG_COND_GTU:
 382         result = (u0 > u1);
 383         break;
 384     default:
 385         TODO();
 386     }
 387     return result;
 388 }
 389
 390 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
 391 {
 392     bool result = false;
 393     int64_t i0 = u0;
 394     int64_t i1 = u1;
 395     switch (condition) {
 396     case TCG_COND_EQ:
 397         result = (u0 == u1);
 398         break;
 399     case TCG_COND_NE:
 400         result = (u0 != u1);
 401         break;
 402     case TCG_COND_LT:
 403         result = (i0 < i1);
 404         break;
 405     case TCG_COND_GE:
 406         result = (i0 >= i1);
 407         break;
 408     case TCG_COND_LE:
 409         result = (i0 <= i1);
 410         break;
 411     case TCG_COND_GT:
 412         result = (i0 > i1);
 413         break;
 414     case TCG_COND_LTU:
 415         result = (u0 < u1);
 416         break;
 417     case TCG_COND_GEU:
 418         result = (u0 >= u1);
 419         break;
 420     case TCG_COND_LEU:
 421         result = (u0 <= u1);
 422         break;
 423     case TCG_COND_GTU:
 424         result = (u0 > u1);
 425         break;
 426     default:
 427         TODO();
 428     }
 429     return result;
 430 }
 431
 432 /* Interpret pseudo code in tb. */
 433 tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
 434 {
 435     tcg_target_ulong next_tb = 0;
 436
 437     env = cpustate;
 438     tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
 439     assert(tb_ptr);
 440
 441     for (;;) {
 442 #if defined(GETPC)
 443         tci_tb_ptr = (uintptr_t)tb_ptr;
 444 #endif
 445         TCGOpcode opc = tb_ptr[0];
 446 #if !defined(NDEBUG)
 447         uint8_t op_size = tb_ptr[1];
 448         uint8_t *old_code_ptr = tb_ptr;
 449 #endif
 450         tcg_target_ulong t0;
 451         tcg_target_ulong t1;
 452         tcg_target_ulong t2;
 453         tcg_target_ulong label;
 454         TCGCond condition;
 455         target_ulong taddr;
 456 #ifndef CONFIG_SOFTMMU
 457         tcg_target_ulong host_addr;
 458 #endif
 459         uint8_t tmp8;
 460         uint16_t tmp16;
 461         uint32_t tmp32;
 462         uint64_t tmp64;
 463 #if TCG_TARGET_REG_BITS == 32
 464         uint64_t v64;
 465 #endif
 466
 467         /* Skip opcode and size entry. */
 468         tb_ptr += 2;
 469
 470         switch (opc) {
 471         case INDEX_op_end:
 472         case INDEX_op_nop:
 473             break;
 474         case INDEX_op_nop1:
 475         case INDEX_op_nop2:
 476         case INDEX_op_nop3:
 477         case INDEX_op_nopn:
 478         case INDEX_op_discard:
 479             TODO();
 480             break;
 481         case INDEX_op_set_label:
 482             TODO();
 483             break;
 484         case INDEX_op_call:
 485             t0 = tci_read_ri(&tb_ptr);
 486 #if TCG_TARGET_REG_BITS == 32
 487             tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
 488                                           tci_read_reg(TCG_REG_R1),
 489                                           tci_read_reg(TCG_REG_R2),
 490                                           tci_read_reg(TCG_REG_R3),
 491                                           tci_read_reg(TCG_REG_R5),
 492                                           tci_read_reg(TCG_REG_R6),
 493                                           tci_read_reg(TCG_REG_R7),
 494                                           tci_read_reg(TCG_REG_R8),
 495                                           tci_read_reg(TCG_REG_R9),
 496                                           tci_read_reg(TCG_REG_R10));
 497             tci_write_reg(TCG_REG_R0, tmp64);
 498             tci_write_reg(TCG_REG_R1, tmp64 >> 32);
 499 #else
 500             tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
 501                                           tci_read_reg(TCG_REG_R1),
 502                                           tci_read_reg(TCG_REG_R2),
 503                                           tci_read_reg(TCG_REG_R3),
 504                                           tci_read_reg(TCG_REG_R5));
 505             tci_write_reg(TCG_REG_R0, tmp64);
 506 #endif
 507             break;
 508         case INDEX_op_br:
 509             label = tci_read_label(&tb_ptr);
 510             assert(tb_ptr == old_code_ptr + op_size);
 511             tb_ptr = (uint8_t *)label;
 512             continue;
 513         case INDEX_op_setcond_i32:
 514             t0 = *tb_ptr++;
 515             t1 = tci_read_r32(&tb_ptr);
 516             t2 = tci_read_ri32(&tb_ptr);
 517             condition = *tb_ptr++;
 518             tci_write_reg32(t0, tci_compare32(t1, t2, condition));
 519             break;
 520 #if TCG_TARGET_REG_BITS == 32
 521         case INDEX_op_setcond2_i32:
 522             t0 = *tb_ptr++;
 523             tmp64 = tci_read_r64(&tb_ptr);
 524             v64 = tci_read_ri64(&tb_ptr);
 525             condition = *tb_ptr++;
 526             tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
 527             break;
 528 #elif TCG_TARGET_REG_BITS == 64
 529         case INDEX_op_setcond_i64:
 530             t0 = *tb_ptr++;
 531             t1 = tci_read_r64(&tb_ptr);
 532             t2 = tci_read_ri64(&tb_ptr);
 533             condition = *tb_ptr++;
 534             tci_write_reg64(t0, tci_compare64(t1, t2, condition));
 535             break;
 536 #endif
 537         case INDEX_op_mov_i32:
 538             t0 = *tb_ptr++;
 539             t1 = tci_read_r32(&tb_ptr);
 540             tci_write_reg32(t0, t1);
 541             break;
 542         case INDEX_op_movi_i32:
 543             t0 = *tb_ptr++;
 544             t1 = tci_read_i32(&tb_ptr);
 545             tci_write_reg32(t0, t1);
 546             break;
 547
 548             /* Load/store operations (32 bit). */
 549
 550         case INDEX_op_ld8u_i32:
 551             t0 = *tb_ptr++;
 552             t1 = tci_read_r(&tb_ptr);
 553             t2 = tci_read_i32(&tb_ptr);
 554             tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
 555             break;
 556         case INDEX_op_ld8s_i32:
 557         case INDEX_op_ld16u_i32:
 558             TODO();
 559             break;
 560         case INDEX_op_ld16s_i32:
 561             TODO();
 562             break;
 563         case INDEX_op_ld_i32:
 564             t0 = *tb_ptr++;
 565             t1 = tci_read_r(&tb_ptr);
 566             t2 = tci_read_i32(&tb_ptr);
 567             tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
 568             break;
 569         case INDEX_op_st8_i32:
 570             t0 = tci_read_r8(&tb_ptr);
 571             t1 = tci_read_r(&tb_ptr);
 572             t2 = tci_read_i32(&tb_ptr);
 573             *(uint8_t *)(t1 + t2) = t0;
 574             break;
 575         case INDEX_op_st16_i32:
 576             t0 = tci_read_r16(&tb_ptr);
 577             t1 = tci_read_r(&tb_ptr);
 578             t2 = tci_read_i32(&tb_ptr);
 579             *(uint16_t *)(t1 + t2) = t0;
 580             break;
 581         case INDEX_op_st_i32:
 582             t0 = tci_read_r32(&tb_ptr);
 583             t1 = tci_read_r(&tb_ptr);
 584             t2 = tci_read_i32(&tb_ptr);
 585             *(uint32_t *)(t1 + t2) = t0;
 586             break;
 587
 588             /* Arithmetic operations (32 bit). */
 589
 590         case INDEX_op_add_i32:
 591             t0 = *tb_ptr++;
 592             t1 = tci_read_ri32(&tb_ptr);
 593             t2 = tci_read_ri32(&tb_ptr);
 594             tci_write_reg32(t0, t1 + t2);
 595             break;
 596         case INDEX_op_sub_i32:
 597             t0 = *tb_ptr++;
 598             t1 = tci_read_ri32(&tb_ptr);
 599             t2 = tci_read_ri32(&tb_ptr);
 600             tci_write_reg32(t0, t1 - t2);
 601             break;
 602         case INDEX_op_mul_i32:
 603             t0 = *tb_ptr++;
 604             t1 = tci_read_ri32(&tb_ptr);
 605             t2 = tci_read_ri32(&tb_ptr);
 606             tci_write_reg32(t0, t1 * t2);
 607             break;
 608 #if TCG_TARGET_HAS_div_i32
 609         case INDEX_op_div_i32:
 610             t0 = *tb_ptr++;
 611             t1 = tci_read_ri32(&tb_ptr);
 612             t2 = tci_read_ri32(&tb_ptr);
 613             tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
 614             break;
 615         case INDEX_op_divu_i32:
 616             t0 = *tb_ptr++;
 617             t1 = tci_read_ri32(&tb_ptr);
 618             t2 = tci_read_ri32(&tb_ptr);
 619             tci_write_reg32(t0, t1 / t2);
 620             break;
 621         case INDEX_op_rem_i32:
 622             t0 = *tb_ptr++;
 623             t1 = tci_read_ri32(&tb_ptr);
 624             t2 = tci_read_ri32(&tb_ptr);
 625             tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
 626             break;
 627         case INDEX_op_remu_i32:
 628             t0 = *tb_ptr++;
 629             t1 = tci_read_ri32(&tb_ptr);
 630             t2 = tci_read_ri32(&tb_ptr);
 631             tci_write_reg32(t0, t1 % t2);
 632             break;
 633 #elif TCG_TARGET_HAS_div2_i32
 634         case INDEX_op_div2_i32:
 635         case INDEX_op_divu2_i32:
 636             TODO();
 637             break;
 638 #endif
 639         case INDEX_op_and_i32:
 640             t0 = *tb_ptr++;
 641             t1 = tci_read_ri32(&tb_ptr);
 642             t2 = tci_read_ri32(&tb_ptr);
 643             tci_write_reg32(t0, t1 & t2);
 644             break;
 645         case INDEX_op_or_i32:
 646             t0 = *tb_ptr++;
 647             t1 = tci_read_ri32(&tb_ptr);
 648             t2 = tci_read_ri32(&tb_ptr);
 649             tci_write_reg32(t0, t1 | t2);
 650             break;
 651         case INDEX_op_xor_i32:
 652             t0 = *tb_ptr++;
 653             t1 = tci_read_ri32(&tb_ptr);
 654             t2 = tci_read_ri32(&tb_ptr);
 655             tci_write_reg32(t0, t1 ^ t2);
 656             break;
 657
 658             /* Shift/rotate operations (32 bit). */
 659
 660         case INDEX_op_shl_i32:
 661             t0 = *tb_ptr++;
 662             t1 = tci_read_ri32(&tb_ptr);
 663             t2 = tci_read_ri32(&tb_ptr);
 664             tci_write_reg32(t0, t1 << t2);
 665             break;
 666         case INDEX_op_shr_i32:
 667             t0 = *tb_ptr++;
 668             t1 = tci_read_ri32(&tb_ptr);
 669             t2 = tci_read_ri32(&tb_ptr);
 670             tci_write_reg32(t0, t1 >> t2);
 671             break;
 672         case INDEX_op_sar_i32:
 673             t0 = *tb_ptr++;
 674             t1 = tci_read_ri32(&tb_ptr);
 675             t2 = tci_read_ri32(&tb_ptr);
 676             tci_write_reg32(t0, ((int32_t)t1 >> t2));
 677             break;
 678 #if TCG_TARGET_HAS_rot_i32
 679         case INDEX_op_rotl_i32:
 680             t0 = *tb_ptr++;
 681             t1 = tci_read_ri32(&tb_ptr);
 682             t2 = tci_read_ri32(&tb_ptr);
 683             tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2)));
 684             break;
 685         case INDEX_op_rotr_i32:
 686             t0 = *tb_ptr++;
 687             t1 = tci_read_ri32(&tb_ptr);
 688             t2 = tci_read_ri32(&tb_ptr);
 689             tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2)));
 690             break;
 691 #endif
 692 #if TCG_TARGET_HAS_deposit_i32
 693         case INDEX_op_deposit_i32:
 694             t0 = *tb_ptr++;
 695             t1 = tci_read_r32(&tb_ptr);
 696             t2 = tci_read_r32(&tb_ptr);
 697             tmp16 = *tb_ptr++;
 698             tmp8 = *tb_ptr++;
 699             tmp32 = (((1 << tmp8) - 1) << tmp16);
 700             tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
 701             break;
 702 #endif
 703         case INDEX_op_brcond_i32:
 704             t0 = tci_read_r32(&tb_ptr);
 705             t1 = tci_read_ri32(&tb_ptr);
 706             condition = *tb_ptr++;
 707             label = tci_read_label(&tb_ptr);
 708             if (tci_compare32(t0, t1, condition)) {
 709                 assert(tb_ptr == old_code_ptr + op_size);
 710                 tb_ptr = (uint8_t *)label;
 711                 continue;
 712             }
 713             break;
 714 #if TCG_TARGET_REG_BITS == 32
 715         case INDEX_op_add2_i32:
 716             t0 = *tb_ptr++;
 717             t1 = *tb_ptr++;
 718             tmp64 = tci_read_r64(&tb_ptr);
 719             tmp64 += tci_read_r64(&tb_ptr);
 720             tci_write_reg64(t1, t0, tmp64);
 721             break;
 722         case INDEX_op_sub2_i32:
 723             t0 = *tb_ptr++;
 724             t1 = *tb_ptr++;
 725             tmp64 = tci_read_r64(&tb_ptr);
 726             tmp64 -= tci_read_r64(&tb_ptr);
 727             tci_write_reg64(t1, t0, tmp64);
 728             break;
 729         case INDEX_op_brcond2_i32:
 730             tmp64 = tci_read_r64(&tb_ptr);
 731             v64 = tci_read_ri64(&tb_ptr);
 732             condition = *tb_ptr++;
 733             label = tci_read_label(&tb_ptr);
 734             if (tci_compare64(tmp64, v64, condition)) {
 735                 assert(tb_ptr == old_code_ptr + op_size);
 736                 tb_ptr = (uint8_t *)label;
 737                 continue;
 738             }
 739             break;
 740         case INDEX_op_mulu2_i32:
 741             t0 = *tb_ptr++;
 742             t1 = *tb_ptr++;
 743             t2 = tci_read_r32(&tb_ptr);
 744             tmp64 = tci_read_r32(&tb_ptr);
 745             tci_write_reg64(t1, t0, t2 * tmp64);
 746             break;
 747 #endif /* TCG_TARGET_REG_BITS == 32 */
 748 #if TCG_TARGET_HAS_ext8s_i32
 749         case INDEX_op_ext8s_i32:
 750             t0 = *tb_ptr++;
 751             t1 = tci_read_r8s(&tb_ptr);
 752             tci_write_reg32(t0, t1);
 753             break;
 754 #endif
 755 #if TCG_TARGET_HAS_ext16s_i32
 756         case INDEX_op_ext16s_i32:
 757             t0 = *tb_ptr++;
 758             t1 = tci_read_r16s(&tb_ptr);
 759             tci_write_reg32(t0, t1);
 760             break;
 761 #endif
 762 #if TCG_TARGET_HAS_ext8u_i32
 763         case INDEX_op_ext8u_i32:
 764             t0 = *tb_ptr++;
 765             t1 = tci_read_r8(&tb_ptr);
 766             tci_write_reg32(t0, t1);
 767             break;
 768 #endif
 769 #if TCG_TARGET_HAS_ext16u_i32
 770         case INDEX_op_ext16u_i32:
 771             t0 = *tb_ptr++;
 772             t1 = tci_read_r16(&tb_ptr);
 773             tci_write_reg32(t0, t1);
 774             break;
 775 #endif
 776 #if TCG_TARGET_HAS_bswap16_i32
 777         case INDEX_op_bswap16_i32:
 778             t0 = *tb_ptr++;
 779             t1 = tci_read_r16(&tb_ptr);
 780             tci_write_reg32(t0, bswap16(t1));
 781             break;
 782 #endif
 783 #if TCG_TARGET_HAS_bswap32_i32
 784         case INDEX_op_bswap32_i32:
 785             t0 = *tb_ptr++;
 786             t1 = tci_read_r32(&tb_ptr);
 787             tci_write_reg32(t0, bswap32(t1));
 788             break;
 789 #endif
 790 #if TCG_TARGET_HAS_not_i32
 791         case INDEX_op_not_i32:
 792             t0 = *tb_ptr++;
 793             t1 = tci_read_r32(&tb_ptr);
 794             tci_write_reg32(t0, ~t1);
 795             break;
 796 #endif
 797 #if TCG_TARGET_HAS_neg_i32
 798         case INDEX_op_neg_i32:
 799             t0 = *tb_ptr++;
 800             t1 = tci_read_r32(&tb_ptr);
 801             tci_write_reg32(t0, -t1);
 802             break;
 803 #endif
 804 #if TCG_TARGET_REG_BITS == 64
 805         case INDEX_op_mov_i64:
 806             t0 = *tb_ptr++;
 807             t1 = tci_read_r64(&tb_ptr);
 808             tci_write_reg64(t0, t1);
 809             break;
 810         case INDEX_op_movi_i64:
 811             t0 = *tb_ptr++;
 812             t1 = tci_read_i64(&tb_ptr);
 813             tci_write_reg64(t0, t1);
 814             break;
 815
 816             /* Load/store operations (64 bit). */
 817
 818         case INDEX_op_ld8u_i64:
 819             t0 = *tb_ptr++;
 820             t1 = tci_read_r(&tb_ptr);
 821             t2 = tci_read_i32(&tb_ptr);
 822             tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
 823             break;
 824         case INDEX_op_ld8s_i64:
 825         case INDEX_op_ld16u_i64:
 826         case INDEX_op_ld16s_i64:
 827             TODO();
 828             break;
 829         case INDEX_op_ld32u_i64:
 830             t0 = *tb_ptr++;
 831             t1 = tci_read_r(&tb_ptr);
 832             t2 = tci_read_i32(&tb_ptr);
 833             tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
 834             break;
 835         case INDEX_op_ld32s_i64:
 836             t0 = *tb_ptr++;
 837             t1 = tci_read_r(&tb_ptr);
 838             t2 = tci_read_i32(&tb_ptr);
 839             tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
 840             break;
 841         case INDEX_op_ld_i64:
 842             t0 = *tb_ptr++;
 843             t1 = tci_read_r(&tb_ptr);
 844             t2 = tci_read_i32(&tb_ptr);
 845             tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
 846             break;
 847         case INDEX_op_st8_i64:
 848             t0 = tci_read_r8(&tb_ptr);
 849             t1 = tci_read_r(&tb_ptr);
 850             t2 = tci_read_i32(&tb_ptr);
 851             *(uint8_t *)(t1 + t2) = t0;
 852             break;
 853         case INDEX_op_st16_i64:
 854             t0 = tci_read_r16(&tb_ptr);
 855             t1 = tci_read_r(&tb_ptr);
 856             t2 = tci_read_i32(&tb_ptr);
 857             *(uint16_t *)(t1 + t2) = t0;
 858             break;
 859         case INDEX_op_st32_i64:
 860             t0 = tci_read_r32(&tb_ptr);
 861             t1 = tci_read_r(&tb_ptr);
 862             t2 = tci_read_i32(&tb_ptr);
 863             *(uint32_t *)(t1 + t2) = t0;
 864             break;
 865         case INDEX_op_st_i64:
 866             t0 = tci_read_r64(&tb_ptr);
 867             t1 = tci_read_r(&tb_ptr);
 868             t2 = tci_read_i32(&tb_ptr);
 869             *(uint64_t *)(t1 + t2) = t0;
 870             break;
 871
 872             /* Arithmetic operations (64 bit). */
 873
 874         case INDEX_op_add_i64:
 875             t0 = *tb_ptr++;
 876             t1 = tci_read_ri64(&tb_ptr);
 877             t2 = tci_read_ri64(&tb_ptr);
 878             tci_write_reg64(t0, t1 + t2);
 879             break;
 880         case INDEX_op_sub_i64:
 881             t0 = *tb_ptr++;
 882             t1 = tci_read_ri64(&tb_ptr);
 883             t2 = tci_read_ri64(&tb_ptr);
 884             tci_write_reg64(t0, t1 - t2);
 885             break;
 886         case INDEX_op_mul_i64:
 887             t0 = *tb_ptr++;
 888             t1 = tci_read_ri64(&tb_ptr);
 889             t2 = tci_read_ri64(&tb_ptr);
 890             tci_write_reg64(t0, t1 * t2);
 891             break;
 892 #if TCG_TARGET_HAS_div_i64
 893         case INDEX_op_div_i64:
 894         case INDEX_op_divu_i64:
 895         case INDEX_op_rem_i64:
 896         case INDEX_op_remu_i64:
 897             TODO();
 898             break;
 899 #elif TCG_TARGET_HAS_div2_i64
 900         case INDEX_op_div2_i64:
 901         case INDEX_op_divu2_i64:
 902             TODO();
 903             break;
 904 #endif
 905         case INDEX_op_and_i64:
 906             t0 = *tb_ptr++;
 907             t1 = tci_read_ri64(&tb_ptr);
 908             t2 = tci_read_ri64(&tb_ptr);
 909             tci_write_reg64(t0, t1 & t2);
 910             break;
 911         case INDEX_op_or_i64:
 912             t0 = *tb_ptr++;
 913             t1 = tci_read_ri64(&tb_ptr);
 914             t2 = tci_read_ri64(&tb_ptr);
 915             tci_write_reg64(t0, t1 | t2);
 916             break;
 917         case INDEX_op_xor_i64:
 918             t0 = *tb_ptr++;
 919             t1 = tci_read_ri64(&tb_ptr);
 920             t2 = tci_read_ri64(&tb_ptr);
 921             tci_write_reg64(t0, t1 ^ t2);
 922             break;
 923
 924             /* Shift/rotate operations (64 bit). */
 925
 926         case INDEX_op_shl_i64:
 927             t0 = *tb_ptr++;
 928             t1 = tci_read_ri64(&tb_ptr);
 929             t2 = tci_read_ri64(&tb_ptr);
 930             tci_write_reg64(t0, t1 << t2);
 931             break;
 932         case INDEX_op_shr_i64:
 933             t0 = *tb_ptr++;
 934             t1 = tci_read_ri64(&tb_ptr);
 935             t2 = tci_read_ri64(&tb_ptr);
 936             tci_write_reg64(t0, t1 >> t2);
 937             break;
 938         case INDEX_op_sar_i64:
 939             t0 = *tb_ptr++;
 940             t1 = tci_read_ri64(&tb_ptr);
 941             t2 = tci_read_ri64(&tb_ptr);
 942             tci_write_reg64(t0, ((int64_t)t1 >> t2));
 943             break;
 944 #if TCG_TARGET_HAS_rot_i64
 945         case INDEX_op_rotl_i64:
 946         case INDEX_op_rotr_i64:
 947             TODO();
 948             break;
 949 #endif
 950 #if TCG_TARGET_HAS_deposit_i64
 951         case INDEX_op_deposit_i64:
 952             t0 = *tb_ptr++;
 953             t1 = tci_read_r64(&tb_ptr);
 954             t2 = tci_read_r64(&tb_ptr);
 955             tmp16 = *tb_ptr++;
 956             tmp8 = *tb_ptr++;
 957             tmp64 = (((1ULL << tmp8) - 1) << tmp16);
 958             tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
 959             break;
 960 #endif
 961         case INDEX_op_brcond_i64:
 962             t0 = tci_read_r64(&tb_ptr);
 963             t1 = tci_read_ri64(&tb_ptr);
 964             condition = *tb_ptr++;
 965             label = tci_read_label(&tb_ptr);
 966             if (tci_compare64(t0, t1, condition)) {
 967                 assert(tb_ptr == old_code_ptr + op_size);
 968                 tb_ptr = (uint8_t *)label;
 969                 continue;
 970             }
 971             break;
 972 #if TCG_TARGET_HAS_ext8u_i64
 973         case INDEX_op_ext8u_i64:
 974             t0 = *tb_ptr++;
 975             t1 = tci_read_r8(&tb_ptr);
 976             tci_write_reg64(t0, t1);
 977             break;
 978 #endif
 979 #if TCG_TARGET_HAS_ext8s_i64
 980         case INDEX_op_ext8s_i64:
 981             t0 = *tb_ptr++;
 982             t1 = tci_read_r8s(&tb_ptr);
 983             tci_write_reg64(t0, t1);
 984             break;
 985 #endif
 986 #if TCG_TARGET_HAS_ext16s_i64
 987         case INDEX_op_ext16s_i64:
 988             t0 = *tb_ptr++;
 989             t1 = tci_read_r16s(&tb_ptr);
 990             tci_write_reg64(t0, t1);
 991             break;
 992 #endif
 993 #if TCG_TARGET_HAS_ext16u_i64
 994         case INDEX_op_ext16u_i64:
 995             t0 = *tb_ptr++;
 996             t1 = tci_read_r16(&tb_ptr);
 997             tci_write_reg64(t0, t1);
 998             break;
 999 #endif
1000 #if TCG_TARGET_HAS_ext32s_i64
1001         case INDEX_op_ext32s_i64:
1002             t0 = *tb_ptr++;
1003             t1 = tci_read_r32s(&tb_ptr);
1004             tci_write_reg64(t0, t1);
1005             break;
1006 #endif
1007 #if TCG_TARGET_HAS_ext32u_i64
1008         case INDEX_op_ext32u_i64:
1009             t0 = *tb_ptr++;
1010             t1 = tci_read_r32(&tb_ptr);
1011             tci_write_reg64(t0, t1);
1012             break;
1013 #endif
1014 #if TCG_TARGET_HAS_bswap16_i64
1015         case INDEX_op_bswap16_i64:
1016             TODO();
1017             t0 = *tb_ptr++;
1018             t1 = tci_read_r16(&tb_ptr);
1019             tci_write_reg64(t0, bswap16(t1));
1020             break;
1021 #endif
1022 #if TCG_TARGET_HAS_bswap32_i64
1023         case INDEX_op_bswap32_i64:
1024             t0 = *tb_ptr++;
1025             t1 = tci_read_r32(&tb_ptr);
1026             tci_write_reg64(t0, bswap32(t1));
1027             break;
1028 #endif
1029 #if TCG_TARGET_HAS_bswap64_i64
1030         case INDEX_op_bswap64_i64:
1031             t0 = *tb_ptr++;
1032             t1 = tci_read_r64(&tb_ptr);
1033             tci_write_reg64(t0, bswap64(t1));
1034             break;
1035 #endif
1036 #if TCG_TARGET_HAS_not_i64
1037         case INDEX_op_not_i64:
1038             t0 = *tb_ptr++;
1039             t1 = tci_read_r64(&tb_ptr);
1040             tci_write_reg64(t0, ~t1);
1041             break;
1042 #endif
1043 #if TCG_TARGET_HAS_neg_i64
1044         case INDEX_op_neg_i64:
1045             t0 = *tb_ptr++;
1046             t1 = tci_read_r64(&tb_ptr);
1047             tci_write_reg64(t0, -t1);
1048             break;
1049 #endif
1050 #endif /* TCG_TARGET_REG_BITS == 64 */
1051
1052             /* QEMU specific operations. */
1053
1054 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1055         case INDEX_op_debug_insn_start:
1056             TODO();
1057             break;
1058 #else
1059         case INDEX_op_debug_insn_start:
1060             TODO();
1061             break;
1062 #endif
1063         case INDEX_op_exit_tb:
1064             next_tb = *(uint64_t *)tb_ptr;
1065             goto exit;
1066             break;
1067         case INDEX_op_goto_tb:
1068             t0 = tci_read_i32(&tb_ptr);
1069             assert(tb_ptr == old_code_ptr + op_size);
1070             tb_ptr += (int32_t)t0;
1071             continue;
1072         case INDEX_op_qemu_ld8u:
1073             t0 = *tb_ptr++;
1074             taddr = tci_read_ulong(&tb_ptr);
1075 #ifdef CONFIG_SOFTMMU
1076             tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
1077 #else
1078             host_addr = (tcg_target_ulong)taddr;
1079             assert(taddr == host_addr);
1080             tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
1081 #endif
1082             tci_write_reg8(t0, tmp8);
1083             break;
1084         case INDEX_op_qemu_ld8s:
1085             t0 = *tb_ptr++;
1086             taddr = tci_read_ulong(&tb_ptr);
1087 #ifdef CONFIG_SOFTMMU
1088             tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
1089 #else
1090             host_addr = (tcg_target_ulong)taddr;
1091             assert(taddr == host_addr);
1092             tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
1093 #endif
1094             tci_write_reg8s(t0, tmp8);
1095             break;
1096         case INDEX_op_qemu_ld16u:
1097             t0 = *tb_ptr++;
1098             taddr = tci_read_ulong(&tb_ptr);
1099 #ifdef CONFIG_SOFTMMU
1100             tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
1101 #else
1102             host_addr = (tcg_target_ulong)taddr;
1103             assert(taddr == host_addr);
1104             tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
1105 #endif
1106             tci_write_reg16(t0, tmp16);
1107             break;
1108         case INDEX_op_qemu_ld16s:
1109             t0 = *tb_ptr++;
1110             taddr = tci_read_ulong(&tb_ptr);
1111 #ifdef CONFIG_SOFTMMU
1112             tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
1113 #else
1114             host_addr = (tcg_target_ulong)taddr;
1115             assert(taddr == host_addr);
1116             tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
1117 #endif
1118             tci_write_reg16s(t0, tmp16);
1119             break;
1120 #if TCG_TARGET_REG_BITS == 64
1121         case INDEX_op_qemu_ld32u:
1122             t0 = *tb_ptr++;
1123             taddr = tci_read_ulong(&tb_ptr);
1124 #ifdef CONFIG_SOFTMMU
1125             tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1126 #else
1127             host_addr = (tcg_target_ulong)taddr;
1128             assert(taddr == host_addr);
1129             tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1130 #endif
1131             tci_write_reg32(t0, tmp32);
1132             break;
1133         case INDEX_op_qemu_ld32s:
1134             t0 = *tb_ptr++;
1135             taddr = tci_read_ulong(&tb_ptr);
1136 #ifdef CONFIG_SOFTMMU
1137             tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1138 #else
1139             host_addr = (tcg_target_ulong)taddr;
1140             assert(taddr == host_addr);
1141             tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1142 #endif
1143             tci_write_reg32s(t0, tmp32);
1144             break;
1145 #endif /* TCG_TARGET_REG_BITS == 64 */
1146         case INDEX_op_qemu_ld32:
1147             t0 = *tb_ptr++;
1148             taddr = tci_read_ulong(&tb_ptr);
1149 #ifdef CONFIG_SOFTMMU
1150             tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1151 #else
1152             host_addr = (tcg_target_ulong)taddr;
1153             assert(taddr == host_addr);
1154             tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1155 #endif
1156             tci_write_reg32(t0, tmp32);
1157             break;
1158         case INDEX_op_qemu_ld64:
1159             t0 = *tb_ptr++;
1160 #if TCG_TARGET_REG_BITS == 32
1161             t1 = *tb_ptr++;
1162 #endif
1163             taddr = tci_read_ulong(&tb_ptr);
1164 #ifdef CONFIG_SOFTMMU
1165             tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr));
1166 #else
1167             host_addr = (tcg_target_ulong)taddr;
1168             assert(taddr == host_addr);
1169             tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE));
1170 #endif
1171             tci_write_reg(t0, tmp64);
1172 #if TCG_TARGET_REG_BITS == 32
1173             tci_write_reg(t1, tmp64 >> 32);
1174 #endif
1175             break;
1176         case INDEX_op_qemu_st8:
1177             t0 = tci_read_r8(&tb_ptr);
1178             taddr = tci_read_ulong(&tb_ptr);
1179 #ifdef CONFIG_SOFTMMU
1180             t2 = tci_read_i(&tb_ptr);
1181             helper_stb_mmu(env, taddr, t0, t2);
1182 #else
1183             host_addr = (tcg_target_ulong)taddr;
1184             assert(taddr == host_addr);
1185             *(uint8_t *)(host_addr + GUEST_BASE) = t0;
1186 #endif
1187             break;
1188         case INDEX_op_qemu_st16:
1189             t0 = tci_read_r16(&tb_ptr);
1190             taddr = tci_read_ulong(&tb_ptr);
1191 #ifdef CONFIG_SOFTMMU
1192             t2 = tci_read_i(&tb_ptr);
1193             helper_stw_mmu(env, taddr, t0, t2);
1194 #else
1195             host_addr = (tcg_target_ulong)taddr;
1196             assert(taddr == host_addr);
1197             *(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0);
1198 #endif
1199             break;
1200         case INDEX_op_qemu_st32:
1201             t0 = tci_read_r32(&tb_ptr);
1202             taddr = tci_read_ulong(&tb_ptr);
1203 #ifdef CONFIG_SOFTMMU
1204             t2 = tci_read_i(&tb_ptr);
1205             helper_stl_mmu(env, taddr, t0, t2);
1206 #else
1207             host_addr = (tcg_target_ulong)taddr;
1208             assert(taddr == host_addr);
1209             *(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0);
1210 #endif
1211             break;
1212         case INDEX_op_qemu_st64:
1213             tmp64 = tci_read_r64(&tb_ptr);
1214             taddr = tci_read_ulong(&tb_ptr);
1215 #ifdef CONFIG_SOFTMMU
1216             t2 = tci_read_i(&tb_ptr);
1217             helper_stq_mmu(env, taddr, tmp64, t2);
1218 #else
1219             host_addr = (tcg_target_ulong)taddr;
1220             assert(taddr == host_addr);
1221             *(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64);
1222 #endif
1223             break;
1224         default:
1225             TODO();
1226             break;
1227         }
1228         assert(tb_ptr == old_code_ptr + op_size);
1229     }
1230 exit:
1231     return next_tb;
1232 }