2 * SSD0323 OLED controller with OSRAM Pictiva 128x64 display.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* The controller can support a variety of different displays, but we only
11 implement one. Most of the commends relating to brightness and geometry
13 #include "qemu/osdep.h"
14 #include "hw/ssi/ssi.h"
15 #include "ui/console.h"
17 //#define DEBUG_SSD0323 1
20 #define DPRINTF(fmt, ...) \
21 do { printf("ssd0323: " fmt , ## __VA_ARGS__); } while (0)
22 #define BADF(fmt, ...) \
24 fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); abort(); \
27 #define DPRINTF(fmt, ...) do {} while(0)
28 #define BADF(fmt, ...) \
29 do { fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__);} while (0)
32 /* Scaling factor for pixels. */
35 #define REMAP_SWAP_COLUMN 0x01
36 #define REMAP_SWAP_NYBBLE 0x02
37 #define REMAP_VERTICAL 0x04
38 #define REMAP_SWAP_COM 0x10
39 #define REMAP_SPLIT_COM 0x40
63 uint8_t framebuffer[128 * 80 / 2];
66 static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
68 ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
72 DPRINTF("data 0x%02x\n", data);
73 s->framebuffer[s->col + s->row * 64] = data;
74 if (s->remap & REMAP_VERTICAL) {
76 if (s->row > s->row_end) {
77 s->row = s->row_start;
80 if (s->col > s->col_end) {
81 s->col = s->col_start;
85 if (s->col > s->col_end) {
87 s->col = s->col_start;
89 if (s->row > s->row_end) {
90 s->row = s->row_start;
96 DPRINTF("cmd 0x%02x\n", data);
97 if (s->cmd_len == 0) {
100 s->cmd_data[s->cmd_len - 1] = data;
104 #define DATA(x) if (s->cmd_len <= (x)) return 0
105 case 0x15: /* Set column. */
107 s->col = s->col_start = s->cmd_data[0] % 64;
108 s->col_end = s->cmd_data[1] % 64;
110 case 0x75: /* Set row. */
112 s->row = s->row_start = s->cmd_data[0] % 80;
113 s->row_end = s->cmd_data[1] % 80;
115 case 0x81: /* Set contrast */
118 case 0x84: case 0x85: case 0x86: /* Max current. */
121 case 0xa0: /* Set remapping. */
122 /* FIXME: Implement this. */
124 s->remap = s->cmd_data[0];
126 case 0xa1: /* Set display start line. */
127 case 0xa2: /* Set display offset. */
128 /* FIXME: Implement these. */
131 case 0xa4: /* Normal mode. */
132 case 0xa5: /* All on. */
133 case 0xa6: /* All off. */
134 case 0xa7: /* Inverse. */
135 /* FIXME: Implement these. */
138 case 0xa8: /* Set multiplex ratio. */
139 case 0xad: /* Set DC-DC converter. */
141 /* Ignored. Don't care. */
143 case 0xae: /* Display off. */
144 case 0xaf: /* Display on. */
146 /* TODO: Implement power control. */
148 case 0xb1: /* Set phase length. */
149 case 0xb2: /* Set row period. */
150 case 0xb3: /* Set clock rate. */
151 case 0xbc: /* Set precharge. */
152 case 0xbe: /* Set VCOMH. */
153 case 0xbf: /* Set segment low. */
155 /* Ignored. Don't care. */
157 case 0xb8: /* Set grey scale table. */
158 /* FIXME: Implement this. */
161 case 0xe3: /* NOP. */
164 case 0xff: /* Nasty hack because we don't handle chip selects
168 BADF("Unknown command: 0x%x\n", data);
176 static void ssd0323_update_display(void *opaque)
178 ssd0323_state *s = (ssd0323_state *)opaque;
179 DisplaySurface *surface = qemu_console_surface(s->con);
187 char colortab[MAGNIFY * 64];
194 switch (surface_bits_per_pixel(surface)) {
210 BADF("Bad color depth\n");
214 for (i = 0; i < 16; i++) {
217 switch (surface_bits_per_pixel(surface)) {
219 n = i * 2 + (i >> 3);
221 p[1] = (n << 2) | (n >> 3);
224 n = i * 2 + (i >> 3);
225 p[0] = n | (n << 6) | ((n << 1) & 0x20);
226 p[1] = (n << 3) | (n >> 2);
231 p[0] = p[1] = p[2] = n;
234 BADF("Bad color depth\n");
239 /* TODO: Implement row/column remapping. */
240 dest = surface_data(surface);
241 for (y = 0; y < 64; y++) {
243 src = s->framebuffer + 64 * line;
244 for (x = 0; x < 64; x++) {
247 for (i = 0; i < MAGNIFY; i++) {
248 memcpy(dest, colors[val], dest_width);
252 for (i = 0; i < MAGNIFY; i++) {
253 memcpy(dest, colors[val], dest_width);
258 for (i = 1; i < MAGNIFY; i++) {
259 memcpy(dest, dest - dest_width * MAGNIFY * 128,
260 dest_width * 128 * MAGNIFY);
261 dest += dest_width * 128 * MAGNIFY;
265 dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
268 static void ssd0323_invalidate_display(void * opaque)
270 ssd0323_state *s = (ssd0323_state *)opaque;
274 /* Command/data input. */
275 static void ssd0323_cd(void *opaque, int n, int level)
277 ssd0323_state *s = (ssd0323_state *)opaque;
278 DPRINTF("%s mode\n", level ? "Data" : "Command");
279 s->mode = level ? SSD0323_DATA : SSD0323_CMD;
282 static int ssd0323_post_load(void *opaque, int version_id)
284 ssd0323_state *s = (ssd0323_state *)opaque;
286 if (s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
289 if (s->row < 0 || s->row >= 80) {
292 if (s->row_start < 0 || s->row_start >= 80) {
295 if (s->row_end < 0 || s->row_end >= 80) {
298 if (s->col < 0 || s->col >= 64) {
301 if (s->col_start < 0 || s->col_start >= 64) {
304 if (s->col_end < 0 || s->col_end >= 64) {
307 if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
314 static const VMStateDescription vmstate_ssd0323 = {
315 .name = "ssd0323_oled",
317 .minimum_version_id = 2,
318 .post_load = ssd0323_post_load,
319 .fields = (VMStateField []) {
320 VMSTATE_UINT32(cmd_len, ssd0323_state),
321 VMSTATE_INT32(cmd, ssd0323_state),
322 VMSTATE_INT32_ARRAY(cmd_data, ssd0323_state, 8),
323 VMSTATE_INT32(row, ssd0323_state),
324 VMSTATE_INT32(row_start, ssd0323_state),
325 VMSTATE_INT32(row_end, ssd0323_state),
326 VMSTATE_INT32(col, ssd0323_state),
327 VMSTATE_INT32(col_start, ssd0323_state),
328 VMSTATE_INT32(col_end, ssd0323_state),
329 VMSTATE_INT32(redraw, ssd0323_state),
330 VMSTATE_INT32(remap, ssd0323_state),
331 VMSTATE_UINT32(mode, ssd0323_state),
332 VMSTATE_BUFFER(framebuffer, ssd0323_state),
333 VMSTATE_SSI_SLAVE(ssidev, ssd0323_state),
334 VMSTATE_END_OF_LIST()
338 static const GraphicHwOps ssd0323_ops = {
339 .invalidate = ssd0323_invalidate_display,
340 .gfx_update = ssd0323_update_display,
343 static void ssd0323_realize(SSISlave *d, Error **errp)
345 DeviceState *dev = DEVICE(d);
346 ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
350 s->con = graphic_console_init(dev, 0, &ssd0323_ops, s);
351 qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY);
353 qdev_init_gpio_in(dev, ssd0323_cd, 1);
356 static void ssd0323_class_init(ObjectClass *klass, void *data)
358 DeviceClass *dc = DEVICE_CLASS(klass);
359 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
361 k->realize = ssd0323_realize;
362 k->transfer = ssd0323_transfer;
363 k->cs_polarity = SSI_CS_HIGH;
364 dc->vmsd = &vmstate_ssd0323;
367 static const TypeInfo ssd0323_info = {
369 .parent = TYPE_SSI_SLAVE,
370 .instance_size = sizeof(ssd0323_state),
371 .class_init = ssd0323_class_init,
374 static void ssd03232_register_types(void)
376 type_register_static(&ssd0323_info);
379 type_init(ssd03232_register_types)