target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         env->pstate = PSTATE_MODE_EL1h;
 117         env->pc = cpu->rvbar;
 118 #endif
 119     } else {
 120 #if defined(CONFIG_USER_ONLY)
 121         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 122         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 123 #endif
 124     }
 125
 126 #if defined(CONFIG_USER_ONLY)
 127     env->uncached_cpsr = ARM_CPU_MODE_USR;
 128     /* For user mode we must enable access to coprocessors */
 129     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 130     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 131         env->cp15.c15_cpar = 3;
 132     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 133         env->cp15.c15_cpar = 1;
 134     }
 135 #else
 136     /* SVC mode with interrupts disabled.  */
 137     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 138     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 139     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 140      * clear at reset. Initial SP and PC are loaded from ROM.
 141      */
 142     if (IS_M(env)) {
 143         uint32_t initial_msp; /* Loaded from 0x0 */
 144         uint32_t initial_pc; /* Loaded from 0x4 */
 145         uint8_t *rom;
 146
 147         env->daif &= ~PSTATE_I;
 148         rom = rom_ptr(0);
 149         if (rom) {
 150             /* Address zero is covered by ROM which hasn't yet been
 151              * copied into physical memory.
 152              */
 153             initial_msp = ldl_p(rom);
 154             initial_pc = ldl_p(rom + 4);
 155         } else {
 156             /* Address zero not covered by a ROM blob, or the ROM blob
 157              * is in non-modifiable memory and this is a second reset after
 158              * it got copied into memory. In the latter case, rom_ptr
 159              * will return a NULL pointer and we should use ldl_phys instead.
 160              */
 161             initial_msp = ldl_phys(s->as, 0);
 162             initial_pc = ldl_phys(s->as, 4);
 163         }
 164
 165         env->regs[13] = initial_msp & 0xFFFFFFFC;
 166         env->regs[15] = initial_pc & ~1;
 167         env->thumb = initial_pc & 1;
 168     }
 169
 170     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 171      * executing as AArch32 then check if highvecs are enabled and
 172      * adjust the PC accordingly.
 173      */
 174     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 175         env->regs[15] = 0xFFFF0000;
 176     }
 177
 178     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 179 #endif
 180     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 181     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 182     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 183     set_float_detect_tininess(float_tininess_before_rounding,
 184                               &env->vfp.fp_status);
 185     set_float_detect_tininess(float_tininess_before_rounding,
 186                               &env->vfp.standard_fp_status);
 187     tlb_flush(s, 1);
 188
 189 #ifndef CONFIG_USER_ONLY
 190     if (kvm_enabled()) {
 191         kvm_arm_reset_vcpu(cpu);
 192     }
 193 #endif
 194
 195     hw_breakpoint_update_all(cpu);
 196     hw_watchpoint_update_all(cpu);
 197 }
 198
 199 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 200 {
 201     CPUClass *cc = CPU_GET_CLASS(cs);
 202     bool ret = false;
 203
 204     if (interrupt_request & CPU_INTERRUPT_FIQ
 205         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 206         cs->exception_index = EXCP_FIQ;
 207         cc->do_interrupt(cs);
 208         ret = true;
 209     }
 210     if (interrupt_request & CPU_INTERRUPT_HARD
 211         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 212         cs->exception_index = EXCP_IRQ;
 213         cc->do_interrupt(cs);
 214         ret = true;
 215     }
 216     if (interrupt_request & CPU_INTERRUPT_VIRQ
 217         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 218         cs->exception_index = EXCP_VIRQ;
 219         cc->do_interrupt(cs);
 220         ret = true;
 221     }
 222     if (interrupt_request & CPU_INTERRUPT_VFIQ
 223         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 224         cs->exception_index = EXCP_VFIQ;
 225         cc->do_interrupt(cs);
 226         ret = true;
 227     }
 228
 229     return ret;
 230 }
 231
 232 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 233 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 234 {
 235     CPUClass *cc = CPU_GET_CLASS(cs);
 236     ARMCPU *cpu = ARM_CPU(cs);
 237     CPUARMState *env = &cpu->env;
 238     bool ret = false;
 239
 240
 241     if (interrupt_request & CPU_INTERRUPT_FIQ
 242         && !(env->daif & PSTATE_F)) {
 243         cs->exception_index = EXCP_FIQ;
 244         cc->do_interrupt(cs);
 245         ret = true;
 246     }
 247     /* ARMv7-M interrupt return works by loading a magic value
 248      * into the PC.  On real hardware the load causes the
 249      * return to occur.  The qemu implementation performs the
 250      * jump normally, then does the exception return when the
 251      * CPU tries to execute code at the magic address.
 252      * This will cause the magic PC value to be pushed to
 253      * the stack if an interrupt occurred at the wrong time.
 254      * We avoid this by disabling interrupts when
 255      * pc contains a magic address.
 256      */
 257     if (interrupt_request & CPU_INTERRUPT_HARD
 258         && !(env->daif & PSTATE_I)
 259         && (env->regs[15] < 0xfffffff0)) {
 260         cs->exception_index = EXCP_IRQ;
 261         cc->do_interrupt(cs);
 262         ret = true;
 263     }
 264     return ret;
 265 }
 266 #endif
 267
 268 #ifndef CONFIG_USER_ONLY
 269 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 270 {
 271     ARMCPU *cpu = opaque;
 272     CPUARMState *env = &cpu->env;
 273     CPUState *cs = CPU(cpu);
 274     static const int mask[] = {
 275         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 276         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 277         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 278         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 279     };
 280
 281     switch (irq) {
 282     case ARM_CPU_VIRQ:
 283     case ARM_CPU_VFIQ:
 284         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 285             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 286                      __func__, irq);
 287         }
 288         /* fall through */
 289     case ARM_CPU_IRQ:
 290     case ARM_CPU_FIQ:
 291         if (level) {
 292             cpu_interrupt(cs, mask[irq]);
 293         } else {
 294             cpu_reset_interrupt(cs, mask[irq]);
 295         }
 296         break;
 297     default:
 298         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 299     }
 300 }
 301
 302 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 303 {
 304 #ifdef CONFIG_KVM
 305     ARMCPU *cpu = opaque;
 306     CPUState *cs = CPU(cpu);
 307     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 308
 309     switch (irq) {
 310     case ARM_CPU_IRQ:
 311         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 312         break;
 313     case ARM_CPU_FIQ:
 314         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 315         break;
 316     default:
 317         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 318     }
 319     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 320     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 321 #endif
 322 }
 323 #endif
 324
 325 static inline void set_feature(CPUARMState *env, int feature)
 326 {
 327     env->features |= 1ULL << feature;
 328 }
 329
 330 static void arm_cpu_initfn(Object *obj)
 331 {
 332     CPUState *cs = CPU(obj);
 333     ARMCPU *cpu = ARM_CPU(obj);
 334     static bool inited;
 335
 336     cs->env_ptr = &cpu->env;
 337     cpu_exec_init(&cpu->env);
 338     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 339                                          g_free, g_free);
 340
 341 #ifndef CONFIG_USER_ONLY
 342     /* Our inbound IRQ and FIQ lines */
 343     if (kvm_enabled()) {
 344         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 345          * the same interface as non-KVM CPUs.
 346          */
 347         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 348     } else {
 349         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 350     }
 351
 352     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 353                                                 arm_gt_ptimer_cb, cpu);
 354     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 355                                                 arm_gt_vtimer_cb, cpu);
 356     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 357                        ARRAY_SIZE(cpu->gt_timer_outputs));
 358 #endif
 359
 360     /* DTB consumers generally don't in fact care what the 'compatible'
 361      * string is, so always provide some string and trust that a hypothetical
 362      * picky DTB consumer will also provide a helpful error message.
 363      */
 364     cpu->dtb_compatible = "qemu,unknown";
 365     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 366     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 367
 368     if (tcg_enabled()) {
 369         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 370         if (!inited) {
 371             inited = true;
 372             arm_translate_init();
 373         }
 374     }
 375 }
 376
 377 static Property arm_cpu_reset_cbar_property =
 378             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 379
 380 static Property arm_cpu_reset_hivecs_property =
 381             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 382
 383 static Property arm_cpu_rvbar_property =
 384             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 385
 386 static void arm_cpu_post_init(Object *obj)
 387 {
 388     ARMCPU *cpu = ARM_CPU(obj);
 389
 390     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 391         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 392         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 393                                  &error_abort);
 394     }
 395
 396     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 397         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 398                                  &error_abort);
 399     }
 400
 401     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 402         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 403                                  &error_abort);
 404     }
 405 }
 406
 407 static void arm_cpu_finalizefn(Object *obj)
 408 {
 409     ARMCPU *cpu = ARM_CPU(obj);
 410     g_hash_table_destroy(cpu->cp_regs);
 411 }
 412
 413 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 414 {
 415     CPUState *cs = CPU(dev);
 416     ARMCPU *cpu = ARM_CPU(dev);
 417     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 418     CPUARMState *env = &cpu->env;
 419
 420     /* Some features automatically imply others: */
 421     if (arm_feature(env, ARM_FEATURE_V8)) {
 422         set_feature(env, ARM_FEATURE_V7);
 423         set_feature(env, ARM_FEATURE_ARM_DIV);
 424         set_feature(env, ARM_FEATURE_LPAE);
 425     }
 426     if (arm_feature(env, ARM_FEATURE_V7)) {
 427         set_feature(env, ARM_FEATURE_VAPA);
 428         set_feature(env, ARM_FEATURE_THUMB2);
 429         set_feature(env, ARM_FEATURE_MPIDR);
 430         if (!arm_feature(env, ARM_FEATURE_M)) {
 431             set_feature(env, ARM_FEATURE_V6K);
 432         } else {
 433             set_feature(env, ARM_FEATURE_V6);
 434         }
 435     }
 436     if (arm_feature(env, ARM_FEATURE_V6K)) {
 437         set_feature(env, ARM_FEATURE_V6);
 438         set_feature(env, ARM_FEATURE_MVFR);
 439     }
 440     if (arm_feature(env, ARM_FEATURE_V6)) {
 441         set_feature(env, ARM_FEATURE_V5);
 442         if (!arm_feature(env, ARM_FEATURE_M)) {
 443             set_feature(env, ARM_FEATURE_AUXCR);
 444         }
 445     }
 446     if (arm_feature(env, ARM_FEATURE_V5)) {
 447         set_feature(env, ARM_FEATURE_V4T);
 448     }
 449     if (arm_feature(env, ARM_FEATURE_M)) {
 450         set_feature(env, ARM_FEATURE_THUMB_DIV);
 451     }
 452     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 453         set_feature(env, ARM_FEATURE_THUMB_DIV);
 454     }
 455     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 456         set_feature(env, ARM_FEATURE_VFP3);
 457         set_feature(env, ARM_FEATURE_VFP_FP16);
 458     }
 459     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 460         set_feature(env, ARM_FEATURE_VFP);
 461     }
 462     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 463         set_feature(env, ARM_FEATURE_V7MP);
 464         set_feature(env, ARM_FEATURE_PXN);
 465     }
 466     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 467         set_feature(env, ARM_FEATURE_CBAR);
 468     }
 469
 470     if (cpu->reset_hivecs) {
 471             cpu->reset_sctlr |= (1 << 13);
 472     }
 473
 474     register_cp_regs_for_features(cpu);
 475     arm_cpu_register_gdb_regs_for_features(cpu);
 476
 477     init_cpreg_list(cpu);
 478
 479     qemu_init_vcpu(cs);
 480     cpu_reset(cs);
 481
 482     acc->parent_realize(dev, errp);
 483 }
 484
 485 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 486 {
 487     ObjectClass *oc;
 488     char *typename;
 489
 490     if (!cpu_model) {
 491         return NULL;
 492     }
 493
 494     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 495     oc = object_class_by_name(typename);
 496     g_free(typename);
 497     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 498         object_class_is_abstract(oc)) {
 499         return NULL;
 500     }
 501     return oc;
 502 }
 503
 504 /* CPU models. These are not needed for the AArch64 linux-user build. */
 505 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 506
 507 static void arm926_initfn(Object *obj)
 508 {
 509     ARMCPU *cpu = ARM_CPU(obj);
 510
 511     cpu->dtb_compatible = "arm,arm926";
 512     set_feature(&cpu->env, ARM_FEATURE_V5);
 513     set_feature(&cpu->env, ARM_FEATURE_VFP);
 514     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 515     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 516     cpu->midr = 0x41069265;
 517     cpu->reset_fpsid = 0x41011090;
 518     cpu->ctr = 0x1dd20d2;
 519     cpu->reset_sctlr = 0x00090078;
 520 }
 521
 522 static void arm946_initfn(Object *obj)
 523 {
 524     ARMCPU *cpu = ARM_CPU(obj);
 525
 526     cpu->dtb_compatible = "arm,arm946";
 527     set_feature(&cpu->env, ARM_FEATURE_V5);
 528     set_feature(&cpu->env, ARM_FEATURE_MPU);
 529     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 530     cpu->midr = 0x41059461;
 531     cpu->ctr = 0x0f004006;
 532     cpu->reset_sctlr = 0x00000078;
 533 }
 534
 535 static void arm1026_initfn(Object *obj)
 536 {
 537     ARMCPU *cpu = ARM_CPU(obj);
 538
 539     cpu->dtb_compatible = "arm,arm1026";
 540     set_feature(&cpu->env, ARM_FEATURE_V5);
 541     set_feature(&cpu->env, ARM_FEATURE_VFP);
 542     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 543     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 544     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 545     cpu->midr = 0x4106a262;
 546     cpu->reset_fpsid = 0x410110a0;
 547     cpu->ctr = 0x1dd20d2;
 548     cpu->reset_sctlr = 0x00090078;
 549     cpu->reset_auxcr = 1;
 550     {
 551         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 552         ARMCPRegInfo ifar = {
 553             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 554             .access = PL1_RW,
 555             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 556             .resetvalue = 0
 557         };
 558         define_one_arm_cp_reg(cpu, &ifar);
 559     }
 560 }
 561
 562 static void arm1136_r2_initfn(Object *obj)
 563 {
 564     ARMCPU *cpu = ARM_CPU(obj);
 565     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 566      * older core than plain "arm1136". In particular this does not
 567      * have the v6K features.
 568      * These ID register values are correct for 1136 but may be wrong
 569      * for 1136_r2 (in particular r0p2 does not actually implement most
 570      * of the ID registers).
 571      */
 572
 573     cpu->dtb_compatible = "arm,arm1136";
 574     set_feature(&cpu->env, ARM_FEATURE_V6);
 575     set_feature(&cpu->env, ARM_FEATURE_VFP);
 576     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 577     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 578     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 579     cpu->midr = 0x4107b362;
 580     cpu->reset_fpsid = 0x410120b4;
 581     cpu->mvfr0 = 0x11111111;
 582     cpu->mvfr1 = 0x00000000;
 583     cpu->ctr = 0x1dd20d2;
 584     cpu->reset_sctlr = 0x00050078;
 585     cpu->id_pfr0 = 0x111;
 586     cpu->id_pfr1 = 0x1;
 587     cpu->id_dfr0 = 0x2;
 588     cpu->id_afr0 = 0x3;
 589     cpu->id_mmfr0 = 0x01130003;
 590     cpu->id_mmfr1 = 0x10030302;
 591     cpu->id_mmfr2 = 0x01222110;
 592     cpu->id_isar0 = 0x00140011;
 593     cpu->id_isar1 = 0x12002111;
 594     cpu->id_isar2 = 0x11231111;
 595     cpu->id_isar3 = 0x01102131;
 596     cpu->id_isar4 = 0x141;
 597     cpu->reset_auxcr = 7;
 598 }
 599
 600 static void arm1136_initfn(Object *obj)
 601 {
 602     ARMCPU *cpu = ARM_CPU(obj);
 603
 604     cpu->dtb_compatible = "arm,arm1136";
 605     set_feature(&cpu->env, ARM_FEATURE_V6K);
 606     set_feature(&cpu->env, ARM_FEATURE_V6);
 607     set_feature(&cpu->env, ARM_FEATURE_VFP);
 608     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 609     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 610     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 611     cpu->midr = 0x4117b363;
 612     cpu->reset_fpsid = 0x410120b4;
 613     cpu->mvfr0 = 0x11111111;
 614     cpu->mvfr1 = 0x00000000;
 615     cpu->ctr = 0x1dd20d2;
 616     cpu->reset_sctlr = 0x00050078;
 617     cpu->id_pfr0 = 0x111;
 618     cpu->id_pfr1 = 0x1;
 619     cpu->id_dfr0 = 0x2;
 620     cpu->id_afr0 = 0x3;
 621     cpu->id_mmfr0 = 0x01130003;
 622     cpu->id_mmfr1 = 0x10030302;
 623     cpu->id_mmfr2 = 0x01222110;
 624     cpu->id_isar0 = 0x00140011;
 625     cpu->id_isar1 = 0x12002111;
 626     cpu->id_isar2 = 0x11231111;
 627     cpu->id_isar3 = 0x01102131;
 628     cpu->id_isar4 = 0x141;
 629     cpu->reset_auxcr = 7;
 630 }
 631
 632 static void arm1176_initfn(Object *obj)
 633 {
 634     ARMCPU *cpu = ARM_CPU(obj);
 635
 636     cpu->dtb_compatible = "arm,arm1176";
 637     set_feature(&cpu->env, ARM_FEATURE_V6K);
 638     set_feature(&cpu->env, ARM_FEATURE_VFP);
 639     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 640     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 641     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 642     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 643     cpu->midr = 0x410fb767;
 644     cpu->reset_fpsid = 0x410120b5;
 645     cpu->mvfr0 = 0x11111111;
 646     cpu->mvfr1 = 0x00000000;
 647     cpu->ctr = 0x1dd20d2;
 648     cpu->reset_sctlr = 0x00050078;
 649     cpu->id_pfr0 = 0x111;
 650     cpu->id_pfr1 = 0x11;
 651     cpu->id_dfr0 = 0x33;
 652     cpu->id_afr0 = 0;
 653     cpu->id_mmfr0 = 0x01130003;
 654     cpu->id_mmfr1 = 0x10030302;
 655     cpu->id_mmfr2 = 0x01222100;
 656     cpu->id_isar0 = 0x0140011;
 657     cpu->id_isar1 = 0x12002111;
 658     cpu->id_isar2 = 0x11231121;
 659     cpu->id_isar3 = 0x01102131;
 660     cpu->id_isar4 = 0x01141;
 661     cpu->reset_auxcr = 7;
 662 }
 663
 664 static void arm11mpcore_initfn(Object *obj)
 665 {
 666     ARMCPU *cpu = ARM_CPU(obj);
 667
 668     cpu->dtb_compatible = "arm,arm11mpcore";
 669     set_feature(&cpu->env, ARM_FEATURE_V6K);
 670     set_feature(&cpu->env, ARM_FEATURE_VFP);
 671     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 672     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 673     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 674     cpu->midr = 0x410fb022;
 675     cpu->reset_fpsid = 0x410120b4;
 676     cpu->mvfr0 = 0x11111111;
 677     cpu->mvfr1 = 0x00000000;
 678     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 679     cpu->id_pfr0 = 0x111;
 680     cpu->id_pfr1 = 0x1;
 681     cpu->id_dfr0 = 0;
 682     cpu->id_afr0 = 0x2;
 683     cpu->id_mmfr0 = 0x01100103;
 684     cpu->id_mmfr1 = 0x10020302;
 685     cpu->id_mmfr2 = 0x01222000;
 686     cpu->id_isar0 = 0x00100011;
 687     cpu->id_isar1 = 0x12002111;
 688     cpu->id_isar2 = 0x11221011;
 689     cpu->id_isar3 = 0x01102131;
 690     cpu->id_isar4 = 0x141;
 691     cpu->reset_auxcr = 1;
 692 }
 693
 694 static void cortex_m3_initfn(Object *obj)
 695 {
 696     ARMCPU *cpu = ARM_CPU(obj);
 697     set_feature(&cpu->env, ARM_FEATURE_V7);
 698     set_feature(&cpu->env, ARM_FEATURE_M);
 699     cpu->midr = 0x410fc231;
 700 }
 701
 702 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 703 {
 704     CPUClass *cc = CPU_CLASS(oc);
 705
 706 #ifndef CONFIG_USER_ONLY
 707     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 708 #endif
 709
 710     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 711 }
 712
 713 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 714     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 715       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 716     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 717       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 718     REGINFO_SENTINEL
 719 };
 720
 721 static void cortex_a8_initfn(Object *obj)
 722 {
 723     ARMCPU *cpu = ARM_CPU(obj);
 724
 725     cpu->dtb_compatible = "arm,cortex-a8";
 726     set_feature(&cpu->env, ARM_FEATURE_V7);
 727     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 728     set_feature(&cpu->env, ARM_FEATURE_NEON);
 729     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 730     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 731     cpu->midr = 0x410fc080;
 732     cpu->reset_fpsid = 0x410330c0;
 733     cpu->mvfr0 = 0x11110222;
 734     cpu->mvfr1 = 0x00011100;
 735     cpu->ctr = 0x82048004;
 736     cpu->reset_sctlr = 0x00c50078;
 737     cpu->id_pfr0 = 0x1031;
 738     cpu->id_pfr1 = 0x11;
 739     cpu->id_dfr0 = 0x400;
 740     cpu->id_afr0 = 0;
 741     cpu->id_mmfr0 = 0x31100003;
 742     cpu->id_mmfr1 = 0x20000000;
 743     cpu->id_mmfr2 = 0x01202000;
 744     cpu->id_mmfr3 = 0x11;
 745     cpu->id_isar0 = 0x00101111;
 746     cpu->id_isar1 = 0x12112111;
 747     cpu->id_isar2 = 0x21232031;
 748     cpu->id_isar3 = 0x11112131;
 749     cpu->id_isar4 = 0x00111142;
 750     cpu->dbgdidr = 0x15141000;
 751     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 752     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 753     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 754     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 755     cpu->reset_auxcr = 2;
 756     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 757 }
 758
 759 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 760     /* power_control should be set to maximum latency. Again,
 761      * default to 0 and set by private hook
 762      */
 763     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 764       .access = PL1_RW, .resetvalue = 0,
 765       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 766     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 767       .access = PL1_RW, .resetvalue = 0,
 768       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 769     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 770       .access = PL1_RW, .resetvalue = 0,
 771       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 772     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 773       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 774     /* TLB lockdown control */
 775     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 776       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 777     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 778       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 779     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 780       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 781     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 782       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 783     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 784       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 785     REGINFO_SENTINEL
 786 };
 787
 788 static void cortex_a9_initfn(Object *obj)
 789 {
 790     ARMCPU *cpu = ARM_CPU(obj);
 791
 792     cpu->dtb_compatible = "arm,cortex-a9";
 793     set_feature(&cpu->env, ARM_FEATURE_V7);
 794     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 795     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 796     set_feature(&cpu->env, ARM_FEATURE_NEON);
 797     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 798     /* Note that A9 supports the MP extensions even for
 799      * A9UP and single-core A9MP (which are both different
 800      * and valid configurations; we don't model A9UP).
 801      */
 802     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 803     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 804     cpu->midr = 0x410fc090;
 805     cpu->reset_fpsid = 0x41033090;
 806     cpu->mvfr0 = 0x11110222;
 807     cpu->mvfr1 = 0x01111111;
 808     cpu->ctr = 0x80038003;
 809     cpu->reset_sctlr = 0x00c50078;
 810     cpu->id_pfr0 = 0x1031;
 811     cpu->id_pfr1 = 0x11;
 812     cpu->id_dfr0 = 0x000;
 813     cpu->id_afr0 = 0;
 814     cpu->id_mmfr0 = 0x00100103;
 815     cpu->id_mmfr1 = 0x20000000;
 816     cpu->id_mmfr2 = 0x01230000;
 817     cpu->id_mmfr3 = 0x00002111;
 818     cpu->id_isar0 = 0x00101111;
 819     cpu->id_isar1 = 0x13112111;
 820     cpu->id_isar2 = 0x21232041;
 821     cpu->id_isar3 = 0x11112131;
 822     cpu->id_isar4 = 0x00111142;
 823     cpu->dbgdidr = 0x35141000;
 824     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 825     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 826     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 827     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 828 }
 829
 830 #ifndef CONFIG_USER_ONLY
 831 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 832 {
 833     /* Linux wants the number of processors from here.
 834      * Might as well set the interrupt-controller bit too.
 835      */
 836     return ((smp_cpus - 1) << 24) | (1 << 23);
 837 }
 838 #endif
 839
 840 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 841 #ifndef CONFIG_USER_ONLY
 842     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 843       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 844       .writefn = arm_cp_write_ignore, },
 845 #endif
 846     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 847       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 848     REGINFO_SENTINEL
 849 };
 850
 851 static void cortex_a15_initfn(Object *obj)
 852 {
 853     ARMCPU *cpu = ARM_CPU(obj);
 854
 855     cpu->dtb_compatible = "arm,cortex-a15";
 856     set_feature(&cpu->env, ARM_FEATURE_V7);
 857     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 858     set_feature(&cpu->env, ARM_FEATURE_NEON);
 859     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 860     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 861     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 862     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 863     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 864     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 865     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 866     cpu->midr = 0x412fc0f1;
 867     cpu->reset_fpsid = 0x410430f0;
 868     cpu->mvfr0 = 0x10110222;
 869     cpu->mvfr1 = 0x11111111;
 870     cpu->ctr = 0x8444c004;
 871     cpu->reset_sctlr = 0x00c50078;
 872     cpu->id_pfr0 = 0x00001131;
 873     cpu->id_pfr1 = 0x00011011;
 874     cpu->id_dfr0 = 0x02010555;
 875     cpu->id_afr0 = 0x00000000;
 876     cpu->id_mmfr0 = 0x10201105;
 877     cpu->id_mmfr1 = 0x20000000;
 878     cpu->id_mmfr2 = 0x01240000;
 879     cpu->id_mmfr3 = 0x02102211;
 880     cpu->id_isar0 = 0x02101110;
 881     cpu->id_isar1 = 0x13112111;
 882     cpu->id_isar2 = 0x21232041;
 883     cpu->id_isar3 = 0x11112131;
 884     cpu->id_isar4 = 0x10011142;
 885     cpu->dbgdidr = 0x3515f021;
 886     cpu->clidr = 0x0a200023;
 887     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 888     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 889     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 890     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 891 }
 892
 893 static void ti925t_initfn(Object *obj)
 894 {
 895     ARMCPU *cpu = ARM_CPU(obj);
 896     set_feature(&cpu->env, ARM_FEATURE_V4T);
 897     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 898     cpu->midr = ARM_CPUID_TI925T;
 899     cpu->ctr = 0x5109149;
 900     cpu->reset_sctlr = 0x00000070;
 901 }
 902
 903 static void sa1100_initfn(Object *obj)
 904 {
 905     ARMCPU *cpu = ARM_CPU(obj);
 906
 907     cpu->dtb_compatible = "intel,sa1100";
 908     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 909     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 910     cpu->midr = 0x4401A11B;
 911     cpu->reset_sctlr = 0x00000070;
 912 }
 913
 914 static void sa1110_initfn(Object *obj)
 915 {
 916     ARMCPU *cpu = ARM_CPU(obj);
 917     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 918     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 919     cpu->midr = 0x6901B119;
 920     cpu->reset_sctlr = 0x00000070;
 921 }
 922
 923 static void pxa250_initfn(Object *obj)
 924 {
 925     ARMCPU *cpu = ARM_CPU(obj);
 926
 927     cpu->dtb_compatible = "marvell,xscale";
 928     set_feature(&cpu->env, ARM_FEATURE_V5);
 929     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 930     cpu->midr = 0x69052100;
 931     cpu->ctr = 0xd172172;
 932     cpu->reset_sctlr = 0x00000078;
 933 }
 934
 935 static void pxa255_initfn(Object *obj)
 936 {
 937     ARMCPU *cpu = ARM_CPU(obj);
 938
 939     cpu->dtb_compatible = "marvell,xscale";
 940     set_feature(&cpu->env, ARM_FEATURE_V5);
 941     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 942     cpu->midr = 0x69052d00;
 943     cpu->ctr = 0xd172172;
 944     cpu->reset_sctlr = 0x00000078;
 945 }
 946
 947 static void pxa260_initfn(Object *obj)
 948 {
 949     ARMCPU *cpu = ARM_CPU(obj);
 950
 951     cpu->dtb_compatible = "marvell,xscale";
 952     set_feature(&cpu->env, ARM_FEATURE_V5);
 953     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 954     cpu->midr = 0x69052903;
 955     cpu->ctr = 0xd172172;
 956     cpu->reset_sctlr = 0x00000078;
 957 }
 958
 959 static void pxa261_initfn(Object *obj)
 960 {
 961     ARMCPU *cpu = ARM_CPU(obj);
 962
 963     cpu->dtb_compatible = "marvell,xscale";
 964     set_feature(&cpu->env, ARM_FEATURE_V5);
 965     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 966     cpu->midr = 0x69052d05;
 967     cpu->ctr = 0xd172172;
 968     cpu->reset_sctlr = 0x00000078;
 969 }
 970
 971 static void pxa262_initfn(Object *obj)
 972 {
 973     ARMCPU *cpu = ARM_CPU(obj);
 974
 975     cpu->dtb_compatible = "marvell,xscale";
 976     set_feature(&cpu->env, ARM_FEATURE_V5);
 977     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 978     cpu->midr = 0x69052d06;
 979     cpu->ctr = 0xd172172;
 980     cpu->reset_sctlr = 0x00000078;
 981 }
 982
 983 static void pxa270a0_initfn(Object *obj)
 984 {
 985     ARMCPU *cpu = ARM_CPU(obj);
 986
 987     cpu->dtb_compatible = "marvell,xscale";
 988     set_feature(&cpu->env, ARM_FEATURE_V5);
 989     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 990     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 991     cpu->midr = 0x69054110;
 992     cpu->ctr = 0xd172172;
 993     cpu->reset_sctlr = 0x00000078;
 994 }
 995
 996 static void pxa270a1_initfn(Object *obj)
 997 {
 998     ARMCPU *cpu = ARM_CPU(obj);
 999
1000     cpu->dtb_compatible = "marvell,xscale";
1001     set_feature(&cpu->env, ARM_FEATURE_V5);
1002     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1003     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1004     cpu->midr = 0x69054111;
1005     cpu->ctr = 0xd172172;
1006     cpu->reset_sctlr = 0x00000078;
1007 }
1008
1009 static void pxa270b0_initfn(Object *obj)
1010 {
1011     ARMCPU *cpu = ARM_CPU(obj);
1012
1013     cpu->dtb_compatible = "marvell,xscale";
1014     set_feature(&cpu->env, ARM_FEATURE_V5);
1015     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1016     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1017     cpu->midr = 0x69054112;
1018     cpu->ctr = 0xd172172;
1019     cpu->reset_sctlr = 0x00000078;
1020 }
1021
1022 static void pxa270b1_initfn(Object *obj)
1023 {
1024     ARMCPU *cpu = ARM_CPU(obj);
1025
1026     cpu->dtb_compatible = "marvell,xscale";
1027     set_feature(&cpu->env, ARM_FEATURE_V5);
1028     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1029     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1030     cpu->midr = 0x69054113;
1031     cpu->ctr = 0xd172172;
1032     cpu->reset_sctlr = 0x00000078;
1033 }
1034
1035 static void pxa270c0_initfn(Object *obj)
1036 {
1037     ARMCPU *cpu = ARM_CPU(obj);
1038
1039     cpu->dtb_compatible = "marvell,xscale";
1040     set_feature(&cpu->env, ARM_FEATURE_V5);
1041     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1042     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1043     cpu->midr = 0x69054114;
1044     cpu->ctr = 0xd172172;
1045     cpu->reset_sctlr = 0x00000078;
1046 }
1047
1048 static void pxa270c5_initfn(Object *obj)
1049 {
1050     ARMCPU *cpu = ARM_CPU(obj);
1051
1052     cpu->dtb_compatible = "marvell,xscale";
1053     set_feature(&cpu->env, ARM_FEATURE_V5);
1054     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1055     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1056     cpu->midr = 0x69054117;
1057     cpu->ctr = 0xd172172;
1058     cpu->reset_sctlr = 0x00000078;
1059 }
1060
1061 #ifdef CONFIG_USER_ONLY
1062 static void arm_any_initfn(Object *obj)
1063 {
1064     ARMCPU *cpu = ARM_CPU(obj);
1065     set_feature(&cpu->env, ARM_FEATURE_V8);
1066     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1067     set_feature(&cpu->env, ARM_FEATURE_NEON);
1068     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1069     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1070     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1071     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1072     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1073     set_feature(&cpu->env, ARM_FEATURE_CRC);
1074     cpu->midr = 0xffffffff;
1075 }
1076 #endif
1077
1078 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1079
1080 typedef struct ARMCPUInfo {
1081     const char *name;
1082     void (*initfn)(Object *obj);
1083     void (*class_init)(ObjectClass *oc, void *data);
1084 } ARMCPUInfo;
1085
1086 static const ARMCPUInfo arm_cpus[] = {
1087 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1088     { .name = "arm926",      .initfn = arm926_initfn },
1089     { .name = "arm946",      .initfn = arm946_initfn },
1090     { .name = "arm1026",     .initfn = arm1026_initfn },
1091     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1092      * older core than plain "arm1136". In particular this does not
1093      * have the v6K features.
1094      */
1095     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1096     { .name = "arm1136",     .initfn = arm1136_initfn },
1097     { .name = "arm1176",     .initfn = arm1176_initfn },
1098     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1099     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1100                              .class_init = arm_v7m_class_init },
1101     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1102     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1103     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1104     { .name = "ti925t",      .initfn = ti925t_initfn },
1105     { .name = "sa1100",      .initfn = sa1100_initfn },
1106     { .name = "sa1110",      .initfn = sa1110_initfn },
1107     { .name = "pxa250",      .initfn = pxa250_initfn },
1108     { .name = "pxa255",      .initfn = pxa255_initfn },
1109     { .name = "pxa260",      .initfn = pxa260_initfn },
1110     { .name = "pxa261",      .initfn = pxa261_initfn },
1111     { .name = "pxa262",      .initfn = pxa262_initfn },
1112     /* "pxa270" is an alias for "pxa270-a0" */
1113     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1114     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1115     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1116     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1117     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1118     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1119     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1120 #ifdef CONFIG_USER_ONLY
1121     { .name = "any",         .initfn = arm_any_initfn },
1122 #endif
1123 #endif
1124     { .name = NULL }
1125 };
1126
1127 static Property arm_cpu_properties[] = {
1128     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1129     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1130     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1131     DEFINE_PROP_END_OF_LIST()
1132 };
1133
1134 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1135 {
1136     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1137     CPUClass *cc = CPU_CLASS(acc);
1138     DeviceClass *dc = DEVICE_CLASS(oc);
1139
1140     acc->parent_realize = dc->realize;
1141     dc->realize = arm_cpu_realizefn;
1142     dc->props = arm_cpu_properties;
1143
1144     acc->parent_reset = cc->reset;
1145     cc->reset = arm_cpu_reset;
1146
1147     cc->class_by_name = arm_cpu_class_by_name;
1148     cc->has_work = arm_cpu_has_work;
1149     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1150     cc->dump_state = arm_cpu_dump_state;
1151     cc->set_pc = arm_cpu_set_pc;
1152     cc->gdb_read_register = arm_cpu_gdb_read_register;
1153     cc->gdb_write_register = arm_cpu_gdb_write_register;
1154 #ifdef CONFIG_USER_ONLY
1155     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1156 #else
1157     cc->do_interrupt = arm_cpu_do_interrupt;
1158     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1159     cc->vmsd = &vmstate_arm_cpu;
1160 #endif
1161     cc->gdb_num_core_regs = 26;
1162     cc->gdb_core_xml_file = "arm-core.xml";
1163     cc->gdb_stop_before_watchpoint = true;
1164     cc->debug_excp_handler = arm_debug_excp_handler;
1165 }
1166
1167 static void cpu_register(const ARMCPUInfo *info)
1168 {
1169     TypeInfo type_info = {
1170         .parent = TYPE_ARM_CPU,
1171         .instance_size = sizeof(ARMCPU),
1172         .instance_init = info->initfn,
1173         .class_size = sizeof(ARMCPUClass),
1174         .class_init = info->class_init,
1175     };
1176
1177     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1178     type_register(&type_info);
1179     g_free((void *)type_info.name);
1180 }
1181
1182 static const TypeInfo arm_cpu_type_info = {
1183     .name = TYPE_ARM_CPU,
1184     .parent = TYPE_CPU,
1185     .instance_size = sizeof(ARMCPU),
1186     .instance_init = arm_cpu_initfn,
1187     .instance_post_init = arm_cpu_post_init,
1188     .instance_finalize = arm_cpu_finalizefn,
1189     .abstract = true,
1190     .class_size = sizeof(ARMCPUClass),
1191     .class_init = arm_cpu_class_init,
1192 };
1193
1194 static void arm_cpu_register_types(void)
1195 {
1196     const ARMCPUInfo *info = arm_cpus;
1197
1198     type_register_static(&arm_cpu_type_info);
1199
1200     while (info->name) {
1201         cpu_register(info);
1202         info++;
1203     }
1204 }
1205
1206 type_init(arm_cpu_register_types)