target/arm/cpu_tcg.c

   1 /*
   2  * QEMU ARM TCG CPUs.
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This code is licensed under the GNU GPL v2 or later.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "cpu.h"
  13 #ifdef CONFIG_TCG
  14 #include "hw/core/tcg-cpu-ops.h"
  15 #endif /* CONFIG_TCG */
  16 #include "internals.h"
  17 #include "target/arm/idau.h"
  18 #if !defined(CONFIG_USER_ONLY)
  19 #include "hw/boards.h"
  20 #endif
  21 #include "cpregs.h"
  22
  23
  24 /* Share AArch32 -cpu max features with AArch64. */
  25 void aa32_max_features(ARMCPU *cpu)
  26 {
  27     uint32_t t;
  28
  29     /* Add additional features supported by QEMU */
  30     t = cpu->isar.id_isar5;
  31     t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
  32     t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
  33     t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
  34     t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
  35     t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
  36     t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
  37     cpu->isar.id_isar5 = t;
  38
  39     t = cpu->isar.id_isar6;
  40     t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
  41     t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
  42     t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
  43     t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
  44     t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
  45     t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
  46     t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
  47     cpu->isar.id_isar6 = t;
  48
  49     t = cpu->isar.mvfr1;
  50     t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
  51     t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
  52     cpu->isar.mvfr1 = t;
  53
  54     t = cpu->isar.mvfr2;
  55     t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
  56     t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
  57     cpu->isar.mvfr2 = t;
  58
  59     t = cpu->isar.id_mmfr3;
  60     t = FIELD_DP32(t, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
  61     cpu->isar.id_mmfr3 = t;
  62
  63     t = cpu->isar.id_mmfr4;
  64     t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
  65     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
  66     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
  67     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
  68     cpu->isar.id_mmfr4 = t;
  69
  70     t = cpu->isar.id_mmfr5;
  71     t = FIELD_DP32(t, ID_MMFR5, ETS, 1);          /* FEAT_ETS */
  72     cpu->isar.id_mmfr5 = t;
  73
  74     t = cpu->isar.id_pfr0;
  75     t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CVS2 */
  76     t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
  77     t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
  78     cpu->isar.id_pfr0 = t;
  79
  80     t = cpu->isar.id_pfr2;
  81     t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
  82     t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
  83     cpu->isar.id_pfr2 = t;
  84
  85     t = cpu->isar.id_dfr0;
  86     t = FIELD_DP32(t, ID_DFR0, COPDBG, 9);        /* FEAT_Debugv8p4 */
  87     t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9);       /* FEAT_Debugv8p4 */
  88     t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
  89     cpu->isar.id_dfr0 = t;
  90 }
  91
  92 #ifndef CONFIG_USER_ONLY
  93 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  94 {
  95     ARMCPU *cpu = env_archcpu(env);
  96
  97     /* Number of cores is in [25:24]; otherwise we RAZ */
  98     return (cpu->core_count - 1) << 24;
  99 }
 100
 101 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
 102     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
 103       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
 104       .access = PL1_RW, .readfn = l2ctlr_read,
 105       .writefn = arm_cp_write_ignore },
 106     { .name = "L2CTLR",
 107       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
 108       .access = PL1_RW, .readfn = l2ctlr_read,
 109       .writefn = arm_cp_write_ignore },
 110     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
 111       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
 112       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 113     { .name = "L2ECTLR",
 114       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
 115       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 116     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
 117       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
 118       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 119     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
 120       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
 121       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 122     { .name = "CPUACTLR",
 123       .cp = 15, .opc1 = 0, .crm = 15,
 124       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 125     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
 126       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
 127       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 128     { .name = "CPUECTLR",
 129       .cp = 15, .opc1 = 1, .crm = 15,
 130       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 131     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
 132       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
 133       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 134     { .name = "CPUMERRSR",
 135       .cp = 15, .opc1 = 2, .crm = 15,
 136       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 137     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
 138       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
 139       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 140     { .name = "L2MERRSR",
 141       .cp = 15, .opc1 = 3, .crm = 15,
 142       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
 143 };
 144
 145 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
 146 {
 147     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 148 }
 149 #endif /* !CONFIG_USER_ONLY */
 150
 151 /* CPU models. These are not needed for the AArch64 linux-user build. */
 152 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 153
 154 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 155 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 156 {
 157     CPUClass *cc = CPU_GET_CLASS(cs);
 158     ARMCPU *cpu = ARM_CPU(cs);
 159     CPUARMState *env = &cpu->env;
 160     bool ret = false;
 161
 162     /*
 163      * ARMv7-M interrupt masking works differently than -A or -R.
 164      * There is no FIQ/IRQ distinction. Instead of I and F bits
 165      * masking FIQ and IRQ interrupts, an exception is taken only
 166      * if it is higher priority than the current execution priority
 167      * (which depends on state like BASEPRI, FAULTMASK and the
 168      * currently active exception).
 169      */
 170     if (interrupt_request & CPU_INTERRUPT_HARD
 171         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 172         cs->exception_index = EXCP_IRQ;
 173         cc->tcg_ops->do_interrupt(cs);
 174         ret = true;
 175     }
 176     return ret;
 177 }
 178 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
 179
 180 static void arm926_initfn(Object *obj)
 181 {
 182     ARMCPU *cpu = ARM_CPU(obj);
 183
 184     cpu->dtb_compatible = "arm,arm926";
 185     set_feature(&cpu->env, ARM_FEATURE_V5);
 186     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 187     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 188     cpu->midr = 0x41069265;
 189     cpu->reset_fpsid = 0x41011090;
 190     cpu->ctr = 0x1dd20d2;
 191     cpu->reset_sctlr = 0x00090078;
 192
 193     /*
 194      * ARMv5 does not have the ID_ISAR registers, but we can still
 195      * set the field to indicate Jazelle support within QEMU.
 196      */
 197     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 198     /*
 199      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 200      * support even though ARMv5 doesn't have this register.
 201      */
 202     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 203     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 204     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 205 }
 206
 207 static void arm946_initfn(Object *obj)
 208 {
 209     ARMCPU *cpu = ARM_CPU(obj);
 210
 211     cpu->dtb_compatible = "arm,arm946";
 212     set_feature(&cpu->env, ARM_FEATURE_V5);
 213     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 214     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 215     cpu->midr = 0x41059461;
 216     cpu->ctr = 0x0f004006;
 217     cpu->reset_sctlr = 0x00000078;
 218 }
 219
 220 static void arm1026_initfn(Object *obj)
 221 {
 222     ARMCPU *cpu = ARM_CPU(obj);
 223
 224     cpu->dtb_compatible = "arm,arm1026";
 225     set_feature(&cpu->env, ARM_FEATURE_V5);
 226     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 227     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 228     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 229     cpu->midr = 0x4106a262;
 230     cpu->reset_fpsid = 0x410110a0;
 231     cpu->ctr = 0x1dd20d2;
 232     cpu->reset_sctlr = 0x00090078;
 233     cpu->reset_auxcr = 1;
 234
 235     /*
 236      * ARMv5 does not have the ID_ISAR registers, but we can still
 237      * set the field to indicate Jazelle support within QEMU.
 238      */
 239     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 240     /*
 241      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 242      * support even though ARMv5 doesn't have this register.
 243      */
 244     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 245     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 246     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 247
 248     {
 249         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 250         ARMCPRegInfo ifar = {
 251             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 252             .access = PL1_RW,
 253             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 254             .resetvalue = 0
 255         };
 256         define_one_arm_cp_reg(cpu, &ifar);
 257     }
 258 }
 259
 260 static void arm1136_r2_initfn(Object *obj)
 261 {
 262     ARMCPU *cpu = ARM_CPU(obj);
 263     /*
 264      * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 265      * older core than plain "arm1136". In particular this does not
 266      * have the v6K features.
 267      * These ID register values are correct for 1136 but may be wrong
 268      * for 1136_r2 (in particular r0p2 does not actually implement most
 269      * of the ID registers).
 270      */
 271
 272     cpu->dtb_compatible = "arm,arm1136";
 273     set_feature(&cpu->env, ARM_FEATURE_V6);
 274     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 275     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 276     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 277     cpu->midr = 0x4107b362;
 278     cpu->reset_fpsid = 0x410120b4;
 279     cpu->isar.mvfr0 = 0x11111111;
 280     cpu->isar.mvfr1 = 0x00000000;
 281     cpu->ctr = 0x1dd20d2;
 282     cpu->reset_sctlr = 0x00050078;
 283     cpu->isar.id_pfr0 = 0x111;
 284     cpu->isar.id_pfr1 = 0x1;
 285     cpu->isar.id_dfr0 = 0x2;
 286     cpu->id_afr0 = 0x3;
 287     cpu->isar.id_mmfr0 = 0x01130003;
 288     cpu->isar.id_mmfr1 = 0x10030302;
 289     cpu->isar.id_mmfr2 = 0x01222110;
 290     cpu->isar.id_isar0 = 0x00140011;
 291     cpu->isar.id_isar1 = 0x12002111;
 292     cpu->isar.id_isar2 = 0x11231111;
 293     cpu->isar.id_isar3 = 0x01102131;
 294     cpu->isar.id_isar4 = 0x141;
 295     cpu->reset_auxcr = 7;
 296 }
 297
 298 static void arm1136_initfn(Object *obj)
 299 {
 300     ARMCPU *cpu = ARM_CPU(obj);
 301
 302     cpu->dtb_compatible = "arm,arm1136";
 303     set_feature(&cpu->env, ARM_FEATURE_V6K);
 304     set_feature(&cpu->env, ARM_FEATURE_V6);
 305     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 306     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 307     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 308     cpu->midr = 0x4117b363;
 309     cpu->reset_fpsid = 0x410120b4;
 310     cpu->isar.mvfr0 = 0x11111111;
 311     cpu->isar.mvfr1 = 0x00000000;
 312     cpu->ctr = 0x1dd20d2;
 313     cpu->reset_sctlr = 0x00050078;
 314     cpu->isar.id_pfr0 = 0x111;
 315     cpu->isar.id_pfr1 = 0x1;
 316     cpu->isar.id_dfr0 = 0x2;
 317     cpu->id_afr0 = 0x3;
 318     cpu->isar.id_mmfr0 = 0x01130003;
 319     cpu->isar.id_mmfr1 = 0x10030302;
 320     cpu->isar.id_mmfr2 = 0x01222110;
 321     cpu->isar.id_isar0 = 0x00140011;
 322     cpu->isar.id_isar1 = 0x12002111;
 323     cpu->isar.id_isar2 = 0x11231111;
 324     cpu->isar.id_isar3 = 0x01102131;
 325     cpu->isar.id_isar4 = 0x141;
 326     cpu->reset_auxcr = 7;
 327 }
 328
 329 static void arm1176_initfn(Object *obj)
 330 {
 331     ARMCPU *cpu = ARM_CPU(obj);
 332
 333     cpu->dtb_compatible = "arm,arm1176";
 334     set_feature(&cpu->env, ARM_FEATURE_V6K);
 335     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 336     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 337     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 338     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 339     set_feature(&cpu->env, ARM_FEATURE_EL3);
 340     cpu->midr = 0x410fb767;
 341     cpu->reset_fpsid = 0x410120b5;
 342     cpu->isar.mvfr0 = 0x11111111;
 343     cpu->isar.mvfr1 = 0x00000000;
 344     cpu->ctr = 0x1dd20d2;
 345     cpu->reset_sctlr = 0x00050078;
 346     cpu->isar.id_pfr0 = 0x111;
 347     cpu->isar.id_pfr1 = 0x11;
 348     cpu->isar.id_dfr0 = 0x33;
 349     cpu->id_afr0 = 0;
 350     cpu->isar.id_mmfr0 = 0x01130003;
 351     cpu->isar.id_mmfr1 = 0x10030302;
 352     cpu->isar.id_mmfr2 = 0x01222100;
 353     cpu->isar.id_isar0 = 0x0140011;
 354     cpu->isar.id_isar1 = 0x12002111;
 355     cpu->isar.id_isar2 = 0x11231121;
 356     cpu->isar.id_isar3 = 0x01102131;
 357     cpu->isar.id_isar4 = 0x01141;
 358     cpu->reset_auxcr = 7;
 359 }
 360
 361 static void arm11mpcore_initfn(Object *obj)
 362 {
 363     ARMCPU *cpu = ARM_CPU(obj);
 364
 365     cpu->dtb_compatible = "arm,arm11mpcore";
 366     set_feature(&cpu->env, ARM_FEATURE_V6K);
 367     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 368     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 369     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 370     cpu->midr = 0x410fb022;
 371     cpu->reset_fpsid = 0x410120b4;
 372     cpu->isar.mvfr0 = 0x11111111;
 373     cpu->isar.mvfr1 = 0x00000000;
 374     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 375     cpu->isar.id_pfr0 = 0x111;
 376     cpu->isar.id_pfr1 = 0x1;
 377     cpu->isar.id_dfr0 = 0;
 378     cpu->id_afr0 = 0x2;
 379     cpu->isar.id_mmfr0 = 0x01100103;
 380     cpu->isar.id_mmfr1 = 0x10020302;
 381     cpu->isar.id_mmfr2 = 0x01222000;
 382     cpu->isar.id_isar0 = 0x00100011;
 383     cpu->isar.id_isar1 = 0x12002111;
 384     cpu->isar.id_isar2 = 0x11221011;
 385     cpu->isar.id_isar3 = 0x01102131;
 386     cpu->isar.id_isar4 = 0x141;
 387     cpu->reset_auxcr = 1;
 388 }
 389
 390 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 391     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 392       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 393     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 394       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 395 };
 396
 397 static void cortex_a8_initfn(Object *obj)
 398 {
 399     ARMCPU *cpu = ARM_CPU(obj);
 400
 401     cpu->dtb_compatible = "arm,cortex-a8";
 402     set_feature(&cpu->env, ARM_FEATURE_V7);
 403     set_feature(&cpu->env, ARM_FEATURE_NEON);
 404     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 405     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 406     set_feature(&cpu->env, ARM_FEATURE_EL3);
 407     cpu->midr = 0x410fc080;
 408     cpu->reset_fpsid = 0x410330c0;
 409     cpu->isar.mvfr0 = 0x11110222;
 410     cpu->isar.mvfr1 = 0x00011111;
 411     cpu->ctr = 0x82048004;
 412     cpu->reset_sctlr = 0x00c50078;
 413     cpu->isar.id_pfr0 = 0x1031;
 414     cpu->isar.id_pfr1 = 0x11;
 415     cpu->isar.id_dfr0 = 0x400;
 416     cpu->id_afr0 = 0;
 417     cpu->isar.id_mmfr0 = 0x31100003;
 418     cpu->isar.id_mmfr1 = 0x20000000;
 419     cpu->isar.id_mmfr2 = 0x01202000;
 420     cpu->isar.id_mmfr3 = 0x11;
 421     cpu->isar.id_isar0 = 0x00101111;
 422     cpu->isar.id_isar1 = 0x12112111;
 423     cpu->isar.id_isar2 = 0x21232031;
 424     cpu->isar.id_isar3 = 0x11112131;
 425     cpu->isar.id_isar4 = 0x00111142;
 426     cpu->isar.dbgdidr = 0x15141000;
 427     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 428     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 429     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 430     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 431     cpu->reset_auxcr = 2;
 432     cpu->isar.reset_pmcr_el0 = 0x41002000;
 433     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 434 }
 435
 436 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 437     /*
 438      * power_control should be set to maximum latency. Again,
 439      * default to 0 and set by private hook
 440      */
 441     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 442       .access = PL1_RW, .resetvalue = 0,
 443       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 444     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 445       .access = PL1_RW, .resetvalue = 0,
 446       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 447     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 448       .access = PL1_RW, .resetvalue = 0,
 449       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 450     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 451       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 452     /* TLB lockdown control */
 453     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 454       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 455     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 456       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 457     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 458       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 459     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 460       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 461     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 462       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 463 };
 464
 465 static void cortex_a9_initfn(Object *obj)
 466 {
 467     ARMCPU *cpu = ARM_CPU(obj);
 468
 469     cpu->dtb_compatible = "arm,cortex-a9";
 470     set_feature(&cpu->env, ARM_FEATURE_V7);
 471     set_feature(&cpu->env, ARM_FEATURE_NEON);
 472     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 473     set_feature(&cpu->env, ARM_FEATURE_EL3);
 474     /*
 475      * Note that A9 supports the MP extensions even for
 476      * A9UP and single-core A9MP (which are both different
 477      * and valid configurations; we don't model A9UP).
 478      */
 479     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 480     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 481     cpu->midr = 0x410fc090;
 482     cpu->reset_fpsid = 0x41033090;
 483     cpu->isar.mvfr0 = 0x11110222;
 484     cpu->isar.mvfr1 = 0x01111111;
 485     cpu->ctr = 0x80038003;
 486     cpu->reset_sctlr = 0x00c50078;
 487     cpu->isar.id_pfr0 = 0x1031;
 488     cpu->isar.id_pfr1 = 0x11;
 489     cpu->isar.id_dfr0 = 0x000;
 490     cpu->id_afr0 = 0;
 491     cpu->isar.id_mmfr0 = 0x00100103;
 492     cpu->isar.id_mmfr1 = 0x20000000;
 493     cpu->isar.id_mmfr2 = 0x01230000;
 494     cpu->isar.id_mmfr3 = 0x00002111;
 495     cpu->isar.id_isar0 = 0x00101111;
 496     cpu->isar.id_isar1 = 0x13112111;
 497     cpu->isar.id_isar2 = 0x21232041;
 498     cpu->isar.id_isar3 = 0x11112131;
 499     cpu->isar.id_isar4 = 0x00111142;
 500     cpu->isar.dbgdidr = 0x35141000;
 501     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 502     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 503     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 504     cpu->isar.reset_pmcr_el0 = 0x41093000;
 505     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 506 }
 507
 508 #ifndef CONFIG_USER_ONLY
 509 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 510 {
 511     MachineState *ms = MACHINE(qdev_get_machine());
 512
 513     /*
 514      * Linux wants the number of processors from here.
 515      * Might as well set the interrupt-controller bit too.
 516      */
 517     return ((ms->smp.cpus - 1) << 24) | (1 << 23);
 518 }
 519 #endif
 520
 521 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 522 #ifndef CONFIG_USER_ONLY
 523     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 524       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 525       .writefn = arm_cp_write_ignore, },
 526 #endif
 527     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 528       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 529 };
 530
 531 static void cortex_a7_initfn(Object *obj)
 532 {
 533     ARMCPU *cpu = ARM_CPU(obj);
 534
 535     cpu->dtb_compatible = "arm,cortex-a7";
 536     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 537     set_feature(&cpu->env, ARM_FEATURE_NEON);
 538     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 539     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 540     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 541     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 542     set_feature(&cpu->env, ARM_FEATURE_EL2);
 543     set_feature(&cpu->env, ARM_FEATURE_EL3);
 544     set_feature(&cpu->env, ARM_FEATURE_PMU);
 545     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
 546     cpu->midr = 0x410fc075;
 547     cpu->reset_fpsid = 0x41023075;
 548     cpu->isar.mvfr0 = 0x10110222;
 549     cpu->isar.mvfr1 = 0x11111111;
 550     cpu->ctr = 0x84448003;
 551     cpu->reset_sctlr = 0x00c50078;
 552     cpu->isar.id_pfr0 = 0x00001131;
 553     cpu->isar.id_pfr1 = 0x00011011;
 554     cpu->isar.id_dfr0 = 0x02010555;
 555     cpu->id_afr0 = 0x00000000;
 556     cpu->isar.id_mmfr0 = 0x10101105;
 557     cpu->isar.id_mmfr1 = 0x40000000;
 558     cpu->isar.id_mmfr2 = 0x01240000;
 559     cpu->isar.id_mmfr3 = 0x02102211;
 560     /*
 561      * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
 562      * table 4-41 gives 0x02101110, which includes the arm div insns.
 563      */
 564     cpu->isar.id_isar0 = 0x02101110;
 565     cpu->isar.id_isar1 = 0x13112111;
 566     cpu->isar.id_isar2 = 0x21232041;
 567     cpu->isar.id_isar3 = 0x11112131;
 568     cpu->isar.id_isar4 = 0x10011142;
 569     cpu->isar.dbgdidr = 0x3515f005;
 570     cpu->isar.dbgdevid = 0x01110f13;
 571     cpu->isar.dbgdevid1 = 0x1;
 572     cpu->clidr = 0x0a200023;
 573     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 574     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 575     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 576     cpu->isar.reset_pmcr_el0 = 0x41072000;
 577     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
 578 }
 579
 580 static void cortex_a15_initfn(Object *obj)
 581 {
 582     ARMCPU *cpu = ARM_CPU(obj);
 583
 584     cpu->dtb_compatible = "arm,cortex-a15";
 585     set_feature(&cpu->env, ARM_FEATURE_V7VE);
 586     set_feature(&cpu->env, ARM_FEATURE_NEON);
 587     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 588     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 589     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 590     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 591     set_feature(&cpu->env, ARM_FEATURE_EL2);
 592     set_feature(&cpu->env, ARM_FEATURE_EL3);
 593     set_feature(&cpu->env, ARM_FEATURE_PMU);
 594     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 595     cpu->midr = 0x412fc0f1;
 596     cpu->reset_fpsid = 0x410430f0;
 597     cpu->isar.mvfr0 = 0x10110222;
 598     cpu->isar.mvfr1 = 0x11111111;
 599     cpu->ctr = 0x8444c004;
 600     cpu->reset_sctlr = 0x00c50078;
 601     cpu->isar.id_pfr0 = 0x00001131;
 602     cpu->isar.id_pfr1 = 0x00011011;
 603     cpu->isar.id_dfr0 = 0x02010555;
 604     cpu->id_afr0 = 0x00000000;
 605     cpu->isar.id_mmfr0 = 0x10201105;
 606     cpu->isar.id_mmfr1 = 0x20000000;
 607     cpu->isar.id_mmfr2 = 0x01240000;
 608     cpu->isar.id_mmfr3 = 0x02102211;
 609     cpu->isar.id_isar0 = 0x02101110;
 610     cpu->isar.id_isar1 = 0x13112111;
 611     cpu->isar.id_isar2 = 0x21232041;
 612     cpu->isar.id_isar3 = 0x11112131;
 613     cpu->isar.id_isar4 = 0x10011142;
 614     cpu->isar.dbgdidr = 0x3515f021;
 615     cpu->isar.dbgdevid = 0x01110f13;
 616     cpu->isar.dbgdevid1 = 0x0;
 617     cpu->clidr = 0x0a200023;
 618     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 619     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 620     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 621     cpu->isar.reset_pmcr_el0 = 0x410F3000;
 622     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 623 }
 624
 625 static void cortex_m0_initfn(Object *obj)
 626 {
 627     ARMCPU *cpu = ARM_CPU(obj);
 628     set_feature(&cpu->env, ARM_FEATURE_V6);
 629     set_feature(&cpu->env, ARM_FEATURE_M);
 630
 631     cpu->midr = 0x410cc200;
 632
 633     /*
 634      * These ID register values are not guest visible, because
 635      * we do not implement the Main Extension. They must be set
 636      * to values corresponding to the Cortex-M0's implemented
 637      * features, because QEMU generally controls its emulation
 638      * by looking at ID register fields. We use the same values as
 639      * for the M3.
 640      */
 641     cpu->isar.id_pfr0 = 0x00000030;
 642     cpu->isar.id_pfr1 = 0x00000200;
 643     cpu->isar.id_dfr0 = 0x00100000;
 644     cpu->id_afr0 = 0x00000000;
 645     cpu->isar.id_mmfr0 = 0x00000030;
 646     cpu->isar.id_mmfr1 = 0x00000000;
 647     cpu->isar.id_mmfr2 = 0x00000000;
 648     cpu->isar.id_mmfr3 = 0x00000000;
 649     cpu->isar.id_isar0 = 0x01141110;
 650     cpu->isar.id_isar1 = 0x02111000;
 651     cpu->isar.id_isar2 = 0x21112231;
 652     cpu->isar.id_isar3 = 0x01111110;
 653     cpu->isar.id_isar4 = 0x01310102;
 654     cpu->isar.id_isar5 = 0x00000000;
 655     cpu->isar.id_isar6 = 0x00000000;
 656 }
 657
 658 static void cortex_m3_initfn(Object *obj)
 659 {
 660     ARMCPU *cpu = ARM_CPU(obj);
 661     set_feature(&cpu->env, ARM_FEATURE_V7);
 662     set_feature(&cpu->env, ARM_FEATURE_M);
 663     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 664     cpu->midr = 0x410fc231;
 665     cpu->pmsav7_dregion = 8;
 666     cpu->isar.id_pfr0 = 0x00000030;
 667     cpu->isar.id_pfr1 = 0x00000200;
 668     cpu->isar.id_dfr0 = 0x00100000;
 669     cpu->id_afr0 = 0x00000000;
 670     cpu->isar.id_mmfr0 = 0x00000030;
 671     cpu->isar.id_mmfr1 = 0x00000000;
 672     cpu->isar.id_mmfr2 = 0x00000000;
 673     cpu->isar.id_mmfr3 = 0x00000000;
 674     cpu->isar.id_isar0 = 0x01141110;
 675     cpu->isar.id_isar1 = 0x02111000;
 676     cpu->isar.id_isar2 = 0x21112231;
 677     cpu->isar.id_isar3 = 0x01111110;
 678     cpu->isar.id_isar4 = 0x01310102;
 679     cpu->isar.id_isar5 = 0x00000000;
 680     cpu->isar.id_isar6 = 0x00000000;
 681 }
 682
 683 static void cortex_m4_initfn(Object *obj)
 684 {
 685     ARMCPU *cpu = ARM_CPU(obj);
 686
 687     set_feature(&cpu->env, ARM_FEATURE_V7);
 688     set_feature(&cpu->env, ARM_FEATURE_M);
 689     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 690     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 691     cpu->midr = 0x410fc240; /* r0p0 */
 692     cpu->pmsav7_dregion = 8;
 693     cpu->isar.mvfr0 = 0x10110021;
 694     cpu->isar.mvfr1 = 0x11000011;
 695     cpu->isar.mvfr2 = 0x00000000;
 696     cpu->isar.id_pfr0 = 0x00000030;
 697     cpu->isar.id_pfr1 = 0x00000200;
 698     cpu->isar.id_dfr0 = 0x00100000;
 699     cpu->id_afr0 = 0x00000000;
 700     cpu->isar.id_mmfr0 = 0x00000030;
 701     cpu->isar.id_mmfr1 = 0x00000000;
 702     cpu->isar.id_mmfr2 = 0x00000000;
 703     cpu->isar.id_mmfr3 = 0x00000000;
 704     cpu->isar.id_isar0 = 0x01141110;
 705     cpu->isar.id_isar1 = 0x02111000;
 706     cpu->isar.id_isar2 = 0x21112231;
 707     cpu->isar.id_isar3 = 0x01111110;
 708     cpu->isar.id_isar4 = 0x01310102;
 709     cpu->isar.id_isar5 = 0x00000000;
 710     cpu->isar.id_isar6 = 0x00000000;
 711 }
 712
 713 static void cortex_m7_initfn(Object *obj)
 714 {
 715     ARMCPU *cpu = ARM_CPU(obj);
 716
 717     set_feature(&cpu->env, ARM_FEATURE_V7);
 718     set_feature(&cpu->env, ARM_FEATURE_M);
 719     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 720     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 721     cpu->midr = 0x411fc272; /* r1p2 */
 722     cpu->pmsav7_dregion = 8;
 723     cpu->isar.mvfr0 = 0x10110221;
 724     cpu->isar.mvfr1 = 0x12000011;
 725     cpu->isar.mvfr2 = 0x00000040;
 726     cpu->isar.id_pfr0 = 0x00000030;
 727     cpu->isar.id_pfr1 = 0x00000200;
 728     cpu->isar.id_dfr0 = 0x00100000;
 729     cpu->id_afr0 = 0x00000000;
 730     cpu->isar.id_mmfr0 = 0x00100030;
 731     cpu->isar.id_mmfr1 = 0x00000000;
 732     cpu->isar.id_mmfr2 = 0x01000000;
 733     cpu->isar.id_mmfr3 = 0x00000000;
 734     cpu->isar.id_isar0 = 0x01101110;
 735     cpu->isar.id_isar1 = 0x02112000;
 736     cpu->isar.id_isar2 = 0x20232231;
 737     cpu->isar.id_isar3 = 0x01111131;
 738     cpu->isar.id_isar4 = 0x01310132;
 739     cpu->isar.id_isar5 = 0x00000000;
 740     cpu->isar.id_isar6 = 0x00000000;
 741 }
 742
 743 static void cortex_m33_initfn(Object *obj)
 744 {
 745     ARMCPU *cpu = ARM_CPU(obj);
 746
 747     set_feature(&cpu->env, ARM_FEATURE_V8);
 748     set_feature(&cpu->env, ARM_FEATURE_M);
 749     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 750     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 751     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 752     cpu->midr = 0x410fd213; /* r0p3 */
 753     cpu->pmsav7_dregion = 16;
 754     cpu->sau_sregion = 8;
 755     cpu->isar.mvfr0 = 0x10110021;
 756     cpu->isar.mvfr1 = 0x11000011;
 757     cpu->isar.mvfr2 = 0x00000040;
 758     cpu->isar.id_pfr0 = 0x00000030;
 759     cpu->isar.id_pfr1 = 0x00000210;
 760     cpu->isar.id_dfr0 = 0x00200000;
 761     cpu->id_afr0 = 0x00000000;
 762     cpu->isar.id_mmfr0 = 0x00101F40;
 763     cpu->isar.id_mmfr1 = 0x00000000;
 764     cpu->isar.id_mmfr2 = 0x01000000;
 765     cpu->isar.id_mmfr3 = 0x00000000;
 766     cpu->isar.id_isar0 = 0x01101110;
 767     cpu->isar.id_isar1 = 0x02212000;
 768     cpu->isar.id_isar2 = 0x20232232;
 769     cpu->isar.id_isar3 = 0x01111131;
 770     cpu->isar.id_isar4 = 0x01310132;
 771     cpu->isar.id_isar5 = 0x00000000;
 772     cpu->isar.id_isar6 = 0x00000000;
 773     cpu->clidr = 0x00000000;
 774     cpu->ctr = 0x8000c000;
 775 }
 776
 777 static void cortex_m55_initfn(Object *obj)
 778 {
 779     ARMCPU *cpu = ARM_CPU(obj);
 780
 781     set_feature(&cpu->env, ARM_FEATURE_V8);
 782     set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 783     set_feature(&cpu->env, ARM_FEATURE_M);
 784     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 785     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 786     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 787     cpu->midr = 0x410fd221; /* r0p1 */
 788     cpu->revidr = 0;
 789     cpu->pmsav7_dregion = 16;
 790     cpu->sau_sregion = 8;
 791     /* These are the MVFR* values for the FPU + full MVE configuration */
 792     cpu->isar.mvfr0 = 0x10110221;
 793     cpu->isar.mvfr1 = 0x12100211;
 794     cpu->isar.mvfr2 = 0x00000040;
 795     cpu->isar.id_pfr0 = 0x20000030;
 796     cpu->isar.id_pfr1 = 0x00000230;
 797     cpu->isar.id_dfr0 = 0x10200000;
 798     cpu->id_afr0 = 0x00000000;
 799     cpu->isar.id_mmfr0 = 0x00111040;
 800     cpu->isar.id_mmfr1 = 0x00000000;
 801     cpu->isar.id_mmfr2 = 0x01000000;
 802     cpu->isar.id_mmfr3 = 0x00000011;
 803     cpu->isar.id_isar0 = 0x01103110;
 804     cpu->isar.id_isar1 = 0x02212000;
 805     cpu->isar.id_isar2 = 0x20232232;
 806     cpu->isar.id_isar3 = 0x01111131;
 807     cpu->isar.id_isar4 = 0x01310132;
 808     cpu->isar.id_isar5 = 0x00000000;
 809     cpu->isar.id_isar6 = 0x00000000;
 810     cpu->clidr = 0x00000000; /* caches not implemented */
 811     cpu->ctr = 0x8303c003;
 812 }
 813
 814 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 815     /* Dummy the TCM region regs for the moment */
 816     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 817       .access = PL1_RW, .type = ARM_CP_CONST },
 818     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 819       .access = PL1_RW, .type = ARM_CP_CONST },
 820     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 821       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 822 };
 823
 824 static void cortex_r5_initfn(Object *obj)
 825 {
 826     ARMCPU *cpu = ARM_CPU(obj);
 827
 828     set_feature(&cpu->env, ARM_FEATURE_V7);
 829     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 830     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 831     set_feature(&cpu->env, ARM_FEATURE_PMU);
 832     cpu->midr = 0x411fc153; /* r1p3 */
 833     cpu->isar.id_pfr0 = 0x0131;
 834     cpu->isar.id_pfr1 = 0x001;
 835     cpu->isar.id_dfr0 = 0x010400;
 836     cpu->id_afr0 = 0x0;
 837     cpu->isar.id_mmfr0 = 0x0210030;
 838     cpu->isar.id_mmfr1 = 0x00000000;
 839     cpu->isar.id_mmfr2 = 0x01200000;
 840     cpu->isar.id_mmfr3 = 0x0211;
 841     cpu->isar.id_isar0 = 0x02101111;
 842     cpu->isar.id_isar1 = 0x13112111;
 843     cpu->isar.id_isar2 = 0x21232141;
 844     cpu->isar.id_isar3 = 0x01112131;
 845     cpu->isar.id_isar4 = 0x0010142;
 846     cpu->isar.id_isar5 = 0x0;
 847     cpu->isar.id_isar6 = 0x0;
 848     cpu->mp_is_up = true;
 849     cpu->pmsav7_dregion = 16;
 850     cpu->isar.reset_pmcr_el0 = 0x41151800;
 851     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 852 }
 853
 854 static void cortex_r5f_initfn(Object *obj)
 855 {
 856     ARMCPU *cpu = ARM_CPU(obj);
 857
 858     cortex_r5_initfn(obj);
 859     cpu->isar.mvfr0 = 0x10110221;
 860     cpu->isar.mvfr1 = 0x00000011;
 861 }
 862
 863 static void ti925t_initfn(Object *obj)
 864 {
 865     ARMCPU *cpu = ARM_CPU(obj);
 866     set_feature(&cpu->env, ARM_FEATURE_V4T);
 867     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 868     cpu->midr = ARM_CPUID_TI925T;
 869     cpu->ctr = 0x5109149;
 870     cpu->reset_sctlr = 0x00000070;
 871 }
 872
 873 static void sa1100_initfn(Object *obj)
 874 {
 875     ARMCPU *cpu = ARM_CPU(obj);
 876
 877     cpu->dtb_compatible = "intel,sa1100";
 878     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 879     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 880     cpu->midr = 0x4401A11B;
 881     cpu->reset_sctlr = 0x00000070;
 882 }
 883
 884 static void sa1110_initfn(Object *obj)
 885 {
 886     ARMCPU *cpu = ARM_CPU(obj);
 887     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 888     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 889     cpu->midr = 0x6901B119;
 890     cpu->reset_sctlr = 0x00000070;
 891 }
 892
 893 static void pxa250_initfn(Object *obj)
 894 {
 895     ARMCPU *cpu = ARM_CPU(obj);
 896
 897     cpu->dtb_compatible = "marvell,xscale";
 898     set_feature(&cpu->env, ARM_FEATURE_V5);
 899     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 900     cpu->midr = 0x69052100;
 901     cpu->ctr = 0xd172172;
 902     cpu->reset_sctlr = 0x00000078;
 903 }
 904
 905 static void pxa255_initfn(Object *obj)
 906 {
 907     ARMCPU *cpu = ARM_CPU(obj);
 908
 909     cpu->dtb_compatible = "marvell,xscale";
 910     set_feature(&cpu->env, ARM_FEATURE_V5);
 911     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 912     cpu->midr = 0x69052d00;
 913     cpu->ctr = 0xd172172;
 914     cpu->reset_sctlr = 0x00000078;
 915 }
 916
 917 static void pxa260_initfn(Object *obj)
 918 {
 919     ARMCPU *cpu = ARM_CPU(obj);
 920
 921     cpu->dtb_compatible = "marvell,xscale";
 922     set_feature(&cpu->env, ARM_FEATURE_V5);
 923     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 924     cpu->midr = 0x69052903;
 925     cpu->ctr = 0xd172172;
 926     cpu->reset_sctlr = 0x00000078;
 927 }
 928
 929 static void pxa261_initfn(Object *obj)
 930 {
 931     ARMCPU *cpu = ARM_CPU(obj);
 932
 933     cpu->dtb_compatible = "marvell,xscale";
 934     set_feature(&cpu->env, ARM_FEATURE_V5);
 935     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 936     cpu->midr = 0x69052d05;
 937     cpu->ctr = 0xd172172;
 938     cpu->reset_sctlr = 0x00000078;
 939 }
 940
 941 static void pxa262_initfn(Object *obj)
 942 {
 943     ARMCPU *cpu = ARM_CPU(obj);
 944
 945     cpu->dtb_compatible = "marvell,xscale";
 946     set_feature(&cpu->env, ARM_FEATURE_V5);
 947     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 948     cpu->midr = 0x69052d06;
 949     cpu->ctr = 0xd172172;
 950     cpu->reset_sctlr = 0x00000078;
 951 }
 952
 953 static void pxa270a0_initfn(Object *obj)
 954 {
 955     ARMCPU *cpu = ARM_CPU(obj);
 956
 957     cpu->dtb_compatible = "marvell,xscale";
 958     set_feature(&cpu->env, ARM_FEATURE_V5);
 959     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 960     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 961     cpu->midr = 0x69054110;
 962     cpu->ctr = 0xd172172;
 963     cpu->reset_sctlr = 0x00000078;
 964 }
 965
 966 static void pxa270a1_initfn(Object *obj)
 967 {
 968     ARMCPU *cpu = ARM_CPU(obj);
 969
 970     cpu->dtb_compatible = "marvell,xscale";
 971     set_feature(&cpu->env, ARM_FEATURE_V5);
 972     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 973     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 974     cpu->midr = 0x69054111;
 975     cpu->ctr = 0xd172172;
 976     cpu->reset_sctlr = 0x00000078;
 977 }
 978
 979 static void pxa270b0_initfn(Object *obj)
 980 {
 981     ARMCPU *cpu = ARM_CPU(obj);
 982
 983     cpu->dtb_compatible = "marvell,xscale";
 984     set_feature(&cpu->env, ARM_FEATURE_V5);
 985     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 986     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 987     cpu->midr = 0x69054112;
 988     cpu->ctr = 0xd172172;
 989     cpu->reset_sctlr = 0x00000078;
 990 }
 991
 992 static void pxa270b1_initfn(Object *obj)
 993 {
 994     ARMCPU *cpu = ARM_CPU(obj);
 995
 996     cpu->dtb_compatible = "marvell,xscale";
 997     set_feature(&cpu->env, ARM_FEATURE_V5);
 998     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 999     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1000     cpu->midr = 0x69054113;
1001     cpu->ctr = 0xd172172;
1002     cpu->reset_sctlr = 0x00000078;
1003 }
1004
1005 static void pxa270c0_initfn(Object *obj)
1006 {
1007     ARMCPU *cpu = ARM_CPU(obj);
1008
1009     cpu->dtb_compatible = "marvell,xscale";
1010     set_feature(&cpu->env, ARM_FEATURE_V5);
1011     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1012     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1013     cpu->midr = 0x69054114;
1014     cpu->ctr = 0xd172172;
1015     cpu->reset_sctlr = 0x00000078;
1016 }
1017
1018 static void pxa270c5_initfn(Object *obj)
1019 {
1020     ARMCPU *cpu = ARM_CPU(obj);
1021
1022     cpu->dtb_compatible = "marvell,xscale";
1023     set_feature(&cpu->env, ARM_FEATURE_V5);
1024     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1025     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1026     cpu->midr = 0x69054117;
1027     cpu->ctr = 0xd172172;
1028     cpu->reset_sctlr = 0x00000078;
1029 }
1030
1031 #ifdef CONFIG_TCG
1032 static const struct TCGCPUOps arm_v7m_tcg_ops = {
1033     .initialize = arm_translate_init,
1034     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
1035     .debug_excp_handler = arm_debug_excp_handler,
1036
1037 #ifdef CONFIG_USER_ONLY
1038     .record_sigsegv = arm_cpu_record_sigsegv,
1039     .record_sigbus = arm_cpu_record_sigbus,
1040 #else
1041     .tlb_fill = arm_cpu_tlb_fill,
1042     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
1043     .do_interrupt = arm_v7m_cpu_do_interrupt,
1044     .do_transaction_failed = arm_cpu_do_transaction_failed,
1045     .do_unaligned_access = arm_cpu_do_unaligned_access,
1046     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1047     .debug_check_watchpoint = arm_debug_check_watchpoint,
1048     .debug_check_breakpoint = arm_debug_check_breakpoint,
1049 #endif /* !CONFIG_USER_ONLY */
1050 };
1051 #endif /* CONFIG_TCG */
1052
1053 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1054 {
1055     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1056     CPUClass *cc = CPU_CLASS(oc);
1057
1058     acc->info = data;
1059 #ifdef CONFIG_TCG
1060     cc->tcg_ops = &arm_v7m_tcg_ops;
1061 #endif /* CONFIG_TCG */
1062
1063     cc->gdb_core_xml_file = "arm-m-profile.xml";
1064 }
1065
1066 #ifndef TARGET_AARCH64
1067 /*
1068  * -cpu max: a CPU with as many features enabled as our emulation supports.
1069  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1070  * this only needs to handle 32 bits, and need not care about KVM.
1071  */
1072 static void arm_max_initfn(Object *obj)
1073 {
1074     ARMCPU *cpu = ARM_CPU(obj);
1075
1076     /* aarch64_a57_initfn, advertising none of the aarch64 features */
1077     cpu->dtb_compatible = "arm,cortex-a57";
1078     set_feature(&cpu->env, ARM_FEATURE_V8);
1079     set_feature(&cpu->env, ARM_FEATURE_NEON);
1080     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1081     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1082     set_feature(&cpu->env, ARM_FEATURE_EL2);
1083     set_feature(&cpu->env, ARM_FEATURE_EL3);
1084     set_feature(&cpu->env, ARM_FEATURE_PMU);
1085     cpu->midr = 0x411fd070;
1086     cpu->revidr = 0x00000000;
1087     cpu->reset_fpsid = 0x41034070;
1088     cpu->isar.mvfr0 = 0x10110222;
1089     cpu->isar.mvfr1 = 0x12111111;
1090     cpu->isar.mvfr2 = 0x00000043;
1091     cpu->ctr = 0x8444c004;
1092     cpu->reset_sctlr = 0x00c50838;
1093     cpu->isar.id_pfr0 = 0x00000131;
1094     cpu->isar.id_pfr1 = 0x00011011;
1095     cpu->isar.id_dfr0 = 0x03010066;
1096     cpu->id_afr0 = 0x00000000;
1097     cpu->isar.id_mmfr0 = 0x10101105;
1098     cpu->isar.id_mmfr1 = 0x40000000;
1099     cpu->isar.id_mmfr2 = 0x01260000;
1100     cpu->isar.id_mmfr3 = 0x02102211;
1101     cpu->isar.id_isar0 = 0x02101110;
1102     cpu->isar.id_isar1 = 0x13112111;
1103     cpu->isar.id_isar2 = 0x21232042;
1104     cpu->isar.id_isar3 = 0x01112131;
1105     cpu->isar.id_isar4 = 0x00011142;
1106     cpu->isar.id_isar5 = 0x00011121;
1107     cpu->isar.id_isar6 = 0;
1108     cpu->isar.dbgdidr = 0x3516d000;
1109     cpu->isar.dbgdevid = 0x00110f13;
1110     cpu->isar.dbgdevid1 = 0x2;
1111     cpu->isar.reset_pmcr_el0 = 0x41013000;
1112     cpu->clidr = 0x0a200023;
1113     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1114     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1115     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1116     define_cortex_a72_a57_a53_cp_reginfo(cpu);
1117
1118     aa32_max_features(cpu);
1119
1120 #ifdef CONFIG_USER_ONLY
1121     /*
1122      * Break with true ARMv8 and add back old-style VFP short-vector support.
1123      * Only do this for user-mode, where -cpu max is the default, so that
1124      * older v6 and v7 programs are more likely to work without adjustment.
1125      */
1126     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1127 #endif
1128 }
1129 #endif /* !TARGET_AARCH64 */
1130
1131 static const ARMCPUInfo arm_tcg_cpus[] = {
1132     { .name = "arm926",      .initfn = arm926_initfn },
1133     { .name = "arm946",      .initfn = arm946_initfn },
1134     { .name = "arm1026",     .initfn = arm1026_initfn },
1135     /*
1136      * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1137      * older core than plain "arm1136". In particular this does not
1138      * have the v6K features.
1139      */
1140     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1141     { .name = "arm1136",     .initfn = arm1136_initfn },
1142     { .name = "arm1176",     .initfn = arm1176_initfn },
1143     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1144     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1145     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1146     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1147     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1148     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
1149                              .class_init = arm_v7m_class_init },
1150     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1151                              .class_init = arm_v7m_class_init },
1152     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1153                              .class_init = arm_v7m_class_init },
1154     { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
1155                              .class_init = arm_v7m_class_init },
1156     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
1157                              .class_init = arm_v7m_class_init },
1158     { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
1159                              .class_init = arm_v7m_class_init },
1160     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1161     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
1162     { .name = "ti925t",      .initfn = ti925t_initfn },
1163     { .name = "sa1100",      .initfn = sa1100_initfn },
1164     { .name = "sa1110",      .initfn = sa1110_initfn },
1165     { .name = "pxa250",      .initfn = pxa250_initfn },
1166     { .name = "pxa255",      .initfn = pxa255_initfn },
1167     { .name = "pxa260",      .initfn = pxa260_initfn },
1168     { .name = "pxa261",      .initfn = pxa261_initfn },
1169     { .name = "pxa262",      .initfn = pxa262_initfn },
1170     /* "pxa270" is an alias for "pxa270-a0" */
1171     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1172     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1173     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1174     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1175     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1176     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1177     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1178 #ifndef TARGET_AARCH64
1179     { .name = "max",         .initfn = arm_max_initfn },
1180 #endif
1181 #ifdef CONFIG_USER_ONLY
1182     { .name = "any",         .initfn = arm_max_initfn },
1183 #endif
1184 };
1185
1186 static const TypeInfo idau_interface_type_info = {
1187     .name = TYPE_IDAU_INTERFACE,
1188     .parent = TYPE_INTERFACE,
1189     .class_size = sizeof(IDAUInterfaceClass),
1190 };
1191
1192 static void arm_tcg_cpu_register_types(void)
1193 {
1194     size_t i;
1195
1196     type_register_static(&idau_interface_type_info);
1197     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1198         arm_cpu_register(&arm_tcg_cpus[i]);
1199     }
1200 }
1201
1202 type_init(arm_tcg_cpu_register_types)
1203
1204 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */