disas/nanomips.cpp

   1 /*
   2  *  Source file for nanoMIPS disassembler component of QEMU
   3  *
   4  *  Copyright (C) 2018  Wave Computing
   5  *  Copyright (C) 2018  Matthew Fortune <[email protected]>
   6  *  Copyright (C) 2018  Aleksandar Markovic <[email protected]>
   7  *
   8  *  This program is free software: you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation, either version 3 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
  20  */
  21
  22 extern "C" {
  23 #include "qemu/osdep.h"
  24 #include "disas/bfd.h"
  25 }
  26
  27 #include <cstring>
  28 #include <stdexcept>
  29 #include <sstream>
  30 #include <stdio.h>
  31 #include <stdarg.h>
  32
  33 #include "nanomips.h"
  34
  35 #define IMGASSERTONCE(test)
  36
  37
  38 int nanomips_dis(char *buf,
  39                  unsigned address,
  40                  unsigned short one,
  41                  unsigned short two,
  42                  unsigned short three)
  43 {
  44     std::string disasm;
  45     uint16 bits[3] = {one, two, three};
  46
  47     NMD::TABLE_ENTRY_TYPE type;
  48     NMD d(address, NMD::ALL_ATTRIBUTES);
  49     int size = d.Disassemble(bits, disasm, type);
  50
  51     strcpy(buf, disasm.c_str());
  52     return size;
  53 }
  54
  55 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
  56 {
  57     int status;
  58     bfd_byte buffer[2];
  59     uint16_t insn1 = 0, insn2 = 0, insn3 = 0;
  60     char buf[200];
  61
  62     info->bytes_per_chunk = 2;
  63     info->display_endian = info->endian;
  64     info->insn_info_valid = 1;
  65     info->branch_delay_insns = 0;
  66     info->data_size = 0;
  67     info->insn_type = dis_nonbranch;
  68     info->target = 0;
  69     info->target2 = 0;
  70
  71     status = (*info->read_memory_func)(memaddr, buffer, 2, info);
  72     if (status != 0) {
  73         (*info->memory_error_func)(status, memaddr, info);
  74         return -1;
  75     }
  76
  77     if (info->endian == BFD_ENDIAN_BIG) {
  78         insn1 = bfd_getb16(buffer);
  79     } else {
  80         insn1 = bfd_getl16(buffer);
  81     }
  82     (*info->fprintf_func)(info->stream, "%04x ", insn1);
  83
  84     /* Handle 32-bit opcodes.  */
  85     if ((insn1 & 0x1000) == 0) {
  86         status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);
  87         if (status != 0) {
  88             (*info->memory_error_func)(status, memaddr + 2, info);
  89             return -1;
  90         }
  91
  92         if (info->endian == BFD_ENDIAN_BIG) {
  93             insn2 = bfd_getb16(buffer);
  94         } else {
  95             insn2 = bfd_getl16(buffer);
  96         }
  97         (*info->fprintf_func)(info->stream, "%04x ", insn2);
  98     } else {
  99         (*info->fprintf_func)(info->stream, "     ");
 100     }
 101     /* Handle 48-bit opcodes.  */
 102     if ((insn1 >> 10) == 0x18) {
 103         status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);
 104         if (status != 0) {
 105             (*info->memory_error_func)(status, memaddr + 4, info);
 106             return -1;
 107         }
 108
 109         if (info->endian == BFD_ENDIAN_BIG) {
 110             insn3 = bfd_getb16(buffer);
 111         } else {
 112             insn3 = bfd_getl16(buffer);
 113         }
 114         (*info->fprintf_func)(info->stream, "%04x ", insn3);
 115     } else {
 116         (*info->fprintf_func)(info->stream, "     ");
 117     }
 118
 119     int length = nanomips_dis(buf, memaddr, insn1, insn2, insn3);
 120
 121     /* FIXME: Should probably use a hash table on the major opcode here.  */
 122
 123     (*info->fprintf_func) (info->stream, "%s", buf);
 124     if (length > 0) {
 125         return length / 8;
 126     }
 127
 128     info->insn_type = dis_noninsn;
 129
 130     return insn3 ? 6 : insn2 ? 4 : 2;
 131 }
 132
 133
 134 namespace img
 135 {
 136     address addr32(address a)
 137     {
 138         return a;
 139     }
 140
 141     std::string format(const char *format, ...)
 142     {
 143         char buffer[256];
 144         va_list args;
 145         va_start(args, format);
 146         int err = vsprintf(buffer, format, args);
 147         if (err < 0) {
 148             perror(buffer);
 149         }
 150         va_end(args);
 151         return buffer;
 152     }
 153
 154     std::string format(const char *format,
 155                        std::string s)
 156     {
 157         char buffer[256];
 158
 159         sprintf(buffer, format, s.c_str());
 160
 161         return buffer;
 162     }
 163
 164     std::string format(const char *format,
 165                        std::string s1,
 166                        std::string s2)
 167     {
 168         char buffer[256];
 169
 170         sprintf(buffer, format, s1.c_str(), s2.c_str());
 171
 172         return buffer;
 173     }
 174
 175     std::string format(const char *format,
 176                        std::string s1,
 177                        std::string s2,
 178                        std::string s3)
 179     {
 180         char buffer[256];
 181
 182         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str());
 183
 184         return buffer;
 185     }
 186
 187     std::string format(const char *format,
 188                        std::string s1,
 189                        std::string s2,
 190                        std::string s3,
 191                        std::string s4)
 192     {
 193         char buffer[256];
 194
 195         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 196                                 s4.c_str());
 197
 198         return buffer;
 199     }
 200
 201     std::string format(const char *format,
 202                        std::string s1,
 203                        std::string s2,
 204                        std::string s3,
 205                        std::string s4,
 206                        std::string s5)
 207     {
 208         char buffer[256];
 209
 210         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 211                                 s4.c_str(), s5.c_str());
 212
 213         return buffer;
 214     }
 215
 216     std::string format(const char *format,
 217                        uint64 d,
 218                        std::string s2)
 219     {
 220         char buffer[256];
 221
 222         sprintf(buffer, format, d, s2.c_str());
 223
 224         return buffer;
 225     }
 226
 227     std::string format(const char *format,
 228                        std::string s1,
 229                        uint64 d,
 230                        std::string s2)
 231     {
 232         char buffer[256];
 233
 234         sprintf(buffer, format, s1.c_str(), d, s2.c_str());
 235
 236         return buffer;
 237     }
 238
 239     std::string format(const char *format,
 240                        std::string s1,
 241                        std::string s2,
 242                        uint64 d)
 243     {
 244         char buffer[256];
 245
 246         sprintf(buffer, format, s1.c_str(), s2.c_str(), d);
 247
 248         return buffer;
 249     }
 250
 251     char as_char(int c)
 252     {
 253         return static_cast<char>(c);
 254     }
 255 };
 256
 257
 258 std::string to_string(img::address a)
 259 {
 260     char buffer[256];
 261     sprintf(buffer, "0x%08llx", a);
 262     return buffer;
 263 }
 264
 265
 266 uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)
 267 {
 268     return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);
 269 }
 270
 271
 272 int64 sign_extend(int64 data, int msb)
 273 {
 274     uint64 shift = 63 - msb;
 275     return (data << shift) >> shift;
 276 }
 277
 278
 279 uint64 NMD::renumber_registers(uint64 index, uint64 *register_list,
 280                                size_t register_list_size)
 281 {
 282     if (index < register_list_size) {
 283         return register_list[index];
 284     }
 285
 286     throw std::runtime_error(img::format(
 287                    "Invalid register mapping index %d, size of list = %d",
 288                    index, register_list_size));
 289 }
 290
 291
 292 /*
 293  * these functions should be decode functions but the json does not have
 294  * decode sections so they are based on the encode, the equivalent decode
 295  * functions need writing eventually.
 296  */
 297 uint64 NMD::encode_gpr3(uint64 d)
 298 {
 299     static uint64 register_list[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
 300     return renumber_registers(d, register_list,
 301                sizeof(register_list) / sizeof(register_list[0]));
 302 }
 303
 304
 305 uint64 NMD::encode_gpr3_store(uint64 d)
 306 {
 307     static uint64 register_list[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
 308     return renumber_registers(d, register_list,
 309                sizeof(register_list) / sizeof(register_list[0]));
 310 }
 311
 312
 313 uint64 NMD::encode_rd1_from_rd(uint64 d)
 314 {
 315     static uint64 register_list[] = {  4,  5 };
 316     return renumber_registers(d, register_list,
 317                sizeof(register_list) / sizeof(register_list[0]));
 318 }
 319
 320
 321 uint64 NMD::encode_gpr4_zero(uint64 d)
 322 {
 323     static uint64 register_list[] = {  8,  9, 10,  0,  4,  5,  6,  7,
 324                                       16, 17, 18, 19, 20, 21, 22, 23 };
 325     return renumber_registers(d, register_list,
 326                sizeof(register_list) / sizeof(register_list[0]));
 327 }
 328
 329
 330 uint64 NMD::encode_gpr4(uint64 d)
 331 {
 332     static uint64 register_list[] = {  8,  9, 10, 11,  4,  5,  6,  7,
 333                                       16, 17, 18, 19, 20, 21, 22, 23 };
 334     return renumber_registers(d, register_list,
 335                sizeof(register_list) / sizeof(register_list[0]));
 336 }
 337
 338
 339 uint64 NMD::encode_rd2_reg1(uint64 d)
 340 {
 341     static uint64 register_list[] = {  4,  5,  6,  7 };
 342     return renumber_registers(d, register_list,
 343                sizeof(register_list) / sizeof(register_list[0]));
 344 }
 345
 346
 347 uint64 NMD::encode_rd2_reg2(uint64 d)
 348 {
 349     static uint64 register_list[] = {  5,  6,  7,  8 };
 350     return renumber_registers(d, register_list,
 351                sizeof(register_list) / sizeof(register_list[0]));
 352 }
 353
 354
 355 uint64 NMD::copy(uint64 d)
 356 {
 357     return d;
 358 }
 359
 360
 361 int64 NMD::copy(int64 d)
 362 {
 363     return d;
 364 }
 365
 366
 367 int64 NMD::neg_copy(uint64 d)
 368 {
 369     return 0ll - d;
 370 }
 371
 372
 373 int64 NMD::neg_copy(int64 d)
 374 {
 375     return -d;
 376 }
 377
 378
 379 /* strange wrapper around  gpr3 */
 380 uint64 NMD::encode_rs3_and_check_rs3_ge_rt3(uint64 d)
 381 {
 382 return encode_gpr3(d);
 383 }
 384
 385
 386 /* strange wrapper around  gpr3 */
 387 uint64 NMD::encode_rs3_and_check_rs3_lt_rt3(uint64 d)
 388 {
 389     return encode_gpr3(d);
 390 }
 391
 392
 393 /* nop - done by extraction function */
 394 uint64 NMD::encode_s_from_address(uint64 d)
 395 {
 396     return d;
 397 }
 398
 399
 400 /* nop - done by extraction function */
 401 uint64 NMD::encode_u_from_address(uint64 d)
 402 {
 403     return d;
 404 }
 405
 406
 407 /* nop - done by extraction function */
 408 uint64 NMD::encode_s_from_s_hi(uint64 d)
 409 {
 410     return d;
 411 }
 412
 413
 414 uint64 NMD::encode_count3_from_count(uint64 d)
 415 {
 416     IMGASSERTONCE(d < 8);
 417     return d == 0ull ? 8ull : d;
 418 }
 419
 420
 421 uint64 NMD::encode_shift3_from_shift(uint64 d)
 422 {
 423     IMGASSERTONCE(d < 8);
 424     return d == 0ull ? 8ull : d;
 425 }
 426
 427
 428 /* special value for load literal */
 429 int64 NMD::encode_eu_from_s_li16(uint64 d)
 430 {
 431     IMGASSERTONCE(d < 128);
 432     return d == 127 ? -1 : (int64)d;
 433 }
 434
 435
 436 uint64 NMD::encode_msbd_from_size(uint64 d)
 437 {
 438     IMGASSERTONCE(d < 32);
 439     return d + 1;
 440 }
 441
 442
 443 uint64 NMD::encode_eu_from_u_andi16(uint64 d)
 444 {
 445     IMGASSERTONCE(d < 16);
 446     if (d == 12) {
 447         return 0x00ffull;
 448     }
 449     if (d == 13) {
 450         return 0xffffull;
 451     }
 452     return d;
 453 }
 454
 455
 456 uint64 NMD::encode_msbd_from_pos_and_size(uint64 d)
 457 {
 458     IMGASSERTONCE(0);
 459     return d;
 460 }
 461
 462
 463 /* save16 / restore16   ???? */
 464 uint64 NMD::encode_rt1_from_rt(uint64 d)
 465 {
 466     return d ? 31 : 30;
 467 }
 468
 469
 470 /* ? */
 471 uint64 NMD::encode_lsb_from_pos_and_size(uint64 d)
 472 {
 473     return d;
 474 }
 475
 476
 477 std::string NMD::save_restore_list(uint64 rt, uint64 count, uint64 gp)
 478 {
 479     std::string str;
 480
 481     for (uint64 counter = 0; counter != count; counter++) {
 482         bool use_gp = gp && (counter == count - 1);
 483         uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;
 484         str += img::format(",%s", GPR(this_rt));
 485     }
 486
 487     return str;
 488 }
 489
 490
 491 std::string NMD::GPR(uint64 reg)
 492 {
 493     static const char *gpr_reg[32] = {
 494         "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
 495         "a4",   "a5",   "a6",   "a7",   "r12",  "r13",  "r14",  "r15",
 496         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 497         "r24",  "r25",  "k0",   "k1",   "gp",   "sp",   "fp",   "ra"
 498     };
 499
 500     if (reg < 32) {
 501         return gpr_reg[reg];
 502     }
 503
 504     throw std::runtime_error(img::format("Invalid GPR register index %d", reg));
 505 }
 506
 507
 508 std::string NMD::FPR(uint64 reg)
 509 {
 510     static const char *fpr_reg[32] = {
 511         "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
 512         "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
 513         "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
 514         "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 515     };
 516
 517     if (reg < 32) {
 518         return fpr_reg[reg];
 519     }
 520
 521     throw std::runtime_error(img::format("Invalid FPR register index %d", reg));
 522 }
 523
 524
 525 std::string NMD::AC(uint64 reg)
 526 {
 527     static const char *ac_reg[4] = {
 528         "ac0",  "ac1",  "ac2",  "ac3"
 529     };
 530
 531     if (reg < 4) {
 532         return ac_reg[reg];
 533     }
 534
 535     throw std::runtime_error(img::format("Invalid AC register index %d", reg));
 536 }
 537
 538
 539 std::string NMD::IMMEDIATE(uint64 value)
 540 {
 541     return img::format("0x%x", value);
 542 }
 543
 544
 545 std::string NMD::IMMEDIATE(int64 value)
 546 {
 547     return img::format("%d", value);
 548 }
 549
 550
 551 std::string NMD::CPR(uint64 reg)
 552 {
 553     /* needs more work */
 554     return img::format("CP%d", reg);
 555 }
 556
 557
 558 std::string NMD::ADDRESS(uint64 value, int instruction_size)
 559 {
 560     /* token for string replace */
 561     /* const char TOKEN_REPLACE = (char)0xa2; */
 562     img::address address = m_pc + value + instruction_size;
 563     /* symbol replacement */
 564     /* return img::as_char(TOKEN_REPLACE) + to_string(address); */
 565     return to_string(address);
 566 }
 567
 568
 569 uint64 NMD::extract_op_code_value(const uint16 * data, int size)
 570 {
 571     switch (size) {
 572     case 16:
 573         return data[0];
 574     case 32:
 575         return ((uint64)data[0] << 16) | data[1];
 576     case 48:
 577         return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];
 578     default:
 579         return data[0];
 580     }
 581 }
 582
 583
 584 int NMD::Disassemble(const uint16 * data, std::string & dis,
 585                      NMD::TABLE_ENTRY_TYPE & type)
 586 {
 587     return Disassemble(data, dis, type, MAJOR, 2);
 588 }
 589
 590
 591 /*
 592  * Recurse through tables until the instruction is found then return
 593  * the string and size
 594  *
 595  * inputs:
 596  *      pointer to a word stream,
 597  *      disassember table and size
 598  * returns:
 599  *      instruction size    - negative is error
 600  *      disassembly string  - on error will constain error string
 601  */
 602 int NMD::Disassemble(const uint16 * data, std::string & dis,
 603                      NMD::TABLE_ENTRY_TYPE & type, const Pool *table,
 604                      int table_size)
 605 {
 606     try
 607     {
 608         for (int i = 0; i < table_size; i++) {
 609             uint64 op_code = extract_op_code_value(data,
 610                                  table[i].instructions_size);
 611             if ((op_code & table[i].mask) == table[i].value) {
 612                 /* possible match */
 613                 conditional_function cond = table[i].condition;
 614                 if ((cond == 0) || (this->*cond)(op_code)) {
 615                     try
 616                     {
 617                         if (table[i].type == pool) {
 618                             return Disassemble(data, dis, type,
 619                                                table[i].next_table,
 620                                                table[i].next_table_size);
 621                         } else if ((table[i].type == instruction) ||
 622                                    (table[i].type == call_instruction) ||
 623                                    (table[i].type == branch_instruction) ||
 624                                    (table[i].type == return_instruction)) {
 625                             if ((table[i].attributes != 0) &&
 626                                 (m_requested_instruction_categories &
 627                                  table[i].attributes) == 0) {
 628                                 /*
 629                                  * failed due to instruction having
 630                                  * an ASE attribute and the requested version
 631                                  * not having that attribute
 632                                  */
 633                                 dis = "ASE attribute missmatch";
 634                                 return -5;
 635                             }
 636                             disassembly_function dis_fn = table[i].disassembly;
 637                             if (dis_fn == 0) {
 638                                 dis = "disassembler failure - bad table entry";
 639                                 return -6;
 640                             }
 641                             type = table[i].type;
 642                             dis = (this->*dis_fn)(op_code);
 643                             return table[i].instructions_size;
 644                         } else {
 645                             dis = "reserved instruction";
 646                             return -2;
 647                         }
 648                     }
 649                     catch (std::runtime_error & e)
 650                     {
 651                         dis = e.what();
 652                         return -3;          /* runtime error */
 653                     }
 654                 }
 655             }
 656         }
 657     }
 658     catch (std::exception & e)
 659     {
 660         dis = e.what();
 661         return -4;          /* runtime error */
 662     }
 663
 664     dis = "failed to disassemble";
 665     return -1;      /* failed to disassemble        */
 666 }
 667
 668
 669 uint64 NMD::extract_code_18_to_0(uint64 instruction)
 670 {
 671     uint64 value = 0;
 672     value |= extract_bits(instruction, 0, 19);
 673     return value;
 674 }
 675
 676
 677 uint64 NMD::extract_shift3_2_1_0(uint64 instruction)
 678 {
 679     uint64 value = 0;
 680     value |= extract_bits(instruction, 0, 3);
 681     return value;
 682 }
 683
 684
 685 uint64 NMD::extr_uil3il3bs9Fmsb11(uint64 instruction)
 686 {
 687     uint64 value = 0;
 688     value |= extract_bits(instruction, 3, 9) << 3;
 689     return value;
 690 }
 691
 692
 693 uint64 NMD::extract_count_3_2_1_0(uint64 instruction)
 694 {
 695     uint64 value = 0;
 696     value |= extract_bits(instruction, 0, 4);
 697     return value;
 698 }
 699
 700
 701 uint64 NMD::extract_rtz3_9_8_7(uint64 instruction)
 702 {
 703     uint64 value = 0;
 704     value |= extract_bits(instruction, 7, 3);
 705     return value;
 706 }
 707
 708
 709 uint64 NMD::extr_uil1il1bs17Fmsb17(uint64 instruction)
 710 {
 711     uint64 value = 0;
 712     value |= extract_bits(instruction, 1, 17) << 1;
 713     return value;
 714 }
 715
 716
 717 int64 NMD::extr_sil11il0bs10Tmsb9(uint64 instruction)
 718 {
 719     int64 value = 0;
 720     value |= extract_bits(instruction, 11, 10);
 721     value = sign_extend(value, 9);
 722     return value;
 723 }
 724
 725
 726 int64 NMD::extr_sil0il11bs1_il1il1bs10Tmsb11(uint64 instruction)
 727 {
 728     int64 value = 0;
 729     value |= extract_bits(instruction, 0, 1) << 11;
 730     value |= extract_bits(instruction, 1, 10) << 1;
 731     value = sign_extend(value, 11);
 732     return value;
 733 }
 734
 735
 736 uint64 NMD::extract_u_10(uint64 instruction)
 737 {
 738     uint64 value = 0;
 739     value |= extract_bits(instruction, 10, 1);
 740     return value;
 741 }
 742
 743
 744 uint64 NMD::extract_rtz4_27_26_25_23_22_21(uint64 instruction)
 745 {
 746     uint64 value = 0;
 747     value |= extract_bits(instruction, 21, 3);
 748     value |= extract_bits(instruction, 25, 1) << 3;
 749     return value;
 750 }
 751
 752
 753 uint64 NMD::extract_sa_15_14_13_12_11(uint64 instruction)
 754 {
 755     uint64 value = 0;
 756     value |= extract_bits(instruction, 11, 5);
 757     return value;
 758 }
 759
 760
 761 uint64 NMD::extract_shift_4_3_2_1_0(uint64 instruction)
 762 {
 763     uint64 value = 0;
 764     value |= extract_bits(instruction, 0, 5);
 765     return value;
 766 }
 767
 768
 769 uint64 NMD::extr_shiftxil7il1bs4Fmsb4(uint64 instruction)
 770 {
 771     uint64 value = 0;
 772     value |= extract_bits(instruction, 7, 4) << 1;
 773     return value;
 774 }
 775
 776
 777 uint64 NMD::extract_hint_25_24_23_22_21(uint64 instruction)
 778 {
 779     uint64 value = 0;
 780     value |= extract_bits(instruction, 21, 5);
 781     return value;
 782 }
 783
 784
 785 uint64 NMD::extract_count3_14_13_12(uint64 instruction)
 786 {
 787     uint64 value = 0;
 788     value |= extract_bits(instruction, 12, 3);
 789     return value;
 790 }
 791
 792
 793 int64 NMD::extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(uint64 instruction)
 794 {
 795     int64 value = 0;
 796     value |= extract_bits(instruction, 0, 1) << 31;
 797     value |= extract_bits(instruction, 2, 10) << 21;
 798     value |= extract_bits(instruction, 12, 9) << 12;
 799     value = sign_extend(value, 31);
 800     return value;
 801 }
 802
 803
 804 int64 NMD::extr_sil0il7bs1_il1il1bs6Tmsb7(uint64 instruction)
 805 {
 806     int64 value = 0;
 807     value |= extract_bits(instruction, 0, 1) << 7;
 808     value |= extract_bits(instruction, 1, 6) << 1;
 809     value = sign_extend(value, 7);
 810     return value;
 811 }
 812
 813
 814 uint64 NMD::extract_u2_10_9(uint64 instruction)
 815 {
 816     uint64 value = 0;
 817     value |= extract_bits(instruction, 9, 2);
 818     return value;
 819 }
 820
 821
 822 uint64 NMD::extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction)
 823 {
 824     uint64 value = 0;
 825     value |= extract_bits(instruction, 16, 10);
 826     return value;
 827 }
 828
 829
 830 uint64 NMD::extract_rs_20_19_18_17_16(uint64 instruction)
 831 {
 832     uint64 value = 0;
 833     value |= extract_bits(instruction, 16, 5);
 834     return value;
 835 }
 836
 837
 838 uint64 NMD::extr_uil1il1bs2Fmsb2(uint64 instruction)
 839 {
 840     uint64 value = 0;
 841     value |= extract_bits(instruction, 1, 2) << 1;
 842     return value;
 843 }
 844
 845
 846 uint64 NMD::extract_stripe_6(uint64 instruction)
 847 {
 848     uint64 value = 0;
 849     value |= extract_bits(instruction, 6, 1);
 850     return value;
 851 }
 852
 853
 854 uint64 NMD::extr_xil17il0bs1Fmsb0(uint64 instruction)
 855 {
 856     uint64 value = 0;
 857     value |= extract_bits(instruction, 17, 1);
 858     return value;
 859 }
 860
 861
 862 uint64 NMD::extr_xil2il0bs1_il15il0bs1Fmsb0(uint64 instruction)
 863 {
 864     uint64 value = 0;
 865     value |= extract_bits(instruction, 2, 1);
 866     value |= extract_bits(instruction, 15, 1);
 867     return value;
 868 }
 869
 870
 871 uint64 NMD::extract_ac_13_12(uint64 instruction)
 872 {
 873     uint64 value = 0;
 874     value |= extract_bits(instruction, 14, 2);
 875     return value;
 876 }
 877
 878
 879 uint64 NMD::extract_shift_20_19_18_17_16(uint64 instruction)
 880 {
 881     uint64 value = 0;
 882     value |= extract_bits(instruction, 16, 5);
 883     return value;
 884 }
 885
 886
 887 uint64 NMD::extract_rdl_25_24(uint64 instruction)
 888 {
 889     uint64 value = 0;
 890     value |= extract_bits(instruction, 24, 1);
 891     return value;
 892 }
 893
 894
 895 int64 NMD::extr_sil0il10bs1_il1il1bs9Tmsb10(uint64 instruction)
 896 {
 897     int64 value = 0;
 898     value |= extract_bits(instruction, 0, 1) << 10;
 899     value |= extract_bits(instruction, 1, 9) << 1;
 900     value = sign_extend(value, 10);
 901     return value;
 902 }
 903
 904
 905 uint64 NMD::extract_eu_6_5_4_3_2_1_0(uint64 instruction)
 906 {
 907     uint64 value = 0;
 908     value |= extract_bits(instruction, 0, 7);
 909     return value;
 910 }
 911
 912
 913 uint64 NMD::extract_shift_5_4_3_2_1_0(uint64 instruction)
 914 {
 915     uint64 value = 0;
 916     value |= extract_bits(instruction, 0, 6);
 917     return value;
 918 }
 919
 920
 921 uint64 NMD::extr_xil10il0bs6Fmsb5(uint64 instruction)
 922 {
 923     uint64 value = 0;
 924     value |= extract_bits(instruction, 10, 6);
 925     return value;
 926 }
 927
 928
 929 uint64 NMD::extract_count_19_18_17_16(uint64 instruction)
 930 {
 931     uint64 value = 0;
 932     value |= extract_bits(instruction, 16, 4);
 933     return value;
 934 }
 935
 936
 937 uint64 NMD::extract_code_2_1_0(uint64 instruction)
 938 {
 939     uint64 value = 0;
 940     value |= extract_bits(instruction, 0, 3);
 941     return value;
 942 }
 943
 944
 945 uint64 NMD::extr_xil10il0bs4_il22il0bs4Fmsb3(uint64 instruction)
 946 {
 947     uint64 value = 0;
 948     value |= extract_bits(instruction, 10, 4);
 949     value |= extract_bits(instruction, 22, 4);
 950     return value;
 951 }
 952
 953
 954 uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
 955 {
 956     uint64 value = 0;
 957     value |= extract_bits(instruction, 0, 12);
 958     return value;
 959 }
 960
 961
 962 uint64 NMD::extract_rs_4_3_2_1_0(uint64 instruction)
 963 {
 964     uint64 value = 0;
 965     value |= extract_bits(instruction, 0, 5);
 966     return value;
 967 }
 968
 969
 970 uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction)
 971 {
 972     uint64 value = 0;
 973     value |= extract_bits(instruction, 3, 18) << 3;
 974     return value;
 975 }
 976
 977
 978 uint64 NMD::extr_xil12il0bs1Fmsb0(uint64 instruction)
 979 {
 980     uint64 value = 0;
 981     value |= extract_bits(instruction, 12, 1);
 982     return value;
 983 }
 984
 985
 986 uint64 NMD::extr_uil0il2bs4Fmsb5(uint64 instruction)
 987 {
 988     uint64 value = 0;
 989     value |= extract_bits(instruction, 0, 4) << 2;
 990     return value;
 991 }
 992
 993
 994 uint64 NMD::extract_cofun_25_24_23(uint64 instruction)
 995 {
 996     uint64 value = 0;
 997     value |= extract_bits(instruction, 3, 23);
 998     return value;
 999 }
1000
1001
1002 uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction)
1003 {
1004     uint64 value = 0;
1005     value |= extract_bits(instruction, 0, 3) << 2;
1006     return value;
1007 }
1008
1009
1010 uint64 NMD::extr_xil10il0bs1Fmsb0(uint64 instruction)
1011 {
1012     uint64 value = 0;
1013     value |= extract_bits(instruction, 10, 1);
1014     return value;
1015 }
1016
1017
1018 uint64 NMD::extract_rd3_3_2_1(uint64 instruction)
1019 {
1020     uint64 value = 0;
1021     value |= extract_bits(instruction, 1, 3);
1022     return value;
1023 }
1024
1025
1026 uint64 NMD::extract_sa_15_14_13_12(uint64 instruction)
1027 {
1028     uint64 value = 0;
1029     value |= extract_bits(instruction, 12, 4);
1030     return value;
1031 }
1032
1033
1034 uint64 NMD::extract_rt_25_24_23_22_21(uint64 instruction)
1035 {
1036     uint64 value = 0;
1037     value |= extract_bits(instruction, 21, 5);
1038     return value;
1039 }
1040
1041
1042 uint64 NMD::extract_ru_7_6_5_4_3(uint64 instruction)
1043 {
1044     uint64 value = 0;
1045     value |= extract_bits(instruction, 3, 5);
1046     return value;
1047 }
1048
1049
1050 uint64 NMD::extr_xil21il0bs5Fmsb4(uint64 instruction)
1051 {
1052     uint64 value = 0;
1053     value |= extract_bits(instruction, 21, 5);
1054     return value;
1055 }
1056
1057
1058 uint64 NMD::extr_xil9il0bs3Fmsb2(uint64 instruction)
1059 {
1060     uint64 value = 0;
1061     value |= extract_bits(instruction, 9, 3);
1062     return value;
1063 }
1064
1065
1066 uint64 NMD::extract_u_17_to_0(uint64 instruction)
1067 {
1068     uint64 value = 0;
1069     value |= extract_bits(instruction, 0, 18);
1070     return value;
1071 }
1072
1073
1074 uint64 NMD::extr_xil14il0bs1_il15il0bs1Fmsb0(uint64 instruction)
1075 {
1076     uint64 value = 0;
1077     value |= extract_bits(instruction, 14, 1);
1078     value |= extract_bits(instruction, 15, 1);
1079     return value;
1080 }
1081
1082
1083 uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction)
1084 {
1085     uint64 value = 0;
1086     value |= extract_bits(instruction, 0, 3);
1087     value |= extract_bits(instruction, 4, 1) << 3;
1088     return value;
1089 }
1090
1091
1092 uint64 NMD::extr_xil24il0bs1Fmsb0(uint64 instruction)
1093 {
1094     uint64 value = 0;
1095     value |= extract_bits(instruction, 24, 1);
1096     return value;
1097 }
1098
1099
1100 int64 NMD::extr_sil0il21bs1_il1il1bs20Tmsb21(uint64 instruction)
1101 {
1102     int64 value = 0;
1103     value |= extract_bits(instruction, 0, 1) << 21;
1104     value |= extract_bits(instruction, 1, 20) << 1;
1105     value = sign_extend(value, 21);
1106     return value;
1107 }
1108
1109
1110 uint64 NMD::extract_op_25_to_3(uint64 instruction)
1111 {
1112     uint64 value = 0;
1113     value |= extract_bits(instruction, 3, 23);
1114     return value;
1115 }
1116
1117
1118 uint64 NMD::extract_rs4_4_2_1_0(uint64 instruction)
1119 {
1120     uint64 value = 0;
1121     value |= extract_bits(instruction, 0, 3);
1122     value |= extract_bits(instruction, 4, 1) << 3;
1123     return value;
1124 }
1125
1126
1127 uint64 NMD::extract_bit_23_22_21(uint64 instruction)
1128 {
1129     uint64 value = 0;
1130     value |= extract_bits(instruction, 21, 3);
1131     return value;
1132 }
1133
1134
1135 uint64 NMD::extract_rt_41_40_39_38_37(uint64 instruction)
1136 {
1137     uint64 value = 0;
1138     value |= extract_bits(instruction, 37, 5);
1139     return value;
1140 }
1141
1142
1143 int64 NMD::extract_shift_21_20_19_18_17_16(uint64 instruction)
1144 {
1145     int64 value = 0;
1146     value |= extract_bits(instruction, 16, 6);
1147     value = sign_extend(value, 5);
1148     return value;
1149 }
1150
1151
1152 uint64 NMD::extr_xil6il0bs3_il10il0bs1Fmsb2(uint64 instruction)
1153 {
1154     uint64 value = 0;
1155     value |= extract_bits(instruction, 6, 3);
1156     value |= extract_bits(instruction, 10, 1);
1157     return value;
1158 }
1159
1160
1161 uint64 NMD::extract_rd2_3_8(uint64 instruction)
1162 {
1163     uint64 value = 0;
1164     value |= extract_bits(instruction, 3, 1) << 1;
1165     value |= extract_bits(instruction, 8, 1);
1166     return value;
1167 }
1168
1169
1170 uint64 NMD::extr_xil16il0bs5Fmsb4(uint64 instruction)
1171 {
1172     uint64 value = 0;
1173     value |= extract_bits(instruction, 16, 5);
1174     return value;
1175 }
1176
1177
1178 uint64 NMD::extract_code_17_to_0(uint64 instruction)
1179 {
1180     uint64 value = 0;
1181     value |= extract_bits(instruction, 0, 18);
1182     return value;
1183 }
1184
1185
1186 uint64 NMD::extr_xil0il0bs12Fmsb11(uint64 instruction)
1187 {
1188     uint64 value = 0;
1189     value |= extract_bits(instruction, 0, 12);
1190     return value;
1191 }
1192
1193
1194 uint64 NMD::extract_size_20_19_18_17_16(uint64 instruction)
1195 {
1196     uint64 value = 0;
1197     value |= extract_bits(instruction, 16, 5);
1198     return value;
1199 }
1200
1201
1202 int64 NMD::extr_sil2il2bs6_il15il8bs1Tmsb8(uint64 instruction)
1203 {
1204     int64 value = 0;
1205     value |= extract_bits(instruction, 2, 6) << 2;
1206     value |= extract_bits(instruction, 15, 1) << 8;
1207     value = sign_extend(value, 8);
1208     return value;
1209 }
1210
1211
1212 uint64 NMD::extract_u_15_to_0(uint64 instruction)
1213 {
1214     uint64 value = 0;
1215     value |= extract_bits(instruction, 0, 16);
1216     return value;
1217 }
1218
1219
1220 uint64 NMD::extract_fs_15_14_13_12_11(uint64 instruction)
1221 {
1222     uint64 value = 0;
1223     value |= extract_bits(instruction, 16, 5);
1224     return value;
1225 }
1226
1227
1228 int64 NMD::extr_sil0il0bs8_il15il8bs1Tmsb8(uint64 instruction)
1229 {
1230     int64 value = 0;
1231     value |= extract_bits(instruction, 0, 8);
1232     value |= extract_bits(instruction, 15, 1) << 8;
1233     value = sign_extend(value, 8);
1234     return value;
1235 }
1236
1237
1238 uint64 NMD::extract_stype_20_19_18_17_16(uint64 instruction)
1239 {
1240     uint64 value = 0;
1241     value |= extract_bits(instruction, 16, 5);
1242     return value;
1243 }
1244
1245
1246 uint64 NMD::extract_rtl_11(uint64 instruction)
1247 {
1248     uint64 value = 0;
1249     value |= extract_bits(instruction, 9, 1);
1250     return value;
1251 }
1252
1253
1254 uint64 NMD::extract_hs_20_19_18_17_16(uint64 instruction)
1255 {
1256     uint64 value = 0;
1257     value |= extract_bits(instruction, 16, 5);
1258     return value;
1259 }
1260
1261
1262 uint64 NMD::extr_xil10il0bs1_il14il0bs2Fmsb1(uint64 instruction)
1263 {
1264     uint64 value = 0;
1265     value |= extract_bits(instruction, 10, 1);
1266     value |= extract_bits(instruction, 14, 2);
1267     return value;
1268 }
1269
1270
1271 uint64 NMD::extract_sel_13_12_11(uint64 instruction)
1272 {
1273     uint64 value = 0;
1274     value |= extract_bits(instruction, 11, 3);
1275     return value;
1276 }
1277
1278
1279 uint64 NMD::extract_lsb_4_3_2_1_0(uint64 instruction)
1280 {
1281     uint64 value = 0;
1282     value |= extract_bits(instruction, 0, 5);
1283     return value;
1284 }
1285
1286
1287 uint64 NMD::extr_xil14il0bs2Fmsb1(uint64 instruction)
1288 {
1289     uint64 value = 0;
1290     value |= extract_bits(instruction, 14, 2);
1291     return value;
1292 }
1293
1294
1295 uint64 NMD::extract_gp_2(uint64 instruction)
1296 {
1297     uint64 value = 0;
1298     value |= extract_bits(instruction, 2, 1);
1299     return value;
1300 }
1301
1302
1303 uint64 NMD::extract_rt3_9_8_7(uint64 instruction)
1304 {
1305     uint64 value = 0;
1306     value |= extract_bits(instruction, 7, 3);
1307     return value;
1308 }
1309
1310
1311 uint64 NMD::extract_ft_20_19_18_17_16(uint64 instruction)
1312 {
1313     uint64 value = 0;
1314     value |= extract_bits(instruction, 21, 5);
1315     return value;
1316 }
1317
1318
1319 uint64 NMD::extract_u_17_16_15_14_13_12_11(uint64 instruction)
1320 {
1321     uint64 value = 0;
1322     value |= extract_bits(instruction, 11, 7);
1323     return value;
1324 }
1325
1326
1327 uint64 NMD::extract_cs_20_19_18_17_16(uint64 instruction)
1328 {
1329     uint64 value = 0;
1330     value |= extract_bits(instruction, 16, 5);
1331     return value;
1332 }
1333
1334
1335 uint64 NMD::extr_xil16il0bs10Fmsb9(uint64 instruction)
1336 {
1337     uint64 value = 0;
1338     value |= extract_bits(instruction, 16, 10);
1339     return value;
1340 }
1341
1342
1343 uint64 NMD::extract_rt4_9_7_6_5(uint64 instruction)
1344 {
1345     uint64 value = 0;
1346     value |= extract_bits(instruction, 5, 3);
1347     value |= extract_bits(instruction, 9, 1) << 3;
1348     return value;
1349 }
1350
1351
1352 uint64 NMD::extract_msbt_10_9_8_7_6(uint64 instruction)
1353 {
1354     uint64 value = 0;
1355     value |= extract_bits(instruction, 6, 5);
1356     return value;
1357 }
1358
1359
1360 uint64 NMD::extr_uil0il2bs6Fmsb7(uint64 instruction)
1361 {
1362     uint64 value = 0;
1363     value |= extract_bits(instruction, 0, 6) << 2;
1364     return value;
1365 }
1366
1367
1368 uint64 NMD::extr_xil17il0bs9Fmsb8(uint64 instruction)
1369 {
1370     uint64 value = 0;
1371     value |= extract_bits(instruction, 17, 9);
1372     return value;
1373 }
1374
1375
1376 uint64 NMD::extract_sa_15_14_13(uint64 instruction)
1377 {
1378     uint64 value = 0;
1379     value |= extract_bits(instruction, 13, 3);
1380     return value;
1381 }
1382
1383
1384 int64 NMD::extr_sil0il14bs1_il1il1bs13Tmsb14(uint64 instruction)
1385 {
1386     int64 value = 0;
1387     value |= extract_bits(instruction, 0, 1) << 14;
1388     value |= extract_bits(instruction, 1, 13) << 1;
1389     value = sign_extend(value, 14);
1390     return value;
1391 }
1392
1393
1394 uint64 NMD::extract_rs3_6_5_4(uint64 instruction)
1395 {
1396     uint64 value = 0;
1397     value |= extract_bits(instruction, 4, 3);
1398     return value;
1399 }
1400
1401
1402 uint64 NMD::extr_uil0il32bs32Fmsb63(uint64 instruction)
1403 {
1404     uint64 value = 0;
1405     value |= extract_bits(instruction, 0, 32) << 32;
1406     return value;
1407 }
1408
1409
1410 uint64 NMD::extract_shift_10_9_8_7_6(uint64 instruction)
1411 {
1412     uint64 value = 0;
1413     value |= extract_bits(instruction, 6, 5);
1414     return value;
1415 }
1416
1417
1418 uint64 NMD::extract_cs_25_24_23_22_21(uint64 instruction)
1419 {
1420     uint64 value = 0;
1421     value |= extract_bits(instruction, 21, 5);
1422     return value;
1423 }
1424
1425
1426 uint64 NMD::extract_shiftx_11_10_9_8_7_6(uint64 instruction)
1427 {
1428     uint64 value = 0;
1429     value |= extract_bits(instruction, 6, 6);
1430     return value;
1431 }
1432
1433
1434 uint64 NMD::extract_rt_9_8_7_6_5(uint64 instruction)
1435 {
1436     uint64 value = 0;
1437     value |= extract_bits(instruction, 5, 5);
1438     return value;
1439 }
1440
1441
1442 uint64 NMD::extract_op_25_24_23_22_21(uint64 instruction)
1443 {
1444     uint64 value = 0;
1445     value |= extract_bits(instruction, 21, 5);
1446     return value;
1447 }
1448
1449
1450 uint64 NMD::extr_uil0il2bs7Fmsb8(uint64 instruction)
1451 {
1452     uint64 value = 0;
1453     value |= extract_bits(instruction, 0, 7) << 2;
1454     return value;
1455 }
1456
1457
1458 uint64 NMD::extract_bit_16_15_14_13_12_11(uint64 instruction)
1459 {
1460     uint64 value = 0;
1461     value |= extract_bits(instruction, 11, 6);
1462     return value;
1463 }
1464
1465
1466 uint64 NMD::extr_xil10il0bs1_il11il0bs5Fmsb4(uint64 instruction)
1467 {
1468     uint64 value = 0;
1469     value |= extract_bits(instruction, 10, 1);
1470     value |= extract_bits(instruction, 11, 5);
1471     return value;
1472 }
1473
1474
1475 uint64 NMD::extract_mask_20_19_18_17_16_15_14(uint64 instruction)
1476 {
1477     uint64 value = 0;
1478     value |= extract_bits(instruction, 14, 7);
1479     return value;
1480 }
1481
1482
1483 uint64 NMD::extract_eu_3_2_1_0(uint64 instruction)
1484 {
1485     uint64 value = 0;
1486     value |= extract_bits(instruction, 0, 4);
1487     return value;
1488 }
1489
1490
1491 uint64 NMD::extr_uil4il4bs4Fmsb7(uint64 instruction)
1492 {
1493     uint64 value = 0;
1494     value |= extract_bits(instruction, 4, 4) << 4;
1495     return value;
1496 }
1497
1498
1499 int64 NMD::extr_sil3il3bs5_il15il8bs1Tmsb8(uint64 instruction)
1500 {
1501     int64 value = 0;
1502     value |= extract_bits(instruction, 3, 5) << 3;
1503     value |= extract_bits(instruction, 15, 1) << 8;
1504     value = sign_extend(value, 8);
1505     return value;
1506 }
1507
1508
1509 uint64 NMD::extract_ft_15_14_13_12_11(uint64 instruction)
1510 {
1511     uint64 value = 0;
1512     value |= extract_bits(instruction, 11, 5);
1513     return value;
1514 }
1515
1516
1517 int64 NMD::extr_sil0il16bs16_il16il0bs16Tmsb31(uint64 instruction)
1518 {
1519     int64 value = 0;
1520     value |= extract_bits(instruction, 0, 16) << 16;
1521     value |= extract_bits(instruction, 16, 16);
1522     value = sign_extend(value, 31);
1523     return value;
1524 }
1525
1526
1527 uint64 NMD::extract_u_20_19_18_17_16_15_14_13(uint64 instruction)
1528 {
1529     uint64 value = 0;
1530     value |= extract_bits(instruction, 13, 8);
1531     return value;
1532 }
1533
1534
1535 uint64 NMD::extr_xil15il0bs1Fmsb0(uint64 instruction)
1536 {
1537     uint64 value = 0;
1538     value |= extract_bits(instruction, 15, 1);
1539     return value;
1540 }
1541
1542
1543 uint64 NMD::extr_xil11il0bs5Fmsb4(uint64 instruction)
1544 {
1545     uint64 value = 0;
1546     value |= extract_bits(instruction, 11, 5);
1547     return value;
1548 }
1549
1550
1551 uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction)
1552 {
1553     uint64 value = 0;
1554     value |= extract_bits(instruction, 2, 16) << 2;
1555     return value;
1556 }
1557
1558
1559 uint64 NMD::extract_rd_20_19_18_17_16(uint64 instruction)
1560 {
1561     uint64 value = 0;
1562     value |= extract_bits(instruction, 11, 5);
1563     return value;
1564 }
1565
1566
1567 uint64 NMD::extract_c0s_20_19_18_17_16(uint64 instruction)
1568 {
1569     uint64 value = 0;
1570     value |= extract_bits(instruction, 16, 5);
1571     return value;
1572 }
1573
1574
1575 uint64 NMD::extract_code_1_0(uint64 instruction)
1576 {
1577     uint64 value = 0;
1578     value |= extract_bits(instruction, 0, 2);
1579     return value;
1580 }
1581
1582
1583 int64 NMD::extr_sil0il25bs1_il1il1bs24Tmsb25(uint64 instruction)
1584 {
1585     int64 value = 0;
1586     value |= extract_bits(instruction, 0, 1) << 25;
1587     value |= extract_bits(instruction, 1, 24) << 1;
1588     value = sign_extend(value, 25);
1589     return value;
1590 }
1591
1592
1593 uint64 NMD::extr_xil0il0bs3_il4il0bs1Fmsb2(uint64 instruction)
1594 {
1595     uint64 value = 0;
1596     value |= extract_bits(instruction, 0, 3);
1597     value |= extract_bits(instruction, 4, 1);
1598     return value;
1599 }
1600
1601
1602 uint64 NMD::extract_u_1_0(uint64 instruction)
1603 {
1604     uint64 value = 0;
1605     value |= extract_bits(instruction, 0, 2);
1606     return value;
1607 }
1608
1609
1610 uint64 NMD::extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction)
1611 {
1612     uint64 value = 0;
1613     value |= extract_bits(instruction, 3, 1) << 3;
1614     value |= extract_bits(instruction, 8, 1) << 2;
1615     return value;
1616 }
1617
1618
1619 uint64 NMD::extr_xil9il0bs3_il16il0bs5Fmsb4(uint64 instruction)
1620 {
1621     uint64 value = 0;
1622     value |= extract_bits(instruction, 9, 3);
1623     value |= extract_bits(instruction, 16, 5);
1624     return value;
1625 }
1626
1627
1628 uint64 NMD::extract_fd_10_9_8_7_6(uint64 instruction)
1629 {
1630     uint64 value = 0;
1631     value |= extract_bits(instruction, 11, 5);
1632     return value;
1633 }
1634
1635
1636 uint64 NMD::extr_xil6il0bs3Fmsb2(uint64 instruction)
1637 {
1638     uint64 value = 0;
1639     value |= extract_bits(instruction, 6, 3);
1640     return value;
1641 }
1642
1643
1644 uint64 NMD::extr_uil0il2bs5Fmsb6(uint64 instruction)
1645 {
1646     uint64 value = 0;
1647     value |= extract_bits(instruction, 0, 5) << 2;
1648     return value;
1649 }
1650
1651
1652 uint64 NMD::extract_rtz4_9_7_6_5(uint64 instruction)
1653 {
1654     uint64 value = 0;
1655     value |= extract_bits(instruction, 5, 3);
1656     value |= extract_bits(instruction, 9, 1) << 3;
1657     return value;
1658 }
1659
1660
1661 uint64 NMD::extract_sel_15_14_13_12_11(uint64 instruction)
1662 {
1663     uint64 value = 0;
1664     value |= extract_bits(instruction, 11, 5);
1665     return value;
1666 }
1667
1668
1669 uint64 NMD::extract_ct_25_24_23_22_21(uint64 instruction)
1670 {
1671     uint64 value = 0;
1672     value |= extract_bits(instruction, 21, 5);
1673     return value;
1674 }
1675
1676
1677 uint64 NMD::extr_xil11il0bs1Fmsb0(uint64 instruction)
1678 {
1679     uint64 value = 0;
1680     value |= extract_bits(instruction, 11, 1);
1681     return value;
1682 }
1683
1684
1685 uint64 NMD::extr_uil2il2bs19Fmsb20(uint64 instruction)
1686 {
1687     uint64 value = 0;
1688     value |= extract_bits(instruction, 2, 19) << 2;
1689     return value;
1690 }
1691
1692
1693 int64 NMD::extract_s_4_2_1_0(uint64 instruction)
1694 {
1695     int64 value = 0;
1696     value |= extract_bits(instruction, 0, 3);
1697     value |= extract_bits(instruction, 4, 1) << 3;
1698     value = sign_extend(value, 3);
1699     return value;
1700 }
1701
1702
1703 uint64 NMD::extr_uil0il1bs4Fmsb4(uint64 instruction)
1704 {
1705     uint64 value = 0;
1706     value |= extract_bits(instruction, 0, 4) << 1;
1707     return value;
1708 }
1709
1710
1711 uint64 NMD::extr_xil9il0bs2Fmsb1(uint64 instruction)
1712 {
1713     uint64 value = 0;
1714     value |= extract_bits(instruction, 9, 2);
1715     return value;
1716 }
1717
1718
1719
1720 bool NMD::ADDIU_32__cond(uint64 instruction)
1721 {
1722     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1723     return rt != 0;
1724 }
1725
1726
1727 bool NMD::ADDIU_RS5__cond(uint64 instruction)
1728 {
1729     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1730     return rt != 0;
1731 }
1732
1733
1734 bool NMD::BALRSC_cond(uint64 instruction)
1735 {
1736     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1737     return rt != 0;
1738 }
1739
1740
1741 bool NMD::BEQC_16__cond(uint64 instruction)
1742 {
1743     uint64 rs3 = extract_rs3_6_5_4(instruction);
1744     uint64 rt3 = extract_rt3_9_8_7(instruction);
1745     uint64 u = extr_uil0il1bs4Fmsb4(instruction);
1746     return rs3 < rt3 && u != 0;
1747 }
1748
1749
1750 bool NMD::BNEC_16__cond(uint64 instruction)
1751 {
1752     uint64 rs3 = extract_rs3_6_5_4(instruction);
1753     uint64 rt3 = extract_rt3_9_8_7(instruction);
1754     uint64 u = extr_uil0il1bs4Fmsb4(instruction);
1755     return rs3 >= rt3 && u != 0;
1756 }
1757
1758
1759 bool NMD::MOVE_cond(uint64 instruction)
1760 {
1761     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1762     return rt != 0;
1763 }
1764
1765
1766 bool NMD::P16_BR1_cond(uint64 instruction)
1767 {
1768     uint64 u = extr_uil0il1bs4Fmsb4(instruction);
1769     return u != 0;
1770 }
1771
1772
1773 bool NMD::PREF_S9__cond(uint64 instruction)
1774 {
1775     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1776     return hint != 31;
1777 }
1778
1779
1780 bool NMD::PREFE_cond(uint64 instruction)
1781 {
1782     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1783     return hint != 31;
1784 }
1785
1786
1787 bool NMD::SLTU_cond(uint64 instruction)
1788 {
1789     uint64 rd = extract_rd_20_19_18_17_16(instruction);
1790     return rd != 0;
1791 }
1792
1793
1794
1795 /*
1796  * ABS.D fd, fs - Floating Point Absolute Value
1797  *
1798  *   3         2         1
1799  *  10987654321098765432109876543210
1800  *  010001     00000          000101
1801  *    fmt -----
1802  *               fs -----
1803  *                    fd -----
1804  */
1805 std::string NMD::ABS_D(uint64 instruction)
1806 {
1807     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
1808     uint64 fd_value = extract_ft_20_19_18_17_16(instruction);
1809
1810     std::string fs = FPR(copy(fs_value));
1811     std::string fd = FPR(copy(fd_value));
1812
1813     return img::format("ABS.D %s, %s", fd, fs);
1814 }
1815
1816
1817 /*
1818  * ABS.S fd, fs - Floating Point Absolute Value
1819  *
1820  *   3         2         1
1821  *  10987654321098765432109876543210
1822  *  010001     00000          000101
1823  *    fmt -----
1824  *               fd -----
1825  *                    fs -----
1826  */
1827 std::string NMD::ABS_S(uint64 instruction)
1828 {
1829     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
1830     uint64 fd_value = extract_ft_20_19_18_17_16(instruction);
1831
1832     std::string fs = FPR(copy(fs_value));
1833     std::string fd = FPR(copy(fd_value));
1834
1835     return img::format("ABS.S %s, %s", fd, fs);
1836 }
1837
1838
1839 /*
1840  * ABSQ_S.PH rt, rs - Find Absolute Value of Two Fractional Halfwords
1841  *
1842  *   3         2         1
1843  *  10987654321098765432109876543210
1844  *  001000          0001000100111111
1845  *     rt -----
1846  *          rs -----
1847  */
1848 std::string NMD::ABSQ_S_PH(uint64 instruction)
1849 {
1850     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1851     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1852
1853     std::string rt = GPR(copy(rt_value));
1854     std::string rs = GPR(copy(rs_value));
1855
1856     return img::format("ABSQ_S.PH %s, %s", rt, rs);
1857 }
1858
1859
1860 /*
1861  * ABSQ_S.QB rt, rs - Find Absolute Value of Four Fractional Byte Values
1862  *
1863  *   3         2         1
1864  *  10987654321098765432109876543210
1865  *  001000          0000000100111111
1866  *     rt -----
1867  *          rs -----
1868  */
1869 std::string NMD::ABSQ_S_QB(uint64 instruction)
1870 {
1871     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1872     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1873
1874     std::string rt = GPR(copy(rt_value));
1875     std::string rs = GPR(copy(rs_value));
1876
1877     return img::format("ABSQ_S.QB %s, %s", rt, rs);
1878 }
1879
1880
1881 /*
1882  *
1883  *
1884  *   3         2         1
1885  *  10987654321098765432109876543210
1886  *  001000          0010000100111111
1887  *     rt -----
1888  *          rs -----
1889  */
1890 std::string NMD::ABSQ_S_W(uint64 instruction)
1891 {
1892     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1893     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1894
1895     std::string rt = GPR(copy(rt_value));
1896     std::string rs = GPR(copy(rs_value));
1897
1898     return img::format("ABSQ_S.W %s, %s", rt, rs);
1899 }
1900
1901
1902 /*
1903  *
1904  *
1905  *   3         2         1
1906  *  10987654321098765432109876543210
1907  *  001000          0010000100111111
1908  *     rt -----
1909  *          rs -----
1910  */
1911 std::string NMD::ACLR(uint64 instruction)
1912 {
1913     uint64 bit_value = extract_bit_23_22_21(instruction);
1914     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
1915     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1916
1917     std::string bit = IMMEDIATE(copy(bit_value));
1918     std::string s = IMMEDIATE(copy(s_value));
1919     std::string rs = GPR(copy(rs_value));
1920
1921     return img::format("ACLR %s, %s(%s)", bit, s, rs);
1922 }
1923
1924
1925 /*
1926  *
1927  *
1928  *   3         2         1
1929  *  10987654321098765432109876543210
1930  *  001000          0010000100111111
1931  *     rt -----
1932  *          rs -----
1933  */
1934 std::string NMD::ADD(uint64 instruction)
1935 {
1936     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1937     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
1938     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1939
1940     std::string rd = GPR(copy(rd_value));
1941     std::string rs = GPR(copy(rs_value));
1942     std::string rt = GPR(copy(rt_value));
1943
1944     return img::format("ADD %s, %s, %s", rd, rs, rt);
1945 }
1946
1947
1948 /*
1949  * ADD.D fd, fs, ft - Floating Point Add
1950  *
1951  *   3         2         1
1952  *  10987654321098765432109876543210
1953  *  010001                    000101
1954  *    fmt -----
1955  *          ft -----
1956  *               fs -----
1957  *                    fd -----
1958  */
1959 std::string NMD::ADD_D(uint64 instruction)
1960 {
1961     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
1962     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
1963     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
1964
1965     std::string ft = FPR(copy(ft_value));
1966     std::string fs = FPR(copy(fs_value));
1967     std::string fd = FPR(copy(fd_value));
1968
1969     return img::format("ADD.D %s, %s, %s", fd, fs, ft);
1970 }
1971
1972
1973 /*
1974  * ADD.S fd, fs, ft - Floating Point Add
1975  *
1976  *   3         2         1
1977  *  10987654321098765432109876543210
1978  *  010001                    000101
1979  *    fmt -----
1980  *          ft -----
1981  *               fs -----
1982  *                    fd -----
1983  */
1984 std::string NMD::ADD_S(uint64 instruction)
1985 {
1986     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
1987     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
1988     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
1989
1990     std::string ft = FPR(copy(ft_value));
1991     std::string fs = FPR(copy(fs_value));
1992     std::string fd = FPR(copy(fd_value));
1993
1994     return img::format("ADD.S %s, %s, %s", fd, fs, ft);
1995 }
1996
1997
1998 /*
1999  *
2000  *
2001  *   3         2         1
2002  *  10987654321098765432109876543210
2003  *  001000          0010000100111111
2004  *     rt -----
2005  *          rs -----
2006  */
2007 std::string NMD::ADDIU_32_(uint64 instruction)
2008 {
2009     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2010     uint64 u_value = extract_u_15_to_0(instruction);
2011     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2012
2013     std::string rt = GPR(copy(rt_value));
2014     std::string rs = GPR(copy(rs_value));
2015     std::string u = IMMEDIATE(copy(u_value));
2016
2017     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2018 }
2019
2020
2021 /*
2022  *
2023  *
2024  *   3         2         1
2025  *  10987654321098765432109876543210
2026  *  001000          0010000100111111
2027  *     rt -----
2028  *          rs -----
2029  */
2030 std::string NMD::ADDIU_48_(uint64 instruction)
2031 {
2032     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2033     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
2034
2035     std::string rt = GPR(copy(rt_value));
2036     std::string s = IMMEDIATE(copy(s_value));
2037
2038     return img::format("ADDIU %s, %s", rt, s);
2039 }
2040
2041
2042 /*
2043  *
2044  *
2045  *   3         2         1
2046  *  10987654321098765432109876543210
2047  *  001000          0010000100111111
2048  *     rt -----
2049  *          rs -----
2050  */
2051 std::string NMD::ADDIU_GP48_(uint64 instruction)
2052 {
2053     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2054     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
2055
2056     std::string rt = GPR(copy(rt_value));
2057     std::string s = IMMEDIATE(copy(s_value));
2058
2059     return img::format("ADDIU %s, $%d, %s", rt, 28, s);
2060 }
2061
2062
2063 /*
2064  *
2065  *
2066  *   3         2         1
2067  *  10987654321098765432109876543210
2068  *  001000          0010000100111111
2069  *     rt -----
2070  *          rs -----
2071  */
2072 std::string NMD::ADDIU_GP_B_(uint64 instruction)
2073 {
2074     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2075     uint64 u_value = extract_u_17_to_0(instruction);
2076
2077     std::string rt = GPR(copy(rt_value));
2078     std::string u = IMMEDIATE(copy(u_value));
2079
2080     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2081 }
2082
2083
2084 /*
2085  *
2086  *
2087  *   3         2         1
2088  *  10987654321098765432109876543210
2089  *  001000          0010000100111111
2090  *     rt -----
2091  *          rs -----
2092  */
2093 std::string NMD::ADDIU_GP_W_(uint64 instruction)
2094 {
2095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2096     uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);
2097
2098     std::string rt = GPR(copy(rt_value));
2099     std::string u = IMMEDIATE(copy(u_value));
2100
2101     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2102 }
2103
2104
2105 /*
2106  *
2107  *
2108  *   3         2         1
2109  *  10987654321098765432109876543210
2110  *  001000          0010000100111111
2111  *     rt -----
2112  *          rs -----
2113  */
2114 std::string NMD::ADDIU_NEG_(uint64 instruction)
2115 {
2116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2117     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2118     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2119
2120     std::string rt = GPR(copy(rt_value));
2121     std::string rs = GPR(copy(rs_value));
2122     std::string u = IMMEDIATE(neg_copy(u_value));
2123
2124     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2125 }
2126
2127
2128 /*
2129  *
2130  *
2131  *   3         2         1
2132  *  10987654321098765432109876543210
2133  *  001000          0010000100111111
2134  *     rt -----
2135  *          rs -----
2136  */
2137 std::string NMD::ADDIU_R1_SP_(uint64 instruction)
2138 {
2139     uint64 u_value = extr_uil0il2bs6Fmsb7(instruction);
2140     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2141
2142     std::string rt3 = GPR(encode_gpr3(rt3_value));
2143     std::string u = IMMEDIATE(copy(u_value));
2144
2145     return img::format("ADDIU %s, $%d, %s", rt3, 29, u);
2146 }
2147
2148
2149 /*
2150  *
2151  *
2152  *   3         2         1
2153  *  10987654321098765432109876543210
2154  *  001000          0010000100111111
2155  *     rt -----
2156  *          rs -----
2157  */
2158 std::string NMD::ADDIU_R2_(uint64 instruction)
2159 {
2160     uint64 u_value = extr_uil0il2bs3Fmsb4(instruction);
2161     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2162     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2163
2164     std::string rt3 = GPR(encode_gpr3(rt3_value));
2165     std::string rs3 = GPR(encode_gpr3(rs3_value));
2166     std::string u = IMMEDIATE(copy(u_value));
2167
2168     return img::format("ADDIU %s, %s, %s", rt3, rs3, u);
2169 }
2170
2171
2172 /*
2173  * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
2174  *
2175  *  5432109876543210
2176  *  100100      1
2177  *     rt -----
2178  *           s - ---
2179  */
2180 std::string NMD::ADDIU_RS5_(uint64 instruction)
2181 {
2182     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
2183     int64 s_value = extract_s_4_2_1_0(instruction);
2184
2185     std::string rt = GPR(copy(rt_value));
2186     std::string s = IMMEDIATE(copy(s_value));
2187
2188     return img::format("ADDIU %s, %s", rt, s);
2189 }
2190
2191
2192 /*
2193  *
2194  *
2195  *   3         2         1
2196  *  10987654321098765432109876543210
2197  *  001000               x1110000101
2198  *     rt -----
2199  *          rs -----
2200  *               rd -----
2201  */
2202 std::string NMD::ADDIUPC_32_(uint64 instruction)
2203 {
2204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2205     int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction);
2206
2207     std::string rt = GPR(copy(rt_value));
2208     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2209
2210     return img::format("ADDIUPC %s, %s", rt, s);
2211 }
2212
2213
2214 /*
2215  *
2216  *
2217  *   3         2         1
2218  *  10987654321098765432109876543210
2219  *  001000               x1110000101
2220  *     rt -----
2221  *          rs -----
2222  *               rd -----
2223  */
2224 std::string NMD::ADDIUPC_48_(uint64 instruction)
2225 {
2226     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2227     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
2228
2229     std::string rt = GPR(copy(rt_value));
2230     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
2231
2232     return img::format("ADDIUPC %s, %s", rt, s);
2233 }
2234
2235
2236 /*
2237  * ADDQ.PH rd, rt, rs - Add Fractional Halfword Vectors
2238  *
2239  *   3         2         1
2240  *  10987654321098765432109876543210
2241  *  001000               00000001101
2242  *     rt -----
2243  *          rs -----
2244  *               rd -----
2245  */
2246 std::string NMD::ADDQ_PH(uint64 instruction)
2247 {
2248     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2249     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2250     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2251
2252     std::string rd = GPR(copy(rd_value));
2253     std::string rs = GPR(copy(rs_value));
2254     std::string rt = GPR(copy(rt_value));
2255
2256     return img::format("ADDQ.PH %s, %s, %s", rd, rs, rt);
2257 }
2258
2259
2260 /*
2261  * ADDQ_S.PH rd, rt, rs - Add Fractional Halfword Vectors
2262  *
2263  *   3         2         1
2264  *  10987654321098765432109876543210
2265  *  001000               10000001101
2266  *     rt -----
2267  *          rs -----
2268  *               rd -----
2269  */
2270 std::string NMD::ADDQ_S_PH(uint64 instruction)
2271 {
2272     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2273     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2274     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2275
2276     std::string rd = GPR(copy(rd_value));
2277     std::string rs = GPR(copy(rs_value));
2278     std::string rt = GPR(copy(rt_value));
2279
2280     return img::format("ADDQ_S.PH %s, %s, %s", rd, rs, rt);
2281 }
2282
2283
2284 /*
2285  * ADDQ_S.W rd, rt, rs - Add Fractional Words
2286  *
2287  *   3         2         1
2288  *  10987654321098765432109876543210
2289  *  001000               x1100000101
2290  *     rt -----
2291  *          rs -----
2292  *               rd -----
2293  */
2294 std::string NMD::ADDQ_S_W(uint64 instruction)
2295 {
2296     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2297     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2298     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2299
2300     std::string rd = GPR(copy(rd_value));
2301     std::string rs = GPR(copy(rs_value));
2302     std::string rt = GPR(copy(rt_value));
2303
2304     return img::format("ADDQ_S.W %s, %s, %s", rd, rs, rt);
2305 }
2306
2307
2308 /*
2309  * ADDQH.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
2310  *                       to Halve Results
2311  *
2312  *   3         2         1
2313  *  10987654321098765432109876543210
2314  *  001000               00001001101
2315  *     rt -----
2316  *          rs -----
2317  *               rd -----
2318  */
2319 std::string NMD::ADDQH_PH(uint64 instruction)
2320 {
2321     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2322     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2323     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2324
2325     std::string rd = GPR(copy(rd_value));
2326     std::string rs = GPR(copy(rs_value));
2327     std::string rt = GPR(copy(rt_value));
2328
2329     return img::format("ADDQH.PH %s, %s, %s", rd, rs, rt);
2330 }
2331
2332
2333 /*
2334  * ADDQH_R.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
2335  *                         to Halve Results
2336  *
2337  *   3         2         1
2338  *  10987654321098765432109876543210
2339  *  001000               10001001101
2340  *     rt -----
2341  *          rs -----
2342  *               rd -----
2343  */
2344 std::string NMD::ADDQH_R_PH(uint64 instruction)
2345 {
2346     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2347     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2348     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2349
2350     std::string rd = GPR(copy(rd_value));
2351     std::string rs = GPR(copy(rs_value));
2352     std::string rt = GPR(copy(rt_value));
2353
2354     return img::format("ADDQH_R.PH %s, %s, %s", rd, rs, rt);
2355 }
2356
2357
2358 /*
2359  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
2360  *
2361  *   3         2         1
2362  *  10987654321098765432109876543210
2363  *  001000               00010001101
2364  *     rt -----
2365  *          rs -----
2366  *               rd -----
2367  */
2368 std::string NMD::ADDQH_R_W(uint64 instruction)
2369 {
2370     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2371     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2372     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2373
2374     std::string rd = GPR(copy(rd_value));
2375     std::string rs = GPR(copy(rs_value));
2376     std::string rt = GPR(copy(rt_value));
2377
2378     return img::format("ADDQH_R.W %s, %s, %s", rd, rs, rt);
2379 }
2380
2381
2382 /*
2383  * ADDQH.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
2384  *
2385  *   3         2         1
2386  *  10987654321098765432109876543210
2387  *  001000               10010001101
2388  *     rt -----
2389  *          rs -----
2390  *               rd -----
2391  */
2392 std::string NMD::ADDQH_W(uint64 instruction)
2393 {
2394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2395     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2396     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2397
2398     std::string rd = GPR(copy(rd_value));
2399     std::string rs = GPR(copy(rs_value));
2400     std::string rt = GPR(copy(rt_value));
2401
2402     return img::format("ADDQH.W %s, %s, %s", rd, rs, rt);
2403 }
2404
2405
2406 /*
2407  * ADDSC rd, rt, rs - Add Signed Word and Set Carry Bit
2408  *
2409  *   3         2         1
2410  *  10987654321098765432109876543210
2411  *  001000               x1110000101
2412  *     rt -----
2413  *          rs -----
2414  *               rd -----
2415  */
2416 std::string NMD::ADDSC(uint64 instruction)
2417 {
2418     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2419     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2420     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2421
2422     std::string rd = GPR(copy(rd_value));
2423     std::string rs = GPR(copy(rs_value));
2424     std::string rt = GPR(copy(rt_value));
2425
2426     return img::format("ADDSC %s, %s, %s", rd, rs, rt);
2427 }
2428
2429
2430 /*
2431  * ADDU[16] rd3, rs3, rt3 -
2432  *
2433  *  5432109876543210
2434  *  101100         0
2435  *    rt3 ---
2436  *       rs3 ---
2437  *          rd3 ---
2438  */
2439 std::string NMD::ADDU_16_(uint64 instruction)
2440 {
2441     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2442     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2443     uint64 rd3_value = extract_rd3_3_2_1(instruction);
2444
2445     std::string rt3 = GPR(encode_gpr3(rt3_value));
2446     std::string rs3 = GPR(encode_gpr3(rs3_value));
2447     std::string rd3 = GPR(encode_gpr3(rd3_value));
2448
2449     return img::format("ADDU %s, %s, %s", rd3, rs3, rt3);
2450 }
2451
2452
2453 /*
2454  *
2455  *
2456  *   3         2         1
2457  *  10987654321098765432109876543210
2458  *  001000               x1110000101
2459  *     rt -----
2460  *          rs -----
2461  *               rd -----
2462  */
2463 std::string NMD::ADDU_32_(uint64 instruction)
2464 {
2465     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2466     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2467     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2468
2469     std::string rd = GPR(copy(rd_value));
2470     std::string rs = GPR(copy(rs_value));
2471     std::string rt = GPR(copy(rt_value));
2472
2473     return img::format("ADDU %s, %s, %s", rd, rs, rt);
2474 }
2475
2476
2477 /*
2478  *
2479  *
2480  *   3         2         1
2481  *  10987654321098765432109876543210
2482  *  001000               x1110000101
2483  *     rt -----
2484  *          rs -----
2485  *               rd -----
2486  */
2487 std::string NMD::ADDU_4X4_(uint64 instruction)
2488 {
2489     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
2490     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
2491
2492     std::string rs4 = GPR(encode_gpr4(rs4_value));
2493     std::string rt4 = GPR(encode_gpr4(rt4_value));
2494
2495     return img::format("ADDU %s, %s", rs4, rt4);
2496 }
2497
2498
2499 /*
2500  * ADDU.PH rd, rt, rs - Unsigned Add Integer Halfwords
2501  *
2502  *   3         2         1
2503  *  10987654321098765432109876543210
2504  *  001000               00100001101
2505  *     rt -----
2506  *          rs -----
2507  *               rd -----
2508  */
2509 std::string NMD::ADDU_PH(uint64 instruction)
2510 {
2511     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2512     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2513     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2514
2515     std::string rd = GPR(copy(rd_value));
2516     std::string rs = GPR(copy(rs_value));
2517     std::string rt = GPR(copy(rt_value));
2518
2519     return img::format("ADDU.PH %s, %s, %s", rd, rs, rt);
2520 }
2521
2522
2523 /*
2524  * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2525  *
2526  *   3         2         1
2527  *  10987654321098765432109876543210
2528  *  001000               00011001101
2529  *     rt -----
2530  *          rs -----
2531  *               rd -----
2532  */
2533 std::string NMD::ADDU_QB(uint64 instruction)
2534 {
2535     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2536     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2537     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2538
2539     std::string rd = GPR(copy(rd_value));
2540     std::string rs = GPR(copy(rs_value));
2541     std::string rt = GPR(copy(rt_value));
2542
2543     return img::format("ADDU.QB %s, %s, %s", rd, rs, rt);
2544 }
2545
2546
2547 /*
2548  * ADDU_S.PH rd, rt, rs - Unsigned Add Integer Halfwords
2549  *
2550  *   3         2         1
2551  *  10987654321098765432109876543210
2552  *  001000               10100001101
2553  *     rt -----
2554  *          rs -----
2555  *               rd -----
2556  */
2557 std::string NMD::ADDU_S_PH(uint64 instruction)
2558 {
2559     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2560     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2561     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2562
2563     std::string rd = GPR(copy(rd_value));
2564     std::string rs = GPR(copy(rs_value));
2565     std::string rt = GPR(copy(rt_value));
2566
2567     return img::format("ADDU_S.PH %s, %s, %s", rd, rs, rt);
2568 }
2569
2570
2571 /*
2572  * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2573  *
2574  *   3         2         1
2575  *  10987654321098765432109876543210
2576  *  001000               10011001101
2577  *     rt -----
2578  *          rs -----
2579  *               rd -----
2580  */
2581 std::string NMD::ADDU_S_QB(uint64 instruction)
2582 {
2583     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2584     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2585     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2586
2587     std::string rd = GPR(copy(rd_value));
2588     std::string rs = GPR(copy(rs_value));
2589     std::string rt = GPR(copy(rt_value));
2590
2591     return img::format("ADDU_S.QB %s, %s, %s", rd, rs, rt);
2592 }
2593
2594
2595 /*
2596  * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2597  *                       to Halve Results
2598  *
2599  *   3         2         1
2600  *  10987654321098765432109876543210
2601  *  001000               00101001101
2602  *     rt -----
2603  *          rs -----
2604  *               rd -----
2605  */
2606 std::string NMD::ADDUH_QB(uint64 instruction)
2607 {
2608     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2609     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2610     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2611
2612     std::string rd = GPR(copy(rd_value));
2613     std::string rs = GPR(copy(rs_value));
2614     std::string rt = GPR(copy(rt_value));
2615
2616     return img::format("ADDUH.QB %s, %s, %s", rd, rs, rt);
2617 }
2618
2619
2620 /*
2621  * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2622  *                         to Halve Results
2623  *
2624  *   3         2         1
2625  *  10987654321098765432109876543210
2626  *  001000               10101001101
2627  *     rt -----
2628  *          rs -----
2629  *               rd -----
2630  */
2631 std::string NMD::ADDUH_R_QB(uint64 instruction)
2632 {
2633     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2634     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2635     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2636
2637     std::string rd = GPR(copy(rd_value));
2638     std::string rs = GPR(copy(rs_value));
2639     std::string rt = GPR(copy(rt_value));
2640
2641     return img::format("ADDUH_R.QB %s, %s, %s", rd, rs, rt);
2642 }
2643
2644 /*
2645  * ADDWC rd, rt, rs - Add Word with Carry Bit
2646  *
2647  *   3         2         1
2648  *  10987654321098765432109876543210
2649  *  001000               x1111000101
2650  *     rt -----
2651  *          rs -----
2652  *               rd -----
2653  */
2654 std::string NMD::ADDWC(uint64 instruction)
2655 {
2656     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2657     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2658     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2659
2660     std::string rd = GPR(copy(rd_value));
2661     std::string rs = GPR(copy(rs_value));
2662     std::string rt = GPR(copy(rt_value));
2663
2664     return img::format("ADDWC %s, %s, %s", rd, rs, rt);
2665 }
2666
2667
2668 /*
2669  *
2670  *
2671  *   3         2         1
2672  *  10987654321098765432109876543210
2673  *  001000               x1110000101
2674  *     rt -----
2675  *          rs -----
2676  *               rd -----
2677  */
2678 std::string NMD::ALUIPC(uint64 instruction)
2679 {
2680     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2681     int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction);
2682
2683     std::string rt = GPR(copy(rt_value));
2684     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2685
2686     return img::format("ALUIPC %s, %%pcrel_hi(%s)", rt, s);
2687 }
2688
2689
2690 /*
2691  * AND[16] rt3, rs3 -
2692  *
2693  *  5432109876543210
2694  *  101100
2695  *    rt3 ---
2696  *       rs3 ---
2697  *           eu ----
2698  */
2699 std::string NMD::AND_16_(uint64 instruction)
2700 {
2701     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2702     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2703
2704     std::string rt3 = GPR(encode_gpr3(rt3_value));
2705     std::string rs3 = GPR(encode_gpr3(rs3_value));
2706
2707     return img::format("AND %s, %s", rs3, rt3);
2708 }
2709
2710
2711 /*
2712  *
2713  *
2714  *   3         2         1
2715  *  10987654321098765432109876543210
2716  *  001000               x1110000101
2717  *     rt -----
2718  *          rs -----
2719  *               rd -----
2720  */
2721 std::string NMD::AND_32_(uint64 instruction)
2722 {
2723     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2724     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
2725     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2726
2727     std::string rd = GPR(copy(rd_value));
2728     std::string rs = GPR(copy(rs_value));
2729     std::string rt = GPR(copy(rt_value));
2730
2731     return img::format("AND %s, %s, %s", rd, rs, rt);
2732 }
2733
2734
2735 /*
2736  * ANDI rt, rs, u -
2737  *
2738  *  5432109876543210
2739  *  101100
2740  *    rt3 ---
2741  *       rs3 ---
2742  *           eu ----
2743  */
2744 std::string NMD::ANDI_16_(uint64 instruction)
2745 {
2746     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2747     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2748     uint64 eu_value = extract_eu_3_2_1_0(instruction);
2749
2750     std::string rt3 = GPR(encode_gpr3(rt3_value));
2751     std::string rs3 = GPR(encode_gpr3(rs3_value));
2752     std::string eu = IMMEDIATE(encode_eu_from_u_andi16(eu_value));
2753
2754     return img::format("ANDI %s, %s, %s", rt3, rs3, eu);
2755 }
2756
2757
2758 /*
2759  *
2760  *
2761  *   3         2         1
2762  *  10987654321098765432109876543210
2763  *  001000               x1110000101
2764  *     rt -----
2765  *          rs -----
2766  *               rd -----
2767  */
2768 std::string NMD::ANDI_32_(uint64 instruction)
2769 {
2770     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2771     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2772     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2773
2774     std::string rt = GPR(copy(rt_value));
2775     std::string rs = GPR(copy(rs_value));
2776     std::string u = IMMEDIATE(copy(u_value));
2777
2778     return img::format("ANDI %s, %s, %s", rt, rs, u);
2779 }
2780
2781
2782 /*
2783  *
2784  *
2785  *   3         2         1
2786  *  10987654321098765432109876543210
2787  *  001000               x1110000101
2788  *     rt -----
2789  *          rs -----
2790  *               rd -----
2791  */
2792 std::string NMD::APPEND(uint64 instruction)
2793 {
2794     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2795     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
2796     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2797
2798     std::string rt = GPR(copy(rt_value));
2799     std::string rs = GPR(copy(rs_value));
2800     std::string sa = IMMEDIATE(copy(sa_value));
2801
2802     return img::format("APPEND %s, %s, %s", rt, rs, sa);
2803 }
2804
2805
2806 /*
2807  *
2808  *
2809  *   3         2         1
2810  *  10987654321098765432109876543210
2811  *  001000               x1110000101
2812  *     rt -----
2813  *          rs -----
2814  *               rd -----
2815  */
2816 std::string NMD::ASET(uint64 instruction)
2817 {
2818     uint64 bit_value = extract_bit_23_22_21(instruction);
2819     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
2820     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2821
2822     std::string bit = IMMEDIATE(copy(bit_value));
2823     std::string s = IMMEDIATE(copy(s_value));
2824     std::string rs = GPR(copy(rs_value));
2825
2826     return img::format("ASET %s, %s(%s)", bit, s, rs);
2827 }
2828
2829
2830 /*
2831  *
2832  *
2833  *   3         2         1
2834  *  10987654321098765432109876543210
2835  *  001000               x1110000101
2836  *     rt -----
2837  *          rs -----
2838  *               rd -----
2839  */
2840 std::string NMD::BALC_16_(uint64 instruction)
2841 {
2842     int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction);
2843
2844     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2845
2846     return img::format("BALC %s", s);
2847 }
2848
2849
2850 /*
2851  *
2852  *
2853  *   3         2         1
2854  *  10987654321098765432109876543210
2855  *  001000               x1110000101
2856  *     rt -----
2857  *          rs -----
2858  *               rd -----
2859  */
2860 std::string NMD::BALC_32_(uint64 instruction)
2861 {
2862     int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction);
2863
2864     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2865
2866     return img::format("BALC %s", s);
2867 }
2868
2869
2870 /*
2871  *
2872  *
2873  *   3         2         1
2874  *  10987654321098765432109876543210
2875  *  001000               x1110000101
2876  *     rt -----
2877  *          rs -----
2878  *               rd -----
2879  */
2880 std::string NMD::BALRSC(uint64 instruction)
2881 {
2882     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2883     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2884
2885     std::string rt = GPR(copy(rt_value));
2886     std::string rs = GPR(copy(rs_value));
2887
2888     return img::format("BALRSC %s, %s", rt, rs);
2889 }
2890
2891
2892 /*
2893  *
2894  *
2895  *   3         2         1
2896  *  10987654321098765432109876543210
2897  *  001000               x1110000101
2898  *     rt -----
2899  *          rs -----
2900  *               rd -----
2901  */
2902 std::string NMD::BBEQZC(uint64 instruction)
2903 {
2904     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2905     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2906     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
2907
2908     std::string rt = GPR(copy(rt_value));
2909     std::string bit = IMMEDIATE(copy(bit_value));
2910     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2911
2912     return img::format("BBEQZC %s, %s, %s", rt, bit, s);
2913 }
2914
2915
2916 /*
2917  *
2918  *
2919  *   3         2         1
2920  *  10987654321098765432109876543210
2921  *  001000               x1110000101
2922  *     rt -----
2923  *          rs -----
2924  *               rd -----
2925  */
2926 std::string NMD::BBNEZC(uint64 instruction)
2927 {
2928     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2929     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2930     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
2931
2932     std::string rt = GPR(copy(rt_value));
2933     std::string bit = IMMEDIATE(copy(bit_value));
2934     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2935
2936     return img::format("BBNEZC %s, %s, %s", rt, bit, s);
2937 }
2938
2939
2940 /*
2941  *
2942  *
2943  *   3         2         1
2944  *  10987654321098765432109876543210
2945  *  001000               x1110000101
2946  *     rt -----
2947  *          rs -----
2948  *               rd -----
2949  */
2950 std::string NMD::BC_16_(uint64 instruction)
2951 {
2952     int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction);
2953
2954     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2955
2956     return img::format("BC %s", s);
2957 }
2958
2959
2960 /*
2961  *
2962  *
2963  *   3         2         1
2964  *  10987654321098765432109876543210
2965  *  001000               x1110000101
2966  *     rt -----
2967  *          rs -----
2968  *               rd -----
2969  */
2970 std::string NMD::BC_32_(uint64 instruction)
2971 {
2972     int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction);
2973
2974     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2975
2976     return img::format("BC %s", s);
2977 }
2978
2979
2980 /*
2981  *
2982  *
2983  *   3         2         1
2984  *  10987654321098765432109876543210
2985  *  001000               x1110000101
2986  *     rt -----
2987  *          rs -----
2988  *               rd -----
2989  */
2990 std::string NMD::BC1EQZC(uint64 instruction)
2991 {
2992     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
2993     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
2994
2995     std::string ft = FPR(copy(ft_value));
2996     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2997
2998     return img::format("BC1EQZC %s, %s", ft, s);
2999 }
3000
3001
3002 /*
3003  *
3004  *
3005  *   3         2         1
3006  *  10987654321098765432109876543210
3007  *  001000               x1110000101
3008  *     rt -----
3009  *          rs -----
3010  *               rd -----
3011  */
3012 std::string NMD::BC1NEZC(uint64 instruction)
3013 {
3014     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3015     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3016
3017     std::string ft = FPR(copy(ft_value));
3018     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3019
3020     return img::format("BC1NEZC %s, %s", ft, s);
3021 }
3022
3023
3024 /*
3025  *
3026  *
3027  *   3         2         1
3028  *  10987654321098765432109876543210
3029  *  001000               x1110000101
3030  *     rt -----
3031  *          rs -----
3032  *               rd -----
3033  */
3034 std::string NMD::BC2EQZC(uint64 instruction)
3035 {
3036     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3037     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3038
3039     std::string ct = CPR(copy(ct_value));
3040     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3041
3042     return img::format("BC2EQZC %s, %s", ct, s);
3043 }
3044
3045
3046 /*
3047  *
3048  *
3049  *   3         2         1
3050  *  10987654321098765432109876543210
3051  *  001000               x1110000101
3052  *     rt -----
3053  *          rs -----
3054  *               rd -----
3055  */
3056 std::string NMD::BC2NEZC(uint64 instruction)
3057 {
3058     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3059     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3060
3061     std::string ct = CPR(copy(ct_value));
3062     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3063
3064     return img::format("BC2NEZC %s, %s", ct, s);
3065 }
3066
3067
3068 /*
3069  *
3070  *
3071  *   3         2         1
3072  *  10987654321098765432109876543210
3073  *  001000               x1110000101
3074  *     rt -----
3075  *          rs -----
3076  *               rd -----
3077  */
3078 std::string NMD::BEQC_16_(uint64 instruction)
3079 {
3080     uint64 u_value = extr_uil0il1bs4Fmsb4(instruction);
3081     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3082     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3083
3084     std::string rs3 = GPR(encode_rs3_and_check_rs3_lt_rt3(rs3_value));
3085     std::string rt3 = GPR(encode_gpr3(rt3_value));
3086     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3087
3088     return img::format("BEQC %s, %s, %s", rs3, rt3, u);
3089 }
3090
3091
3092 /*
3093  *
3094  *
3095  *   3         2         1
3096  *  10987654321098765432109876543210
3097  *  001000               x1110000101
3098  *     rt -----
3099  *          rs -----
3100  *               rd -----
3101  */
3102 std::string NMD::BEQC_32_(uint64 instruction)
3103 {
3104     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3105     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3106     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3107
3108     std::string rs = GPR(copy(rs_value));
3109     std::string rt = GPR(copy(rt_value));
3110     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3111
3112     return img::format("BEQC %s, %s, %s", rs, rt, s);
3113 }
3114
3115
3116 /*
3117  *
3118  *
3119  *   3         2         1
3120  *  10987654321098765432109876543210
3121  *  001000               x1110000101
3122  *     rt -----
3123  *          rs -----
3124  *               rd -----
3125  */
3126 std::string NMD::BEQIC(uint64 instruction)
3127 {
3128     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3129     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3130     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3131
3132     std::string rt = GPR(copy(rt_value));
3133     std::string u = IMMEDIATE(copy(u_value));
3134     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3135
3136     return img::format("BEQIC %s, %s, %s", rt, u, s);
3137 }
3138
3139
3140 /*
3141  *
3142  *
3143  *   3         2         1
3144  *  10987654321098765432109876543210
3145  *  001000               x1110000101
3146  *     rt -----
3147  *          rs -----
3148  *               rd -----
3149  */
3150 std::string NMD::BEQZC_16_(uint64 instruction)
3151 {
3152     int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction);
3153     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3154
3155     std::string rt3 = GPR(encode_gpr3(rt3_value));
3156     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3157
3158     return img::format("BEQZC %s, %s", rt3, s);
3159 }
3160
3161
3162 /*
3163  *
3164  *
3165  *   3         2         1
3166  *  10987654321098765432109876543210
3167  *  001000               x1110000101
3168  *     rt -----
3169  *          rs -----
3170  *               rd -----
3171  */
3172 std::string NMD::BGEC(uint64 instruction)
3173 {
3174     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3175     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3176     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3177
3178     std::string rs = GPR(copy(rs_value));
3179     std::string rt = GPR(copy(rt_value));
3180     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3181
3182     return img::format("BGEC %s, %s, %s", rs, rt, s);
3183 }
3184
3185
3186 /*
3187  *
3188  *
3189  *   3         2         1
3190  *  10987654321098765432109876543210
3191  *  001000               x1110000101
3192  *     rt -----
3193  *          rs -----
3194  *               rd -----
3195  */
3196 std::string NMD::BGEIC(uint64 instruction)
3197 {
3198     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3199     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3200     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3201
3202     std::string rt = GPR(copy(rt_value));
3203     std::string u = IMMEDIATE(copy(u_value));
3204     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3205
3206     return img::format("BGEIC %s, %s, %s", rt, u, s);
3207 }
3208
3209
3210 /*
3211  *
3212  *
3213  *   3         2         1
3214  *  10987654321098765432109876543210
3215  *  001000               x1110000101
3216  *     rt -----
3217  *          rs -----
3218  *               rd -----
3219  */
3220 std::string NMD::BGEIUC(uint64 instruction)
3221 {
3222     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3223     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3224     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3225
3226     std::string rt = GPR(copy(rt_value));
3227     std::string u = IMMEDIATE(copy(u_value));
3228     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3229
3230     return img::format("BGEIUC %s, %s, %s", rt, u, s);
3231 }
3232
3233
3234 /*
3235  *
3236  *
3237  *   3         2         1
3238  *  10987654321098765432109876543210
3239  *  001000               x1110000101
3240  *     rt -----
3241  *          rs -----
3242  *               rd -----
3243  */
3244 std::string NMD::BGEUC(uint64 instruction)
3245 {
3246     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3247     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3248     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3249
3250     std::string rs = GPR(copy(rs_value));
3251     std::string rt = GPR(copy(rt_value));
3252     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3253
3254     return img::format("BGEUC %s, %s, %s", rs, rt, s);
3255 }
3256
3257
3258 /*
3259  *
3260  *
3261  *   3         2         1
3262  *  10987654321098765432109876543210
3263  *  001000               x1110000101
3264  *     rt -----
3265  *          rs -----
3266  *               rd -----
3267  */
3268 std::string NMD::BLTC(uint64 instruction)
3269 {
3270     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3271     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3272     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3273
3274     std::string rs = GPR(copy(rs_value));
3275     std::string rt = GPR(copy(rt_value));
3276     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3277
3278     return img::format("BLTC %s, %s, %s", rs, rt, s);
3279 }
3280
3281
3282 /*
3283  *
3284  *
3285  *   3         2         1
3286  *  10987654321098765432109876543210
3287  *  001000               x1110000101
3288  *     rt -----
3289  *          rs -----
3290  *               rd -----
3291  */
3292 std::string NMD::BLTIC(uint64 instruction)
3293 {
3294     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3295     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3296     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3297
3298     std::string rt = GPR(copy(rt_value));
3299     std::string u = IMMEDIATE(copy(u_value));
3300     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3301
3302     return img::format("BLTIC %s, %s, %s", rt, u, s);
3303 }
3304
3305
3306 /*
3307  *
3308  *
3309  *   3         2         1
3310  *  10987654321098765432109876543210
3311  *  001000               x1110000101
3312  *     rt -----
3313  *          rs -----
3314  *               rd -----
3315  */
3316 std::string NMD::BLTIUC(uint64 instruction)
3317 {
3318     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3319     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3320     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3321
3322     std::string rt = GPR(copy(rt_value));
3323     std::string u = IMMEDIATE(copy(u_value));
3324     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3325
3326     return img::format("BLTIUC %s, %s, %s", rt, u, s);
3327 }
3328
3329
3330 /*
3331  *
3332  *
3333  *   3         2         1
3334  *  10987654321098765432109876543210
3335  *  001000               x1110000101
3336  *     rt -----
3337  *          rs -----
3338  *               rd -----
3339  */
3340 std::string NMD::BLTUC(uint64 instruction)
3341 {
3342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3343     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3344     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3345
3346     std::string rs = GPR(copy(rs_value));
3347     std::string rt = GPR(copy(rt_value));
3348     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3349
3350     return img::format("BLTUC %s, %s, %s", rs, rt, s);
3351 }
3352
3353
3354 /*
3355  *
3356  *
3357  *   3         2         1
3358  *  10987654321098765432109876543210
3359  *  001000               x1110000101
3360  *     rt -----
3361  *          rs -----
3362  *               rd -----
3363  */
3364 std::string NMD::BNEC_16_(uint64 instruction)
3365 {
3366     uint64 u_value = extr_uil0il1bs4Fmsb4(instruction);
3367     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3368     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3369
3370     std::string rs3 = GPR(encode_rs3_and_check_rs3_ge_rt3(rs3_value));
3371     std::string rt3 = GPR(encode_gpr3(rt3_value));
3372     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3373
3374     return img::format("BNEC %s, %s, %s", rs3, rt3, u);
3375 }
3376
3377
3378 /*
3379  *
3380  *
3381  *   3         2         1
3382  *  10987654321098765432109876543210
3383  *  001000               x1110000101
3384  *     rt -----
3385  *          rs -----
3386  *               rd -----
3387  */
3388 std::string NMD::BNEC_32_(uint64 instruction)
3389 {
3390     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3391     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3392     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3393
3394     std::string rs = GPR(copy(rs_value));
3395     std::string rt = GPR(copy(rt_value));
3396     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3397
3398     return img::format("BNEC %s, %s, %s", rs, rt, s);
3399 }
3400
3401
3402 /*
3403  *
3404  *
3405  *   3         2         1
3406  *  10987654321098765432109876543210
3407  *  001000               x1110000101
3408  *     rt -----
3409  *          rs -----
3410  *               rd -----
3411  */
3412 std::string NMD::BNEIC(uint64 instruction)
3413 {
3414     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3415     int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction);
3416     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3417
3418     std::string rt = GPR(copy(rt_value));
3419     std::string u = IMMEDIATE(copy(u_value));
3420     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3421
3422     return img::format("BNEIC %s, %s, %s", rt, u, s);
3423 }
3424
3425
3426 /*
3427  *
3428  *
3429  *   3         2         1
3430  *  10987654321098765432109876543210
3431  *  001000               x1110000101
3432  *     rt -----
3433  *          rs -----
3434  *               rd -----
3435  */
3436 std::string NMD::BNEZC_16_(uint64 instruction)
3437 {
3438     int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction);
3439     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3440
3441     std::string rt3 = GPR(encode_gpr3(rt3_value));
3442     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3443
3444     return img::format("BNEZC %s, %s", rt3, s);
3445 }
3446
3447
3448 /*
3449  *
3450  *
3451  *   3         2         1
3452  *  10987654321098765432109876543210
3453  *  001000               x1110000101
3454  *     rt -----
3455  *          rs -----
3456  *               rd -----
3457  */
3458 std::string NMD::BPOSGE32C(uint64 instruction)
3459 {
3460     int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction);
3461
3462     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3463
3464     return img::format("BPOSGE32C %s", s);
3465 }
3466
3467
3468 /*
3469  *
3470  *
3471  *   3         2         1
3472  *  10987654321098765432109876543210
3473  *  001000               x1110000101
3474  *     rt -----
3475  *          rs -----
3476  *               rd -----
3477  */
3478 std::string NMD::BREAK_16_(uint64 instruction)
3479 {
3480     uint64 code_value = extract_code_2_1_0(instruction);
3481
3482     std::string code = IMMEDIATE(copy(code_value));
3483
3484     return img::format("BREAK %s", code);
3485 }
3486
3487
3488 /*
3489  * BREAK code - Break. Cause a Breakpoint exception
3490  *
3491  *   3         2         1
3492  *  10987654321098765432109876543210
3493  *  001000               x1110000101
3494  *     rt -----
3495  *          rs -----
3496  *               rd -----
3497  */
3498 std::string NMD::BREAK_32_(uint64 instruction)
3499 {
3500     uint64 code_value = extract_code_18_to_0(instruction);
3501
3502     std::string code = IMMEDIATE(copy(code_value));
3503
3504     return img::format("BREAK %s", code);
3505 }
3506
3507
3508 /*
3509  *
3510  *
3511  *   3         2         1
3512  *  10987654321098765432109876543210
3513  *  001000               x1110000101
3514  *     rt -----
3515  *          rs -----
3516  *               rd -----
3517  */
3518 std::string NMD::BRSC(uint64 instruction)
3519 {
3520     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3521
3522     std::string rs = GPR(copy(rs_value));
3523
3524     return img::format("BRSC %s", rs);
3525 }
3526
3527
3528 /*
3529  *
3530  *
3531  *   3         2         1
3532  *  10987654321098765432109876543210
3533  *  001000               x1110000101
3534  *     rt -----
3535  *          rs -----
3536  *               rd -----
3537  */
3538 std::string NMD::CACHE(uint64 instruction)
3539 {
3540     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
3541     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3542     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3543
3544     std::string op = IMMEDIATE(copy(op_value));
3545     std::string s = IMMEDIATE(copy(s_value));
3546     std::string rs = GPR(copy(rs_value));
3547
3548     return img::format("CACHE %s, %s(%s)", op, s, rs);
3549 }
3550
3551
3552 /*
3553  *
3554  *
3555  *   3         2         1
3556  *  10987654321098765432109876543210
3557  *  001000               x1110000101
3558  *     rt -----
3559  *          rs -----
3560  *               rd -----
3561  */
3562 std::string NMD::CACHEE(uint64 instruction)
3563 {
3564     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
3565     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3566     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3567
3568     std::string op = IMMEDIATE(copy(op_value));
3569     std::string s = IMMEDIATE(copy(s_value));
3570     std::string rs = GPR(copy(rs_value));
3571
3572     return img::format("CACHEE %s, %s(%s)", op, s, rs);
3573 }
3574
3575
3576 /*
3577  *
3578  *
3579  *   3         2         1
3580  *  10987654321098765432109876543210
3581  *  001000               x1110000101
3582  *     rt -----
3583  *          rs -----
3584  *               rd -----
3585  */
3586 std::string NMD::CEIL_L_D(uint64 instruction)
3587 {
3588     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3589     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3590
3591     std::string ft = FPR(copy(ft_value));
3592     std::string fs = FPR(copy(fs_value));
3593
3594     return img::format("CEIL.L.D %s, %s", ft, fs);
3595 }
3596
3597
3598 /*
3599  *
3600  *
3601  *   3         2         1
3602  *  10987654321098765432109876543210
3603  *  001000               x1110000101
3604  *     rt -----
3605  *          rs -----
3606  *               rd -----
3607  */
3608 std::string NMD::CEIL_L_S(uint64 instruction)
3609 {
3610     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3611     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3612
3613     std::string ft = FPR(copy(ft_value));
3614     std::string fs = FPR(copy(fs_value));
3615
3616     return img::format("CEIL.L.S %s, %s", ft, fs);
3617 }
3618
3619
3620 /*
3621  *
3622  *
3623  *   3         2         1
3624  *  10987654321098765432109876543210
3625  *  001000               x1110000101
3626  *     rt -----
3627  *          rs -----
3628  *               rd -----
3629  */
3630 std::string NMD::CEIL_W_D(uint64 instruction)
3631 {
3632     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3633     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3634
3635     std::string ft = FPR(copy(ft_value));
3636     std::string fs = FPR(copy(fs_value));
3637
3638     return img::format("CEIL.W.D %s, %s", ft, fs);
3639 }
3640
3641
3642 /*
3643  *
3644  *
3645  *   3         2         1
3646  *  10987654321098765432109876543210
3647  *  001000               x1110000101
3648  *     rt -----
3649  *          rs -----
3650  *               rd -----
3651  */
3652 std::string NMD::CEIL_W_S(uint64 instruction)
3653 {
3654     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3655     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3656
3657     std::string ft = FPR(copy(ft_value));
3658     std::string fs = FPR(copy(fs_value));
3659
3660     return img::format("CEIL.W.S %s, %s", ft, fs);
3661 }
3662
3663
3664 /*
3665  *
3666  *
3667  *   3         2         1
3668  *  10987654321098765432109876543210
3669  *  001000               x1110000101
3670  *     rt -----
3671  *          rs -----
3672  *               rd -----
3673  */
3674 std::string NMD::CFC1(uint64 instruction)
3675 {
3676     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3677     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3678
3679     std::string rt = GPR(copy(rt_value));
3680     std::string cs = CPR(copy(cs_value));
3681
3682     return img::format("CFC1 %s, %s", rt, cs);
3683 }
3684
3685
3686 /*
3687  *
3688  *
3689  *   3         2         1
3690  *  10987654321098765432109876543210
3691  *  001000               x1110000101
3692  *     rt -----
3693  *          rs -----
3694  *               rd -----
3695  */
3696 std::string NMD::CFC2(uint64 instruction)
3697 {
3698     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3699     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3700
3701     std::string rt = GPR(copy(rt_value));
3702     std::string cs = CPR(copy(cs_value));
3703
3704     return img::format("CFC2 %s, %s", rt, cs);
3705 }
3706
3707
3708 /*
3709  *
3710  *
3711  *   3         2         1
3712  *  10987654321098765432109876543210
3713  *  001000               x1110000101
3714  *     rt -----
3715  *          rs -----
3716  *               rd -----
3717  */
3718 std::string NMD::CLASS_D(uint64 instruction)
3719 {
3720     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3721     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3722
3723     std::string ft = FPR(copy(ft_value));
3724     std::string fs = FPR(copy(fs_value));
3725
3726     return img::format("CLASS.D %s, %s", ft, fs);
3727 }
3728
3729
3730 /*
3731  *
3732  *
3733  *   3         2         1
3734  *  10987654321098765432109876543210
3735  *  001000               x1110000101
3736  *     rt -----
3737  *          rs -----
3738  *               rd -----
3739  */
3740 std::string NMD::CLASS_S(uint64 instruction)
3741 {
3742     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3743     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3744
3745     std::string ft = FPR(copy(ft_value));
3746     std::string fs = FPR(copy(fs_value));
3747
3748     return img::format("CLASS.S %s, %s", ft, fs);
3749 }
3750
3751
3752 /*
3753  *
3754  *
3755  *   3         2         1
3756  *  10987654321098765432109876543210
3757  *  001000               x1110000101
3758  *     rt -----
3759  *          rs -----
3760  *               rd -----
3761  */
3762 std::string NMD::CLO(uint64 instruction)
3763 {
3764     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3765     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3766
3767     std::string rt = GPR(copy(rt_value));
3768     std::string rs = GPR(copy(rs_value));
3769
3770     return img::format("CLO %s, %s", rt, rs);
3771 }
3772
3773
3774 /*
3775  *
3776  *
3777  *   3         2         1
3778  *  10987654321098765432109876543210
3779  *  001000               x1110000101
3780  *     rt -----
3781  *          rs -----
3782  *               rd -----
3783  */
3784 std::string NMD::CLZ(uint64 instruction)
3785 {
3786     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3787     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3788
3789     std::string rt = GPR(copy(rt_value));
3790     std::string rs = GPR(copy(rs_value));
3791
3792     return img::format("CLZ %s, %s", rt, rs);
3793 }
3794
3795
3796 /*
3797  *
3798  *
3799  *   3         2         1
3800  *  10987654321098765432109876543210
3801  *  001000               x1110000101
3802  *     rt -----
3803  *          rs -----
3804  *               rd -----
3805  */
3806 std::string NMD::CMP_AF_D(uint64 instruction)
3807 {
3808     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3809     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3810     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3811
3812     std::string fd = FPR(copy(fd_value));
3813     std::string fs = FPR(copy(fs_value));
3814     std::string ft = FPR(copy(ft_value));
3815
3816     return img::format("CMP.AF.D %s, %s, %s", fd, fs, ft);
3817 }
3818
3819
3820 /*
3821  *
3822  *
3823  *   3         2         1
3824  *  10987654321098765432109876543210
3825  *  001000               x1110000101
3826  *     rt -----
3827  *          rs -----
3828  *               rd -----
3829  */
3830 std::string NMD::CMP_AF_S(uint64 instruction)
3831 {
3832     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3833     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3834     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3835
3836     std::string fd = FPR(copy(fd_value));
3837     std::string fs = FPR(copy(fs_value));
3838     std::string ft = FPR(copy(ft_value));
3839
3840     return img::format("CMP.AF.S %s, %s, %s", fd, fs, ft);
3841 }
3842
3843
3844 /*
3845  *
3846  *
3847  *   3         2         1
3848  *  10987654321098765432109876543210
3849  *  001000               x1110000101
3850  *     rt -----
3851  *          rs -----
3852  *               rd -----
3853  */
3854 std::string NMD::CMP_EQ_D(uint64 instruction)
3855 {
3856     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3857     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3858     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3859
3860     std::string fd = FPR(copy(fd_value));
3861     std::string fs = FPR(copy(fs_value));
3862     std::string ft = FPR(copy(ft_value));
3863
3864     return img::format("CMP.EQ.D %s, %s, %s", fd, fs, ft);
3865 }
3866
3867
3868 /*
3869  *
3870  *
3871  *   3         2         1
3872  *  10987654321098765432109876543210
3873  *  001000               x1110000101
3874  *     rt -----
3875  *          rs -----
3876  *               rd -----
3877  */
3878 std::string NMD::CMP_EQ_PH(uint64 instruction)
3879 {
3880     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3881     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3882
3883     std::string rs = GPR(copy(rs_value));
3884     std::string rt = GPR(copy(rt_value));
3885
3886     return img::format("CMP.EQ.PH %s, %s", rs, rt);
3887 }
3888
3889
3890 /*
3891  *
3892  *
3893  *   3         2         1
3894  *  10987654321098765432109876543210
3895  *  001000               x1110000101
3896  *     rt -----
3897  *          rs -----
3898  *               rd -----
3899  */
3900 std::string NMD::CMP_EQ_S(uint64 instruction)
3901 {
3902     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3903     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3904     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3905
3906     std::string fd = FPR(copy(fd_value));
3907     std::string fs = FPR(copy(fs_value));
3908     std::string ft = FPR(copy(ft_value));
3909
3910     return img::format("CMP.EQ.S %s, %s, %s", fd, fs, ft);
3911 }
3912
3913
3914 /*
3915  *
3916  *
3917  *   3         2         1
3918  *  10987654321098765432109876543210
3919  *  001000               x1110000101
3920  *     rt -----
3921  *          rs -----
3922  *               rd -----
3923  */
3924 std::string NMD::CMP_LE_D(uint64 instruction)
3925 {
3926     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3927     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3928     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3929
3930     std::string fd = FPR(copy(fd_value));
3931     std::string fs = FPR(copy(fs_value));
3932     std::string ft = FPR(copy(ft_value));
3933
3934     return img::format("CMP.LE.D %s, %s, %s", fd, fs, ft);
3935 }
3936
3937
3938 /*
3939  *
3940  *
3941  *   3         2         1
3942  *  10987654321098765432109876543210
3943  *  001000               x1110000101
3944  *     rt -----
3945  *          rs -----
3946  *               rd -----
3947  */
3948 std::string NMD::CMP_LE_PH(uint64 instruction)
3949 {
3950     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3951     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3952
3953     std::string rs = GPR(copy(rs_value));
3954     std::string rt = GPR(copy(rt_value));
3955
3956     return img::format("CMP.LE.PH %s, %s", rs, rt);
3957 }
3958
3959
3960 /*
3961  *
3962  *
3963  *   3         2         1
3964  *  10987654321098765432109876543210
3965  *  001000               x1110000101
3966  *     rt -----
3967  *          rs -----
3968  *               rd -----
3969  */
3970 std::string NMD::CMP_LE_S(uint64 instruction)
3971 {
3972     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3973     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3974     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3975
3976     std::string fd = FPR(copy(fd_value));
3977     std::string fs = FPR(copy(fs_value));
3978     std::string ft = FPR(copy(ft_value));
3979
3980     return img::format("CMP.LE.S %s, %s, %s", fd, fs, ft);
3981 }
3982
3983
3984 /*
3985  *
3986  *
3987  *   3         2         1
3988  *  10987654321098765432109876543210
3989  *  001000               x1110000101
3990  *     rt -----
3991  *          rs -----
3992  *               rd -----
3993  */
3994 std::string NMD::CMP_LT_D(uint64 instruction)
3995 {
3996     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
3997     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
3998     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
3999
4000     std::string fd = FPR(copy(fd_value));
4001     std::string fs = FPR(copy(fs_value));
4002     std::string ft = FPR(copy(ft_value));
4003
4004     return img::format("CMP.LT.D %s, %s, %s", fd, fs, ft);
4005 }
4006
4007
4008 /*
4009  *
4010  *
4011  *   3         2         1
4012  *  10987654321098765432109876543210
4013  *  001000               x1110000101
4014  *     rt -----
4015  *          rs -----
4016  *               rd -----
4017  */
4018 std::string NMD::CMP_LT_PH(uint64 instruction)
4019 {
4020     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4021     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4022
4023     std::string rs = GPR(copy(rs_value));
4024     std::string rt = GPR(copy(rt_value));
4025
4026     return img::format("CMP.LT.PH %s, %s", rs, rt);
4027 }
4028
4029
4030 /*
4031  *
4032  *
4033  *   3         2         1
4034  *  10987654321098765432109876543210
4035  *  001000               x1110000101
4036  *     rt -----
4037  *          rs -----
4038  *               rd -----
4039  */
4040 std::string NMD::CMP_LT_S(uint64 instruction)
4041 {
4042     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4043     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4044     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4045
4046     std::string fd = FPR(copy(fd_value));
4047     std::string fs = FPR(copy(fs_value));
4048     std::string ft = FPR(copy(ft_value));
4049
4050     return img::format("CMP.LT.S %s, %s, %s", fd, fs, ft);
4051 }
4052
4053
4054 /*
4055  *
4056  *
4057  *   3         2         1
4058  *  10987654321098765432109876543210
4059  *  001000               x1110000101
4060  *     rt -----
4061  *          rs -----
4062  *               rd -----
4063  */
4064 std::string NMD::CMP_NE_D(uint64 instruction)
4065 {
4066     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4067     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4068     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4069
4070     std::string fd = FPR(copy(fd_value));
4071     std::string fs = FPR(copy(fs_value));
4072     std::string ft = FPR(copy(ft_value));
4073
4074     return img::format("CMP.NE.D %s, %s, %s", fd, fs, ft);
4075 }
4076
4077
4078 /*
4079  *
4080  *
4081  *   3         2         1
4082  *  10987654321098765432109876543210
4083  *  001000               x1110000101
4084  *     rt -----
4085  *          rs -----
4086  *               rd -----
4087  */
4088 std::string NMD::CMP_NE_S(uint64 instruction)
4089 {
4090     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4091     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4092     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4093
4094     std::string fd = FPR(copy(fd_value));
4095     std::string fs = FPR(copy(fs_value));
4096     std::string ft = FPR(copy(ft_value));
4097
4098     return img::format("CMP.NE.S %s, %s, %s", fd, fs, ft);
4099 }
4100
4101
4102 /*
4103  *
4104  *
4105  *   3         2         1
4106  *  10987654321098765432109876543210
4107  *  001000               x1110000101
4108  *     rt -----
4109  *          rs -----
4110  *               rd -----
4111  */
4112 std::string NMD::CMP_OR_D(uint64 instruction)
4113 {
4114     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4115     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4116     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4117
4118     std::string fd = FPR(copy(fd_value));
4119     std::string fs = FPR(copy(fs_value));
4120     std::string ft = FPR(copy(ft_value));
4121
4122     return img::format("CMP.OR.D %s, %s, %s", fd, fs, ft);
4123 }
4124
4125
4126 /*
4127  *
4128  *
4129  *   3         2         1
4130  *  10987654321098765432109876543210
4131  *  001000               x1110000101
4132  *     rt -----
4133  *          rs -----
4134  *               rd -----
4135  */
4136 std::string NMD::CMP_OR_S(uint64 instruction)
4137 {
4138     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4139     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4140     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4141
4142     std::string fd = FPR(copy(fd_value));
4143     std::string fs = FPR(copy(fs_value));
4144     std::string ft = FPR(copy(ft_value));
4145
4146     return img::format("CMP.OR.S %s, %s, %s", fd, fs, ft);
4147 }
4148
4149
4150 /*
4151  *
4152  *
4153  *   3         2         1
4154  *  10987654321098765432109876543210
4155  *  001000               x1110000101
4156  *     rt -----
4157  *          rs -----
4158  *               rd -----
4159  */
4160 std::string NMD::CMP_SAF_D(uint64 instruction)
4161 {
4162     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4163     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4164     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4165
4166     std::string fd = FPR(copy(fd_value));
4167     std::string fs = FPR(copy(fs_value));
4168     std::string ft = FPR(copy(ft_value));
4169
4170     return img::format("CMP.SAF.D %s, %s, %s", fd, fs, ft);
4171 }
4172
4173
4174 /*
4175  *
4176  *
4177  *   3         2         1
4178  *  10987654321098765432109876543210
4179  *  001000               x1110000101
4180  *     rt -----
4181  *          rs -----
4182  *               rd -----
4183  */
4184 std::string NMD::CMP_SAF_S(uint64 instruction)
4185 {
4186     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4187     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4188     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4189
4190     std::string fd = FPR(copy(fd_value));
4191     std::string fs = FPR(copy(fs_value));
4192     std::string ft = FPR(copy(ft_value));
4193
4194     return img::format("CMP.SAF.S %s, %s, %s", fd, fs, ft);
4195 }
4196
4197
4198 /*
4199  *
4200  *
4201  *   3         2         1
4202  *  10987654321098765432109876543210
4203  *  001000               x1110000101
4204  *     rt -----
4205  *          rs -----
4206  *               rd -----
4207  */
4208 std::string NMD::CMP_SEQ_D(uint64 instruction)
4209 {
4210     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4211     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4212     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4213
4214     std::string fd = FPR(copy(fd_value));
4215     std::string fs = FPR(copy(fs_value));
4216     std::string ft = FPR(copy(ft_value));
4217
4218     return img::format("CMP.SEQ.D %s, %s, %s", fd, fs, ft);
4219 }
4220
4221
4222 /*
4223  *
4224  *
4225  *   3         2         1
4226  *  10987654321098765432109876543210
4227  *  001000               x1110000101
4228  *     rt -----
4229  *          rs -----
4230  *               rd -----
4231  */
4232 std::string NMD::CMP_SEQ_S(uint64 instruction)
4233 {
4234     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4235     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4236     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4237
4238     std::string fd = FPR(copy(fd_value));
4239     std::string fs = FPR(copy(fs_value));
4240     std::string ft = FPR(copy(ft_value));
4241
4242     return img::format("CMP.SEQ.S %s, %s, %s", fd, fs, ft);
4243 }
4244
4245
4246 /*
4247  *
4248  *
4249  *   3         2         1
4250  *  10987654321098765432109876543210
4251  *  001000               x1110000101
4252  *     rt -----
4253  *          rs -----
4254  *               rd -----
4255  */
4256 std::string NMD::CMP_SLE_D(uint64 instruction)
4257 {
4258     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4259     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4260     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4261
4262     std::string fd = FPR(copy(fd_value));
4263     std::string fs = FPR(copy(fs_value));
4264     std::string ft = FPR(copy(ft_value));
4265
4266     return img::format("CMP.SLE.D %s, %s, %s", fd, fs, ft);
4267 }
4268
4269
4270 /*
4271  *
4272  *
4273  *   3         2         1
4274  *  10987654321098765432109876543210
4275  *  001000               x1110000101
4276  *     rt -----
4277  *          rs -----
4278  *               rd -----
4279  */
4280 std::string NMD::CMP_SLE_S(uint64 instruction)
4281 {
4282     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4283     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4284     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4285
4286     std::string fd = FPR(copy(fd_value));
4287     std::string fs = FPR(copy(fs_value));
4288     std::string ft = FPR(copy(ft_value));
4289
4290     return img::format("CMP.SLE.S %s, %s, %s", fd, fs, ft);
4291 }
4292
4293
4294 /*
4295  *
4296  *
4297  *   3         2         1
4298  *  10987654321098765432109876543210
4299  *  001000               x1110000101
4300  *     rt -----
4301  *          rs -----
4302  *               rd -----
4303  */
4304 std::string NMD::CMP_SLT_D(uint64 instruction)
4305 {
4306     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4307     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4308     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4309
4310     std::string fd = FPR(copy(fd_value));
4311     std::string fs = FPR(copy(fs_value));
4312     std::string ft = FPR(copy(ft_value));
4313
4314     return img::format("CMP.SLT.D %s, %s, %s", fd, fs, ft);
4315 }
4316
4317
4318 /*
4319  *
4320  *
4321  *   3         2         1
4322  *  10987654321098765432109876543210
4323  *  001000               x1110000101
4324  *     rt -----
4325  *          rs -----
4326  *               rd -----
4327  */
4328 std::string NMD::CMP_SLT_S(uint64 instruction)
4329 {
4330     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4331     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4332     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4333
4334     std::string fd = FPR(copy(fd_value));
4335     std::string fs = FPR(copy(fs_value));
4336     std::string ft = FPR(copy(ft_value));
4337
4338     return img::format("CMP.SLT.S %s, %s, %s", fd, fs, ft);
4339 }
4340
4341
4342 /*
4343  *
4344  *
4345  *   3         2         1
4346  *  10987654321098765432109876543210
4347  *  001000               x1110000101
4348  *     rt -----
4349  *          rs -----
4350  *               rd -----
4351  */
4352 std::string NMD::CMP_SNE_D(uint64 instruction)
4353 {
4354     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4355     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4356     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4357
4358     std::string fd = FPR(copy(fd_value));
4359     std::string fs = FPR(copy(fs_value));
4360     std::string ft = FPR(copy(ft_value));
4361
4362     return img::format("CMP.SNE.D %s, %s, %s", fd, fs, ft);
4363 }
4364
4365
4366 /*
4367  *
4368  *
4369  *   3         2         1
4370  *  10987654321098765432109876543210
4371  *  001000               x1110000101
4372  *     rt -----
4373  *          rs -----
4374  *               rd -----
4375  */
4376 std::string NMD::CMP_SNE_S(uint64 instruction)
4377 {
4378     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4379     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4380     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4381
4382     std::string fd = FPR(copy(fd_value));
4383     std::string fs = FPR(copy(fs_value));
4384     std::string ft = FPR(copy(ft_value));
4385
4386     return img::format("CMP.SNE.S %s, %s, %s", fd, fs, ft);
4387 }
4388
4389
4390 /*
4391  *
4392  *
4393  *   3         2         1
4394  *  10987654321098765432109876543210
4395  *  001000               x1110000101
4396  *     rt -----
4397  *          rs -----
4398  *               rd -----
4399  */
4400 std::string NMD::CMP_SOR_D(uint64 instruction)
4401 {
4402     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4403     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4404     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4405
4406     std::string fd = FPR(copy(fd_value));
4407     std::string fs = FPR(copy(fs_value));
4408     std::string ft = FPR(copy(ft_value));
4409
4410     return img::format("CMP.SOR.D %s, %s, %s", fd, fs, ft);
4411 }
4412
4413
4414 /*
4415  *
4416  *
4417  *   3         2         1
4418  *  10987654321098765432109876543210
4419  *  001000               x1110000101
4420  *     rt -----
4421  *          rs -----
4422  *               rd -----
4423  */
4424 std::string NMD::CMP_SOR_S(uint64 instruction)
4425 {
4426     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4427     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4428     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4429
4430     std::string fd = FPR(copy(fd_value));
4431     std::string fs = FPR(copy(fs_value));
4432     std::string ft = FPR(copy(ft_value));
4433
4434     return img::format("CMP.SOR.S %s, %s, %s", fd, fs, ft);
4435 }
4436
4437
4438 /*
4439  *
4440  *
4441  *   3         2         1
4442  *  10987654321098765432109876543210
4443  *  001000               x1110000101
4444  *     rt -----
4445  *          rs -----
4446  *               rd -----
4447  */
4448 std::string NMD::CMP_SUEQ_D(uint64 instruction)
4449 {
4450     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4451     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4452     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4453
4454     std::string fd = FPR(copy(fd_value));
4455     std::string fs = FPR(copy(fs_value));
4456     std::string ft = FPR(copy(ft_value));
4457
4458     return img::format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft);
4459 }
4460
4461
4462 /*
4463  *
4464  *
4465  *   3         2         1
4466  *  10987654321098765432109876543210
4467  *  001000               x1110000101
4468  *     rt -----
4469  *          rs -----
4470  *               rd -----
4471  */
4472 std::string NMD::CMP_SUEQ_S(uint64 instruction)
4473 {
4474     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4475     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4476     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4477
4478     std::string fd = FPR(copy(fd_value));
4479     std::string fs = FPR(copy(fs_value));
4480     std::string ft = FPR(copy(ft_value));
4481
4482     return img::format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft);
4483 }
4484
4485
4486 /*
4487  *
4488  *
4489  *   3         2         1
4490  *  10987654321098765432109876543210
4491  *  001000               x1110000101
4492  *     rt -----
4493  *          rs -----
4494  *               rd -----
4495  */
4496 std::string NMD::CMP_SULE_D(uint64 instruction)
4497 {
4498     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4499     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4500     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4501
4502     std::string fd = FPR(copy(fd_value));
4503     std::string fs = FPR(copy(fs_value));
4504     std::string ft = FPR(copy(ft_value));
4505
4506     return img::format("CMP.SULE.D %s, %s, %s", fd, fs, ft);
4507 }
4508
4509
4510 /*
4511  *
4512  *
4513  *   3         2         1
4514  *  10987654321098765432109876543210
4515  *  001000               x1110000101
4516  *     rt -----
4517  *          rs -----
4518  *               rd -----
4519  */
4520 std::string NMD::CMP_SULE_S(uint64 instruction)
4521 {
4522     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4523     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4524     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4525
4526     std::string fd = FPR(copy(fd_value));
4527     std::string fs = FPR(copy(fs_value));
4528     std::string ft = FPR(copy(ft_value));
4529
4530     return img::format("CMP.SULE.S %s, %s, %s", fd, fs, ft);
4531 }
4532
4533
4534 /*
4535  *
4536  *
4537  *   3         2         1
4538  *  10987654321098765432109876543210
4539  *  001000               x1110000101
4540  *     rt -----
4541  *          rs -----
4542  *               rd -----
4543  */
4544 std::string NMD::CMP_SULT_D(uint64 instruction)
4545 {
4546     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4547     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4548     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4549
4550     std::string fd = FPR(copy(fd_value));
4551     std::string fs = FPR(copy(fs_value));
4552     std::string ft = FPR(copy(ft_value));
4553
4554     return img::format("CMP.SULT.D %s, %s, %s", fd, fs, ft);
4555 }
4556
4557
4558 /*
4559  *
4560  *
4561  *   3         2         1
4562  *  10987654321098765432109876543210
4563  *  001000               x1110000101
4564  *     rt -----
4565  *          rs -----
4566  *               rd -----
4567  */
4568 std::string NMD::CMP_SULT_S(uint64 instruction)
4569 {
4570     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4571     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4572     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4573
4574     std::string fd = FPR(copy(fd_value));
4575     std::string fs = FPR(copy(fs_value));
4576     std::string ft = FPR(copy(ft_value));
4577
4578     return img::format("CMP.SULT.S %s, %s, %s", fd, fs, ft);
4579 }
4580
4581
4582 /*
4583  *
4584  *
4585  *   3         2         1
4586  *  10987654321098765432109876543210
4587  *  001000               x1110000101
4588  *     rt -----
4589  *          rs -----
4590  *               rd -----
4591  */
4592 std::string NMD::CMP_SUN_D(uint64 instruction)
4593 {
4594     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4595     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4596     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4597
4598     std::string fd = FPR(copy(fd_value));
4599     std::string fs = FPR(copy(fs_value));
4600     std::string ft = FPR(copy(ft_value));
4601
4602     return img::format("CMP.SUN.D %s, %s, %s", fd, fs, ft);
4603 }
4604
4605
4606 /*
4607  *
4608  *
4609  *   3         2         1
4610  *  10987654321098765432109876543210
4611  *  001000               x1110000101
4612  *     rt -----
4613  *          rs -----
4614  *               rd -----
4615  */
4616 std::string NMD::CMP_SUNE_D(uint64 instruction)
4617 {
4618     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4619     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4620     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4621
4622     std::string fd = FPR(copy(fd_value));
4623     std::string fs = FPR(copy(fs_value));
4624     std::string ft = FPR(copy(ft_value));
4625
4626     return img::format("CMP.SUNE.D %s, %s, %s", fd, fs, ft);
4627 }
4628
4629
4630 /*
4631  *
4632  *
4633  *   3         2         1
4634  *  10987654321098765432109876543210
4635  *  001000               x1110000101
4636  *     rt -----
4637  *          rs -----
4638  *               rd -----
4639  */
4640 std::string NMD::CMP_SUNE_S(uint64 instruction)
4641 {
4642     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4643     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4644     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4645
4646     std::string fd = FPR(copy(fd_value));
4647     std::string fs = FPR(copy(fs_value));
4648     std::string ft = FPR(copy(ft_value));
4649
4650     return img::format("CMP.SUNE.S %s, %s, %s", fd, fs, ft);
4651 }
4652
4653
4654 /*
4655  *
4656  *
4657  *   3         2         1
4658  *  10987654321098765432109876543210
4659  *  001000               x1110000101
4660  *     rt -----
4661  *          rs -----
4662  *               rd -----
4663  */
4664 std::string NMD::CMP_SUN_S(uint64 instruction)
4665 {
4666     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4667     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4668     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4669
4670     std::string fd = FPR(copy(fd_value));
4671     std::string fs = FPR(copy(fs_value));
4672     std::string ft = FPR(copy(ft_value));
4673
4674     return img::format("CMP.SUN.S %s, %s, %s", fd, fs, ft);
4675 }
4676
4677
4678 /*
4679  *
4680  *
4681  *   3         2         1
4682  *  10987654321098765432109876543210
4683  *  001000               x1110000101
4684  *     rt -----
4685  *          rs -----
4686  *               rd -----
4687  */
4688 std::string NMD::CMP_UEQ_D(uint64 instruction)
4689 {
4690     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4691     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4692     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4693
4694     std::string fd = FPR(copy(fd_value));
4695     std::string fs = FPR(copy(fs_value));
4696     std::string ft = FPR(copy(ft_value));
4697
4698     return img::format("CMP.UEQ.D %s, %s, %s", fd, fs, ft);
4699 }
4700
4701
4702 /*
4703  *
4704  *
4705  *   3         2         1
4706  *  10987654321098765432109876543210
4707  *  001000               x1110000101
4708  *     rt -----
4709  *          rs -----
4710  *               rd -----
4711  */
4712 std::string NMD::CMP_UEQ_S(uint64 instruction)
4713 {
4714     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4715     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4716     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4717
4718     std::string fd = FPR(copy(fd_value));
4719     std::string fs = FPR(copy(fs_value));
4720     std::string ft = FPR(copy(ft_value));
4721
4722     return img::format("CMP.UEQ.S %s, %s, %s", fd, fs, ft);
4723 }
4724
4725
4726 /*
4727  *
4728  *
4729  *   3         2         1
4730  *  10987654321098765432109876543210
4731  *  001000               x1110000101
4732  *     rt -----
4733  *          rs -----
4734  *               rd -----
4735  */
4736 std::string NMD::CMP_ULE_D(uint64 instruction)
4737 {
4738     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4739     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4740     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4741
4742     std::string fd = FPR(copy(fd_value));
4743     std::string fs = FPR(copy(fs_value));
4744     std::string ft = FPR(copy(ft_value));
4745
4746     return img::format("CMP.ULE.D %s, %s, %s", fd, fs, ft);
4747 }
4748
4749
4750 /*
4751  *
4752  *
4753  *   3         2         1
4754  *  10987654321098765432109876543210
4755  *  001000               x1110000101
4756  *     rt -----
4757  *          rs -----
4758  *               rd -----
4759  */
4760 std::string NMD::CMP_ULE_S(uint64 instruction)
4761 {
4762     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4763     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4764     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4765
4766     std::string fd = FPR(copy(fd_value));
4767     std::string fs = FPR(copy(fs_value));
4768     std::string ft = FPR(copy(ft_value));
4769
4770     return img::format("CMP.ULE.S %s, %s, %s", fd, fs, ft);
4771 }
4772
4773
4774 /*
4775  *
4776  *
4777  *   3         2         1
4778  *  10987654321098765432109876543210
4779  *  001000               x1110000101
4780  *     rt -----
4781  *          rs -----
4782  *               rd -----
4783  */
4784 std::string NMD::CMP_ULT_D(uint64 instruction)
4785 {
4786     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4787     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4788     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4789
4790     std::string fd = FPR(copy(fd_value));
4791     std::string fs = FPR(copy(fs_value));
4792     std::string ft = FPR(copy(ft_value));
4793
4794     return img::format("CMP.ULT.D %s, %s, %s", fd, fs, ft);
4795 }
4796
4797
4798 /*
4799  *
4800  *
4801  *   3         2         1
4802  *  10987654321098765432109876543210
4803  *  001000               x1110000101
4804  *     rt -----
4805  *          rs -----
4806  *               rd -----
4807  */
4808 std::string NMD::CMP_ULT_S(uint64 instruction)
4809 {
4810     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4811     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4812     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4813
4814     std::string fd = FPR(copy(fd_value));
4815     std::string fs = FPR(copy(fs_value));
4816     std::string ft = FPR(copy(ft_value));
4817
4818     return img::format("CMP.ULT.S %s, %s, %s", fd, fs, ft);
4819 }
4820
4821
4822 /*
4823  *
4824  *
4825  *   3         2         1
4826  *  10987654321098765432109876543210
4827  *  001000               x1110000101
4828  *     rt -----
4829  *          rs -----
4830  *               rd -----
4831  */
4832 std::string NMD::CMP_UN_D(uint64 instruction)
4833 {
4834     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4835     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4836     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4837
4838     std::string fd = FPR(copy(fd_value));
4839     std::string fs = FPR(copy(fs_value));
4840     std::string ft = FPR(copy(ft_value));
4841
4842     return img::format("CMP.UN.D %s, %s, %s", fd, fs, ft);
4843 }
4844
4845
4846 /*
4847  *
4848  *
4849  *   3         2         1
4850  *  10987654321098765432109876543210
4851  *  001000               x1110000101
4852  *     rt -----
4853  *          rs -----
4854  *               rd -----
4855  */
4856 std::string NMD::CMP_UNE_D(uint64 instruction)
4857 {
4858     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4859     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4860     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4861
4862     std::string fd = FPR(copy(fd_value));
4863     std::string fs = FPR(copy(fs_value));
4864     std::string ft = FPR(copy(ft_value));
4865
4866     return img::format("CMP.UNE.D %s, %s, %s", fd, fs, ft);
4867 }
4868
4869
4870 /*
4871  *
4872  *
4873  *   3         2         1
4874  *  10987654321098765432109876543210
4875  *  001000               x1110000101
4876  *     rt -----
4877  *          rs -----
4878  *               rd -----
4879  */
4880 std::string NMD::CMP_UNE_S(uint64 instruction)
4881 {
4882     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4883     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4884     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4885
4886     std::string fd = FPR(copy(fd_value));
4887     std::string fs = FPR(copy(fs_value));
4888     std::string ft = FPR(copy(ft_value));
4889
4890     return img::format("CMP.UNE.S %s, %s, %s", fd, fs, ft);
4891 }
4892
4893
4894 /*
4895  *
4896  *
4897  *   3         2         1
4898  *  10987654321098765432109876543210
4899  *  001000               x1110000101
4900  *     rt -----
4901  *          rs -----
4902  *               rd -----
4903  */
4904 std::string NMD::CMP_UN_S(uint64 instruction)
4905 {
4906     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
4907     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
4908     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
4909
4910     std::string fd = FPR(copy(fd_value));
4911     std::string fs = FPR(copy(fs_value));
4912     std::string ft = FPR(copy(ft_value));
4913
4914     return img::format("CMP.UN.S %s, %s, %s", fd, fs, ft);
4915 }
4916
4917
4918 /*
4919  *
4920  *
4921  *   3         2         1
4922  *  10987654321098765432109876543210
4923  *  001000               x1110000101
4924  *     rt -----
4925  *          rs -----
4926  *               rd -----
4927  */
4928 std::string NMD::CMPGDU_EQ_QB(uint64 instruction)
4929 {
4930     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4931     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
4932     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4933
4934     std::string rd = GPR(copy(rd_value));
4935     std::string rs = GPR(copy(rs_value));
4936     std::string rt = GPR(copy(rt_value));
4937
4938     return img::format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt);
4939 }
4940
4941
4942 /*
4943  *
4944  *
4945  *   3         2         1
4946  *  10987654321098765432109876543210
4947  *  001000               x1110000101
4948  *     rt -----
4949  *          rs -----
4950  *               rd -----
4951  */
4952 std::string NMD::CMPGDU_LE_QB(uint64 instruction)
4953 {
4954     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4955     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
4956     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4957
4958     std::string rd = GPR(copy(rd_value));
4959     std::string rs = GPR(copy(rs_value));
4960     std::string rt = GPR(copy(rt_value));
4961
4962     return img::format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt);
4963 }
4964
4965
4966 /*
4967  *
4968  *
4969  *   3         2         1
4970  *  10987654321098765432109876543210
4971  *  001000               x1110000101
4972  *     rt -----
4973  *          rs -----
4974  *               rd -----
4975  */
4976 std::string NMD::CMPGDU_LT_QB(uint64 instruction)
4977 {
4978     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4979     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
4980     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4981
4982     std::string rd = GPR(copy(rd_value));
4983     std::string rs = GPR(copy(rs_value));
4984     std::string rt = GPR(copy(rt_value));
4985
4986     return img::format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt);
4987 }
4988
4989
4990 /*
4991  *
4992  *
4993  *   3         2         1
4994  *  10987654321098765432109876543210
4995  *  001000               x1110000101
4996  *     rt -----
4997  *          rs -----
4998  *               rd -----
4999  */
5000 std::string NMD::CMPGU_EQ_QB(uint64 instruction)
5001 {
5002     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5003     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5004     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5005
5006     std::string rd = GPR(copy(rd_value));
5007     std::string rs = GPR(copy(rs_value));
5008     std::string rt = GPR(copy(rt_value));
5009
5010     return img::format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt);
5011 }
5012
5013
5014 /*
5015  *
5016  *
5017  *   3         2         1
5018  *  10987654321098765432109876543210
5019  *  001000               x1110000101
5020  *     rt -----
5021  *          rs -----
5022  *               rd -----
5023  */
5024 std::string NMD::CMPGU_LE_QB(uint64 instruction)
5025 {
5026     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5027     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5028     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5029
5030     std::string rd = GPR(copy(rd_value));
5031     std::string rs = GPR(copy(rs_value));
5032     std::string rt = GPR(copy(rt_value));
5033
5034     return img::format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt);
5035 }
5036
5037
5038 /*
5039  *
5040  *
5041  *   3         2         1
5042  *  10987654321098765432109876543210
5043  *  001000               x1110000101
5044  *     rt -----
5045  *          rs -----
5046  *               rd -----
5047  */
5048 std::string NMD::CMPGU_LT_QB(uint64 instruction)
5049 {
5050     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5051     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5052     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5053
5054     std::string rd = GPR(copy(rd_value));
5055     std::string rs = GPR(copy(rs_value));
5056     std::string rt = GPR(copy(rt_value));
5057
5058     return img::format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt);
5059 }
5060
5061
5062 /*
5063  *
5064  *
5065  *   3         2         1
5066  *  10987654321098765432109876543210
5067  *  001000               x1110000101
5068  *     rt -----
5069  *          rs -----
5070  *               rd -----
5071  */
5072 std::string NMD::CMPU_EQ_QB(uint64 instruction)
5073 {
5074     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5075     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5076
5077     std::string rs = GPR(copy(rs_value));
5078     std::string rt = GPR(copy(rt_value));
5079
5080     return img::format("CMPU.EQ.QB %s, %s", rs, rt);
5081 }
5082
5083
5084 /*
5085  *
5086  *
5087  *   3         2         1
5088  *  10987654321098765432109876543210
5089  *  001000               x1110000101
5090  *     rt -----
5091  *          rs -----
5092  *               rd -----
5093  */
5094 std::string NMD::CMPU_LE_QB(uint64 instruction)
5095 {
5096     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5098
5099     std::string rs = GPR(copy(rs_value));
5100     std::string rt = GPR(copy(rt_value));
5101
5102     return img::format("CMPU.LE.QB %s, %s", rs, rt);
5103 }
5104
5105
5106 /*
5107  *
5108  *
5109  *   3         2         1
5110  *  10987654321098765432109876543210
5111  *  001000               x1110000101
5112  *     rt -----
5113  *          rs -----
5114  *               rd -----
5115  */
5116 std::string NMD::CMPU_LT_QB(uint64 instruction)
5117 {
5118     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5120
5121     std::string rs = GPR(copy(rs_value));
5122     std::string rt = GPR(copy(rt_value));
5123
5124     return img::format("CMPU.LT.QB %s, %s", rs, rt);
5125 }
5126
5127
5128 /*
5129  *
5130  *
5131  *   3         2         1
5132  *  10987654321098765432109876543210
5133  *  001000               x1110000101
5134  *     rt -----
5135  *          rs -----
5136  *               rd -----
5137  */
5138 std::string NMD::COP2_1(uint64 instruction)
5139 {
5140     uint64 cofun_value = extract_cofun_25_24_23(instruction);
5141
5142     std::string cofun = IMMEDIATE(copy(cofun_value));
5143
5144     return img::format("COP2_1 %s", cofun);
5145 }
5146
5147
5148 /*
5149  *
5150  *
5151  *   3         2         1
5152  *  10987654321098765432109876543210
5153  *  001000               x1110000101
5154  *     rt -----
5155  *          rs -----
5156  *               rd -----
5157  */
5158 std::string NMD::CTC1(uint64 instruction)
5159 {
5160     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5161     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5162
5163     std::string rt = GPR(copy(rt_value));
5164     std::string cs = CPR(copy(cs_value));
5165
5166     return img::format("CTC1 %s, %s", rt, cs);
5167 }
5168
5169
5170 /*
5171  *
5172  *
5173  *   3         2         1
5174  *  10987654321098765432109876543210
5175  *  001000               x1110000101
5176  *     rt -----
5177  *          rs -----
5178  *               rd -----
5179  */
5180 std::string NMD::CTC2(uint64 instruction)
5181 {
5182     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5183     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5184
5185     std::string rt = GPR(copy(rt_value));
5186     std::string cs = CPR(copy(cs_value));
5187
5188     return img::format("CTC2 %s, %s", rt, cs);
5189 }
5190
5191
5192 /*
5193  *
5194  *
5195  *   3         2         1
5196  *  10987654321098765432109876543210
5197  *  001000               x1110000101
5198  *     rt -----
5199  *          rs -----
5200  *               rd -----
5201  */
5202 std::string NMD::CVT_D_L(uint64 instruction)
5203 {
5204     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5205     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5206
5207     std::string ft = FPR(copy(ft_value));
5208     std::string fs = FPR(copy(fs_value));
5209
5210     return img::format("CVT.D.L %s, %s", ft, fs);
5211 }
5212
5213
5214 /*
5215  *
5216  *
5217  *   3         2         1
5218  *  10987654321098765432109876543210
5219  *  001000               x1110000101
5220  *     rt -----
5221  *          rs -----
5222  *               rd -----
5223  */
5224 std::string NMD::CVT_D_S(uint64 instruction)
5225 {
5226     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5227     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5228
5229     std::string ft = FPR(copy(ft_value));
5230     std::string fs = FPR(copy(fs_value));
5231
5232     return img::format("CVT.D.S %s, %s", ft, fs);
5233 }
5234
5235
5236 /*
5237  *
5238  *
5239  *   3         2         1
5240  *  10987654321098765432109876543210
5241  *  001000               x1110000101
5242  *     rt -----
5243  *          rs -----
5244  *               rd -----
5245  */
5246 std::string NMD::CVT_D_W(uint64 instruction)
5247 {
5248     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5249     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5250
5251     std::string ft = FPR(copy(ft_value));
5252     std::string fs = FPR(copy(fs_value));
5253
5254     return img::format("CVT.D.W %s, %s", ft, fs);
5255 }
5256
5257
5258 /*
5259  *
5260  *
5261  *   3         2         1
5262  *  10987654321098765432109876543210
5263  *  001000               x1110000101
5264  *     rt -----
5265  *          rs -----
5266  *               rd -----
5267  */
5268 std::string NMD::CVT_L_D(uint64 instruction)
5269 {
5270     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5271     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5272
5273     std::string ft = FPR(copy(ft_value));
5274     std::string fs = FPR(copy(fs_value));
5275
5276     return img::format("CVT.L.D %s, %s", ft, fs);
5277 }
5278
5279
5280 /*
5281  *
5282  *
5283  *   3         2         1
5284  *  10987654321098765432109876543210
5285  *  001000               x1110000101
5286  *     rt -----
5287  *          rs -----
5288  *               rd -----
5289  */
5290 std::string NMD::CVT_L_S(uint64 instruction)
5291 {
5292     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5293     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5294
5295     std::string ft = FPR(copy(ft_value));
5296     std::string fs = FPR(copy(fs_value));
5297
5298     return img::format("CVT.L.S %s, %s", ft, fs);
5299 }
5300
5301
5302 /*
5303  *
5304  *
5305  *   3         2         1
5306  *  10987654321098765432109876543210
5307  *  001000               x1110000101
5308  *     rt -----
5309  *          rs -----
5310  *               rd -----
5311  */
5312 std::string NMD::CVT_S_D(uint64 instruction)
5313 {
5314     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5315     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5316
5317     std::string ft = FPR(copy(ft_value));
5318     std::string fs = FPR(copy(fs_value));
5319
5320     return img::format("CVT.S.D %s, %s", ft, fs);
5321 }
5322
5323
5324 /*
5325  *
5326  *
5327  *   3         2         1
5328  *  10987654321098765432109876543210
5329  *  001000               x1110000101
5330  *     rt -----
5331  *          rs -----
5332  *               rd -----
5333  */
5334 std::string NMD::CVT_S_L(uint64 instruction)
5335 {
5336     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5337     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5338
5339     std::string ft = FPR(copy(ft_value));
5340     std::string fs = FPR(copy(fs_value));
5341
5342     return img::format("CVT.S.L %s, %s", ft, fs);
5343 }
5344
5345
5346 /*
5347  *
5348  *
5349  *   3         2         1
5350  *  10987654321098765432109876543210
5351  *  001000               x1110000101
5352  *     rt -----
5353  *          rs -----
5354  *               rd -----
5355  */
5356 std::string NMD::CVT_S_PL(uint64 instruction)
5357 {
5358     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5359     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5360
5361     std::string ft = FPR(copy(ft_value));
5362     std::string fs = FPR(copy(fs_value));
5363
5364     return img::format("CVT.S.PL %s, %s", ft, fs);
5365 }
5366
5367
5368 /*
5369  *
5370  *
5371  *   3         2         1
5372  *  10987654321098765432109876543210
5373  *  001000               x1110000101
5374  *     rt -----
5375  *          rs -----
5376  *               rd -----
5377  */
5378 std::string NMD::CVT_S_PU(uint64 instruction)
5379 {
5380     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5381     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5382
5383     std::string ft = FPR(copy(ft_value));
5384     std::string fs = FPR(copy(fs_value));
5385
5386     return img::format("CVT.S.PU %s, %s", ft, fs);
5387 }
5388
5389
5390 /*
5391  *
5392  *
5393  *   3         2         1
5394  *  10987654321098765432109876543210
5395  *  001000               x1110000101
5396  *     rt -----
5397  *          rs -----
5398  *               rd -----
5399  */
5400 std::string NMD::CVT_S_W(uint64 instruction)
5401 {
5402     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5403     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5404
5405     std::string ft = FPR(copy(ft_value));
5406     std::string fs = FPR(copy(fs_value));
5407
5408     return img::format("CVT.S.W %s, %s", ft, fs);
5409 }
5410
5411
5412 /*
5413  *
5414  *
5415  *   3         2         1
5416  *  10987654321098765432109876543210
5417  *  001000               x1110000101
5418  *     rt -----
5419  *          rs -----
5420  *               rd -----
5421  */
5422 std::string NMD::CVT_W_D(uint64 instruction)
5423 {
5424     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5425     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5426
5427     std::string ft = FPR(copy(ft_value));
5428     std::string fs = FPR(copy(fs_value));
5429
5430     return img::format("CVT.W.D %s, %s", ft, fs);
5431 }
5432
5433
5434 /*
5435  *
5436  *
5437  *   3         2         1
5438  *  10987654321098765432109876543210
5439  *  001000               x1110000101
5440  *     rt -----
5441  *          rs -----
5442  *               rd -----
5443  */
5444 std::string NMD::CVT_W_S(uint64 instruction)
5445 {
5446     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5447     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5448
5449     std::string ft = FPR(copy(ft_value));
5450     std::string fs = FPR(copy(fs_value));
5451
5452     return img::format("CVT.W.S %s, %s", ft, fs);
5453 }
5454
5455
5456 /*
5457  *
5458  *
5459  *   3         2         1
5460  *  10987654321098765432109876543210
5461  *  001000               x1110000101
5462  *     rt -----
5463  *          rs -----
5464  *               rd -----
5465  */
5466 std::string NMD::DADDIU_48_(uint64 instruction)
5467 {
5468     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5469     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
5470
5471     std::string rt = GPR(copy(rt_value));
5472     std::string s = IMMEDIATE(copy(s_value));
5473
5474     return img::format("DADDIU %s, %s", rt, s);
5475 }
5476
5477
5478 /*
5479  *
5480  *
5481  *   3         2         1
5482  *  10987654321098765432109876543210
5483  *  001000               x1110000101
5484  *     rt -----
5485  *          rs -----
5486  *               rd -----
5487  */
5488 std::string NMD::DADDIU_NEG_(uint64 instruction)
5489 {
5490     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5491     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5492     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5493
5494     std::string rt = GPR(copy(rt_value));
5495     std::string rs = GPR(copy(rs_value));
5496     std::string u = IMMEDIATE(neg_copy(u_value));
5497
5498     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5499 }
5500
5501
5502 /*
5503  *
5504  *
5505  *   3         2         1
5506  *  10987654321098765432109876543210
5507  *  001000               x1110000101
5508  *     rt -----
5509  *          rs -----
5510  *               rd -----
5511  */
5512 std::string NMD::DADDIU_U12_(uint64 instruction)
5513 {
5514     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5515     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5516     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5517
5518     std::string rt = GPR(copy(rt_value));
5519     std::string rs = GPR(copy(rs_value));
5520     std::string u = IMMEDIATE(copy(u_value));
5521
5522     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5523 }
5524
5525
5526 /*
5527  *
5528  *
5529  *   3         2         1
5530  *  10987654321098765432109876543210
5531  *  001000               x1110000101
5532  *     rt -----
5533  *          rs -----
5534  *               rd -----
5535  */
5536 std::string NMD::DADD(uint64 instruction)
5537 {
5538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5539     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5540     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5541
5542     std::string rd = GPR(copy(rd_value));
5543     std::string rs = GPR(copy(rs_value));
5544     std::string rt = GPR(copy(rt_value));
5545
5546     return img::format("DADD %s, %s, %s", rd, rs, rt);
5547 }
5548
5549
5550 /*
5551  *
5552  *
5553  *   3         2         1
5554  *  10987654321098765432109876543210
5555  *  001000               x1110000101
5556  *     rt -----
5557  *          rs -----
5558  *               rd -----
5559  */
5560 std::string NMD::DADDU(uint64 instruction)
5561 {
5562     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5563     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5564     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5565
5566     std::string rd = GPR(copy(rd_value));
5567     std::string rs = GPR(copy(rs_value));
5568     std::string rt = GPR(copy(rt_value));
5569
5570     return img::format("DADDU %s, %s, %s", rd, rs, rt);
5571 }
5572
5573
5574 /*
5575  *
5576  *
5577  *   3         2         1
5578  *  10987654321098765432109876543210
5579  *  001000               x1110000101
5580  *     rt -----
5581  *          rs -----
5582  *               rd -----
5583  */
5584 std::string NMD::DCLO(uint64 instruction)
5585 {
5586     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5587     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5588
5589     std::string rt = GPR(copy(rt_value));
5590     std::string rs = GPR(copy(rs_value));
5591
5592     return img::format("DCLO %s, %s", rt, rs);
5593 }
5594
5595
5596 /*
5597  *
5598  *
5599  *   3         2         1
5600  *  10987654321098765432109876543210
5601  *  001000               x1110000101
5602  *     rt -----
5603  *          rs -----
5604  *               rd -----
5605  */
5606 std::string NMD::DCLZ(uint64 instruction)
5607 {
5608     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5609     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5610
5611     std::string rt = GPR(copy(rt_value));
5612     std::string rs = GPR(copy(rs_value));
5613
5614     return img::format("DCLZ %s, %s", rt, rs);
5615 }
5616
5617
5618 /*
5619  *
5620  *
5621  *   3         2         1
5622  *  10987654321098765432109876543210
5623  *  001000               x1110000101
5624  *     rt -----
5625  *          rs -----
5626  *               rd -----
5627  */
5628 std::string NMD::DDIV(uint64 instruction)
5629 {
5630     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5631     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5632     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5633
5634     std::string rd = GPR(copy(rd_value));
5635     std::string rs = GPR(copy(rs_value));
5636     std::string rt = GPR(copy(rt_value));
5637
5638     return img::format("DDIV %s, %s, %s", rd, rs, rt);
5639 }
5640
5641
5642 /*
5643  *
5644  *
5645  *   3         2         1
5646  *  10987654321098765432109876543210
5647  *  001000               x1110000101
5648  *     rt -----
5649  *          rs -----
5650  *               rd -----
5651  */
5652 std::string NMD::DDIVU(uint64 instruction)
5653 {
5654     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5655     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5656     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5657
5658     std::string rd = GPR(copy(rd_value));
5659     std::string rs = GPR(copy(rs_value));
5660     std::string rt = GPR(copy(rt_value));
5661
5662     return img::format("DDIVU %s, %s, %s", rd, rs, rt);
5663 }
5664
5665
5666 /*
5667  *
5668  *
5669  *   3         2         1
5670  *  10987654321098765432109876543210
5671  *  001000               x1110000101
5672  *     rt -----
5673  *          rs -----
5674  *               rd -----
5675  */
5676 std::string NMD::DERET(uint64 instruction)
5677 {
5678     (void)instruction;
5679
5680     return "DERET ";
5681 }
5682
5683
5684 /*
5685  *
5686  *
5687  *   3         2         1
5688  *  10987654321098765432109876543210
5689  *  001000               x1110000101
5690  *     rt -----
5691  *          rs -----
5692  *               rd -----
5693  */
5694 std::string NMD::DEXTM(uint64 instruction)
5695 {
5696     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5697     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5698     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5699     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5700
5701     std::string rt = GPR(copy(rt_value));
5702     std::string rs = GPR(copy(rs_value));
5703     std::string lsb = IMMEDIATE(copy(lsb_value));
5704     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5705
5706     return img::format("DEXTM %s, %s, %s, %s", rt, rs, lsb, msbd);
5707 }
5708
5709
5710 /*
5711  *
5712  *
5713  *   3         2         1
5714  *  10987654321098765432109876543210
5715  *  001000               x1110000101
5716  *     rt -----
5717  *          rs -----
5718  *               rd -----
5719  */
5720 std::string NMD::DEXT(uint64 instruction)
5721 {
5722     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5723     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5724     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5725     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5726
5727     std::string rt = GPR(copy(rt_value));
5728     std::string rs = GPR(copy(rs_value));
5729     std::string lsb = IMMEDIATE(copy(lsb_value));
5730     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5731
5732     return img::format("DEXT %s, %s, %s, %s", rt, rs, lsb, msbd);
5733 }
5734
5735
5736 /*
5737  *
5738  *
5739  *   3         2         1
5740  *  10987654321098765432109876543210
5741  *  001000               x1110000101
5742  *     rt -----
5743  *          rs -----
5744  *               rd -----
5745  */
5746 std::string NMD::DEXTU(uint64 instruction)
5747 {
5748     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5749     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5750     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5751     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5752
5753     std::string rt = GPR(copy(rt_value));
5754     std::string rs = GPR(copy(rs_value));
5755     std::string lsb = IMMEDIATE(copy(lsb_value));
5756     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5757
5758     return img::format("DEXTU %s, %s, %s, %s", rt, rs, lsb, msbd);
5759 }
5760
5761
5762 /*
5763  *
5764  *
5765  *   3         2         1
5766  *  10987654321098765432109876543210
5767  *  001000               x1110000101
5768  *     rt -----
5769  *          rs -----
5770  *               rd -----
5771  */
5772 std::string NMD::DINSM(uint64 instruction)
5773 {
5774     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5775     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5776     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5777     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5778
5779     std::string rt = GPR(copy(rt_value));
5780     std::string rs = GPR(copy(rs_value));
5781     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5782     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5783     /* !!!!!!!!!! - no conversion function */
5784
5785     return img::format("DINSM %s, %s, %s, %s", rt, rs, pos, size);
5786     /* hand edited */
5787 }
5788
5789
5790 /*
5791  *
5792  *
5793  *   3         2         1
5794  *  10987654321098765432109876543210
5795  *  001000               x1110000101
5796  *     rt -----
5797  *          rs -----
5798  *               rd -----
5799  */
5800 std::string NMD::DINS(uint64 instruction)
5801 {
5802     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5803     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5804     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5805     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5806
5807     std::string rt = GPR(copy(rt_value));
5808     std::string rs = GPR(copy(rs_value));
5809     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5810     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5811     /* !!!!!!!!!! - no conversion function */
5812
5813     return img::format("DINS %s, %s, %s, %s", rt, rs, pos, size);
5814     /* hand edited */
5815 }
5816
5817
5818 /*
5819  *
5820  *
5821  *   3         2         1
5822  *  10987654321098765432109876543210
5823  *  001000               x1110000101
5824  *     rt -----
5825  *          rs -----
5826  *               rd -----
5827  */
5828 std::string NMD::DINSU(uint64 instruction)
5829 {
5830     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5831     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5832     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5833     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5834
5835     std::string rt = GPR(copy(rt_value));
5836     std::string rs = GPR(copy(rs_value));
5837     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5838     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5839     /* !!!!!!!!!! - no conversion function */
5840
5841     return img::format("DINSU %s, %s, %s, %s", rt, rs, pos, size);
5842     /* hand edited */
5843 }
5844
5845
5846 /*
5847  *
5848  *
5849  *   3         2         1
5850  *  10987654321098765432109876543210
5851  *  001000               x1110000101
5852  *     rt -----
5853  *          rs -----
5854  *               rd -----
5855  */
5856 std::string NMD::DI(uint64 instruction)
5857 {
5858     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5859
5860     std::string rt = GPR(copy(rt_value));
5861
5862     return img::format("DI %s", rt);
5863 }
5864
5865
5866 /*
5867  *
5868  *
5869  *   3         2         1
5870  *  10987654321098765432109876543210
5871  *  001000               x1110000101
5872  *     rt -----
5873  *          rs -----
5874  *               rd -----
5875  */
5876 std::string NMD::DIV(uint64 instruction)
5877 {
5878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5879     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5881
5882     std::string rd = GPR(copy(rd_value));
5883     std::string rs = GPR(copy(rs_value));
5884     std::string rt = GPR(copy(rt_value));
5885
5886     return img::format("DIV %s, %s, %s", rd, rs, rt);
5887 }
5888
5889
5890 /*
5891  *
5892  *
5893  *   3         2         1
5894  *  10987654321098765432109876543210
5895  *  001000               x1110000101
5896  *     rt -----
5897  *          rs -----
5898  *               rd -----
5899  */
5900 std::string NMD::DIV_D(uint64 instruction)
5901 {
5902     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5903     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5904     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
5905
5906     std::string fd = FPR(copy(fd_value));
5907     std::string fs = FPR(copy(fs_value));
5908     std::string ft = FPR(copy(ft_value));
5909
5910     return img::format("DIV.D %s, %s, %s", fd, fs, ft);
5911 }
5912
5913
5914 /*
5915  *
5916  *
5917  *   3         2         1
5918  *  10987654321098765432109876543210
5919  *  001000               x1110000101
5920  *     rt -----
5921  *          rs -----
5922  *               rd -----
5923  */
5924 std::string NMD::DIV_S(uint64 instruction)
5925 {
5926     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
5927     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
5928     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
5929
5930     std::string fd = FPR(copy(fd_value));
5931     std::string fs = FPR(copy(fs_value));
5932     std::string ft = FPR(copy(ft_value));
5933
5934     return img::format("DIV.S %s, %s, %s", fd, fs, ft);
5935 }
5936
5937
5938 /*
5939  *
5940  *
5941  *   3         2         1
5942  *  10987654321098765432109876543210
5943  *  001000               x1110000101
5944  *     rt -----
5945  *          rs -----
5946  *               rd -----
5947  */
5948 std::string NMD::DIVU(uint64 instruction)
5949 {
5950     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5951     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5952     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5953
5954     std::string rd = GPR(copy(rd_value));
5955     std::string rs = GPR(copy(rs_value));
5956     std::string rt = GPR(copy(rt_value));
5957
5958     return img::format("DIVU %s, %s, %s", rd, rs, rt);
5959 }
5960
5961
5962 /*
5963  *
5964  *
5965  *   3         2         1
5966  *  10987654321098765432109876543210
5967  *  001000               x1110000101
5968  *     rt -----
5969  *          rs -----
5970  *               rd -----
5971  */
5972 std::string NMD::DLSA(uint64 instruction)
5973 {
5974     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5975     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
5976     uint64 u2_value = extract_u2_10_9(instruction);
5977     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5978
5979     std::string rd = GPR(copy(rd_value));
5980     std::string rs = GPR(copy(rs_value));
5981     std::string rt = GPR(copy(rt_value));
5982     std::string u2 = IMMEDIATE(copy(u2_value));
5983
5984     return img::format("DLSA %s, %s, %s, %s", rd, rs, rt, u2);
5985 }
5986
5987
5988 /*
5989  *
5990  *
5991  *   3         2         1
5992  *  10987654321098765432109876543210
5993  *  001000               x1110000101
5994  *     rt -----
5995  *          rs -----
5996  *               rd -----
5997  */
5998 std::string NMD::DLUI_48_(uint64 instruction)
5999 {
6000     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
6001     uint64 u_value = extr_uil0il32bs32Fmsb63(instruction);
6002
6003     std::string rt = GPR(copy(rt_value));
6004     std::string u = IMMEDIATE(copy(u_value));
6005
6006     return img::format("DLUI %s, %s", rt, u);
6007 }
6008
6009
6010 /*
6011  *
6012  *
6013  *   3         2         1
6014  *  10987654321098765432109876543210
6015  *  001000               x1110000101
6016  *     rt -----
6017  *          rs -----
6018  *               rd -----
6019  */
6020 std::string NMD::DMFC0(uint64 instruction)
6021 {
6022     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6023     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6024     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6025
6026     std::string rt = GPR(copy(rt_value));
6027     std::string c0s = CPR(copy(c0s_value));
6028     std::string sel = IMMEDIATE(copy(sel_value));
6029
6030     return img::format("DMFC0 %s, %s, %s", rt, c0s, sel);
6031 }
6032
6033
6034 /*
6035  *
6036  *
6037  *   3         2         1
6038  *  10987654321098765432109876543210
6039  *  001000               x1110000101
6040  *     rt -----
6041  *          rs -----
6042  *               rd -----
6043  */
6044 std::string NMD::DMFC1(uint64 instruction)
6045 {
6046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6047     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
6048
6049     std::string rt = GPR(copy(rt_value));
6050     std::string fs = FPR(copy(fs_value));
6051
6052     return img::format("DMFC1 %s, %s", rt, fs);
6053 }
6054
6055
6056 /*
6057  *
6058  *
6059  *   3         2         1
6060  *  10987654321098765432109876543210
6061  *  001000               x1110000101
6062  *     rt -----
6063  *          rs -----
6064  *               rd -----
6065  */
6066 std::string NMD::DMFC2(uint64 instruction)
6067 {
6068     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6069     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6070
6071     std::string rt = GPR(copy(rt_value));
6072     std::string cs = CPR(copy(cs_value));
6073
6074     return img::format("DMFC2 %s, %s", rt, cs);
6075 }
6076
6077
6078 /*
6079  *
6080  *
6081  *   3         2         1
6082  *  10987654321098765432109876543210
6083  *  001000               x1110000101
6084  *     rt -----
6085  *          rs -----
6086  *               rd -----
6087  */
6088 std::string NMD::DMFGC0(uint64 instruction)
6089 {
6090     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6091     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6092     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6093
6094     std::string rt = GPR(copy(rt_value));
6095     std::string c0s = CPR(copy(c0s_value));
6096     std::string sel = IMMEDIATE(copy(sel_value));
6097
6098     return img::format("DMFGC0 %s, %s, %s", rt, c0s, sel);
6099 }
6100
6101
6102 /*
6103  *
6104  *
6105  *   3         2         1
6106  *  10987654321098765432109876543210
6107  *  001000               x1110000101
6108  *     rt -----
6109  *          rs -----
6110  *               rd -----
6111  */
6112 std::string NMD::DMOD(uint64 instruction)
6113 {
6114     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6115     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6116     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6117
6118     std::string rd = GPR(copy(rd_value));
6119     std::string rs = GPR(copy(rs_value));
6120     std::string rt = GPR(copy(rt_value));
6121
6122     return img::format("DMOD %s, %s, %s", rd, rs, rt);
6123 }
6124
6125
6126 /*
6127  *
6128  *
6129  *   3         2         1
6130  *  10987654321098765432109876543210
6131  *  001000               x1110000101
6132  *     rt -----
6133  *          rs -----
6134  *               rd -----
6135  */
6136 std::string NMD::DMODU(uint64 instruction)
6137 {
6138     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6139     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6140     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6141
6142     std::string rd = GPR(copy(rd_value));
6143     std::string rs = GPR(copy(rs_value));
6144     std::string rt = GPR(copy(rt_value));
6145
6146     return img::format("DMODU %s, %s, %s", rd, rs, rt);
6147 }
6148
6149
6150 /*
6151  *
6152  *
6153  *   3         2         1
6154  *  10987654321098765432109876543210
6155  *  001000               x1110000101
6156  *     rt -----
6157  *          rs -----
6158  *               rd -----
6159  */
6160 std::string NMD::DMTC0(uint64 instruction)
6161 {
6162     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6163     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6164     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6165
6166     std::string rt = GPR(copy(rt_value));
6167     std::string c0s = CPR(copy(c0s_value));
6168     std::string sel = IMMEDIATE(copy(sel_value));
6169
6170     return img::format("DMTC0 %s, %s, %s", rt, c0s, sel);
6171 }
6172
6173
6174 /*
6175  *
6176  *
6177  *   3         2         1
6178  *  10987654321098765432109876543210
6179  *  001000               x1110000101
6180  *     rt -----
6181  *          rs -----
6182  *               rd -----
6183  */
6184 std::string NMD::DMTC1(uint64 instruction)
6185 {
6186     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6187     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
6188
6189     std::string rt = GPR(copy(rt_value));
6190     std::string fs = FPR(copy(fs_value));
6191
6192     return img::format("DMTC1 %s, %s", rt, fs);
6193 }
6194
6195
6196 /*
6197  *
6198  *
6199  *   3         2         1
6200  *  10987654321098765432109876543210
6201  *  001000               x1110000101
6202  *     rt -----
6203  *          rs -----
6204  *               rd -----
6205  */
6206 std::string NMD::DMTC2(uint64 instruction)
6207 {
6208     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6209     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6210
6211     std::string rt = GPR(copy(rt_value));
6212     std::string cs = CPR(copy(cs_value));
6213
6214     return img::format("DMTC2 %s, %s", rt, cs);
6215 }
6216
6217
6218 /*
6219  *
6220  *
6221  *   3         2         1
6222  *  10987654321098765432109876543210
6223  *  001000               x1110000101
6224  *     rt -----
6225  *          rs -----
6226  *               rd -----
6227  */
6228 std::string NMD::DMTGC0(uint64 instruction)
6229 {
6230     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6231     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6232     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6233
6234     std::string rt = GPR(copy(rt_value));
6235     std::string c0s = CPR(copy(c0s_value));
6236     std::string sel = IMMEDIATE(copy(sel_value));
6237
6238     return img::format("DMTGC0 %s, %s, %s", rt, c0s, sel);
6239 }
6240
6241
6242 /*
6243  *
6244  *
6245  *   3         2         1
6246  *  10987654321098765432109876543210
6247  *  001000               x1110000101
6248  *     rt -----
6249  *          rs -----
6250  *               rd -----
6251  */
6252 std::string NMD::DMT(uint64 instruction)
6253 {
6254     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6255
6256     std::string rt = GPR(copy(rt_value));
6257
6258     return img::format("DMT %s", rt);
6259 }
6260
6261
6262 /*
6263  *
6264  *
6265  *   3         2         1
6266  *  10987654321098765432109876543210
6267  *  001000               x1110000101
6268  *     rt -----
6269  *          rs -----
6270  *               rd -----
6271  */
6272 std::string NMD::DMUH(uint64 instruction)
6273 {
6274     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6275     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6276     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6277
6278     std::string rd = GPR(copy(rd_value));
6279     std::string rs = GPR(copy(rs_value));
6280     std::string rt = GPR(copy(rt_value));
6281
6282     return img::format("DMUH %s, %s, %s", rd, rs, rt);
6283 }
6284
6285
6286 /*
6287  *
6288  *
6289  *   3         2         1
6290  *  10987654321098765432109876543210
6291  *  001000               x1110000101
6292  *     rt -----
6293  *          rs -----
6294  *               rd -----
6295  */
6296 std::string NMD::DMUHU(uint64 instruction)
6297 {
6298     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6299     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6300     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6301
6302     std::string rd = GPR(copy(rd_value));
6303     std::string rs = GPR(copy(rs_value));
6304     std::string rt = GPR(copy(rt_value));
6305
6306     return img::format("DMUHU %s, %s, %s", rd, rs, rt);
6307 }
6308
6309
6310 /*
6311  *
6312  *
6313  *   3         2         1
6314  *  10987654321098765432109876543210
6315  *  001000               x1110000101
6316  *     rt -----
6317  *          rs -----
6318  *               rd -----
6319  */
6320 std::string NMD::DMUL(uint64 instruction)
6321 {
6322     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6323     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6324     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6325
6326     std::string rd = GPR(copy(rd_value));
6327     std::string rs = GPR(copy(rs_value));
6328     std::string rt = GPR(copy(rt_value));
6329
6330     return img::format("DMUL %s, %s, %s", rd, rs, rt);
6331 }
6332
6333
6334 /*
6335  *
6336  *
6337  *   3         2         1
6338  *  10987654321098765432109876543210
6339  *  001000               x1110000101
6340  *     rt -----
6341  *          rs -----
6342  *               rd -----
6343  */
6344 std::string NMD::DMULU(uint64 instruction)
6345 {
6346     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6347     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6348     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6349
6350     std::string rd = GPR(copy(rd_value));
6351     std::string rs = GPR(copy(rs_value));
6352     std::string rt = GPR(copy(rt_value));
6353
6354     return img::format("DMULU %s, %s, %s", rd, rs, rt);
6355 }
6356
6357
6358 /*
6359  *
6360  *
6361  *   3         2         1
6362  *  10987654321098765432109876543210
6363  *  001000               x1110000101
6364  *     rt -----
6365  *          rs -----
6366  *               rd -----
6367  */
6368 std::string NMD::DPA_W_PH(uint64 instruction)
6369 {
6370     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6371     uint64 ac_value = extract_ac_13_12(instruction);
6372     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6373
6374     std::string ac = AC(copy(ac_value));
6375     std::string rs = GPR(copy(rs_value));
6376     std::string rt = GPR(copy(rt_value));
6377
6378     return img::format("DPA.W.PH %s, %s, %s", ac, rs, rt);
6379 }
6380
6381
6382 /*
6383  *
6384  *
6385  *   3         2         1
6386  *  10987654321098765432109876543210
6387  *  001000               x1110000101
6388  *     rt -----
6389  *          rs -----
6390  *               rd -----
6391  */
6392 std::string NMD::DPAQ_SA_L_W(uint64 instruction)
6393 {
6394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6395     uint64 ac_value = extract_ac_13_12(instruction);
6396     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6397
6398     std::string ac = AC(copy(ac_value));
6399     std::string rs = GPR(copy(rs_value));
6400     std::string rt = GPR(copy(rt_value));
6401
6402     return img::format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt);
6403 }
6404
6405
6406 /*
6407  *
6408  *
6409  *   3         2         1
6410  *  10987654321098765432109876543210
6411  *  001000               x1110000101
6412  *     rt -----
6413  *          rs -----
6414  *               rd -----
6415  */
6416 std::string NMD::DPAQ_S_W_PH(uint64 instruction)
6417 {
6418     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6419     uint64 ac_value = extract_ac_13_12(instruction);
6420     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6421
6422     std::string ac = AC(copy(ac_value));
6423     std::string rs = GPR(copy(rs_value));
6424     std::string rt = GPR(copy(rt_value));
6425
6426     return img::format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt);
6427 }
6428
6429
6430 /*
6431  *
6432  *
6433  *   3         2         1
6434  *  10987654321098765432109876543210
6435  *  001000               x1110000101
6436  *     rt -----
6437  *          rs -----
6438  *               rd -----
6439  */
6440 std::string NMD::DPAQX_SA_W_PH(uint64 instruction)
6441 {
6442     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6443     uint64 ac_value = extract_ac_13_12(instruction);
6444     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6445
6446     std::string ac = AC(copy(ac_value));
6447     std::string rs = GPR(copy(rs_value));
6448     std::string rt = GPR(copy(rt_value));
6449
6450     return img::format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6451 }
6452
6453
6454 /*
6455  *
6456  *
6457  *   3         2         1
6458  *  10987654321098765432109876543210
6459  *  001000               x1110000101
6460  *     rt -----
6461  *          rs -----
6462  *               rd -----
6463  */
6464 std::string NMD::DPAQX_S_W_PH(uint64 instruction)
6465 {
6466     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6467     uint64 ac_value = extract_ac_13_12(instruction);
6468     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6469
6470     std::string ac = AC(copy(ac_value));
6471     std::string rs = GPR(copy(rs_value));
6472     std::string rt = GPR(copy(rt_value));
6473
6474     return img::format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt);
6475 }
6476
6477
6478 /*
6479  *
6480  *
6481  *   3         2         1
6482  *  10987654321098765432109876543210
6483  *  001000               x1110000101
6484  *     rt -----
6485  *          rs -----
6486  *               rd -----
6487  */
6488 std::string NMD::DPAU_H_QBL(uint64 instruction)
6489 {
6490     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6491     uint64 ac_value = extract_ac_13_12(instruction);
6492     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6493
6494     std::string ac = AC(copy(ac_value));
6495     std::string rs = GPR(copy(rs_value));
6496     std::string rt = GPR(copy(rt_value));
6497
6498     return img::format("DPAU.H.QBL %s, %s, %s", ac, rs, rt);
6499 }
6500
6501
6502 /*
6503  *
6504  *
6505  *   3         2         1
6506  *  10987654321098765432109876543210
6507  *  001000               x1110000101
6508  *     rt -----
6509  *          rs -----
6510  *               rd -----
6511  */
6512 std::string NMD::DPAU_H_QBR(uint64 instruction)
6513 {
6514     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6515     uint64 ac_value = extract_ac_13_12(instruction);
6516     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6517
6518     std::string ac = AC(copy(ac_value));
6519     std::string rs = GPR(copy(rs_value));
6520     std::string rt = GPR(copy(rt_value));
6521
6522     return img::format("DPAU.H.QBR %s, %s, %s", ac, rs, rt);
6523 }
6524
6525
6526 /*
6527  *
6528  *
6529  *   3         2         1
6530  *  10987654321098765432109876543210
6531  *  001000               x1110000101
6532  *     rt -----
6533  *          rs -----
6534  *               rd -----
6535  */
6536 std::string NMD::DPAX_W_PH(uint64 instruction)
6537 {
6538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6539     uint64 ac_value = extract_ac_13_12(instruction);
6540     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6541
6542     std::string ac = AC(copy(ac_value));
6543     std::string rs = GPR(copy(rs_value));
6544     std::string rt = GPR(copy(rt_value));
6545
6546     return img::format("DPAX.W.PH %s, %s, %s", ac, rs, rt);
6547 }
6548
6549
6550 /*
6551  *
6552  *
6553  *   3         2         1
6554  *  10987654321098765432109876543210
6555  *  001000               x1110000101
6556  *     rt -----
6557  *          rs -----
6558  *               rd -----
6559  */
6560 std::string NMD::DPS_W_PH(uint64 instruction)
6561 {
6562     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6563     uint64 ac_value = extract_ac_13_12(instruction);
6564     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6565
6566     std::string ac = AC(copy(ac_value));
6567     std::string rs = GPR(copy(rs_value));
6568     std::string rt = GPR(copy(rt_value));
6569
6570     return img::format("DPS.W.PH %s, %s, %s", ac, rs, rt);
6571 }
6572
6573
6574 /*
6575  *
6576  *
6577  *   3         2         1
6578  *  10987654321098765432109876543210
6579  *  001000               x1110000101
6580  *     rt -----
6581  *          rs -----
6582  *               rd -----
6583  */
6584 std::string NMD::DPSQ_SA_L_W(uint64 instruction)
6585 {
6586     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6587     uint64 ac_value = extract_ac_13_12(instruction);
6588     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6589
6590     std::string ac = AC(copy(ac_value));
6591     std::string rs = GPR(copy(rs_value));
6592     std::string rt = GPR(copy(rt_value));
6593
6594     return img::format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt);
6595 }
6596
6597
6598 /*
6599  *
6600  *
6601  *   3         2         1
6602  *  10987654321098765432109876543210
6603  *  001000               x1110000101
6604  *     rt -----
6605  *          rs -----
6606  *               rd -----
6607  */
6608 std::string NMD::DPSQ_S_W_PH(uint64 instruction)
6609 {
6610     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6611     uint64 ac_value = extract_ac_13_12(instruction);
6612     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6613
6614     std::string ac = AC(copy(ac_value));
6615     std::string rs = GPR(copy(rs_value));
6616     std::string rt = GPR(copy(rt_value));
6617
6618     return img::format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt);
6619 }
6620
6621
6622 /*
6623  *
6624  *
6625  *   3         2         1
6626  *  10987654321098765432109876543210
6627  *  001000               x1110000101
6628  *     rt -----
6629  *          rs -----
6630  *               rd -----
6631  */
6632 std::string NMD::DPSQX_SA_W_PH(uint64 instruction)
6633 {
6634     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6635     uint64 ac_value = extract_ac_13_12(instruction);
6636     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6637
6638     std::string ac = AC(copy(ac_value));
6639     std::string rs = GPR(copy(rs_value));
6640     std::string rt = GPR(copy(rt_value));
6641
6642     return img::format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6643 }
6644
6645
6646 /*
6647  *
6648  *
6649  *   3         2         1
6650  *  10987654321098765432109876543210
6651  *  001000               x1110000101
6652  *     rt -----
6653  *          rs -----
6654  *               rd -----
6655  */
6656 std::string NMD::DPSQX_S_W_PH(uint64 instruction)
6657 {
6658     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6659     uint64 ac_value = extract_ac_13_12(instruction);
6660     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6661
6662     std::string ac = AC(copy(ac_value));
6663     std::string rs = GPR(copy(rs_value));
6664     std::string rt = GPR(copy(rt_value));
6665
6666     return img::format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt);
6667 }
6668
6669
6670 /*
6671  *
6672  *
6673  *   3         2         1
6674  *  10987654321098765432109876543210
6675  *  001000               x1110000101
6676  *     rt -----
6677  *          rs -----
6678  *               rd -----
6679  */
6680 std::string NMD::DPSU_H_QBL(uint64 instruction)
6681 {
6682     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6683     uint64 ac_value = extract_ac_13_12(instruction);
6684     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6685
6686     std::string ac = AC(copy(ac_value));
6687     std::string rs = GPR(copy(rs_value));
6688     std::string rt = GPR(copy(rt_value));
6689
6690     return img::format("DPSU.H.QBL %s, %s, %s", ac, rs, rt);
6691 }
6692
6693
6694 /*
6695  *
6696  *
6697  *   3         2         1
6698  *  10987654321098765432109876543210
6699  *  001000               x1110000101
6700  *     rt -----
6701  *          rs -----
6702  *               rd -----
6703  */
6704 std::string NMD::DPSU_H_QBR(uint64 instruction)
6705 {
6706     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6707     uint64 ac_value = extract_ac_13_12(instruction);
6708     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6709
6710     std::string ac = AC(copy(ac_value));
6711     std::string rs = GPR(copy(rs_value));
6712     std::string rt = GPR(copy(rt_value));
6713
6714     return img::format("DPSU.H.QBR %s, %s, %s", ac, rs, rt);
6715 }
6716
6717
6718 /*
6719  *
6720  *
6721  *   3         2         1
6722  *  10987654321098765432109876543210
6723  *  001000               x1110000101
6724  *     rt -----
6725  *          rs -----
6726  *               rd -----
6727  */
6728 std::string NMD::DPSX_W_PH(uint64 instruction)
6729 {
6730     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6731     uint64 ac_value = extract_ac_13_12(instruction);
6732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6733
6734     std::string ac = AC(copy(ac_value));
6735     std::string rs = GPR(copy(rs_value));
6736     std::string rt = GPR(copy(rt_value));
6737
6738     return img::format("DPSX.W.PH %s, %s, %s", ac, rs, rt);
6739 }
6740
6741
6742 /*
6743  * DROTR -
6744  *
6745  *   3         2         1
6746  *  10987654321098765432109876543210
6747  *  001000               x1110000101
6748  *     rt -----
6749  *          rs -----
6750  *               rd -----
6751  */
6752 std::string NMD::DROTR(uint64 instruction)
6753 {
6754     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6755     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6756     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6757
6758     std::string rt = GPR(copy(rt_value));
6759     std::string rs = GPR(copy(rs_value));
6760     std::string shift = IMMEDIATE(copy(shift_value));
6761
6762     return img::format("DROTR %s, %s, %s", rt, rs, shift);
6763 }
6764
6765
6766 /*
6767  * DROTR[32] -
6768  *
6769  *   3         2         1
6770  *  10987654321098765432109876543210
6771  *  10o000          1100xxx0110
6772  *     rt -----
6773  *          rs -----
6774  *                       shift -----
6775  */
6776 std::string NMD::DROTR32(uint64 instruction)
6777 {
6778     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6779     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6780     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6781
6782     std::string rt = GPR(copy(rt_value));
6783     std::string rs = GPR(copy(rs_value));
6784     std::string shift = IMMEDIATE(copy(shift_value));
6785
6786     return img::format("DROTR32 %s, %s, %s", rt, rs, shift);
6787 }
6788
6789
6790 /*
6791  *
6792  *
6793  *   3         2         1
6794  *  10987654321098765432109876543210
6795  *  001000               x1110000101
6796  *     rt -----
6797  *          rs -----
6798  *               rd -----
6799  */
6800 std::string NMD::DROTRV(uint64 instruction)
6801 {
6802     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6803     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6804     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6805
6806     std::string rd = GPR(copy(rd_value));
6807     std::string rs = GPR(copy(rs_value));
6808     std::string rt = GPR(copy(rt_value));
6809
6810     return img::format("DROTRV %s, %s, %s", rd, rs, rt);
6811 }
6812
6813
6814 /*
6815  *
6816  *
6817  *   3         2         1
6818  *  10987654321098765432109876543210
6819  *  001000               x1110000101
6820  *     rt -----
6821  *          rs -----
6822  *               rd -----
6823  */
6824 std::string NMD::DROTX(uint64 instruction)
6825 {
6826     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6827     uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction);
6828     uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction);
6829     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6830
6831     std::string rt = GPR(copy(rt_value));
6832     std::string rs = GPR(copy(rs_value));
6833     std::string shift = IMMEDIATE(copy(shift_value));
6834     std::string shiftx = IMMEDIATE(copy(shiftx_value));
6835
6836     return img::format("DROTX %s, %s, %s, %s", rt, rs, shift, shiftx);
6837 }
6838
6839
6840 /*
6841  * DSLL -
6842  *
6843  *   3         2         1
6844  *  10987654321098765432109876543210
6845  *  10o000          1100xxx0000
6846  *     rt -----
6847  *          rs -----
6848  *                       shift -----
6849  */
6850 std::string NMD::DSLL(uint64 instruction)
6851 {
6852     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6853     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6854     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6855
6856     std::string rt = GPR(copy(rt_value));
6857     std::string rs = GPR(copy(rs_value));
6858     std::string shift = IMMEDIATE(copy(shift_value));
6859
6860     return img::format("DSLL %s, %s, %s", rt, rs, shift);
6861 }
6862
6863
6864 /*
6865  * DSLL[32] -
6866  *
6867  *   3         2         1
6868  *  10987654321098765432109876543210
6869  *  10o000          1100xxx0000
6870  *     rt -----
6871  *          rs -----
6872  *                       shift -----
6873  */
6874 std::string NMD::DSLL32(uint64 instruction)
6875 {
6876     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6877     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6878     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6879
6880     std::string rt = GPR(copy(rt_value));
6881     std::string rs = GPR(copy(rs_value));
6882     std::string shift = IMMEDIATE(copy(shift_value));
6883
6884     return img::format("DSLL32 %s, %s, %s", rt, rs, shift);
6885 }
6886
6887
6888 /*
6889  *
6890  *
6891  *   3         2         1
6892  *  10987654321098765432109876543210
6893  *  001000               x1110000101
6894  *     rt -----
6895  *          rs -----
6896  *               rd -----
6897  */
6898 std::string NMD::DSLLV(uint64 instruction)
6899 {
6900     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6901     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6902     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6903
6904     std::string rd = GPR(copy(rd_value));
6905     std::string rs = GPR(copy(rs_value));
6906     std::string rt = GPR(copy(rt_value));
6907
6908     return img::format("DSLLV %s, %s, %s", rd, rs, rt);
6909 }
6910
6911
6912 /*
6913  * DSRA -
6914  *
6915  *   3         2         1
6916  *  10987654321098765432109876543210
6917  *  10o000          1100xxx0100
6918  *     rt -----
6919  *          rs -----
6920  *                       shift -----
6921  */
6922 std::string NMD::DSRA(uint64 instruction)
6923 {
6924     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6925     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6926     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6927
6928     std::string rt = GPR(copy(rt_value));
6929     std::string rs = GPR(copy(rs_value));
6930     std::string shift = IMMEDIATE(copy(shift_value));
6931
6932     return img::format("DSRA %s, %s, %s", rt, rs, shift);
6933 }
6934
6935
6936 /*
6937  * DSRA[32] -
6938  *
6939  *   3         2         1
6940  *  10987654321098765432109876543210
6941  *  10o000          1100xxx0100
6942  *     rt -----
6943  *          rs -----
6944  *                       shift -----
6945  */
6946 std::string NMD::DSRA32(uint64 instruction)
6947 {
6948     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6949     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6950     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6951
6952     std::string rt = GPR(copy(rt_value));
6953     std::string rs = GPR(copy(rs_value));
6954     std::string shift = IMMEDIATE(copy(shift_value));
6955
6956     return img::format("DSRA32 %s, %s, %s", rt, rs, shift);
6957 }
6958
6959
6960 /*
6961  *
6962  *
6963  *   3         2         1
6964  *  10987654321098765432109876543210
6965  *  001000               x1110000101
6966  *     rt -----
6967  *          rs -----
6968  *               rd -----
6969  */
6970 std::string NMD::DSRAV(uint64 instruction)
6971 {
6972     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6973     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
6974     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6975
6976     std::string rd = GPR(copy(rd_value));
6977     std::string rs = GPR(copy(rs_value));
6978     std::string rt = GPR(copy(rt_value));
6979
6980     return img::format("DSRAV %s, %s, %s", rd, rs, rt);
6981 }
6982
6983
6984 /*
6985  * DSRL -
6986  *
6987  *   3         2         1
6988  *  10987654321098765432109876543210
6989  *  10o000          1100xxx0100
6990  *     rt -----
6991  *          rs -----
6992  *                       shift -----
6993  */
6994 std::string NMD::DSRL(uint64 instruction)
6995 {
6996     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6997     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6998     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6999
7000     std::string rt = GPR(copy(rt_value));
7001     std::string rs = GPR(copy(rs_value));
7002     std::string shift = IMMEDIATE(copy(shift_value));
7003
7004     return img::format("DSRL %s, %s, %s", rt, rs, shift);
7005 }
7006
7007
7008 /*
7009  * DSRL[32] -
7010  *
7011  *   3         2         1
7012  *  10987654321098765432109876543210
7013  *  10o000          1100xxx0010
7014  *     rt -----
7015  *          rs -----
7016  *                       shift -----
7017  */
7018 std::string NMD::DSRL32(uint64 instruction)
7019 {
7020     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7021     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
7022     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7023
7024     std::string rt = GPR(copy(rt_value));
7025     std::string rs = GPR(copy(rs_value));
7026     std::string shift = IMMEDIATE(copy(shift_value));
7027
7028     return img::format("DSRL32 %s, %s, %s", rt, rs, shift);
7029 }
7030
7031
7032 /*
7033  *
7034  *
7035  *   3         2         1
7036  *  10987654321098765432109876543210
7037  *  001000               x1110000101
7038  *     rt -----
7039  *          rs -----
7040  *               rd -----
7041  */
7042 std::string NMD::DSRLV(uint64 instruction)
7043 {
7044     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7045     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7046     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7047
7048     std::string rd = GPR(copy(rd_value));
7049     std::string rs = GPR(copy(rs_value));
7050     std::string rt = GPR(copy(rt_value));
7051
7052     return img::format("DSRLV %s, %s, %s", rd, rs, rt);
7053 }
7054
7055
7056 /*
7057  *
7058  *
7059  *   3         2         1
7060  *  10987654321098765432109876543210
7061  *  001000               x1110000101
7062  *     rt -----
7063  *          rs -----
7064  *               rd -----
7065  */
7066 std::string NMD::DSUB(uint64 instruction)
7067 {
7068     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7069     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7070     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7071
7072     std::string rd = GPR(copy(rd_value));
7073     std::string rs = GPR(copy(rs_value));
7074     std::string rt = GPR(copy(rt_value));
7075
7076     return img::format("DSUB %s, %s, %s", rd, rs, rt);
7077 }
7078
7079
7080 /*
7081  *
7082  *
7083  *   3         2         1
7084  *  10987654321098765432109876543210
7085  *  001000               x1110000101
7086  *     rt -----
7087  *          rs -----
7088  *               rd -----
7089  */
7090 std::string NMD::DSUBU(uint64 instruction)
7091 {
7092     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7093     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7094     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7095
7096     std::string rd = GPR(copy(rd_value));
7097     std::string rs = GPR(copy(rs_value));
7098     std::string rt = GPR(copy(rt_value));
7099
7100     return img::format("DSUBU %s, %s, %s", rd, rs, rt);
7101 }
7102
7103
7104 /*
7105  *
7106  *
7107  *   3         2         1
7108  *  10987654321098765432109876543210
7109  *  001000               x1110000101
7110  *     rt -----
7111  *          rs -----
7112  *               rd -----
7113  */
7114 std::string NMD::DVPE(uint64 instruction)
7115 {
7116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7117
7118     std::string rt = GPR(copy(rt_value));
7119
7120     return img::format("DVPE %s", rt);
7121 }
7122
7123
7124 /*
7125  *
7126  *
7127  *   3         2         1
7128  *  10987654321098765432109876543210
7129  *  001000               x1110000101
7130  *     rt -----
7131  *          rs -----
7132  *               rd -----
7133  */
7134 std::string NMD::DVP(uint64 instruction)
7135 {
7136     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7137
7138     std::string rt = GPR(copy(rt_value));
7139
7140     return img::format("DVP %s", rt);
7141 }
7142
7143
7144 /*
7145  *
7146  *
7147  *   3         2         1
7148  *  10987654321098765432109876543210
7149  *  001000               x1110000101
7150  *     rt -----
7151  *          rs -----
7152  *               rd -----
7153  */
7154 std::string NMD::EHB(uint64 instruction)
7155 {
7156     (void)instruction;
7157
7158     return "EHB ";
7159 }
7160
7161
7162 /*
7163  *
7164  *
7165  *   3         2         1
7166  *  10987654321098765432109876543210
7167  *  001000               x1110000101
7168  *     rt -----
7169  *          rs -----
7170  *               rd -----
7171  */
7172 std::string NMD::EI(uint64 instruction)
7173 {
7174     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7175
7176     std::string rt = GPR(copy(rt_value));
7177
7178     return img::format("EI %s", rt);
7179 }
7180
7181
7182 /*
7183  *
7184  *
7185  *   3         2         1
7186  *  10987654321098765432109876543210
7187  *  001000               x1110000101
7188  *     rt -----
7189  *          rs -----
7190  *               rd -----
7191  */
7192 std::string NMD::EMT(uint64 instruction)
7193 {
7194     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7195
7196     std::string rt = GPR(copy(rt_value));
7197
7198     return img::format("EMT %s", rt);
7199 }
7200
7201
7202 /*
7203  *
7204  *
7205  *   3         2         1
7206  *  10987654321098765432109876543210
7207  *  001000               x1110000101
7208  *     rt -----
7209  *          rs -----
7210  *               rd -----
7211  */
7212 std::string NMD::ERET(uint64 instruction)
7213 {
7214     (void)instruction;
7215
7216     return "ERET ";
7217 }
7218
7219
7220 /*
7221  *
7222  *
7223  *   3         2         1
7224  *  10987654321098765432109876543210
7225  *  001000               x1110000101
7226  *     rt -----
7227  *          rs -----
7228  *               rd -----
7229  */
7230 std::string NMD::ERETNC(uint64 instruction)
7231 {
7232     (void)instruction;
7233
7234     return "ERETNC ";
7235 }
7236
7237
7238 /*
7239  *
7240  *
7241  *   3         2         1
7242  *  10987654321098765432109876543210
7243  *  001000               x1110000101
7244  *     rt -----
7245  *          rs -----
7246  *               rd -----
7247  */
7248 std::string NMD::EVP(uint64 instruction)
7249 {
7250     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7251
7252     std::string rt = GPR(copy(rt_value));
7253
7254     return img::format("EVP %s", rt);
7255 }
7256
7257
7258 /*
7259  *
7260  *
7261  *   3         2         1
7262  *  10987654321098765432109876543210
7263  *  001000               x1110000101
7264  *     rt -----
7265  *          rs -----
7266  *               rd -----
7267  */
7268 std::string NMD::EVPE(uint64 instruction)
7269 {
7270     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7271
7272     std::string rt = GPR(copy(rt_value));
7273
7274     return img::format("EVPE %s", rt);
7275 }
7276
7277
7278 /*
7279  *
7280  *
7281  *   3         2         1
7282  *  10987654321098765432109876543210
7283  *  001000               x1110000101
7284  *     rt -----
7285  *          rs -----
7286  *               rd -----
7287  */
7288 std::string NMD::EXT(uint64 instruction)
7289 {
7290     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7291     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7292     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7293     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7294
7295     std::string rt = GPR(copy(rt_value));
7296     std::string rs = GPR(copy(rs_value));
7297     std::string lsb = IMMEDIATE(copy(lsb_value));
7298     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
7299
7300     return img::format("EXT %s, %s, %s, %s", rt, rs, lsb, msbd);
7301 }
7302
7303
7304 /*
7305  *
7306  *
7307  *   3         2         1
7308  *  10987654321098765432109876543210
7309  *  001000               x1110000101
7310  *     rt -----
7311  *          rs -----
7312  *               rd -----
7313  */
7314 std::string NMD::EXTD(uint64 instruction)
7315 {
7316     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7317     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7318     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7320
7321     std::string rd = GPR(copy(rd_value));
7322     std::string rs = GPR(copy(rs_value));
7323     std::string rt = GPR(copy(rt_value));
7324     std::string shift = IMMEDIATE(copy(shift_value));
7325
7326     return img::format("EXTD %s, %s, %s, %s", rd, rs, rt, shift);
7327 }
7328
7329
7330 /*
7331  *
7332  *
7333  *   3         2         1
7334  *  10987654321098765432109876543210
7335  *  001000               x1110000101
7336  *     rt -----
7337  *          rs -----
7338  *               rd -----
7339  */
7340 std::string NMD::EXTD32(uint64 instruction)
7341 {
7342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7343     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7344     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7345     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7346
7347     std::string rd = GPR(copy(rd_value));
7348     std::string rs = GPR(copy(rs_value));
7349     std::string rt = GPR(copy(rt_value));
7350     std::string shift = IMMEDIATE(copy(shift_value));
7351
7352     return img::format("EXTD32 %s, %s, %s, %s", rd, rs, rt, shift);
7353 }
7354
7355
7356 /*
7357  *
7358  *
7359  *   3         2         1
7360  *  10987654321098765432109876543210
7361  *  001000               x1110000101
7362  *     rt -----
7363  *          rs -----
7364  *               rd -----
7365  */
7366 std::string NMD::EXTPDP(uint64 instruction)
7367 {
7368     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7369     uint64 ac_value = extract_ac_13_12(instruction);
7370     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7371
7372     std::string rt = GPR(copy(rt_value));
7373     std::string ac = AC(copy(ac_value));
7374     std::string size = IMMEDIATE(copy(size_value));
7375
7376     return img::format("EXTPDP %s, %s, %s", rt, ac, size);
7377 }
7378
7379
7380 /*
7381  *
7382  *
7383  *   3         2         1
7384  *  10987654321098765432109876543210
7385  *  001000               x1110000101
7386  *     rt -----
7387  *          rs -----
7388  *               rd -----
7389  */
7390 std::string NMD::EXTPDPV(uint64 instruction)
7391 {
7392     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7393     uint64 ac_value = extract_ac_13_12(instruction);
7394     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7395
7396     std::string rt = GPR(copy(rt_value));
7397     std::string ac = AC(copy(ac_value));
7398     std::string rs = GPR(copy(rs_value));
7399
7400     return img::format("EXTPDPV %s, %s, %s", rt, ac, rs);
7401 }
7402
7403
7404 /*
7405  *
7406  *
7407  *   3         2         1
7408  *  10987654321098765432109876543210
7409  *  001000               x1110000101
7410  *     rt -----
7411  *          rs -----
7412  *               rd -----
7413  */
7414 std::string NMD::EXTP(uint64 instruction)
7415 {
7416     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7417     uint64 ac_value = extract_ac_13_12(instruction);
7418     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7419
7420     std::string rt = GPR(copy(rt_value));
7421     std::string ac = AC(copy(ac_value));
7422     std::string size = IMMEDIATE(copy(size_value));
7423
7424     return img::format("EXTP %s, %s, %s", rt, ac, size);
7425 }
7426
7427
7428 /*
7429  *
7430  *
7431  *   3         2         1
7432  *  10987654321098765432109876543210
7433  *  001000               x1110000101
7434  *     rt -----
7435  *          rs -----
7436  *               rd -----
7437  */
7438 std::string NMD::EXTPV(uint64 instruction)
7439 {
7440     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7441     uint64 ac_value = extract_ac_13_12(instruction);
7442     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7443
7444     std::string rt = GPR(copy(rt_value));
7445     std::string ac = AC(copy(ac_value));
7446     std::string rs = GPR(copy(rs_value));
7447
7448     return img::format("EXTPV %s, %s, %s", rt, ac, rs);
7449 }
7450
7451
7452 /*
7453  *
7454  *
7455  *   3         2         1
7456  *  10987654321098765432109876543210
7457  *  001000               x1110000101
7458  *     rt -----
7459  *          rs -----
7460  *               rd -----
7461  */
7462 std::string NMD::EXTR_RS_W(uint64 instruction)
7463 {
7464     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7465     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7466     uint64 ac_value = extract_ac_13_12(instruction);
7467
7468     std::string rt = GPR(copy(rt_value));
7469     std::string ac = AC(copy(ac_value));
7470     std::string shift = IMMEDIATE(copy(shift_value));
7471
7472     return img::format("EXTR_RS.W %s, %s, %s", rt, ac, shift);
7473 }
7474
7475
7476 /*
7477  *
7478  *
7479  *   3         2         1
7480  *  10987654321098765432109876543210
7481  *  001000               x1110000101
7482  *     rt -----
7483  *          rs -----
7484  *               rd -----
7485  */
7486 std::string NMD::EXTR_R_W(uint64 instruction)
7487 {
7488     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7489     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7490     uint64 ac_value = extract_ac_13_12(instruction);
7491
7492     std::string rt = GPR(copy(rt_value));
7493     std::string ac = AC(copy(ac_value));
7494     std::string shift = IMMEDIATE(copy(shift_value));
7495
7496     return img::format("EXTR_R.W %s, %s, %s", rt, ac, shift);
7497 }
7498
7499
7500 /*
7501  *
7502  *
7503  *   3         2         1
7504  *  10987654321098765432109876543210
7505  *  001000               x1110000101
7506  *     rt -----
7507  *          rs -----
7508  *               rd -----
7509  */
7510 std::string NMD::EXTR_S_H(uint64 instruction)
7511 {
7512     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7513     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7514     uint64 ac_value = extract_ac_13_12(instruction);
7515
7516     std::string rt = GPR(copy(rt_value));
7517     std::string ac = AC(copy(ac_value));
7518     std::string shift = IMMEDIATE(copy(shift_value));
7519
7520     return img::format("EXTR_S.H %s, %s, %s", rt, ac, shift);
7521 }
7522
7523
7524 /*
7525  *
7526  *
7527  *   3         2         1
7528  *  10987654321098765432109876543210
7529  *  001000               x1110000101
7530  *     rt -----
7531  *          rs -----
7532  *               rd -----
7533  */
7534 std::string NMD::EXTR_W(uint64 instruction)
7535 {
7536     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7537     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7538     uint64 ac_value = extract_ac_13_12(instruction);
7539
7540     std::string rt = GPR(copy(rt_value));
7541     std::string ac = AC(copy(ac_value));
7542     std::string shift = IMMEDIATE(copy(shift_value));
7543
7544     return img::format("EXTR.W %s, %s, %s", rt, ac, shift);
7545 }
7546
7547
7548 /*
7549  *
7550  *
7551  *   3         2         1
7552  *  10987654321098765432109876543210
7553  *  001000               x1110000101
7554  *     rt -----
7555  *          rs -----
7556  *               rd -----
7557  */
7558 std::string NMD::EXTRV_RS_W(uint64 instruction)
7559 {
7560     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7561     uint64 ac_value = extract_ac_13_12(instruction);
7562     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7563
7564     std::string rt = GPR(copy(rt_value));
7565     std::string ac = AC(copy(ac_value));
7566     std::string rs = GPR(copy(rs_value));
7567
7568     return img::format("EXTRV_RS.W %s, %s, %s", rt, ac, rs);
7569 }
7570
7571
7572 /*
7573  *
7574  *
7575  *   3         2         1
7576  *  10987654321098765432109876543210
7577  *  001000               x1110000101
7578  *     rt -----
7579  *          rs -----
7580  *               rd -----
7581  */
7582 std::string NMD::EXTRV_R_W(uint64 instruction)
7583 {
7584     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7585     uint64 ac_value = extract_ac_13_12(instruction);
7586     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7587
7588     std::string rt = GPR(copy(rt_value));
7589     std::string ac = AC(copy(ac_value));
7590     std::string rs = GPR(copy(rs_value));
7591
7592     return img::format("EXTRV_R.W %s, %s, %s", rt, ac, rs);
7593 }
7594
7595
7596 /*
7597  *
7598  *
7599  *   3         2         1
7600  *  10987654321098765432109876543210
7601  *  001000               x1110000101
7602  *     rt -----
7603  *          rs -----
7604  *               rd -----
7605  */
7606 std::string NMD::EXTRV_S_H(uint64 instruction)
7607 {
7608     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7609     uint64 ac_value = extract_ac_13_12(instruction);
7610     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7611
7612     std::string rt = GPR(copy(rt_value));
7613     std::string ac = AC(copy(ac_value));
7614     std::string rs = GPR(copy(rs_value));
7615
7616     return img::format("EXTRV_S.H %s, %s, %s", rt, ac, rs);
7617 }
7618
7619
7620 /*
7621  *
7622  *
7623  *   3         2         1
7624  *  10987654321098765432109876543210
7625  *  001000               x1110000101
7626  *     rt -----
7627  *          rs -----
7628  *               rd -----
7629  */
7630 std::string NMD::EXTRV_W(uint64 instruction)
7631 {
7632     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7633     uint64 ac_value = extract_ac_13_12(instruction);
7634     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7635
7636     std::string rt = GPR(copy(rt_value));
7637     std::string ac = AC(copy(ac_value));
7638     std::string rs = GPR(copy(rs_value));
7639
7640     return img::format("EXTRV.W %s, %s, %s", rt, ac, rs);
7641 }
7642
7643
7644 /*
7645  * EXTW - Extract Word
7646  *
7647  *   3         2         1
7648  *  10987654321098765432109876543210
7649  *  001000                    011111
7650  *     rt -----
7651  *          rs -----
7652  *               rd -----
7653  *                 shift -----
7654  */
7655 std::string NMD::EXTW(uint64 instruction)
7656 {
7657     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7658     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7659     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7660     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7661
7662     std::string rd = GPR(copy(rd_value));
7663     std::string rs = GPR(copy(rs_value));
7664     std::string rt = GPR(copy(rt_value));
7665     std::string shift = IMMEDIATE(copy(shift_value));
7666
7667     return img::format("EXTW %s, %s, %s, %s", rd, rs, rt, shift);
7668 }
7669
7670
7671 /*
7672  *
7673  *
7674  *   3         2         1
7675  *  10987654321098765432109876543210
7676  *  001000               x1110000101
7677  *     rt -----
7678  *          rs -----
7679  *               rd -----
7680  */
7681 std::string NMD::FLOOR_L_D(uint64 instruction)
7682 {
7683     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
7684     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
7685
7686     std::string ft = FPR(copy(ft_value));
7687     std::string fs = FPR(copy(fs_value));
7688
7689     return img::format("FLOOR.L.D %s, %s", ft, fs);
7690 }
7691
7692
7693 /*
7694  *
7695  *
7696  *   3         2         1
7697  *  10987654321098765432109876543210
7698  *  001000               x1110000101
7699  *     rt -----
7700  *          rs -----
7701  *               rd -----
7702  */
7703 std::string NMD::FLOOR_L_S(uint64 instruction)
7704 {
7705     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
7706     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
7707
7708     std::string ft = FPR(copy(ft_value));
7709     std::string fs = FPR(copy(fs_value));
7710
7711     return img::format("FLOOR.L.S %s, %s", ft, fs);
7712 }
7713
7714
7715 /*
7716  *
7717  *
7718  *   3         2         1
7719  *  10987654321098765432109876543210
7720  *  001000               x1110000101
7721  *     rt -----
7722  *          rs -----
7723  *               rd -----
7724  */
7725 std::string NMD::FLOOR_W_D(uint64 instruction)
7726 {
7727     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
7728     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
7729
7730     std::string ft = FPR(copy(ft_value));
7731     std::string fs = FPR(copy(fs_value));
7732
7733     return img::format("FLOOR.W.D %s, %s", ft, fs);
7734 }
7735
7736
7737 /*
7738  *
7739  *
7740  *   3         2         1
7741  *  10987654321098765432109876543210
7742  *  001000               x1110000101
7743  *     rt -----
7744  *          rs -----
7745  *               rd -----
7746  */
7747 std::string NMD::FLOOR_W_S(uint64 instruction)
7748 {
7749     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
7750     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
7751
7752     std::string ft = FPR(copy(ft_value));
7753     std::string fs = FPR(copy(fs_value));
7754
7755     return img::format("FLOOR.W.S %s, %s", ft, fs);
7756 }
7757
7758
7759 /*
7760  *
7761  *
7762  *   3         2         1
7763  *  10987654321098765432109876543210
7764  *  001000               x1110000101
7765  *     rt -----
7766  *          rs -----
7767  *               rd -----
7768  */
7769 std::string NMD::FORK(uint64 instruction)
7770 {
7771     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7772     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
7773     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7774
7775     std::string rd = GPR(copy(rd_value));
7776     std::string rs = GPR(copy(rs_value));
7777     std::string rt = GPR(copy(rt_value));
7778
7779     return img::format("FORK %s, %s, %s", rd, rs, rt);
7780 }
7781
7782
7783 /*
7784  *
7785  *
7786  *   3         2         1
7787  *  10987654321098765432109876543210
7788  *  001000               x1110000101
7789  *     rt -----
7790  *          rs -----
7791  *               rd -----
7792  */
7793 std::string NMD::HYPCALL(uint64 instruction)
7794 {
7795     uint64 code_value = extract_code_17_to_0(instruction);
7796
7797     std::string code = IMMEDIATE(copy(code_value));
7798
7799     return img::format("HYPCALL %s", code);
7800 }
7801
7802
7803 /*
7804  *
7805  *
7806  *   3         2         1
7807  *  10987654321098765432109876543210
7808  *  001000               x1110000101
7809  *     rt -----
7810  *          rs -----
7811  *               rd -----
7812  */
7813 std::string NMD::HYPCALL_16_(uint64 instruction)
7814 {
7815     uint64 code_value = extract_code_1_0(instruction);
7816
7817     std::string code = IMMEDIATE(copy(code_value));
7818
7819     return img::format("HYPCALL %s", code);
7820 }
7821
7822
7823 /*
7824  *
7825  *
7826  *   3         2         1
7827  *  10987654321098765432109876543210
7828  *  001000               x1110000101
7829  *     rt -----
7830  *          rs -----
7831  *               rd -----
7832  */
7833 std::string NMD::INS(uint64 instruction)
7834 {
7835     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7836     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7837     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7838     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7839
7840     std::string rt = GPR(copy(rt_value));
7841     std::string rs = GPR(copy(rs_value));
7842     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
7843     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
7844     /* !!!!!!!!!! - no conversion function */
7845
7846     return img::format("INS %s, %s, %s, %s", rt, rs, pos, size);
7847     /* hand edited */
7848 }
7849
7850
7851 /*
7852  *
7853  *
7854  *   3         2         1
7855  *  10987654321098765432109876543210
7856  *  001000               x1110000101
7857  *     rt -----
7858  *          rs -----
7859  *               rd -----
7860  */
7861 std::string NMD::INSV(uint64 instruction)
7862 {
7863     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7864     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7865
7866     std::string rt = GPR(copy(rt_value));
7867     std::string rs = GPR(copy(rs_value));
7868
7869     return img::format("INSV %s, %s", rt, rs);
7870 }
7871
7872
7873 /*
7874  *
7875  *
7876  *   3         2         1
7877  *  10987654321098765432109876543210
7878  *  001000               x1110000101
7879  *     rt -----
7880  *          rs -----
7881  *               rd -----
7882  */
7883 std::string NMD::IRET(uint64 instruction)
7884 {
7885     (void)instruction;
7886
7887     return "IRET ";
7888 }
7889
7890
7891 /*
7892  *
7893  *
7894  *   3         2         1
7895  *  10987654321098765432109876543210
7896  *  001000               x1110000101
7897  *     rt -----
7898  *          rs -----
7899  *               rd -----
7900  */
7901 std::string NMD::JALRC_16_(uint64 instruction)
7902 {
7903     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7904
7905     std::string rt = GPR(copy(rt_value));
7906
7907     return img::format("JALRC $%d, %s", 31, rt);
7908 }
7909
7910
7911 /*
7912  *
7913  *
7914  *   3         2         1
7915  *  10987654321098765432109876543210
7916  *  001000               x1110000101
7917  *     rt -----
7918  *          rs -----
7919  *               rd -----
7920  */
7921 std::string NMD::JALRC_32_(uint64 instruction)
7922 {
7923     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7924     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7925
7926     std::string rt = GPR(copy(rt_value));
7927     std::string rs = GPR(copy(rs_value));
7928
7929     return img::format("JALRC %s, %s", rt, rs);
7930 }
7931
7932
7933 /*
7934  *
7935  *
7936  *   3         2         1
7937  *  10987654321098765432109876543210
7938  *  001000               x1110000101
7939  *     rt -----
7940  *          rs -----
7941  *               rd -----
7942  */
7943 std::string NMD::JALRC_HB(uint64 instruction)
7944 {
7945     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7946     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7947
7948     std::string rt = GPR(copy(rt_value));
7949     std::string rs = GPR(copy(rs_value));
7950
7951     return img::format("JALRC.HB %s, %s", rt, rs);
7952 }
7953
7954
7955 /*
7956  *
7957  *
7958  *   3         2         1
7959  *  10987654321098765432109876543210
7960  *  001000               x1110000101
7961  *     rt -----
7962  *          rs -----
7963  *               rd -----
7964  */
7965 std::string NMD::JRC(uint64 instruction)
7966 {
7967     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7968
7969     std::string rt = GPR(copy(rt_value));
7970
7971     return img::format("JRC %s", rt);
7972 }
7973
7974
7975 /*
7976  *
7977  *
7978  *   3         2         1
7979  *  10987654321098765432109876543210
7980  *  001000               x1110000101
7981  *     rt -----
7982  *          rs -----
7983  *               rd -----
7984  */
7985 std::string NMD::LB_16_(uint64 instruction)
7986 {
7987     uint64 u_value = extract_u_1_0(instruction);
7988     uint64 rt3_value = extract_rt3_9_8_7(instruction);
7989     uint64 rs3_value = extract_rs3_6_5_4(instruction);
7990
7991     std::string rt3 = GPR(encode_gpr3(rt3_value));
7992     std::string u = IMMEDIATE(copy(u_value));
7993     std::string rs3 = GPR(encode_gpr3(rs3_value));
7994
7995     return img::format("LB %s, %s(%s)", rt3, u, rs3);
7996 }
7997
7998
7999 /*
8000  *
8001  *
8002  *   3         2         1
8003  *  10987654321098765432109876543210
8004  *  001000               x1110000101
8005  *     rt -----
8006  *          rs -----
8007  *               rd -----
8008  */
8009 std::string NMD::LB_GP_(uint64 instruction)
8010 {
8011     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8012     uint64 u_value = extract_u_17_to_0(instruction);
8013
8014     std::string rt = GPR(copy(rt_value));
8015     std::string u = IMMEDIATE(copy(u_value));
8016
8017     return img::format("LB %s, %s($%d)", rt, u, 28);
8018 }
8019
8020
8021 /*
8022  *
8023  *
8024  *   3         2         1
8025  *  10987654321098765432109876543210
8026  *  001000               x1110000101
8027  *     rt -----
8028  *          rs -----
8029  *               rd -----
8030  */
8031 std::string NMD::LB_S9_(uint64 instruction)
8032 {
8033     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8034     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8035     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8036
8037     std::string rt = GPR(copy(rt_value));
8038     std::string s = IMMEDIATE(copy(s_value));
8039     std::string rs = GPR(copy(rs_value));
8040
8041     return img::format("LB %s, %s(%s)", rt, s, rs);
8042 }
8043
8044
8045 /*
8046  *
8047  *
8048  *   3         2         1
8049  *  10987654321098765432109876543210
8050  *  001000               x1110000101
8051  *     rt -----
8052  *          rs -----
8053  *               rd -----
8054  */
8055 std::string NMD::LB_U12_(uint64 instruction)
8056 {
8057     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8058     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8059     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8060
8061     std::string rt = GPR(copy(rt_value));
8062     std::string u = IMMEDIATE(copy(u_value));
8063     std::string rs = GPR(copy(rs_value));
8064
8065     return img::format("LB %s, %s(%s)", rt, u, rs);
8066 }
8067
8068
8069 /*
8070  *
8071  *
8072  *   3         2         1
8073  *  10987654321098765432109876543210
8074  *  001000               x1110000101
8075  *     rt -----
8076  *          rs -----
8077  *               rd -----
8078  */
8079 std::string NMD::LBE(uint64 instruction)
8080 {
8081     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8082     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8083     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8084
8085     std::string rt = GPR(copy(rt_value));
8086     std::string s = IMMEDIATE(copy(s_value));
8087     std::string rs = GPR(copy(rs_value));
8088
8089     return img::format("LBE %s, %s(%s)", rt, s, rs);
8090 }
8091
8092
8093 /*
8094  *
8095  *
8096  *   3         2         1
8097  *  10987654321098765432109876543210
8098  *  001000               x1110000101
8099  *     rt -----
8100  *          rs -----
8101  *               rd -----
8102  */
8103 std::string NMD::LBU_16_(uint64 instruction)
8104 {
8105     uint64 u_value = extract_u_1_0(instruction);
8106     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8107     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8108
8109     std::string rt3 = GPR(encode_gpr3(rt3_value));
8110     std::string u = IMMEDIATE(copy(u_value));
8111     std::string rs3 = GPR(encode_gpr3(rs3_value));
8112
8113     return img::format("LBU %s, %s(%s)", rt3, u, rs3);
8114 }
8115
8116
8117 /*
8118  *
8119  *
8120  *   3         2         1
8121  *  10987654321098765432109876543210
8122  *  001000               x1110000101
8123  *     rt -----
8124  *          rs -----
8125  *               rd -----
8126  */
8127 std::string NMD::LBU_GP_(uint64 instruction)
8128 {
8129     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8130     uint64 u_value = extract_u_17_to_0(instruction);
8131
8132     std::string rt = GPR(copy(rt_value));
8133     std::string u = IMMEDIATE(copy(u_value));
8134
8135     return img::format("LBU %s, %s($%d)", rt, u, 28);
8136 }
8137
8138
8139 /*
8140  *
8141  *
8142  *   3         2         1
8143  *  10987654321098765432109876543210
8144  *  001000               x1110000101
8145  *     rt -----
8146  *          rs -----
8147  *               rd -----
8148  */
8149 std::string NMD::LBU_S9_(uint64 instruction)
8150 {
8151     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8152     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8153     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8154
8155     std::string rt = GPR(copy(rt_value));
8156     std::string s = IMMEDIATE(copy(s_value));
8157     std::string rs = GPR(copy(rs_value));
8158
8159     return img::format("LBU %s, %s(%s)", rt, s, rs);
8160 }
8161
8162
8163 /*
8164  *
8165  *
8166  *   3         2         1
8167  *  10987654321098765432109876543210
8168  *  001000               x1110000101
8169  *     rt -----
8170  *          rs -----
8171  *               rd -----
8172  */
8173 std::string NMD::LBU_U12_(uint64 instruction)
8174 {
8175     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8176     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8177     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8178
8179     std::string rt = GPR(copy(rt_value));
8180     std::string u = IMMEDIATE(copy(u_value));
8181     std::string rs = GPR(copy(rs_value));
8182
8183     return img::format("LBU %s, %s(%s)", rt, u, rs);
8184 }
8185
8186
8187 /*
8188  *
8189  *
8190  *   3         2         1
8191  *  10987654321098765432109876543210
8192  *  001000               x1110000101
8193  *     rt -----
8194  *          rs -----
8195  *               rd -----
8196  */
8197 std::string NMD::LBUE(uint64 instruction)
8198 {
8199     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8200     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8201     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8202
8203     std::string rt = GPR(copy(rt_value));
8204     std::string s = IMMEDIATE(copy(s_value));
8205     std::string rs = GPR(copy(rs_value));
8206
8207     return img::format("LBUE %s, %s(%s)", rt, s, rs);
8208 }
8209
8210
8211 /*
8212  *
8213  *
8214  *   3         2         1
8215  *  10987654321098765432109876543210
8216  *  001000               x1110000101
8217  *     rt -----
8218  *          rs -----
8219  *               rd -----
8220  */
8221 std::string NMD::LBUX(uint64 instruction)
8222 {
8223     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8224     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8225     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8226
8227     std::string rd = GPR(copy(rd_value));
8228     std::string rs = GPR(copy(rs_value));
8229     std::string rt = GPR(copy(rt_value));
8230
8231     return img::format("LBUX %s, %s(%s)", rd, rs, rt);
8232 }
8233
8234
8235 /*
8236  *
8237  *
8238  *   3         2         1
8239  *  10987654321098765432109876543210
8240  *  001000               x1110000101
8241  *     rt -----
8242  *          rs -----
8243  *               rd -----
8244  */
8245 std::string NMD::LBX(uint64 instruction)
8246 {
8247     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8248     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8249     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8250
8251     std::string rd = GPR(copy(rd_value));
8252     std::string rs = GPR(copy(rs_value));
8253     std::string rt = GPR(copy(rt_value));
8254
8255     return img::format("LBX %s, %s(%s)", rd, rs, rt);
8256 }
8257
8258
8259 /*
8260  *
8261  *
8262  *   3         2         1
8263  *  10987654321098765432109876543210
8264  *  001000               x1110000101
8265  *     rt -----
8266  *          rs -----
8267  *               rd -----
8268  */
8269 std::string NMD::LD_GP_(uint64 instruction)
8270 {
8271     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8272     uint64 u_value = extr_uil3il3bs18Fmsb20(instruction);
8273
8274     std::string rt = GPR(copy(rt_value));
8275     std::string u = IMMEDIATE(copy(u_value));
8276
8277     return img::format("LD %s, %s($%d)", rt, u, 28);
8278 }
8279
8280
8281 /*
8282  *
8283  *
8284  *   3         2         1
8285  *  10987654321098765432109876543210
8286  *  001000               x1110000101
8287  *     rt -----
8288  *          rs -----
8289  *               rd -----
8290  */
8291 std::string NMD::LD_S9_(uint64 instruction)
8292 {
8293     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8294     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8295     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8296
8297     std::string rt = GPR(copy(rt_value));
8298     std::string s = IMMEDIATE(copy(s_value));
8299     std::string rs = GPR(copy(rs_value));
8300
8301     return img::format("LD %s, %s(%s)", rt, s, rs);
8302 }
8303
8304
8305 /*
8306  *
8307  *
8308  *   3         2         1
8309  *  10987654321098765432109876543210
8310  *  001000               x1110000101
8311  *     rt -----
8312  *          rs -----
8313  *               rd -----
8314  */
8315 std::string NMD::LD_U12_(uint64 instruction)
8316 {
8317     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8318     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8320
8321     std::string rt = GPR(copy(rt_value));
8322     std::string u = IMMEDIATE(copy(u_value));
8323     std::string rs = GPR(copy(rs_value));
8324
8325     return img::format("LD %s, %s(%s)", rt, u, rs);
8326 }
8327
8328
8329 /*
8330  *
8331  *
8332  *   3         2         1
8333  *  10987654321098765432109876543210
8334  *  001000               x1110000101
8335  *     rt -----
8336  *          rs -----
8337  *               rd -----
8338  */
8339 std::string NMD::LDC1_GP_(uint64 instruction)
8340 {
8341     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
8342     uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);
8343
8344     std::string ft = FPR(copy(ft_value));
8345     std::string u = IMMEDIATE(copy(u_value));
8346
8347     return img::format("LDC1 %s, %s($%d)", ft, u, 28);
8348 }
8349
8350
8351 /*
8352  *
8353  *
8354  *   3         2         1
8355  *  10987654321098765432109876543210
8356  *  001000               x1110000101
8357  *     rt -----
8358  *          rs -----
8359  *               rd -----
8360  */
8361 std::string NMD::LDC1_S9_(uint64 instruction)
8362 {
8363     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8364     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
8365     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8366
8367     std::string ft = FPR(copy(ft_value));
8368     std::string s = IMMEDIATE(copy(s_value));
8369     std::string rs = GPR(copy(rs_value));
8370
8371     return img::format("LDC1 %s, %s(%s)", ft, s, rs);
8372 }
8373
8374
8375 /*
8376  *
8377  *
8378  *   3         2         1
8379  *  10987654321098765432109876543210
8380  *  001000               x1110000101
8381  *     rt -----
8382  *          rs -----
8383  *               rd -----
8384  */
8385 std::string NMD::LDC1_U12_(uint64 instruction)
8386 {
8387     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
8388     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8389     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8390
8391     std::string ft = FPR(copy(ft_value));
8392     std::string u = IMMEDIATE(copy(u_value));
8393     std::string rs = GPR(copy(rs_value));
8394
8395     return img::format("LDC1 %s, %s(%s)", ft, u, rs);
8396 }
8397
8398
8399 /*
8400  *
8401  *
8402  *   3         2         1
8403  *  10987654321098765432109876543210
8404  *  001000               x1110000101
8405  *     rt -----
8406  *          rs -----
8407  *               rd -----
8408  */
8409 std::string NMD::LDC1XS(uint64 instruction)
8410 {
8411     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8412     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8413     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8414
8415     std::string ft = FPR(copy(ft_value));
8416     std::string rs = GPR(copy(rs_value));
8417     std::string rt = GPR(copy(rt_value));
8418
8419     return img::format("LDC1XS %s, %s(%s)", ft, rs, rt);
8420 }
8421
8422
8423 /*
8424  *
8425  *
8426  *   3         2         1
8427  *  10987654321098765432109876543210
8428  *  001000               x1110000101
8429  *     rt -----
8430  *          rs -----
8431  *               rd -----
8432  */
8433 std::string NMD::LDC1X(uint64 instruction)
8434 {
8435     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8436     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8437     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8438
8439     std::string ft = FPR(copy(ft_value));
8440     std::string rs = GPR(copy(rs_value));
8441     std::string rt = GPR(copy(rt_value));
8442
8443     return img::format("LDC1X %s, %s(%s)", ft, rs, rt);
8444 }
8445
8446
8447 /*
8448  *
8449  *
8450  *   3         2         1
8451  *  10987654321098765432109876543210
8452  *  001000               x1110000101
8453  *     rt -----
8454  *          rs -----
8455  *               rd -----
8456  */
8457 std::string NMD::LDC2(uint64 instruction)
8458 {
8459     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8460     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
8461     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8462
8463     std::string ct = CPR(copy(ct_value));
8464     std::string s = IMMEDIATE(copy(s_value));
8465     std::string rs = GPR(copy(rs_value));
8466
8467     return img::format("LDC2 %s, %s(%s)", ct, s, rs);
8468 }
8469
8470
8471 /*
8472  *
8473  *
8474  *   3         2         1
8475  *  10987654321098765432109876543210
8476  *  001000               x1110000101
8477  *     rt -----
8478  *          rs -----
8479  *               rd -----
8480  */
8481 std::string NMD::LDM(uint64 instruction)
8482 {
8483     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8484     uint64 count3_value = extract_count3_14_13_12(instruction);
8485     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8486     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8487
8488     std::string rt = GPR(copy(rt_value));
8489     std::string s = IMMEDIATE(copy(s_value));
8490     std::string rs = GPR(copy(rs_value));
8491     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
8492
8493     return img::format("LDM %s, %s(%s), %s", rt, s, rs, count3);
8494 }
8495
8496
8497 /*
8498  *
8499  *
8500  *   3         2         1
8501  *  10987654321098765432109876543210
8502  *  001000               x1110000101
8503  *     rt -----
8504  *          rs -----
8505  *               rd -----
8506  */
8507 std::string NMD::LDPC_48_(uint64 instruction)
8508 {
8509     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8510     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
8511
8512     std::string rt = GPR(copy(rt_value));
8513     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
8514
8515     return img::format("LDPC %s, %s", rt, s);
8516 }
8517
8518
8519 /*
8520  *
8521  *
8522  *   3         2         1
8523  *  10987654321098765432109876543210
8524  *  001000               x1110000101
8525  *     rt -----
8526  *          rs -----
8527  *               rd -----
8528  */
8529 std::string NMD::LDX(uint64 instruction)
8530 {
8531     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8532     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8533     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8534
8535     std::string rd = GPR(copy(rd_value));
8536     std::string rs = GPR(copy(rs_value));
8537     std::string rt = GPR(copy(rt_value));
8538
8539     return img::format("LDX %s, %s(%s)", rd, rs, rt);
8540 }
8541
8542
8543 /*
8544  *
8545  *
8546  *   3         2         1
8547  *  10987654321098765432109876543210
8548  *  001000               x1110000101
8549  *     rt -----
8550  *          rs -----
8551  *               rd -----
8552  */
8553 std::string NMD::LDXS(uint64 instruction)
8554 {
8555     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8556     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8557     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8558
8559     std::string rd = GPR(copy(rd_value));
8560     std::string rs = GPR(copy(rs_value));
8561     std::string rt = GPR(copy(rt_value));
8562
8563     return img::format("LDXS %s, %s(%s)", rd, rs, rt);
8564 }
8565
8566
8567 /*
8568  *
8569  *
8570  *   3         2         1
8571  *  10987654321098765432109876543210
8572  *  001000               x1110000101
8573  *     rt -----
8574  *          rs -----
8575  *               rd -----
8576  */
8577 std::string NMD::LH_16_(uint64 instruction)
8578 {
8579     uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);
8580     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8581     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8582
8583     std::string rt3 = GPR(encode_gpr3(rt3_value));
8584     std::string u = IMMEDIATE(copy(u_value));
8585     std::string rs3 = GPR(encode_gpr3(rs3_value));
8586
8587     return img::format("LH %s, %s(%s)", rt3, u, rs3);
8588 }
8589
8590
8591 /*
8592  *
8593  *
8594  *   3         2         1
8595  *  10987654321098765432109876543210
8596  *  001000               x1110000101
8597  *     rt -----
8598  *          rs -----
8599  *               rd -----
8600  */
8601 std::string NMD::LH_GP_(uint64 instruction)
8602 {
8603     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8604     uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);
8605
8606     std::string rt = GPR(copy(rt_value));
8607     std::string u = IMMEDIATE(copy(u_value));
8608
8609     return img::format("LH %s, %s($%d)", rt, u, 28);
8610 }
8611
8612
8613 /*
8614  *
8615  *
8616  *   3         2         1
8617  *  10987654321098765432109876543210
8618  *  001000               x1110000101
8619  *     rt -----
8620  *          rs -----
8621  *               rd -----
8622  */
8623 std::string NMD::LH_S9_(uint64 instruction)
8624 {
8625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8626     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8627     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8628
8629     std::string rt = GPR(copy(rt_value));
8630     std::string s = IMMEDIATE(copy(s_value));
8631     std::string rs = GPR(copy(rs_value));
8632
8633     return img::format("LH %s, %s(%s)", rt, s, rs);
8634 }
8635
8636
8637 /*
8638  *
8639  *
8640  *   3         2         1
8641  *  10987654321098765432109876543210
8642  *  001000               x1110000101
8643  *     rt -----
8644  *          rs -----
8645  *               rd -----
8646  */
8647 std::string NMD::LH_U12_(uint64 instruction)
8648 {
8649     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8650     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8651     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8652
8653     std::string rt = GPR(copy(rt_value));
8654     std::string u = IMMEDIATE(copy(u_value));
8655     std::string rs = GPR(copy(rs_value));
8656
8657     return img::format("LH %s, %s(%s)", rt, u, rs);
8658 }
8659
8660
8661 /*
8662  *
8663  *
8664  *   3         2         1
8665  *  10987654321098765432109876543210
8666  *  001000               x1110000101
8667  *     rt -----
8668  *          rs -----
8669  *               rd -----
8670  */
8671 std::string NMD::LHE(uint64 instruction)
8672 {
8673     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8674     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8675     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8676
8677     std::string rt = GPR(copy(rt_value));
8678     std::string s = IMMEDIATE(copy(s_value));
8679     std::string rs = GPR(copy(rs_value));
8680
8681     return img::format("LHE %s, %s(%s)", rt, s, rs);
8682 }
8683
8684
8685 /*
8686  *
8687  *
8688  *   3         2         1
8689  *  10987654321098765432109876543210
8690  *  001000               x1110000101
8691  *     rt -----
8692  *          rs -----
8693  *               rd -----
8694  */
8695 std::string NMD::LHU_16_(uint64 instruction)
8696 {
8697     uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);
8698     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8699     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8700
8701     std::string rt3 = GPR(encode_gpr3(rt3_value));
8702     std::string u = IMMEDIATE(copy(u_value));
8703     std::string rs3 = GPR(encode_gpr3(rs3_value));
8704
8705     return img::format("LHU %s, %s(%s)", rt3, u, rs3);
8706 }
8707
8708
8709 /*
8710  *
8711  *
8712  *   3         2         1
8713  *  10987654321098765432109876543210
8714  *  001000               x1110000101
8715  *     rt -----
8716  *          rs -----
8717  *               rd -----
8718  */
8719 std::string NMD::LHU_GP_(uint64 instruction)
8720 {
8721     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8722     uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);
8723
8724     std::string rt = GPR(copy(rt_value));
8725     std::string u = IMMEDIATE(copy(u_value));
8726
8727     return img::format("LHU %s, %s($%d)", rt, u, 28);
8728 }
8729
8730
8731 /*
8732  *
8733  *
8734  *   3         2         1
8735  *  10987654321098765432109876543210
8736  *  001000               x1110000101
8737  *     rt -----
8738  *          rs -----
8739  *               rd -----
8740  */
8741 std::string NMD::LHU_S9_(uint64 instruction)
8742 {
8743     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8744     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8745     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8746
8747     std::string rt = GPR(copy(rt_value));
8748     std::string s = IMMEDIATE(copy(s_value));
8749     std::string rs = GPR(copy(rs_value));
8750
8751     return img::format("LHU %s, %s(%s)", rt, s, rs);
8752 }
8753
8754
8755 /*
8756  *
8757  *
8758  *   3         2         1
8759  *  10987654321098765432109876543210
8760  *  001000               x1110000101
8761  *     rt -----
8762  *          rs -----
8763  *               rd -----
8764  */
8765 std::string NMD::LHU_U12_(uint64 instruction)
8766 {
8767     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8768     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8769     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8770
8771     std::string rt = GPR(copy(rt_value));
8772     std::string u = IMMEDIATE(copy(u_value));
8773     std::string rs = GPR(copy(rs_value));
8774
8775     return img::format("LHU %s, %s(%s)", rt, u, rs);
8776 }
8777
8778
8779 /*
8780  *
8781  *
8782  *   3         2         1
8783  *  10987654321098765432109876543210
8784  *  001000               x1110000101
8785  *     rt -----
8786  *          rs -----
8787  *               rd -----
8788  */
8789 std::string NMD::LHUE(uint64 instruction)
8790 {
8791     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8792     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
8793     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8794
8795     std::string rt = GPR(copy(rt_value));
8796     std::string s = IMMEDIATE(copy(s_value));
8797     std::string rs = GPR(copy(rs_value));
8798
8799     return img::format("LHUE %s, %s(%s)", rt, s, rs);
8800 }
8801
8802
8803 /*
8804  *
8805  *
8806  *   3         2         1
8807  *  10987654321098765432109876543210
8808  *  001000               x1110000101
8809  *     rt -----
8810  *          rs -----
8811  *               rd -----
8812  */
8813 std::string NMD::LHUX(uint64 instruction)
8814 {
8815     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8816     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8817     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8818
8819     std::string rd = GPR(copy(rd_value));
8820     std::string rs = GPR(copy(rs_value));
8821     std::string rt = GPR(copy(rt_value));
8822
8823     return img::format("LHUX %s, %s(%s)", rd, rs, rt);
8824 }
8825
8826
8827 /*
8828  *
8829  *
8830  *   3         2         1
8831  *  10987654321098765432109876543210
8832  *  001000               x1110000101
8833  *     rt -----
8834  *          rs -----
8835  *               rd -----
8836  */
8837 std::string NMD::LHUXS(uint64 instruction)
8838 {
8839     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8840     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8841     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8842
8843     std::string rd = GPR(copy(rd_value));
8844     std::string rs = GPR(copy(rs_value));
8845     std::string rt = GPR(copy(rt_value));
8846
8847     return img::format("LHUXS %s, %s(%s)", rd, rs, rt);
8848 }
8849
8850
8851 /*
8852  *
8853  *
8854  *   3         2         1
8855  *  10987654321098765432109876543210
8856  *  001000               x1110000101
8857  *     rt -----
8858  *          rs -----
8859  *               rd -----
8860  */
8861 std::string NMD::LHXS(uint64 instruction)
8862 {
8863     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8864     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8865     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8866
8867     std::string rd = GPR(copy(rd_value));
8868     std::string rs = GPR(copy(rs_value));
8869     std::string rt = GPR(copy(rt_value));
8870
8871     return img::format("LHXS %s, %s(%s)", rd, rs, rt);
8872 }
8873
8874
8875 /*
8876  *
8877  *
8878  *   3         2         1
8879  *  10987654321098765432109876543210
8880  *  001000               x1110000101
8881  *     rt -----
8882  *          rs -----
8883  *               rd -----
8884  */
8885 std::string NMD::LHX(uint64 instruction)
8886 {
8887     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8888     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
8889     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8890
8891     std::string rd = GPR(copy(rd_value));
8892     std::string rs = GPR(copy(rs_value));
8893     std::string rt = GPR(copy(rt_value));
8894
8895     return img::format("LHX %s, %s(%s)", rd, rs, rt);
8896 }
8897
8898
8899 /*
8900  *
8901  *
8902  *   3         2         1
8903  *  10987654321098765432109876543210
8904  *  001000               x1110000101
8905  *     rt -----
8906  *          rs -----
8907  *               rd -----
8908  */
8909 std::string NMD::LI_16_(uint64 instruction)
8910 {
8911     uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction);
8912     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8913
8914     std::string rt3 = GPR(encode_gpr3(rt3_value));
8915     std::string eu = IMMEDIATE(encode_eu_from_s_li16(eu_value));
8916
8917     return img::format("LI %s, %s", rt3, eu);
8918 }
8919
8920
8921 /*
8922  *
8923  *
8924  *   3         2         1
8925  *  10987654321098765432109876543210
8926  *  001000               x1110000101
8927  *     rt -----
8928  *          rs -----
8929  *               rd -----
8930  */
8931 std::string NMD::LI_48_(uint64 instruction)
8932 {
8933     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8934     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
8935
8936     std::string rt = GPR(copy(rt_value));
8937     std::string s = IMMEDIATE(copy(s_value));
8938
8939     return img::format("LI %s, %s", rt, s);
8940 }
8941
8942
8943 /*
8944  *
8945  *
8946  *   3         2         1
8947  *  10987654321098765432109876543210
8948  *  001000               x1110000101
8949  *     rt -----
8950  *          rs -----
8951  *               rd -----
8952  */
8953 std::string NMD::LL(uint64 instruction)
8954 {
8955     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8956     int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);
8957     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8958
8959     std::string rt = GPR(copy(rt_value));
8960     std::string s = IMMEDIATE(copy(s_value));
8961     std::string rs = GPR(copy(rs_value));
8962
8963     return img::format("LL %s, %s(%s)", rt, s, rs);
8964 }
8965
8966
8967 /*
8968  *
8969  *
8970  *   3         2         1
8971  *  10987654321098765432109876543210
8972  *  001000               x1110000101
8973  *     rt -----
8974  *          rs -----
8975  *               rd -----
8976  */
8977 std::string NMD::LLD(uint64 instruction)
8978 {
8979     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8980     int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction);
8981     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8982
8983     std::string rt = GPR(copy(rt_value));
8984     std::string s = IMMEDIATE(copy(s_value));
8985     std::string rs = GPR(copy(rs_value));
8986
8987     return img::format("LLD %s, %s(%s)", rt, s, rs);
8988 }
8989
8990
8991 /*
8992  *
8993  *
8994  *   3         2         1
8995  *  10987654321098765432109876543210
8996  *  001000               x1110000101
8997  *     rt -----
8998  *          rs -----
8999  *               rd -----
9000  */
9001 std::string NMD::LLDP(uint64 instruction)
9002 {
9003     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9004     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9005     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9006
9007     std::string rt = GPR(copy(rt_value));
9008     std::string ru = GPR(copy(ru_value));
9009     std::string rs = GPR(copy(rs_value));
9010
9011     return img::format("LLDP %s, %s, (%s)", rt, ru, rs);
9012 }
9013
9014
9015 /*
9016  *
9017  *
9018  *   3         2         1
9019  *  10987654321098765432109876543210
9020  *  001000               x1110000101
9021  *     rt -----
9022  *          rs -----
9023  *               rd -----
9024  */
9025 std::string NMD::LLE(uint64 instruction)
9026 {
9027     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9028     int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);
9029     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9030
9031     std::string rt = GPR(copy(rt_value));
9032     std::string s = IMMEDIATE(copy(s_value));
9033     std::string rs = GPR(copy(rs_value));
9034
9035     return img::format("LLE %s, %s(%s)", rt, s, rs);
9036 }
9037
9038
9039 /*
9040  *
9041  *
9042  *   3         2         1
9043  *  10987654321098765432109876543210
9044  *  001000               x1110000101
9045  *     rt -----
9046  *          rs -----
9047  *               rd -----
9048  */
9049 std::string NMD::LLWP(uint64 instruction)
9050 {
9051     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9052     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9053     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9054
9055     std::string rt = GPR(copy(rt_value));
9056     std::string ru = GPR(copy(ru_value));
9057     std::string rs = GPR(copy(rs_value));
9058
9059     return img::format("LLWP %s, %s, (%s)", rt, ru, rs);
9060 }
9061
9062
9063 /*
9064  *
9065  *
9066  *   3         2         1
9067  *  10987654321098765432109876543210
9068  *  001000               x1110000101
9069  *     rt -----
9070  *          rs -----
9071  *               rd -----
9072  */
9073 std::string NMD::LLWPE(uint64 instruction)
9074 {
9075     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9076     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9077     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9078
9079     std::string rt = GPR(copy(rt_value));
9080     std::string ru = GPR(copy(ru_value));
9081     std::string rs = GPR(copy(rs_value));
9082
9083     return img::format("LLWPE %s, %s, (%s)", rt, ru, rs);
9084 }
9085
9086
9087 /*
9088  *
9089  *
9090  *   3         2         1
9091  *  10987654321098765432109876543210
9092  *  001000               x1110000101
9093  *     rt -----
9094  *          rs -----
9095  *               rd -----
9096  */
9097 std::string NMD::LSA(uint64 instruction)
9098 {
9099     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9100     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
9101     uint64 u2_value = extract_u2_10_9(instruction);
9102     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9103
9104     std::string rd = GPR(copy(rd_value));
9105     std::string rs = GPR(copy(rs_value));
9106     std::string rt = GPR(copy(rt_value));
9107     std::string u2 = IMMEDIATE(copy(u2_value));
9108
9109     return img::format("LSA %s, %s, %s, %s", rd, rs, rt, u2);
9110 }
9111
9112
9113 /*
9114  *
9115  *
9116  *   3         2         1
9117  *  10987654321098765432109876543210
9118  *  001000               x1110000101
9119  *     rt -----
9120  *          rs -----
9121  *               rd -----
9122  */
9123 std::string NMD::LUI(uint64 instruction)
9124 {
9125     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9126     int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction);
9127
9128     std::string rt = GPR(copy(rt_value));
9129     std::string s = IMMEDIATE(copy(s_value));
9130
9131     return img::format("LUI %s, %%hi(%s)", rt, s);
9132 }
9133
9134
9135 /*
9136  *
9137  *
9138  *   3         2         1
9139  *  10987654321098765432109876543210
9140  *  001000               x1110000101
9141  *     rt -----
9142  *          rs -----
9143  *               rd -----
9144  */
9145 std::string NMD::LW_16_(uint64 instruction)
9146 {
9147     uint64 u_value = extr_uil0il2bs4Fmsb5(instruction);
9148     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9149     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9150
9151     std::string rt3 = GPR(encode_gpr3(rt3_value));
9152     std::string u = IMMEDIATE(copy(u_value));
9153     std::string rs3 = GPR(encode_gpr3(rs3_value));
9154
9155     return img::format("LW %s, %s(%s)", rt3, u, rs3);
9156 }
9157
9158
9159 /*
9160  *
9161  *
9162  *   3         2         1
9163  *  10987654321098765432109876543210
9164  *  001000               x1110000101
9165  *     rt -----
9166  *          rs -----
9167  *               rd -----
9168  */
9169 std::string NMD::LW_4X4_(uint64 instruction)
9170 {
9171     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
9172     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
9173     uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction);
9174
9175     std::string rt4 = GPR(encode_gpr4(rt4_value));
9176     std::string u = IMMEDIATE(copy(u_value));
9177     std::string rs4 = GPR(encode_gpr4(rs4_value));
9178
9179     return img::format("LW %s, %s(%s)", rt4, u, rs4);
9180 }
9181
9182
9183 /*
9184  *
9185  *
9186  *   3         2         1
9187  *  10987654321098765432109876543210
9188  *  001000               x1110000101
9189  *     rt -----
9190  *          rs -----
9191  *               rd -----
9192  */
9193 std::string NMD::LW_GP_(uint64 instruction)
9194 {
9195     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9196     uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);
9197
9198     std::string rt = GPR(copy(rt_value));
9199     std::string u = IMMEDIATE(copy(u_value));
9200
9201     return img::format("LW %s, %s($%d)", rt, u, 28);
9202 }
9203
9204
9205 /*
9206  *
9207  *
9208  *   3         2         1
9209  *  10987654321098765432109876543210
9210  *  001000               x1110000101
9211  *     rt -----
9212  *          rs -----
9213  *               rd -----
9214  */
9215 std::string NMD::LW_GP16_(uint64 instruction)
9216 {
9217     uint64 u_value = extr_uil0il2bs7Fmsb8(instruction);
9218     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9219
9220     std::string rt3 = GPR(encode_gpr3(rt3_value));
9221     std::string u = IMMEDIATE(copy(u_value));
9222
9223     return img::format("LW %s, %s($%d)", rt3, u, 28);
9224 }
9225
9226
9227 /*
9228  *
9229  *
9230  *   3         2         1
9231  *  10987654321098765432109876543210
9232  *  001000               x1110000101
9233  *     rt -----
9234  *          rs -----
9235  *               rd -----
9236  */
9237 std::string NMD::LW_S9_(uint64 instruction)
9238 {
9239     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9240     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9242
9243     std::string rt = GPR(copy(rt_value));
9244     std::string s = IMMEDIATE(copy(s_value));
9245     std::string rs = GPR(copy(rs_value));
9246
9247     return img::format("LW %s, %s(%s)", rt, s, rs);
9248 }
9249
9250
9251 /*
9252  *
9253  *
9254  *   3         2         1
9255  *  10987654321098765432109876543210
9256  *  001000               x1110000101
9257  *     rt -----
9258  *          rs -----
9259  *               rd -----
9260  */
9261 std::string NMD::LW_SP_(uint64 instruction)
9262 {
9263     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
9264     uint64 u_value = extr_uil0il2bs5Fmsb6(instruction);
9265
9266     std::string rt = GPR(copy(rt_value));
9267     std::string u = IMMEDIATE(copy(u_value));
9268
9269     return img::format("LW %s, %s($%d)", rt, u, 29);
9270 }
9271
9272
9273 /*
9274  *
9275  *
9276  *   3         2         1
9277  *  10987654321098765432109876543210
9278  *  001000               x1110000101
9279  *     rt -----
9280  *          rs -----
9281  *               rd -----
9282  */
9283 std::string NMD::LW_U12_(uint64 instruction)
9284 {
9285     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9286     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9287     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9288
9289     std::string rt = GPR(copy(rt_value));
9290     std::string u = IMMEDIATE(copy(u_value));
9291     std::string rs = GPR(copy(rs_value));
9292
9293     return img::format("LW %s, %s(%s)", rt, u, rs);
9294 }
9295
9296
9297 /*
9298  *
9299  *
9300  *   3         2         1
9301  *  10987654321098765432109876543210
9302  *  001000               x1110000101
9303  *     rt -----
9304  *          rs -----
9305  *               rd -----
9306  */
9307 std::string NMD::LWC1_GP_(uint64 instruction)
9308 {
9309     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9310     uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);
9311
9312     std::string ft = FPR(copy(ft_value));
9313     std::string u = IMMEDIATE(copy(u_value));
9314
9315     return img::format("LWC1 %s, %s($%d)", ft, u, 28);
9316 }
9317
9318
9319 /*
9320  *
9321  *
9322  *   3         2         1
9323  *  10987654321098765432109876543210
9324  *  001000               x1110000101
9325  *     rt -----
9326  *          rs -----
9327  *               rd -----
9328  */
9329 std::string NMD::LWC1_S9_(uint64 instruction)
9330 {
9331     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9332     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9333     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9334
9335     std::string ft = FPR(copy(ft_value));
9336     std::string s = IMMEDIATE(copy(s_value));
9337     std::string rs = GPR(copy(rs_value));
9338
9339     return img::format("LWC1 %s, %s(%s)", ft, s, rs);
9340 }
9341
9342
9343 /*
9344  *
9345  *
9346  *   3         2         1
9347  *  10987654321098765432109876543210
9348  *  001000               x1110000101
9349  *     rt -----
9350  *          rs -----
9351  *               rd -----
9352  */
9353 std::string NMD::LWC1_U12_(uint64 instruction)
9354 {
9355     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9356     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9357     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9358
9359     std::string ft = FPR(copy(ft_value));
9360     std::string u = IMMEDIATE(copy(u_value));
9361     std::string rs = GPR(copy(rs_value));
9362
9363     return img::format("LWC1 %s, %s(%s)", ft, u, rs);
9364 }
9365
9366
9367 /*
9368  *
9369  *
9370  *   3         2         1
9371  *  10987654321098765432109876543210
9372  *  001000               x1110000101
9373  *     rt -----
9374  *          rs -----
9375  *               rd -----
9376  */
9377 std::string NMD::LWC1X(uint64 instruction)
9378 {
9379     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9380     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9381     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9382
9383     std::string ft = FPR(copy(ft_value));
9384     std::string rs = GPR(copy(rs_value));
9385     std::string rt = GPR(copy(rt_value));
9386
9387     return img::format("LWC1X %s, %s(%s)", ft, rs, rt);
9388 }
9389
9390
9391 /*
9392  *
9393  *
9394  *   3         2         1
9395  *  10987654321098765432109876543210
9396  *  001000               x1110000101
9397  *     rt -----
9398  *          rs -----
9399  *               rd -----
9400  */
9401 std::string NMD::LWC1XS(uint64 instruction)
9402 {
9403     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9404     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9405     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9406
9407     std::string ft = FPR(copy(ft_value));
9408     std::string rs = GPR(copy(rs_value));
9409     std::string rt = GPR(copy(rt_value));
9410
9411     return img::format("LWC1XS %s, %s(%s)", ft, rs, rt);
9412 }
9413
9414
9415 /*
9416  *
9417  *
9418  *   3         2         1
9419  *  10987654321098765432109876543210
9420  *  001000               x1110000101
9421  *     rt -----
9422  *          rs -----
9423  *               rd -----
9424  */
9425 std::string NMD::LWC2(uint64 instruction)
9426 {
9427     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9428     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
9429     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9430
9431     std::string ct = CPR(copy(ct_value));
9432     std::string s = IMMEDIATE(copy(s_value));
9433     std::string rs = GPR(copy(rs_value));
9434
9435     return img::format("LWC2 %s, %s(%s)", ct, s, rs);
9436 }
9437
9438
9439 /*
9440  *
9441  *
9442  *   3         2         1
9443  *  10987654321098765432109876543210
9444  *  001000               x1110000101
9445  *     rt -----
9446  *          rs -----
9447  *               rd -----
9448  */
9449 std::string NMD::LWE(uint64 instruction)
9450 {
9451     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9452     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9453     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9454
9455     std::string rt = GPR(copy(rt_value));
9456     std::string s = IMMEDIATE(copy(s_value));
9457     std::string rs = GPR(copy(rs_value));
9458
9459     return img::format("LWE %s, %s(%s)", rt, s, rs);
9460 }
9461
9462
9463 /*
9464  *
9465  *
9466  *   3         2         1
9467  *  10987654321098765432109876543210
9468  *  001000               x1110000101
9469  *     rt -----
9470  *          rs -----
9471  *               rd -----
9472  */
9473 std::string NMD::LWM(uint64 instruction)
9474 {
9475     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9476     uint64 count3_value = extract_count3_14_13_12(instruction);
9477     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9478     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9479
9480     std::string rt = GPR(copy(rt_value));
9481     std::string s = IMMEDIATE(copy(s_value));
9482     std::string rs = GPR(copy(rs_value));
9483     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
9484
9485     return img::format("LWM %s, %s(%s), %s", rt, s, rs, count3);
9486 }
9487
9488
9489 /*
9490  *
9491  *
9492  *   3         2         1
9493  *  10987654321098765432109876543210
9494  *  001000               x1110000101
9495  *     rt -----
9496  *          rs -----
9497  *               rd -----
9498  */
9499 std::string NMD::LWPC_48_(uint64 instruction)
9500 {
9501     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
9502     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
9503
9504     std::string rt = GPR(copy(rt_value));
9505     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
9506
9507     return img::format("LWPC %s, %s", rt, s);
9508 }
9509
9510
9511 /*
9512  *
9513  *
9514  *   3         2         1
9515  *  10987654321098765432109876543210
9516  *  001000               x1110000101
9517  *     rt -----
9518  *          rs -----
9519  *               rd -----
9520  */
9521 std::string NMD::LWU_GP_(uint64 instruction)
9522 {
9523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9524     uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);
9525
9526     std::string rt = GPR(copy(rt_value));
9527     std::string u = IMMEDIATE(copy(u_value));
9528
9529     return img::format("LWU %s, %s($%d)", rt, u, 28);
9530 }
9531
9532
9533 /*
9534  *
9535  *
9536  *   3         2         1
9537  *  10987654321098765432109876543210
9538  *  001000               x1110000101
9539  *     rt -----
9540  *          rs -----
9541  *               rd -----
9542  */
9543 std::string NMD::LWU_S9_(uint64 instruction)
9544 {
9545     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9546     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
9547     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9548
9549     std::string rt = GPR(copy(rt_value));
9550     std::string s = IMMEDIATE(copy(s_value));
9551     std::string rs = GPR(copy(rs_value));
9552
9553     return img::format("LWU %s, %s(%s)", rt, s, rs);
9554 }
9555
9556
9557 /*
9558  *
9559  *
9560  *   3         2         1
9561  *  10987654321098765432109876543210
9562  *  001000               x1110000101
9563  *     rt -----
9564  *          rs -----
9565  *               rd -----
9566  */
9567 std::string NMD::LWU_U12_(uint64 instruction)
9568 {
9569     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9570     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9572
9573     std::string rt = GPR(copy(rt_value));
9574     std::string u = IMMEDIATE(copy(u_value));
9575     std::string rs = GPR(copy(rs_value));
9576
9577     return img::format("LWU %s, %s(%s)", rt, u, rs);
9578 }
9579
9580
9581 /*
9582  *
9583  *
9584  *   3         2         1
9585  *  10987654321098765432109876543210
9586  *  001000               x1110000101
9587  *     rt -----
9588  *          rs -----
9589  *               rd -----
9590  */
9591 std::string NMD::LWUX(uint64 instruction)
9592 {
9593     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9594     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
9595     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9596
9597     std::string rd = GPR(copy(rd_value));
9598     std::string rs = GPR(copy(rs_value));
9599     std::string rt = GPR(copy(rt_value));
9600
9601     return img::format("LWUX %s, %s(%s)", rd, rs, rt);
9602 }
9603
9604
9605 /*
9606  *
9607  *
9608  *   3         2         1
9609  *  10987654321098765432109876543210
9610  *  001000               x1110000101
9611  *     rt -----
9612  *          rs -----
9613  *               rd -----
9614  */
9615 std::string NMD::LWUXS(uint64 instruction)
9616 {
9617     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9618     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
9619     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9620
9621     std::string rd = GPR(copy(rd_value));
9622     std::string rs = GPR(copy(rs_value));
9623     std::string rt = GPR(copy(rt_value));
9624
9625     return img::format("LWUXS %s, %s(%s)", rd, rs, rt);
9626 }
9627
9628
9629 /*
9630  *
9631  *
9632  *   3         2         1
9633  *  10987654321098765432109876543210
9634  *  001000               x1110000101
9635  *     rt -----
9636  *          rs -----
9637  *               rd -----
9638  */
9639 std::string NMD::LWX(uint64 instruction)
9640 {
9641     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9642     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
9643     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9644
9645     std::string rd = GPR(copy(rd_value));
9646     std::string rs = GPR(copy(rs_value));
9647     std::string rt = GPR(copy(rt_value));
9648
9649     return img::format("LWX %s, %s(%s)", rd, rs, rt);
9650 }
9651
9652
9653 /*
9654  *
9655  *
9656  *   3         2         1
9657  *  10987654321098765432109876543210
9658  *  001000               x1110000101
9659  *     rt -----
9660  *          rs -----
9661  *               rd -----
9662  */
9663 std::string NMD::LWXS_16_(uint64 instruction)
9664 {
9665     uint64 rd3_value = extract_rd3_3_2_1(instruction);
9666     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9667     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9668
9669     std::string rd3 = GPR(encode_gpr3(rd3_value));
9670     std::string rs3 = GPR(encode_gpr3(rs3_value));
9671     std::string rt3 = IMMEDIATE(encode_gpr3(rt3_value));
9672
9673     return img::format("LWXS %s, %s(%s)", rd3, rs3, rt3);
9674 }
9675
9676
9677 /*
9678  *
9679  *
9680  *   3         2         1
9681  *  10987654321098765432109876543210
9682  *  001000               x1110000101
9683  *     rt -----
9684  *          rs -----
9685  *               rd -----
9686  */
9687 std::string NMD::LWXS_32_(uint64 instruction)
9688 {
9689     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9690     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
9691     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9692
9693     std::string rd = GPR(copy(rd_value));
9694     std::string rs = GPR(copy(rs_value));
9695     std::string rt = GPR(copy(rt_value));
9696
9697     return img::format("LWXS %s, %s(%s)", rd, rs, rt);
9698 }
9699
9700
9701 /*
9702  *
9703  *
9704  *   3         2         1
9705  *  10987654321098765432109876543210
9706  *  001000               x1110000101
9707  *     rt -----
9708  *          rs -----
9709  *               rd -----
9710  */
9711 std::string NMD::MADD_DSP_(uint64 instruction)
9712 {
9713     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9714     uint64 ac_value = extract_ac_13_12(instruction);
9715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9716
9717     std::string ac = AC(copy(ac_value));
9718     std::string rs = GPR(copy(rs_value));
9719     std::string rt = GPR(copy(rt_value));
9720
9721     return img::format("MADD %s, %s, %s", ac, rs, rt);
9722 }
9723
9724
9725 /*
9726  *
9727  *
9728  *   3         2         1
9729  *  10987654321098765432109876543210
9730  *  001000               x1110000101
9731  *     rt -----
9732  *          rs -----
9733  *               rd -----
9734  */
9735 std::string NMD::MADDF_D(uint64 instruction)
9736 {
9737     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9738     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9739     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9740
9741     std::string fd = FPR(copy(fd_value));
9742     std::string fs = FPR(copy(fs_value));
9743     std::string ft = FPR(copy(ft_value));
9744
9745     return img::format("MADDF.D %s, %s, %s", fd, fs, ft);
9746 }
9747
9748
9749 /*
9750  *
9751  *
9752  *   3         2         1
9753  *  10987654321098765432109876543210
9754  *  001000               x1110000101
9755  *     rt -----
9756  *          rs -----
9757  *               rd -----
9758  */
9759 std::string NMD::MADDF_S(uint64 instruction)
9760 {
9761     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9762     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9763     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9764
9765     std::string fd = FPR(copy(fd_value));
9766     std::string fs = FPR(copy(fs_value));
9767     std::string ft = FPR(copy(ft_value));
9768
9769     return img::format("MADDF.S %s, %s, %s", fd, fs, ft);
9770 }
9771
9772
9773 /*
9774  *
9775  *
9776  *   3         2         1
9777  *  10987654321098765432109876543210
9778  *  001000               x1110000101
9779  *     rt -----
9780  *          rs -----
9781  *               rd -----
9782  */
9783 std::string NMD::MADDU_DSP_(uint64 instruction)
9784 {
9785     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9786     uint64 ac_value = extract_ac_13_12(instruction);
9787     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9788
9789     std::string ac = AC(copy(ac_value));
9790     std::string rs = GPR(copy(rs_value));
9791     std::string rt = GPR(copy(rt_value));
9792
9793     return img::format("MADDU %s, %s, %s", ac, rs, rt);
9794 }
9795
9796
9797 /*
9798  *
9799  *
9800  *   3         2         1
9801  *  10987654321098765432109876543210
9802  *  001000               x1110000101
9803  *     rt -----
9804  *          rs -----
9805  *               rd -----
9806  */
9807 std::string NMD::MAQ_S_W_PHL(uint64 instruction)
9808 {
9809     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9810     uint64 ac_value = extract_ac_13_12(instruction);
9811     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9812
9813     std::string ac = AC(copy(ac_value));
9814     std::string rs = GPR(copy(rs_value));
9815     std::string rt = GPR(copy(rt_value));
9816
9817     return img::format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt);
9818 }
9819
9820
9821 /*
9822  *
9823  *
9824  *   3         2         1
9825  *  10987654321098765432109876543210
9826  *  001000               x1110000101
9827  *     rt -----
9828  *          rs -----
9829  *               rd -----
9830  */
9831 std::string NMD::MAQ_S_W_PHR(uint64 instruction)
9832 {
9833     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9834     uint64 ac_value = extract_ac_13_12(instruction);
9835     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9836
9837     std::string ac = AC(copy(ac_value));
9838     std::string rs = GPR(copy(rs_value));
9839     std::string rt = GPR(copy(rt_value));
9840
9841     return img::format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt);
9842 }
9843
9844
9845 /*
9846  *
9847  *
9848  *   3         2         1
9849  *  10987654321098765432109876543210
9850  *  001000               x1110000101
9851  *     rt -----
9852  *          rs -----
9853  *               rd -----
9854  */
9855 std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
9856 {
9857     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9858     uint64 ac_value = extract_ac_13_12(instruction);
9859     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9860
9861     std::string ac = AC(copy(ac_value));
9862     std::string rs = GPR(copy(rs_value));
9863     std::string rt = GPR(copy(rt_value));
9864
9865     return img::format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt);
9866 }
9867
9868
9869 /*
9870  *
9871  *
9872  *   3         2         1
9873  *  10987654321098765432109876543210
9874  *  001000               x1110000101
9875  *     rt -----
9876  *          rs -----
9877  *               rd -----
9878  */
9879 std::string NMD::MAQ_SA_W_PHR(uint64 instruction)
9880 {
9881     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9882     uint64 ac_value = extract_ac_13_12(instruction);
9883     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9884
9885     std::string ac = AC(copy(ac_value));
9886     std::string rs = GPR(copy(rs_value));
9887     std::string rt = GPR(copy(rt_value));
9888
9889     return img::format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt);
9890 }
9891
9892
9893 /*
9894  *
9895  *
9896  *   3         2         1
9897  *  10987654321098765432109876543210
9898  *  001000               x1110000101
9899  *     rt -----
9900  *          rs -----
9901  *               rd -----
9902  */
9903 std::string NMD::MAX_D(uint64 instruction)
9904 {
9905     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9906     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9907     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9908
9909     std::string fd = FPR(copy(fd_value));
9910     std::string fs = FPR(copy(fs_value));
9911     std::string ft = FPR(copy(ft_value));
9912
9913     return img::format("MAX.D %s, %s, %s", fd, fs, ft);
9914 }
9915
9916
9917 /*
9918  *
9919  *
9920  *   3         2         1
9921  *  10987654321098765432109876543210
9922  *  001000               x1110000101
9923  *     rt -----
9924  *          rs -----
9925  *               rd -----
9926  */
9927 std::string NMD::MAX_S(uint64 instruction)
9928 {
9929     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9930     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9931     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9932
9933     std::string fd = FPR(copy(fd_value));
9934     std::string fs = FPR(copy(fs_value));
9935     std::string ft = FPR(copy(ft_value));
9936
9937     return img::format("MAX.S %s, %s, %s", fd, fs, ft);
9938 }
9939
9940
9941 /*
9942  *
9943  *
9944  *   3         2         1
9945  *  10987654321098765432109876543210
9946  *  001000               x1110000101
9947  *     rt -----
9948  *          rs -----
9949  *               rd -----
9950  */
9951 std::string NMD::MAXA_D(uint64 instruction)
9952 {
9953     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9954     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9955     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9956
9957     std::string fd = FPR(copy(fd_value));
9958     std::string fs = FPR(copy(fs_value));
9959     std::string ft = FPR(copy(ft_value));
9960
9961     return img::format("MAXA.D %s, %s, %s", fd, fs, ft);
9962 }
9963
9964
9965 /*
9966  *
9967  *
9968  *   3         2         1
9969  *  10987654321098765432109876543210
9970  *  001000               x1110000101
9971  *     rt -----
9972  *          rs -----
9973  *               rd -----
9974  */
9975 std::string NMD::MAXA_S(uint64 instruction)
9976 {
9977     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
9978     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
9979     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
9980
9981     std::string fd = FPR(copy(fd_value));
9982     std::string fs = FPR(copy(fs_value));
9983     std::string ft = FPR(copy(ft_value));
9984
9985     return img::format("MAXA.S %s, %s, %s", fd, fs, ft);
9986 }
9987
9988
9989 /*
9990  *
9991  *
9992  *   3         2         1
9993  *  10987654321098765432109876543210
9994  *  001000               x1110000101
9995  *     rt -----
9996  *          rs -----
9997  *               rd -----
9998  */
9999 std::string NMD::MFC0(uint64 instruction)
10000 {
10001     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10002     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10003     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10004
10005     std::string rt = GPR(copy(rt_value));
10006     std::string c0s = CPR(copy(c0s_value));
10007     std::string sel = IMMEDIATE(copy(sel_value));
10008
10009     return img::format("MFC0 %s, %s, %s", rt, c0s, sel);
10010 }
10011
10012
10013 /*
10014  *
10015  *
10016  *   3         2         1
10017  *  10987654321098765432109876543210
10018  *  001000               x1110000101
10019  *     rt -----
10020  *          rs -----
10021  *               rd -----
10022  */
10023 std::string NMD::MFC1(uint64 instruction)
10024 {
10025     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10026     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10027
10028     std::string rt = GPR(copy(rt_value));
10029     std::string fs = FPR(copy(fs_value));
10030
10031     return img::format("MFC1 %s, %s", rt, fs);
10032 }
10033
10034
10035 /*
10036  *
10037  *
10038  *   3         2         1
10039  *  10987654321098765432109876543210
10040  *  001000               x1110000101
10041  *     rt -----
10042  *          rs -----
10043  *               rd -----
10044  */
10045 std::string NMD::MFC2(uint64 instruction)
10046 {
10047     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10049
10050     std::string rt = GPR(copy(rt_value));
10051     std::string cs = CPR(copy(cs_value));
10052
10053     return img::format("MFC2 %s, %s", rt, cs);
10054 }
10055
10056
10057 /*
10058  *
10059  *
10060  *   3         2         1
10061  *  10987654321098765432109876543210
10062  *  001000               x1110000101
10063  *     rt -----
10064  *          rs -----
10065  *               rd -----
10066  */
10067 std::string NMD::MFGC0(uint64 instruction)
10068 {
10069     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10070     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10071     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10072
10073     std::string rt = GPR(copy(rt_value));
10074     std::string c0s = CPR(copy(c0s_value));
10075     std::string sel = IMMEDIATE(copy(sel_value));
10076
10077     return img::format("MFGC0 %s, %s, %s", rt, c0s, sel);
10078 }
10079
10080
10081 /*
10082  *
10083  *
10084  *   3         2         1
10085  *  10987654321098765432109876543210
10086  *  001000               x1110000101
10087  *     rt -----
10088  *          rs -----
10089  *               rd -----
10090  */
10091 std::string NMD::MFHC0(uint64 instruction)
10092 {
10093     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10094     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10095     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10096
10097     std::string rt = GPR(copy(rt_value));
10098     std::string c0s = CPR(copy(c0s_value));
10099     std::string sel = IMMEDIATE(copy(sel_value));
10100
10101     return img::format("MFHC0 %s, %s, %s", rt, c0s, sel);
10102 }
10103
10104
10105 /*
10106  *
10107  *
10108  *   3         2         1
10109  *  10987654321098765432109876543210
10110  *  001000               x1110000101
10111  *     rt -----
10112  *          rs -----
10113  *               rd -----
10114  */
10115 std::string NMD::MFHC1(uint64 instruction)
10116 {
10117     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10118     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10119
10120     std::string rt = GPR(copy(rt_value));
10121     std::string fs = FPR(copy(fs_value));
10122
10123     return img::format("MFHC1 %s, %s", rt, fs);
10124 }
10125
10126
10127 /*
10128  *
10129  *
10130  *   3         2         1
10131  *  10987654321098765432109876543210
10132  *  001000               x1110000101
10133  *     rt -----
10134  *          rs -----
10135  *               rd -----
10136  */
10137 std::string NMD::MFHC2(uint64 instruction)
10138 {
10139     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10140     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10141
10142     std::string rt = GPR(copy(rt_value));
10143     std::string cs = CPR(copy(cs_value));
10144
10145     return img::format("MFHC2 %s, %s", rt, cs);
10146 }
10147
10148
10149 /*
10150  *
10151  *
10152  *   3         2         1
10153  *  10987654321098765432109876543210
10154  *  001000               x1110000101
10155  *     rt -----
10156  *          rs -----
10157  *               rd -----
10158  */
10159 std::string NMD::MFHGC0(uint64 instruction)
10160 {
10161     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10162     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10163     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10164
10165     std::string rt = GPR(copy(rt_value));
10166     std::string c0s = CPR(copy(c0s_value));
10167     std::string sel = IMMEDIATE(copy(sel_value));
10168
10169     return img::format("MFHGC0 %s, %s, %s", rt, c0s, sel);
10170 }
10171
10172
10173 /*
10174  *
10175  *
10176  *   3         2         1
10177  *  10987654321098765432109876543210
10178  *  001000               x1110000101
10179  *     rt -----
10180  *          rs -----
10181  *               rd -----
10182  */
10183 std::string NMD::MFHI_DSP_(uint64 instruction)
10184 {
10185     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10186     uint64 ac_value = extract_ac_13_12(instruction);
10187
10188     std::string rt = GPR(copy(rt_value));
10189     std::string ac = AC(copy(ac_value));
10190
10191     return img::format("MFHI %s, %s", rt, ac);
10192 }
10193
10194
10195 /*
10196  *
10197  *
10198  *   3         2         1
10199  *  10987654321098765432109876543210
10200  *  001000               x1110000101
10201  *     rt -----
10202  *          rs -----
10203  *               rd -----
10204  */
10205 std::string NMD::MFHTR(uint64 instruction)
10206 {
10207     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10208     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10209     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10210     uint64 u_value = extract_u_10(instruction);
10211
10212     std::string rt = GPR(copy(rt_value));
10213     std::string c0s = IMMEDIATE(copy(c0s_value));
10214     std::string u = IMMEDIATE(copy(u_value));
10215     std::string sel = IMMEDIATE(copy(sel_value));
10216
10217     return img::format("MFHTR %s, %s, %s, %s", rt, c0s, u, sel);
10218 }
10219
10220
10221 /*
10222  *
10223  *
10224  *   3         2         1
10225  *  10987654321098765432109876543210
10226  *  001000               x1110000101
10227  *     rt -----
10228  *          rs -----
10229  *               rd -----
10230  */
10231 std::string NMD::MFLO_DSP_(uint64 instruction)
10232 {
10233     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10234     uint64 ac_value = extract_ac_13_12(instruction);
10235
10236     std::string rt = GPR(copy(rt_value));
10237     std::string ac = AC(copy(ac_value));
10238
10239     return img::format("MFLO %s, %s", rt, ac);
10240 }
10241
10242
10243 /*
10244  *
10245  *
10246  *   3         2         1
10247  *  10987654321098765432109876543210
10248  *  001000               x1110000101
10249  *     rt -----
10250  *          rs -----
10251  *               rd -----
10252  */
10253 std::string NMD::MFTR(uint64 instruction)
10254 {
10255     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10256     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10257     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10258     uint64 u_value = extract_u_10(instruction);
10259
10260     std::string rt = GPR(copy(rt_value));
10261     std::string c0s = IMMEDIATE(copy(c0s_value));
10262     std::string u = IMMEDIATE(copy(u_value));
10263     std::string sel = IMMEDIATE(copy(sel_value));
10264
10265     return img::format("MFTR %s, %s, %s, %s", rt, c0s, u, sel);
10266 }
10267
10268
10269 /*
10270  *
10271  *
10272  *   3         2         1
10273  *  10987654321098765432109876543210
10274  *  001000               x1110000101
10275  *     rt -----
10276  *          rs -----
10277  *               rd -----
10278  */
10279 std::string NMD::MIN_D(uint64 instruction)
10280 {
10281     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10282     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10283     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10284
10285     std::string fd = FPR(copy(fd_value));
10286     std::string fs = FPR(copy(fs_value));
10287     std::string ft = FPR(copy(ft_value));
10288
10289     return img::format("MIN.D %s, %s, %s", fd, fs, ft);
10290 }
10291
10292
10293 /*
10294  *
10295  *
10296  *   3         2         1
10297  *  10987654321098765432109876543210
10298  *  001000               x1110000101
10299  *     rt -----
10300  *          rs -----
10301  *               rd -----
10302  */
10303 std::string NMD::MIN_S(uint64 instruction)
10304 {
10305     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10306     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10307     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10308
10309     std::string fd = FPR(copy(fd_value));
10310     std::string fs = FPR(copy(fs_value));
10311     std::string ft = FPR(copy(ft_value));
10312
10313     return img::format("MIN.S %s, %s, %s", fd, fs, ft);
10314 }
10315
10316
10317 /*
10318  *
10319  *
10320  *   3         2         1
10321  *  10987654321098765432109876543210
10322  *  001000               x1110000101
10323  *     rt -----
10324  *          rs -----
10325  *               rd -----
10326  */
10327 std::string NMD::MINA_D(uint64 instruction)
10328 {
10329     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10330     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10331     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10332
10333     std::string fd = FPR(copy(fd_value));
10334     std::string fs = FPR(copy(fs_value));
10335     std::string ft = FPR(copy(ft_value));
10336
10337     return img::format("MINA.D %s, %s, %s", fd, fs, ft);
10338 }
10339
10340
10341 /*
10342  *
10343  *
10344  *   3         2         1
10345  *  10987654321098765432109876543210
10346  *  001000               x1110000101
10347  *     rt -----
10348  *          rs -----
10349  *               rd -----
10350  */
10351 std::string NMD::MINA_S(uint64 instruction)
10352 {
10353     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10354     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10355     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10356
10357     std::string fd = FPR(copy(fd_value));
10358     std::string fs = FPR(copy(fs_value));
10359     std::string ft = FPR(copy(ft_value));
10360
10361     return img::format("MINA.S %s, %s, %s", fd, fs, ft);
10362 }
10363
10364
10365 /*
10366  *
10367  *
10368  *   3         2         1
10369  *  10987654321098765432109876543210
10370  *  001000               x1110000101
10371  *     rt -----
10372  *          rs -----
10373  *               rd -----
10374  */
10375 std::string NMD::MOD(uint64 instruction)
10376 {
10377     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10378     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
10379     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10380
10381     std::string rd = GPR(copy(rd_value));
10382     std::string rs = GPR(copy(rs_value));
10383     std::string rt = GPR(copy(rt_value));
10384
10385     return img::format("MOD %s, %s, %s", rd, rs, rt);
10386 }
10387
10388
10389 /*
10390  *
10391  *
10392  *   3         2         1
10393  *  10987654321098765432109876543210
10394  *  001000               x1110000101
10395  *     rt -----
10396  *          rs -----
10397  *               rd -----
10398  */
10399 std::string NMD::MODSUB(uint64 instruction)
10400 {
10401     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10402     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
10403     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10404
10405     std::string rd = GPR(copy(rd_value));
10406     std::string rs = GPR(copy(rs_value));
10407     std::string rt = GPR(copy(rt_value));
10408
10409     return img::format("MODSUB %s, %s, %s", rd, rs, rt);
10410 }
10411
10412
10413 /*
10414  *
10415  *
10416  *   3         2         1
10417  *  10987654321098765432109876543210
10418  *  001000               x1110000101
10419  *     rt -----
10420  *          rs -----
10421  *               rd -----
10422  */
10423 std::string NMD::MODU(uint64 instruction)
10424 {
10425     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10426     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
10427     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10428
10429     std::string rd = GPR(copy(rd_value));
10430     std::string rs = GPR(copy(rs_value));
10431     std::string rt = GPR(copy(rt_value));
10432
10433     return img::format("MODU %s, %s, %s", rd, rs, rt);
10434 }
10435
10436
10437 /*
10438  *
10439  *
10440  *   3         2         1
10441  *  10987654321098765432109876543210
10442  *  001000               x1110000101
10443  *     rt -----
10444  *          rs -----
10445  *               rd -----
10446  */
10447 std::string NMD::MOV_D(uint64 instruction)
10448 {
10449     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10450     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10451
10452     std::string ft = FPR(copy(ft_value));
10453     std::string fs = FPR(copy(fs_value));
10454
10455     return img::format("MOV.D %s, %s", ft, fs);
10456 }
10457
10458
10459 /*
10460  *
10461  *
10462  *   3         2         1
10463  *  10987654321098765432109876543210
10464  *  001000               x1110000101
10465  *     rt -----
10466  *          rs -----
10467  *               rd -----
10468  */
10469 std::string NMD::MOV_S(uint64 instruction)
10470 {
10471     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10472     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10473
10474     std::string ft = FPR(copy(ft_value));
10475     std::string fs = FPR(copy(fs_value));
10476
10477     return img::format("MOV.S %s, %s", ft, fs);
10478 }
10479
10480
10481 /*
10482  *
10483  *
10484  *   3         2         1
10485  *  10987654321098765432109876543210
10486  *  001000               x1110000101
10487  *     rt -----
10488  *          rs -----
10489  *               rd -----
10490  */
10491 std::string NMD::MOVE_BALC(uint64 instruction)
10492 {
10493     uint64 rd1_value = extract_rdl_25_24(instruction);
10494     int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction);
10495     uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction);
10496
10497     std::string rd1 = GPR(encode_rd1_from_rd(rd1_value));
10498     std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));
10499     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
10500
10501     return img::format("MOVE.BALC %s, %s, %s", rd1, rtz4, s);
10502 }
10503
10504
10505 /*
10506  *
10507  *
10508  *   3         2         1
10509  *  10987654321098765432109876543210
10510  *  001000               x1110000101
10511  *     rt -----
10512  *          rs -----
10513  *               rd -----
10514  */
10515 std::string NMD::MOVEP(uint64 instruction)
10516 {
10517     uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction);
10518     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
10519     uint64 rd2_value = extract_rd2_3_8(instruction);
10520
10521     std::string rd2 = GPR(encode_rd2_reg1(rd2_value));
10522     std::string re2 = GPR(encode_rd2_reg2(rd2_value));
10523     /* !!!!!!!!!! - no conversion function */
10524     std::string rsz4 = GPR(encode_gpr4_zero(rsz4_value));
10525     std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));
10526
10527     return img::format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4);
10528     /* hand edited */
10529 }
10530
10531
10532 /*
10533  *
10534  *
10535  *   3         2         1
10536  *  10987654321098765432109876543210
10537  *  001000               x1110000101
10538  *     rt -----
10539  *          rs -----
10540  *               rd -----
10541  */
10542 std::string NMD::MOVEP_REV_(uint64 instruction)
10543 {
10544     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10545     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10546     uint64 rd2_value = extract_rd2_3_8(instruction);
10547
10548     std::string rs4 = GPR(encode_gpr4(rs4_value));
10549     std::string rt4 = GPR(encode_gpr4(rt4_value));
10550     std::string rd2 = GPR(encode_rd2_reg1(rd2_value));
10551     std::string rs2 = GPR(encode_rd2_reg2(rd2_value));
10552     /* !!!!!!!!!! - no conversion function */
10553
10554     return img::format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2);
10555     /* hand edited */
10556 }
10557
10558
10559 /*
10560  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10561  *
10562  *   3         2         1
10563  *  10987654321098765432109876543210
10564  *  001000               00010001101
10565  *     rt -----
10566  *          rs -----
10567  *               rd -----
10568  */
10569 std::string NMD::MOVE(uint64 instruction)
10570 {
10571     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
10572     uint64 rs_value = extract_rs_4_3_2_1_0(instruction);
10573
10574     std::string rt = GPR(copy(rt_value));
10575     std::string rs = GPR(copy(rs_value));
10576
10577     return img::format("MOVE %s, %s", rt, rs);
10578 }
10579
10580
10581 /*
10582  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10583  *
10584  *   3         2         1
10585  *  10987654321098765432109876543210
10586  *  001000               00010001101
10587  *     rt -----
10588  *          rs -----
10589  *               rd -----
10590  */
10591 std::string NMD::MOVN(uint64 instruction)
10592 {
10593     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10594     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
10595     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10596
10597     std::string rd = GPR(copy(rd_value));
10598     std::string rs = GPR(copy(rs_value));
10599     std::string rt = GPR(copy(rt_value));
10600
10601     return img::format("MOVN %s, %s, %s", rd, rs, rt);
10602 }
10603
10604
10605 /*
10606  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10607  *
10608  *   3         2         1
10609  *  10987654321098765432109876543210
10610  *  001000               00010001101
10611  *     rt -----
10612  *          rs -----
10613  *               rd -----
10614  */
10615 std::string NMD::MOVZ(uint64 instruction)
10616 {
10617     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10618     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
10619     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10620
10621     std::string rd = GPR(copy(rd_value));
10622     std::string rs = GPR(copy(rs_value));
10623     std::string rt = GPR(copy(rt_value));
10624
10625     return img::format("MOVZ %s, %s, %s", rd, rs, rt);
10626 }
10627
10628
10629 /*
10630  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10631  *
10632  *   3         2         1
10633  *  10987654321098765432109876543210
10634  *  001000               00010001101
10635  *     rt -----
10636  *          rs -----
10637  *               rd -----
10638  */
10639 std::string NMD::MSUB_DSP_(uint64 instruction)
10640 {
10641     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10642     uint64 ac_value = extract_ac_13_12(instruction);
10643     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10644
10645     std::string ac = AC(copy(ac_value));
10646     std::string rs = GPR(copy(rs_value));
10647     std::string rt = GPR(copy(rt_value));
10648
10649     return img::format("MSUB %s, %s, %s", ac, rs, rt);
10650 }
10651
10652
10653 /*
10654  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10655  *
10656  *   3         2         1
10657  *  10987654321098765432109876543210
10658  *  001000               00010001101
10659  *     rt -----
10660  *          rs -----
10661  *               rd -----
10662  */
10663 std::string NMD::MSUBF_D(uint64 instruction)
10664 {
10665     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10666     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10667     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10668
10669     std::string fd = FPR(copy(fd_value));
10670     std::string fs = FPR(copy(fs_value));
10671     std::string ft = FPR(copy(ft_value));
10672
10673     return img::format("MSUBF.D %s, %s, %s", fd, fs, ft);
10674 }
10675
10676
10677 /*
10678  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10679  *
10680  *   3         2         1
10681  *  10987654321098765432109876543210
10682  *  001000               00010001101
10683  *     rt -----
10684  *          rs -----
10685  *               rd -----
10686  */
10687 std::string NMD::MSUBF_S(uint64 instruction)
10688 {
10689     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10690     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
10691     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
10692
10693     std::string fd = FPR(copy(fd_value));
10694     std::string fs = FPR(copy(fs_value));
10695     std::string ft = FPR(copy(ft_value));
10696
10697     return img::format("MSUBF.S %s, %s, %s", fd, fs, ft);
10698 }
10699
10700
10701 /*
10702  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10703  *
10704  *   3         2         1
10705  *  10987654321098765432109876543210
10706  *  001000               00010001101
10707  *     rt -----
10708  *          rs -----
10709  *               rd -----
10710  */
10711 std::string NMD::MSUBU_DSP_(uint64 instruction)
10712 {
10713     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10714     uint64 ac_value = extract_ac_13_12(instruction);
10715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10716
10717     std::string ac = AC(copy(ac_value));
10718     std::string rs = GPR(copy(rs_value));
10719     std::string rt = GPR(copy(rt_value));
10720
10721     return img::format("MSUBU %s, %s, %s", ac, rs, rt);
10722 }
10723
10724
10725 /*
10726  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10727  *
10728  *   3         2         1
10729  *  10987654321098765432109876543210
10730  *  001000               00010001101
10731  *     rt -----
10732  *          rs -----
10733  *               rd -----
10734  */
10735 std::string NMD::MTC0(uint64 instruction)
10736 {
10737     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10738     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10739     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10740
10741     std::string rt = GPR(copy(rt_value));
10742     std::string c0s = CPR(copy(c0s_value));
10743     std::string sel = IMMEDIATE(copy(sel_value));
10744
10745     return img::format("MTC0 %s, %s, %s", rt, c0s, sel);
10746 }
10747
10748
10749 /*
10750  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10751  *
10752  *   3         2         1
10753  *  10987654321098765432109876543210
10754  *  001000               00010001101
10755  *     rt -----
10756  *          rs -----
10757  *               rd -----
10758  */
10759 std::string NMD::MTC1(uint64 instruction)
10760 {
10761     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10762     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10763
10764     std::string rt = GPR(copy(rt_value));
10765     std::string fs = FPR(copy(fs_value));
10766
10767     return img::format("MTC1 %s, %s", rt, fs);
10768 }
10769
10770
10771 /*
10772  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10773  *
10774  *   3         2         1
10775  *  10987654321098765432109876543210
10776  *  001000               00010001101
10777  *     rt -----
10778  *          rs -----
10779  *               rd -----
10780  */
10781 std::string NMD::MTC2(uint64 instruction)
10782 {
10783     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10784     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10785
10786     std::string rt = GPR(copy(rt_value));
10787     std::string cs = CPR(copy(cs_value));
10788
10789     return img::format("MTC2 %s, %s", rt, cs);
10790 }
10791
10792
10793 /*
10794  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10795  *
10796  *   3         2         1
10797  *  10987654321098765432109876543210
10798  *  001000               00010001101
10799  *     rt -----
10800  *          rs -----
10801  *               rd -----
10802  */
10803 std::string NMD::MTGC0(uint64 instruction)
10804 {
10805     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10806     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10807     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10808
10809     std::string rt = GPR(copy(rt_value));
10810     std::string c0s = CPR(copy(c0s_value));
10811     std::string sel = IMMEDIATE(copy(sel_value));
10812
10813     return img::format("MTGC0 %s, %s, %s", rt, c0s, sel);
10814 }
10815
10816
10817 /*
10818  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10819  *
10820  *   3         2         1
10821  *  10987654321098765432109876543210
10822  *  001000               00010001101
10823  *     rt -----
10824  *          rs -----
10825  *               rd -----
10826  */
10827 std::string NMD::MTHC0(uint64 instruction)
10828 {
10829     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10830     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10831     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10832
10833     std::string rt = GPR(copy(rt_value));
10834     std::string c0s = CPR(copy(c0s_value));
10835     std::string sel = IMMEDIATE(copy(sel_value));
10836
10837     return img::format("MTHC0 %s, %s, %s", rt, c0s, sel);
10838 }
10839
10840
10841 /*
10842  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10843  *
10844  *   3         2         1
10845  *  10987654321098765432109876543210
10846  *  001000               00010001101
10847  *     rt -----
10848  *          rs -----
10849  *               rd -----
10850  */
10851 std::string NMD::MTHC1(uint64 instruction)
10852 {
10853     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10854     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
10855
10856     std::string rt = GPR(copy(rt_value));
10857     std::string fs = FPR(copy(fs_value));
10858
10859     return img::format("MTHC1 %s, %s", rt, fs);
10860 }
10861
10862
10863 /*
10864  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10865  *
10866  *   3         2         1
10867  *  10987654321098765432109876543210
10868  *  001000               00010001101
10869  *     rt -----
10870  *          rs -----
10871  *               rd -----
10872  */
10873 std::string NMD::MTHC2(uint64 instruction)
10874 {
10875     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10876     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10877
10878     std::string rt = GPR(copy(rt_value));
10879     std::string cs = CPR(copy(cs_value));
10880
10881     return img::format("MTHC2 %s, %s", rt, cs);
10882 }
10883
10884
10885 /*
10886  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10887  *
10888  *   3         2         1
10889  *  10987654321098765432109876543210
10890  *  001000               00010001101
10891  *     rt -----
10892  *          rs -----
10893  *               rd -----
10894  */
10895 std::string NMD::MTHGC0(uint64 instruction)
10896 {
10897     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10898     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10899     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10900
10901     std::string rt = GPR(copy(rt_value));
10902     std::string c0s = CPR(copy(c0s_value));
10903     std::string sel = IMMEDIATE(copy(sel_value));
10904
10905     return img::format("MTHGC0 %s, %s, %s", rt, c0s, sel);
10906 }
10907
10908
10909 /*
10910  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10911  *
10912  *   3         2         1
10913  *  10987654321098765432109876543210
10914  *  001000               00010001101
10915  *     rt -----
10916  *          rs -----
10917  *               rd -----
10918  */
10919 std::string NMD::MTHI_DSP_(uint64 instruction)
10920 {
10921     uint64 ac_value = extract_ac_13_12(instruction);
10922     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10923
10924     std::string rs = GPR(copy(rs_value));
10925     std::string ac = AC(copy(ac_value));
10926
10927     return img::format("MTHI %s, %s", rs, ac);
10928 }
10929
10930
10931 /*
10932  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10933  *
10934  *   3         2         1
10935  *  10987654321098765432109876543210
10936  *  001000               00010001101
10937  *     rt -----
10938  *          rs -----
10939  *               rd -----
10940  */
10941 std::string NMD::MTHLIP(uint64 instruction)
10942 {
10943     uint64 ac_value = extract_ac_13_12(instruction);
10944     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10945
10946     std::string rs = GPR(copy(rs_value));
10947     std::string ac = AC(copy(ac_value));
10948
10949     return img::format("MTHLIP %s, %s", rs, ac);
10950 }
10951
10952
10953 /*
10954  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10955  *
10956  *   3         2         1
10957  *  10987654321098765432109876543210
10958  *  001000               00010001101
10959  *     rt -----
10960  *          rs -----
10961  *               rd -----
10962  */
10963 std::string NMD::MTHTR(uint64 instruction)
10964 {
10965     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10966     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10967     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10968     uint64 u_value = extract_u_10(instruction);
10969
10970     std::string rt = GPR(copy(rt_value));
10971     std::string c0s = IMMEDIATE(copy(c0s_value));
10972     std::string u = IMMEDIATE(copy(u_value));
10973     std::string sel = IMMEDIATE(copy(sel_value));
10974
10975     return img::format("MTHTR %s, %s, %s, %s", rt, c0s, u, sel);
10976 }
10977
10978
10979 /*
10980  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10981  *
10982  *   3         2         1
10983  *  10987654321098765432109876543210
10984  *  001000               00010001101
10985  *     rt -----
10986  *          rs -----
10987  *               rd -----
10988  */
10989 std::string NMD::MTLO_DSP_(uint64 instruction)
10990 {
10991     uint64 ac_value = extract_ac_13_12(instruction);
10992     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10993
10994     std::string rs = GPR(copy(rs_value));
10995     std::string ac = AC(copy(ac_value));
10996
10997     return img::format("MTLO %s, %s", rs, ac);
10998 }
10999
11000
11001 /*
11002  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11003  *
11004  *   3         2         1
11005  *  10987654321098765432109876543210
11006  *  001000               00010001101
11007  *     rt -----
11008  *          rs -----
11009  *               rd -----
11010  */
11011 std::string NMD::MTTR(uint64 instruction)
11012 {
11013     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11014     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
11015     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
11016     uint64 u_value = extract_u_10(instruction);
11017
11018     std::string rt = GPR(copy(rt_value));
11019     std::string c0s = IMMEDIATE(copy(c0s_value));
11020     std::string u = IMMEDIATE(copy(u_value));
11021     std::string sel = IMMEDIATE(copy(sel_value));
11022
11023     return img::format("MTTR %s, %s, %s, %s", rt, c0s, u, sel);
11024 }
11025
11026
11027 /*
11028  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11029  *
11030  *   3         2         1
11031  *  10987654321098765432109876543210
11032  *  001000               00010001101
11033  *     rt -----
11034  *          rs -----
11035  *               rd -----
11036  */
11037 std::string NMD::MUH(uint64 instruction)
11038 {
11039     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11040     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11041     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11042
11043     std::string rd = GPR(copy(rd_value));
11044     std::string rs = GPR(copy(rs_value));
11045     std::string rt = GPR(copy(rt_value));
11046
11047     return img::format("MUH %s, %s, %s", rd, rs, rt);
11048 }
11049
11050
11051 /*
11052  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11053  *
11054  *   3         2         1
11055  *  10987654321098765432109876543210
11056  *  001000               00010001101
11057  *     rt -----
11058  *          rs -----
11059  *               rd -----
11060  */
11061 std::string NMD::MUHU(uint64 instruction)
11062 {
11063     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11064     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11065     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11066
11067     std::string rd = GPR(copy(rd_value));
11068     std::string rs = GPR(copy(rs_value));
11069     std::string rt = GPR(copy(rt_value));
11070
11071     return img::format("MUHU %s, %s, %s", rd, rs, rt);
11072 }
11073
11074
11075 /*
11076  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11077  *
11078  *   3         2         1
11079  *  10987654321098765432109876543210
11080  *  001000               00010001101
11081  *     rt -----
11082  *          rs -----
11083  *               rd -----
11084  */
11085 std::string NMD::MUL_32_(uint64 instruction)
11086 {
11087     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11088     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11089     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11090
11091     std::string rd = GPR(copy(rd_value));
11092     std::string rs = GPR(copy(rs_value));
11093     std::string rt = GPR(copy(rt_value));
11094
11095     return img::format("MUL %s, %s, %s", rd, rs, rt);
11096 }
11097
11098
11099 /*
11100  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11101  *
11102  *   3         2         1
11103  *  10987654321098765432109876543210
11104  *  001000               00010001101
11105  *     rt -----
11106  *          rs -----
11107  *               rd -----
11108  */
11109 std::string NMD::MUL_4X4_(uint64 instruction)
11110 {
11111     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
11112     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
11113
11114     std::string rs4 = GPR(encode_gpr4(rs4_value));
11115     std::string rt4 = GPR(encode_gpr4(rt4_value));
11116
11117     return img::format("MUL %s, %s", rs4, rt4);
11118 }
11119
11120
11121 /*
11122  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11123  *
11124  *   3         2         1
11125  *  10987654321098765432109876543210
11126  *  001000               00010001101
11127  *     rt -----
11128  *          rs -----
11129  *               rd -----
11130  */
11131 std::string NMD::MUL_D(uint64 instruction)
11132 {
11133     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
11134     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
11135     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
11136
11137     std::string fd = FPR(copy(fd_value));
11138     std::string fs = FPR(copy(fs_value));
11139     std::string ft = FPR(copy(ft_value));
11140
11141     return img::format("MUL.D %s, %s, %s", fd, fs, ft);
11142 }
11143
11144
11145 /*
11146  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11147  *
11148  *   3         2         1
11149  *  10987654321098765432109876543210
11150  *  001000               00010001101
11151  *     rt -----
11152  *          rs -----
11153  *               rd -----
11154  */
11155 std::string NMD::MUL_PH(uint64 instruction)
11156 {
11157     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11158     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11159     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11160
11161     std::string rd = GPR(copy(rd_value));
11162     std::string rs = GPR(copy(rs_value));
11163     std::string rt = GPR(copy(rt_value));
11164
11165     return img::format("MUL.PH %s, %s, %s", rd, rs, rt);
11166 }
11167
11168
11169 /*
11170  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11171  *
11172  *   3         2         1
11173  *  10987654321098765432109876543210
11174  *  001000               00010001101
11175  *     rt -----
11176  *          rs -----
11177  *               rd -----
11178  */
11179 std::string NMD::MUL_S_PH(uint64 instruction)
11180 {
11181     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11182     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11184
11185     std::string rd = GPR(copy(rd_value));
11186     std::string rs = GPR(copy(rs_value));
11187     std::string rt = GPR(copy(rt_value));
11188
11189     return img::format("MUL_S.PH %s, %s, %s", rd, rs, rt);
11190 }
11191
11192
11193 /*
11194  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11195  *
11196  *   3         2         1
11197  *  10987654321098765432109876543210
11198  *  001000               00010001101
11199  *     rt -----
11200  *          rs -----
11201  *               rd -----
11202  */
11203 std::string NMD::MUL_S(uint64 instruction)
11204 {
11205     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
11206     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
11207     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
11208
11209     std::string fd = FPR(copy(fd_value));
11210     std::string fs = FPR(copy(fs_value));
11211     std::string ft = FPR(copy(ft_value));
11212
11213     return img::format("MUL.S %s, %s, %s", fd, fs, ft);
11214 }
11215
11216
11217 /*
11218  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11219  *
11220  *   3         2         1
11221  *  10987654321098765432109876543210
11222  *  001000               00010001101
11223  *     rt -----
11224  *          rs -----
11225  *               rd -----
11226  */
11227 std::string NMD::MULEQ_S_W_PHL(uint64 instruction)
11228 {
11229     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11230     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11231     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11232
11233     std::string rd = GPR(copy(rd_value));
11234     std::string rs = GPR(copy(rs_value));
11235     std::string rt = GPR(copy(rt_value));
11236
11237     return img::format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt);
11238 }
11239
11240
11241 /*
11242  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11243  *
11244  *   3         2         1
11245  *  10987654321098765432109876543210
11246  *  001000               00010001101
11247  *     rt -----
11248  *          rs -----
11249  *               rd -----
11250  */
11251 std::string NMD::MULEQ_S_W_PHR(uint64 instruction)
11252 {
11253     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11254     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11255     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11256
11257     std::string rd = GPR(copy(rd_value));
11258     std::string rs = GPR(copy(rs_value));
11259     std::string rt = GPR(copy(rt_value));
11260
11261     return img::format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt);
11262 }
11263
11264
11265 /*
11266  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11267  *
11268  *   3         2         1
11269  *  10987654321098765432109876543210
11270  *  001000               00010001101
11271  *     rt -----
11272  *          rs -----
11273  *               rd -----
11274  */
11275 std::string NMD::MULEU_S_PH_QBL(uint64 instruction)
11276 {
11277     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11278     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11279     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11280
11281     std::string rd = GPR(copy(rd_value));
11282     std::string rs = GPR(copy(rs_value));
11283     std::string rt = GPR(copy(rt_value));
11284
11285     return img::format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt);
11286 }
11287
11288
11289 /*
11290  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11291  *
11292  *   3         2         1
11293  *  10987654321098765432109876543210
11294  *  001000               00010001101
11295  *     rt -----
11296  *          rs -----
11297  *               rd -----
11298  */
11299 std::string NMD::MULEU_S_PH_QBR(uint64 instruction)
11300 {
11301     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11302     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11303     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11304
11305     std::string rd = GPR(copy(rd_value));
11306     std::string rs = GPR(copy(rs_value));
11307     std::string rt = GPR(copy(rt_value));
11308
11309     return img::format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt);
11310 }
11311
11312
11313 /*
11314  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11315  *
11316  *   3         2         1
11317  *  10987654321098765432109876543210
11318  *  001000               00010001101
11319  *     rt -----
11320  *          rs -----
11321  *               rd -----
11322  */
11323 std::string NMD::MULQ_RS_PH(uint64 instruction)
11324 {
11325     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11326     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11327     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11328
11329     std::string rd = GPR(copy(rd_value));
11330     std::string rs = GPR(copy(rs_value));
11331     std::string rt = GPR(copy(rt_value));
11332
11333     return img::format("MULQ_RS.PH %s, %s, %s", rd, rs, rt);
11334 }
11335
11336
11337 /*
11338  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11339  *
11340  *   3         2         1
11341  *  10987654321098765432109876543210
11342  *  001000               00010001101
11343  *     rt -----
11344  *          rs -----
11345  *               rd -----
11346  */
11347 std::string NMD::MULQ_RS_W(uint64 instruction)
11348 {
11349     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11350     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11351     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11352
11353     std::string rd = GPR(copy(rd_value));
11354     std::string rs = GPR(copy(rs_value));
11355     std::string rt = GPR(copy(rt_value));
11356
11357     return img::format("MULQ_RS.W %s, %s, %s", rd, rs, rt);
11358 }
11359
11360
11361 /*
11362  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11363  *
11364  *   3         2         1
11365  *  10987654321098765432109876543210
11366  *  001000               00010001101
11367  *     rt -----
11368  *          rs -----
11369  *               rd -----
11370  */
11371 std::string NMD::MULQ_S_PH(uint64 instruction)
11372 {
11373     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11374     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11375     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11376
11377     std::string rd = GPR(copy(rd_value));
11378     std::string rs = GPR(copy(rs_value));
11379     std::string rt = GPR(copy(rt_value));
11380
11381     return img::format("MULQ_S.PH %s, %s, %s", rd, rs, rt);
11382 }
11383
11384
11385 /*
11386  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11387  *
11388  *   3         2         1
11389  *  10987654321098765432109876543210
11390  *  001000               00010001101
11391  *     rt -----
11392  *          rs -----
11393  *               rd -----
11394  */
11395 std::string NMD::MULQ_S_W(uint64 instruction)
11396 {
11397     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11398     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11399     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11400
11401     std::string rd = GPR(copy(rd_value));
11402     std::string rs = GPR(copy(rs_value));
11403     std::string rt = GPR(copy(rt_value));
11404
11405     return img::format("MULQ_S.W %s, %s, %s", rd, rs, rt);
11406 }
11407
11408
11409 /*
11410  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11411  *
11412  *   3         2         1
11413  *  10987654321098765432109876543210
11414  *  001000               00010001101
11415  *     rt -----
11416  *          rs -----
11417  *               rd -----
11418  */
11419 std::string NMD::MULSA_W_PH(uint64 instruction)
11420 {
11421     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11422     uint64 ac_value = extract_ac_13_12(instruction);
11423     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11424
11425     std::string ac = AC(copy(ac_value));
11426     std::string rs = GPR(copy(rs_value));
11427     std::string rt = GPR(copy(rt_value));
11428
11429     return img::format("MULSA.W.PH %s, %s, %s", ac, rs, rt);
11430 }
11431
11432
11433 /*
11434  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11435  *
11436  *   3         2         1
11437  *  10987654321098765432109876543210
11438  *  001000               00010001101
11439  *     rt -----
11440  *          rs -----
11441  *               rd -----
11442  */
11443 std::string NMD::MULSAQ_S_W_PH(uint64 instruction)
11444 {
11445     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11446     uint64 ac_value = extract_ac_13_12(instruction);
11447     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11448
11449     std::string ac = AC(copy(ac_value));
11450     std::string rs = GPR(copy(rs_value));
11451     std::string rt = GPR(copy(rt_value));
11452
11453     return img::format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt);
11454 }
11455
11456
11457 /*
11458  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11459  *
11460  *   3         2         1
11461  *  10987654321098765432109876543210
11462  *  001000               00010001101
11463  *     rt -----
11464  *          rs -----
11465  *               rd -----
11466  */
11467 std::string NMD::MULT_DSP_(uint64 instruction)
11468 {
11469     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11470     uint64 ac_value = extract_ac_13_12(instruction);
11471     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11472
11473     std::string ac = AC(copy(ac_value));
11474     std::string rs = GPR(copy(rs_value));
11475     std::string rt = GPR(copy(rt_value));
11476
11477     return img::format("MULT %s, %s, %s", ac, rs, rt);
11478 }
11479
11480
11481 /*
11482  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11483  *
11484  *   3         2         1
11485  *  10987654321098765432109876543210
11486  *  001000               00010001101
11487  *     rt -----
11488  *          rs -----
11489  *               rd -----
11490  */
11491 std::string NMD::MULTU_DSP_(uint64 instruction)
11492 {
11493     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11494     uint64 ac_value = extract_ac_13_12(instruction);
11495     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11496
11497     std::string ac = AC(copy(ac_value));
11498     std::string rs = GPR(copy(rs_value));
11499     std::string rt = GPR(copy(rt_value));
11500
11501     return img::format("MULTU %s, %s, %s", ac, rs, rt);
11502 }
11503
11504
11505 /*
11506  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11507  *
11508  *   3         2         1
11509  *  10987654321098765432109876543210
11510  *  001000               00010001101
11511  *     rt -----
11512  *          rs -----
11513  *               rd -----
11514  */
11515 std::string NMD::MULU(uint64 instruction)
11516 {
11517     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11518     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11519     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11520
11521     std::string rd = GPR(copy(rd_value));
11522     std::string rs = GPR(copy(rs_value));
11523     std::string rt = GPR(copy(rt_value));
11524
11525     return img::format("MULU %s, %s, %s", rd, rs, rt);
11526 }
11527
11528
11529 /*
11530  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11531  *
11532  *   3         2         1
11533  *  10987654321098765432109876543210
11534  *  001000               00010001101
11535  *     rt -----
11536  *          rs -----
11537  *               rd -----
11538  */
11539 std::string NMD::NEG_D(uint64 instruction)
11540 {
11541     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
11542     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
11543
11544     std::string ft = FPR(copy(ft_value));
11545     std::string fs = FPR(copy(fs_value));
11546
11547     return img::format("NEG.D %s, %s", ft, fs);
11548 }
11549
11550
11551 /*
11552  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11553  *
11554  *   3         2         1
11555  *  10987654321098765432109876543210
11556  *  001000               00010001101
11557  *     rt -----
11558  *          rs -----
11559  *               rd -----
11560  */
11561 std::string NMD::NEG_S(uint64 instruction)
11562 {
11563     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
11564     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
11565
11566     std::string ft = FPR(copy(ft_value));
11567     std::string fs = FPR(copy(fs_value));
11568
11569     return img::format("NEG.S %s, %s", ft, fs);
11570 }
11571
11572
11573 /*
11574  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11575  *
11576  *   3         2         1
11577  *  10987654321098765432109876543210
11578  *  001000               00010001101
11579  *     rt -----
11580  *          rs -----
11581  *               rd -----
11582  */
11583 std::string NMD::NOP_16_(uint64 instruction)
11584 {
11585     (void)instruction;
11586
11587     return "NOP ";
11588 }
11589
11590
11591 /*
11592  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11593  *
11594  *   3         2         1
11595  *  10987654321098765432109876543210
11596  *  001000               00010001101
11597  *     rt -----
11598  *          rs -----
11599  *               rd -----
11600  */
11601 std::string NMD::NOP_32_(uint64 instruction)
11602 {
11603     (void)instruction;
11604
11605     return "NOP ";
11606 }
11607
11608
11609 /*
11610  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11611  *
11612  *   3         2         1
11613  *  10987654321098765432109876543210
11614  *  001000               00010001101
11615  *     rt -----
11616  *          rs -----
11617  *               rd -----
11618  */
11619 std::string NMD::NOR(uint64 instruction)
11620 {
11621     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11622     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11623     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11624
11625     std::string rd = GPR(copy(rd_value));
11626     std::string rs = GPR(copy(rs_value));
11627     std::string rt = GPR(copy(rt_value));
11628
11629     return img::format("NOR %s, %s, %s", rd, rs, rt);
11630 }
11631
11632
11633 /*
11634  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11635  *
11636  *   3         2         1
11637  *  10987654321098765432109876543210
11638  *  001000               00010001101
11639  *     rt -----
11640  *          rs -----
11641  *               rd -----
11642  */
11643 std::string NMD::NOT_16_(uint64 instruction)
11644 {
11645     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11646     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11647
11648     std::string rt3 = GPR(encode_gpr3(rt3_value));
11649     std::string rs3 = GPR(encode_gpr3(rs3_value));
11650
11651     return img::format("NOT %s, %s", rt3, rs3);
11652 }
11653
11654
11655 /*
11656  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11657  *
11658  *   3         2         1
11659  *  10987654321098765432109876543210
11660  *  001000               00010001101
11661  *     rt -----
11662  *          rs -----
11663  *               rd -----
11664  */
11665 std::string NMD::OR_16_(uint64 instruction)
11666 {
11667     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11668     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11669
11670     std::string rs3 = GPR(encode_gpr3(rs3_value));
11671     std::string rt3 = GPR(encode_gpr3(rt3_value));
11672
11673     return img::format("OR %s, %s", rs3, rt3);
11674 }
11675
11676
11677 /*
11678  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11679  *
11680  *   3         2         1
11681  *  10987654321098765432109876543210
11682  *  001000               00010001101
11683  *     rt -----
11684  *          rs -----
11685  *               rd -----
11686  */
11687 std::string NMD::OR_32_(uint64 instruction)
11688 {
11689     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11690     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11691     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11692
11693     std::string rd = GPR(copy(rd_value));
11694     std::string rs = GPR(copy(rs_value));
11695     std::string rt = GPR(copy(rt_value));
11696
11697     return img::format("OR %s, %s, %s", rd, rs, rt);
11698 }
11699
11700
11701 /*
11702  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11703  *
11704  *   3         2         1
11705  *  10987654321098765432109876543210
11706  *  001000               00010001101
11707  *     rt -----
11708  *          rs -----
11709  *               rd -----
11710  */
11711 std::string NMD::ORI(uint64 instruction)
11712 {
11713     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11714     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11716
11717     std::string rt = GPR(copy(rt_value));
11718     std::string rs = GPR(copy(rs_value));
11719     std::string u = IMMEDIATE(copy(u_value));
11720
11721     return img::format("ORI %s, %s, %s", rt, rs, u);
11722 }
11723
11724
11725 /*
11726  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11727  *
11728  *   3         2         1
11729  *  10987654321098765432109876543210
11730  *  001000               00010001101
11731  *     rt -----
11732  *          rs -----
11733  *               rd -----
11734  */
11735 std::string NMD::PACKRL_PH(uint64 instruction)
11736 {
11737     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11738     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11739     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11740
11741     std::string rd = GPR(copy(rd_value));
11742     std::string rs = GPR(copy(rs_value));
11743     std::string rt = GPR(copy(rt_value));
11744
11745     return img::format("PACKRL.PH %s, %s, %s", rd, rs, rt);
11746 }
11747
11748
11749 /*
11750  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11751  *
11752  *   3         2         1
11753  *  10987654321098765432109876543210
11754  *  001000               00010001101
11755  *     rt -----
11756  *          rs -----
11757  *               rd -----
11758  */
11759 std::string NMD::PAUSE(uint64 instruction)
11760 {
11761     (void)instruction;
11762
11763     return "PAUSE ";
11764 }
11765
11766
11767 /*
11768  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11769  *
11770  *   3         2         1
11771  *  10987654321098765432109876543210
11772  *  001000               00010001101
11773  *     rt -----
11774  *          rs -----
11775  *               rd -----
11776  */
11777 std::string NMD::PICK_PH(uint64 instruction)
11778 {
11779     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11780     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11781     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11782
11783     std::string rd = GPR(copy(rd_value));
11784     std::string rs = GPR(copy(rs_value));
11785     std::string rt = GPR(copy(rt_value));
11786
11787     return img::format("PICK.PH %s, %s, %s", rd, rs, rt);
11788 }
11789
11790
11791 /*
11792  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11793  *
11794  *   3         2         1
11795  *  10987654321098765432109876543210
11796  *  001000               00010001101
11797  *     rt -----
11798  *          rs -----
11799  *               rd -----
11800  */
11801 std::string NMD::PICK_QB(uint64 instruction)
11802 {
11803     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11804     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
11805     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11806
11807     std::string rd = GPR(copy(rd_value));
11808     std::string rs = GPR(copy(rs_value));
11809     std::string rt = GPR(copy(rt_value));
11810
11811     return img::format("PICK.QB %s, %s, %s", rd, rs, rt);
11812 }
11813
11814
11815 /*
11816  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11817  *
11818  *   3         2         1
11819  *  10987654321098765432109876543210
11820  *  001000               00010001101
11821  *     rt -----
11822  *          rs -----
11823  *               rd -----
11824  */
11825 std::string NMD::PRECEQ_W_PHL(uint64 instruction)
11826 {
11827     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11828     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11829
11830     std::string rt = GPR(copy(rt_value));
11831     std::string rs = GPR(copy(rs_value));
11832
11833     return img::format("PRECEQ.W.PHL %s, %s", rt, rs);
11834 }
11835
11836
11837 /*
11838  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11839  *
11840  *   3         2         1
11841  *  10987654321098765432109876543210
11842  *  001000               00010001101
11843  *     rt -----
11844  *          rs -----
11845  *               rd -----
11846  */
11847 std::string NMD::PRECEQ_W_PHR(uint64 instruction)
11848 {
11849     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11850     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11851
11852     std::string rt = GPR(copy(rt_value));
11853     std::string rs = GPR(copy(rs_value));
11854
11855     return img::format("PRECEQ.W.PHR %s, %s", rt, rs);
11856 }
11857
11858
11859 /*
11860  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11861  *
11862  *   3         2         1
11863  *  10987654321098765432109876543210
11864  *  001000               00010001101
11865  *     rt -----
11866  *          rs -----
11867  *               rd -----
11868  */
11869 std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
11870 {
11871     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11872     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11873
11874     std::string rt = GPR(copy(rt_value));
11875     std::string rs = GPR(copy(rs_value));
11876
11877     return img::format("PRECEQU.PH.QBLA %s, %s", rt, rs);
11878 }
11879
11880
11881 /*
11882  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11883  *
11884  *   3         2         1
11885  *  10987654321098765432109876543210
11886  *  001000               00010001101
11887  *     rt -----
11888  *          rs -----
11889  *               rd -----
11890  */
11891 std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
11892 {
11893     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11894     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11895
11896     std::string rt = GPR(copy(rt_value));
11897     std::string rs = GPR(copy(rs_value));
11898
11899     return img::format("PRECEQU.PH.QBL %s, %s", rt, rs);
11900 }
11901
11902
11903 /*
11904  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11905  *
11906  *   3         2         1
11907  *  10987654321098765432109876543210
11908  *  001000               00010001101
11909  *     rt -----
11910  *          rs -----
11911  *               rd -----
11912  */
11913 std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
11914 {
11915     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11916     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11917
11918     std::string rt = GPR(copy(rt_value));
11919     std::string rs = GPR(copy(rs_value));
11920
11921     return img::format("PRECEQU.PH.QBRA %s, %s", rt, rs);
11922 }
11923
11924
11925 /*
11926  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11927  *
11928  *   3         2         1
11929  *  10987654321098765432109876543210
11930  *  001000               00010001101
11931  *     rt -----
11932  *          rs -----
11933  *               rd -----
11934  */
11935 std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
11936 {
11937     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11938     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11939
11940     std::string rt = GPR(copy(rt_value));
11941     std::string rs = GPR(copy(rs_value));
11942
11943     return img::format("PRECEQU.PH.QBR %s, %s", rt, rs);
11944 }
11945
11946
11947 /*
11948  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11949  *
11950  *   3         2         1
11951  *  10987654321098765432109876543210
11952  *  001000               00010001101
11953  *     rt -----
11954  *          rs -----
11955  *               rd -----
11956  */
11957 std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
11958 {
11959     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11960     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11961
11962     std::string rt = GPR(copy(rt_value));
11963     std::string rs = GPR(copy(rs_value));
11964
11965     return img::format("PRECEU.PH.QBLA %s, %s", rt, rs);
11966 }
11967
11968
11969 /*
11970  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11971  *
11972  *   3         2         1
11973  *  10987654321098765432109876543210
11974  *  001000               00010001101
11975  *     rt -----
11976  *          rs -----
11977  *               rd -----
11978  */
11979 std::string NMD::PRECEU_PH_QBL(uint64 instruction)
11980 {
11981     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11982     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11983
11984     std::string rt = GPR(copy(rt_value));
11985     std::string rs = GPR(copy(rs_value));
11986
11987     return img::format("PRECEU.PH.QBL %s, %s", rt, rs);
11988 }
11989
11990
11991 /*
11992  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11993  *
11994  *   3         2         1
11995  *  10987654321098765432109876543210
11996  *  001000               00010001101
11997  *     rt -----
11998  *          rs -----
11999  *               rd -----
12000  */
12001 std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
12002 {
12003     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12004     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12005
12006     std::string rt = GPR(copy(rt_value));
12007     std::string rs = GPR(copy(rs_value));
12008
12009     return img::format("PRECEU.PH.QBRA %s, %s", rt, rs);
12010 }
12011
12012
12013 /*
12014  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
12015  *
12016  *   3         2         1
12017  *  10987654321098765432109876543210
12018  *  001000               00010001101
12019  *     rt -----
12020  *          rs -----
12021  *               rd -----
12022  */
12023 std::string NMD::PRECEU_PH_QBR(uint64 instruction)
12024 {
12025     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12026     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12027
12028     std::string rt = GPR(copy(rt_value));
12029     std::string rs = GPR(copy(rs_value));
12030
12031     return img::format("PRECEU.PH.QBR %s, %s", rt, rs);
12032 }
12033
12034
12035 /*
12036  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
12037  *
12038  *   3         2         1
12039  *  10987654321098765432109876543210
12040  *  001000               00010001101
12041  *     rt -----
12042  *          rs -----
12043  *               rd -----
12044  */
12045 std::string NMD::PRECR_QB_PH(uint64 instruction)
12046 {
12047     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12048     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12049     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12050
12051     std::string rd = GPR(copy(rd_value));
12052     std::string rs = GPR(copy(rs_value));
12053     std::string rt = GPR(copy(rt_value));
12054
12055     return img::format("PRECR.QB.PH %s, %s, %s", rd, rs, rt);
12056 }
12057
12058
12059 /*
12060  *
12061  *
12062  *   3         2         1
12063  *  10987654321098765432109876543210
12064  *  001000               x1110000101
12065  *     rt -----
12066  *          rs -----
12067  *               rd -----
12068  */
12069 std::string NMD::PRECR_SRA_PH_W(uint64 instruction)
12070 {
12071     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12072     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12073     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12074
12075     std::string rt = GPR(copy(rt_value));
12076     std::string rs = GPR(copy(rs_value));
12077     std::string sa = IMMEDIATE(copy(sa_value));
12078
12079     return img::format("PRECR_SRA.PH.W %s, %s, %s", rt, rs, sa);
12080 }
12081
12082
12083 /*
12084  *
12085  *
12086  *   3         2         1
12087  *  10987654321098765432109876543210
12088  *  001000               x1110000101
12089  *     rt -----
12090  *          rs -----
12091  *               rd -----
12092  */
12093 std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction)
12094 {
12095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12096     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12098
12099     std::string rt = GPR(copy(rt_value));
12100     std::string rs = GPR(copy(rs_value));
12101     std::string sa = IMMEDIATE(copy(sa_value));
12102
12103     return img::format("PRECR_SRA_R.PH.W %s, %s, %s", rt, rs, sa);
12104 }
12105
12106
12107 /*
12108  *
12109  *
12110  *   3         2         1
12111  *  10987654321098765432109876543210
12112  *  001000               x1110000101
12113  *     rt -----
12114  *          rs -----
12115  *               rd -----
12116  */
12117 std::string NMD::PRECRQ_PH_W(uint64 instruction)
12118 {
12119     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12120     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12121     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12122
12123     std::string rd = GPR(copy(rd_value));
12124     std::string rs = GPR(copy(rs_value));
12125     std::string rt = GPR(copy(rt_value));
12126
12127     return img::format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt);
12128 }
12129
12130
12131 /*
12132  *
12133  *
12134  *   3         2         1
12135  *  10987654321098765432109876543210
12136  *  001000               x1110000101
12137  *     rt -----
12138  *          rs -----
12139  *               rd -----
12140  */
12141 std::string NMD::PRECRQ_QB_PH(uint64 instruction)
12142 {
12143     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12144     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12145     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12146
12147     std::string rd = GPR(copy(rd_value));
12148     std::string rs = GPR(copy(rs_value));
12149     std::string rt = GPR(copy(rt_value));
12150
12151     return img::format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt);
12152 }
12153
12154
12155 /*
12156  *
12157  *
12158  *   3         2         1
12159  *  10987654321098765432109876543210
12160  *  001000               x1110000101
12161  *     rt -----
12162  *          rs -----
12163  *               rd -----
12164  */
12165 std::string NMD::PRECRQ_RS_PH_W(uint64 instruction)
12166 {
12167     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12168     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12169     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12170
12171     std::string rd = GPR(copy(rd_value));
12172     std::string rs = GPR(copy(rs_value));
12173     std::string rt = GPR(copy(rt_value));
12174
12175     return img::format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt);
12176 }
12177
12178
12179 /*
12180  *
12181  *
12182  *   3         2         1
12183  *  10987654321098765432109876543210
12184  *  001000               x1110000101
12185  *     rt -----
12186  *          rs -----
12187  *               rd -----
12188  */
12189 std::string NMD::PRECRQU_S_QB_PH(uint64 instruction)
12190 {
12191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12192     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12193     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12194
12195     std::string rd = GPR(copy(rd_value));
12196     std::string rs = GPR(copy(rs_value));
12197     std::string rt = GPR(copy(rt_value));
12198
12199     return img::format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt);
12200 }
12201
12202
12203 /*
12204  *
12205  *
12206  *   3         2         1
12207  *  10987654321098765432109876543210
12208  *  001000               x1110000101
12209  *     rt -----
12210  *          rs -----
12211  *               rd -----
12212  */
12213 std::string NMD::PREF_S9_(uint64 instruction)
12214 {
12215     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
12216     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12218
12219     std::string hint = IMMEDIATE(copy(hint_value));
12220     std::string s = IMMEDIATE(copy(s_value));
12221     std::string rs = GPR(copy(rs_value));
12222
12223     return img::format("PREF %s, %s(%s)", hint, s, rs);
12224 }
12225
12226
12227 /*
12228  *
12229  *
12230  *   3         2         1
12231  *  10987654321098765432109876543210
12232  *  001000               x1110000101
12233  *     rt -----
12234  *          rs -----
12235  *               rd -----
12236  */
12237 std::string NMD::PREF_U12_(uint64 instruction)
12238 {
12239     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12240     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12242
12243     std::string hint = IMMEDIATE(copy(hint_value));
12244     std::string u = IMMEDIATE(copy(u_value));
12245     std::string rs = GPR(copy(rs_value));
12246
12247     return img::format("PREF %s, %s(%s)", hint, u, rs);
12248 }
12249
12250
12251 /*
12252  *
12253  *
12254  *   3         2         1
12255  *  10987654321098765432109876543210
12256  *  001000               x1110000101
12257  *     rt -----
12258  *          rs -----
12259  *               rd -----
12260  */
12261 std::string NMD::PREFE(uint64 instruction)
12262 {
12263     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
12264     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12266
12267     std::string hint = IMMEDIATE(copy(hint_value));
12268     std::string s = IMMEDIATE(copy(s_value));
12269     std::string rs = GPR(copy(rs_value));
12270
12271     return img::format("PREFE %s, %s(%s)", hint, s, rs);
12272 }
12273
12274
12275 /*
12276  *
12277  *
12278  *   3         2         1
12279  *  10987654321098765432109876543210
12280  *  001000               x1110000101
12281  *     rt -----
12282  *          rs -----
12283  *               rd -----
12284  */
12285 std::string NMD::PREPEND(uint64 instruction)
12286 {
12287     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12288     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12289     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12290
12291     std::string rt = GPR(copy(rt_value));
12292     std::string rs = GPR(copy(rs_value));
12293     std::string sa = IMMEDIATE(copy(sa_value));
12294
12295     return img::format("PREPEND %s, %s, %s", rt, rs, sa);
12296 }
12297
12298
12299 /*
12300  *
12301  *
12302  *   3         2         1
12303  *  10987654321098765432109876543210
12304  *  001000               x1110000101
12305  *     rt -----
12306  *          rs -----
12307  *               rd -----
12308  */
12309 std::string NMD::RADDU_W_QB(uint64 instruction)
12310 {
12311     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12312     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12313
12314     std::string rt = GPR(copy(rt_value));
12315     std::string rs = GPR(copy(rs_value));
12316
12317     return img::format("RADDU.W.QB %s, %s", rt, rs);
12318 }
12319
12320
12321 /*
12322  *
12323  *
12324  *   3         2         1
12325  *  10987654321098765432109876543210
12326  *  001000               x1110000101
12327  *     rt -----
12328  *          rs -----
12329  *               rd -----
12330  */
12331 std::string NMD::RDDSP(uint64 instruction)
12332 {
12333     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12334     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
12335
12336     std::string rt = GPR(copy(rt_value));
12337     std::string mask = IMMEDIATE(copy(mask_value));
12338
12339     return img::format("RDDSP %s, %s", rt, mask);
12340 }
12341
12342
12343 /*
12344  *
12345  *
12346  *   3         2         1
12347  *  10987654321098765432109876543210
12348  *  001000               x1110000101
12349  *     rt -----
12350  *          rs -----
12351  *               rd -----
12352  */
12353 std::string NMD::RDHWR(uint64 instruction)
12354 {
12355     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12356     uint64 hs_value = extract_hs_20_19_18_17_16(instruction);
12357     uint64 sel_value = extract_sel_13_12_11(instruction);
12358
12359     std::string rt = GPR(copy(rt_value));
12360     std::string hs = CPR(copy(hs_value));
12361     std::string sel = IMMEDIATE(copy(sel_value));
12362
12363     return img::format("RDHWR %s, %s, %s", rt, hs, sel);
12364 }
12365
12366
12367 /*
12368  *
12369  *
12370  *   3         2         1
12371  *  10987654321098765432109876543210
12372  *  001000               x1110000101
12373  *     rt -----
12374  *          rs -----
12375  *               rd -----
12376  */
12377 std::string NMD::RDPGPR(uint64 instruction)
12378 {
12379     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12380     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12381
12382     std::string rt = GPR(copy(rt_value));
12383     std::string rs = GPR(copy(rs_value));
12384
12385     return img::format("RDPGPR %s, %s", rt, rs);
12386 }
12387
12388
12389 /*
12390  *
12391  *
12392  *   3         2         1
12393  *  10987654321098765432109876543210
12394  *  001000               x1110000101
12395  *     rt -----
12396  *          rs -----
12397  *               rd -----
12398  */
12399 std::string NMD::RECIP_D(uint64 instruction)
12400 {
12401     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12402     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12403
12404     std::string ft = FPR(copy(ft_value));
12405     std::string fs = FPR(copy(fs_value));
12406
12407     return img::format("RECIP.D %s, %s", ft, fs);
12408 }
12409
12410
12411 /*
12412  *
12413  *
12414  *   3         2         1
12415  *  10987654321098765432109876543210
12416  *  001000               x1110000101
12417  *     rt -----
12418  *          rs -----
12419  *               rd -----
12420  */
12421 std::string NMD::RECIP_S(uint64 instruction)
12422 {
12423     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12424     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12425
12426     std::string ft = FPR(copy(ft_value));
12427     std::string fs = FPR(copy(fs_value));
12428
12429     return img::format("RECIP.S %s, %s", ft, fs);
12430 }
12431
12432
12433 /*
12434  *
12435  *
12436  *   3         2         1
12437  *  10987654321098765432109876543210
12438  *  001000               x1110000101
12439  *     rt -----
12440  *          rs -----
12441  *               rd -----
12442  */
12443 std::string NMD::REPL_PH(uint64 instruction)
12444 {
12445     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12446     int64 s_value = extr_sil11il0bs10Tmsb9(instruction);
12447
12448     std::string rt = GPR(copy(rt_value));
12449     std::string s = IMMEDIATE(copy(s_value));
12450
12451     return img::format("REPL.PH %s, %s", rt, s);
12452 }
12453
12454
12455 /*
12456  *
12457  *
12458  *   3         2         1
12459  *  10987654321098765432109876543210
12460  *  001000               x1110000101
12461  *     rt -----
12462  *          rs -----
12463  *               rd -----
12464  */
12465 std::string NMD::REPL_QB(uint64 instruction)
12466 {
12467     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12468     uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction);
12469
12470     std::string rt = GPR(copy(rt_value));
12471     std::string u = IMMEDIATE(copy(u_value));
12472
12473     return img::format("REPL.QB %s, %s", rt, u);
12474 }
12475
12476
12477 /*
12478  *
12479  *
12480  *   3         2         1
12481  *  10987654321098765432109876543210
12482  *  001000               x1110000101
12483  *     rt -----
12484  *          rs -----
12485  *               rd -----
12486  */
12487 std::string NMD::REPLV_PH(uint64 instruction)
12488 {
12489     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12490     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12491
12492     std::string rt = GPR(copy(rt_value));
12493     std::string rs = GPR(copy(rs_value));
12494
12495     return img::format("REPLV.PH %s, %s", rt, rs);
12496 }
12497
12498
12499 /*
12500  *
12501  *
12502  *   3         2         1
12503  *  10987654321098765432109876543210
12504  *  001000               x1110000101
12505  *     rt -----
12506  *          rs -----
12507  *               rd -----
12508  */
12509 std::string NMD::REPLV_QB(uint64 instruction)
12510 {
12511     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12512     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12513
12514     std::string rt = GPR(copy(rt_value));
12515     std::string rs = GPR(copy(rs_value));
12516
12517     return img::format("REPLV.QB %s, %s", rt, rs);
12518 }
12519
12520
12521 /*
12522  *
12523  *
12524  *   3         2         1
12525  *  10987654321098765432109876543210
12526  *  001000               x1110000101
12527  *     rt -----
12528  *          rs -----
12529  *               rd -----
12530  */
12531 std::string NMD::RESTORE_32_(uint64 instruction)
12532 {
12533     uint64 count_value = extract_count_19_18_17_16(instruction);
12534     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12535     uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);
12536     uint64 gp_value = extract_gp_2(instruction);
12537
12538     std::string u = IMMEDIATE(copy(u_value));
12539     return img::format("RESTORE %s%s", u,
12540                save_restore_list(rt_value, count_value, gp_value));
12541 }
12542
12543
12544 /*
12545  *
12546  *
12547  *   3         2         1
12548  *  10987654321098765432109876543210
12549  *  001000               x1110000101
12550  *     rt -----
12551  *          rs -----
12552  *               rd -----
12553  */
12554 std::string NMD::RESTORE_JRC_16_(uint64 instruction)
12555 {
12556     uint64 count_value = extract_count_3_2_1_0(instruction);
12557     uint64 rt1_value = extract_rtl_11(instruction);
12558     uint64 u_value = extr_uil4il4bs4Fmsb7(instruction);
12559
12560     std::string u = IMMEDIATE(copy(u_value));
12561     return img::format("RESTORE.JRC %s%s", u,
12562         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12563 }
12564
12565
12566 /*
12567  *
12568  *
12569  *   3         2         1
12570  *  10987654321098765432109876543210
12571  *  001000               x1110000101
12572  *     rt -----
12573  *          rs -----
12574  *               rd -----
12575  */
12576 std::string NMD::RESTORE_JRC_32_(uint64 instruction)
12577 {
12578     uint64 count_value = extract_count_19_18_17_16(instruction);
12579     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12580     uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);
12581     uint64 gp_value = extract_gp_2(instruction);
12582
12583     std::string u = IMMEDIATE(copy(u_value));
12584     return img::format("RESTORE.JRC %s%s", u,
12585                save_restore_list(rt_value, count_value, gp_value));
12586 }
12587
12588
12589 /*
12590  *
12591  *
12592  *   3         2         1
12593  *  10987654321098765432109876543210
12594  *  001000               x1110000101
12595  *     rt -----
12596  *          rs -----
12597  *               rd -----
12598  */
12599 std::string NMD::RESTOREF(uint64 instruction)
12600 {
12601     uint64 count_value = extract_count_19_18_17_16(instruction);
12602     uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);
12603
12604     std::string u = IMMEDIATE(copy(u_value));
12605     std::string count = IMMEDIATE(copy(count_value));
12606
12607     return img::format("RESTOREF %s, %s", u, count);
12608 }
12609
12610
12611 /*
12612  *
12613  *
12614  *   3         2         1
12615  *  10987654321098765432109876543210
12616  *  001000               x1110000101
12617  *     rt -----
12618  *          rs -----
12619  *               rd -----
12620  */
12621 std::string NMD::RINT_D(uint64 instruction)
12622 {
12623     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12624     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12625
12626     std::string ft = FPR(copy(ft_value));
12627     std::string fs = FPR(copy(fs_value));
12628
12629     return img::format("RINT.D %s, %s", ft, fs);
12630 }
12631
12632
12633 /*
12634  *
12635  *
12636  *   3         2         1
12637  *  10987654321098765432109876543210
12638  *  001000               x1110000101
12639  *     rt -----
12640  *          rs -----
12641  *               rd -----
12642  */
12643 std::string NMD::RINT_S(uint64 instruction)
12644 {
12645     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12646     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12647
12648     std::string ft = FPR(copy(ft_value));
12649     std::string fs = FPR(copy(fs_value));
12650
12651     return img::format("RINT.S %s, %s", ft, fs);
12652 }
12653
12654
12655 /*
12656  *
12657  *
12658  *   3         2         1
12659  *  10987654321098765432109876543210
12660  *  001000               x1110000101
12661  *     rt -----
12662  *          rs -----
12663  *               rd -----
12664  */
12665 std::string NMD::ROTR(uint64 instruction)
12666 {
12667     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12668     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12669     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12670
12671     std::string rt = GPR(copy(rt_value));
12672     std::string rs = GPR(copy(rs_value));
12673     std::string shift = IMMEDIATE(copy(shift_value));
12674
12675     return img::format("ROTR %s, %s, %s", rt, rs, shift);
12676 }
12677
12678
12679 /*
12680  *
12681  *
12682  *   3         2         1
12683  *  10987654321098765432109876543210
12684  *  001000               x1110000101
12685  *     rt -----
12686  *          rs -----
12687  *               rd -----
12688  */
12689 std::string NMD::ROTRV(uint64 instruction)
12690 {
12691     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12692     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
12693     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12694
12695     std::string rd = GPR(copy(rd_value));
12696     std::string rs = GPR(copy(rs_value));
12697     std::string rt = GPR(copy(rt_value));
12698
12699     return img::format("ROTRV %s, %s, %s", rd, rs, rt);
12700 }
12701
12702
12703 /*
12704  *
12705  *
12706  *   3         2         1
12707  *  10987654321098765432109876543210
12708  *  001000               x1110000101
12709  *     rt -----
12710  *          rs -----
12711  *               rd -----
12712  */
12713 std::string NMD::ROTX(uint64 instruction)
12714 {
12715     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12716     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12717     uint64 shiftx_value = extr_shiftxil7il1bs4Fmsb4(instruction);
12718     uint64 stripe_value = extract_stripe_6(instruction);
12719     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12720
12721     std::string rt = GPR(copy(rt_value));
12722     std::string rs = GPR(copy(rs_value));
12723     std::string shift = IMMEDIATE(copy(shift_value));
12724     std::string shiftx = IMMEDIATE(copy(shiftx_value));
12725     std::string stripe = IMMEDIATE(copy(stripe_value));
12726
12727     return img::format("ROTX %s, %s, %s, %s, %s",
12728                        rt, rs, shift, shiftx, stripe);
12729 }
12730
12731
12732 /*
12733  *
12734  *
12735  *   3         2         1
12736  *  10987654321098765432109876543210
12737  *  001000               x1110000101
12738  *     rt -----
12739  *          rs -----
12740  *               rd -----
12741  */
12742 std::string NMD::ROUND_L_D(uint64 instruction)
12743 {
12744     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12745     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12746
12747     std::string ft = FPR(copy(ft_value));
12748     std::string fs = FPR(copy(fs_value));
12749
12750     return img::format("ROUND.L.D %s, %s", ft, fs);
12751 }
12752
12753
12754 /*
12755  *
12756  *
12757  *   3         2         1
12758  *  10987654321098765432109876543210
12759  *  001000               x1110000101
12760  *     rt -----
12761  *          rs -----
12762  *               rd -----
12763  */
12764 std::string NMD::ROUND_L_S(uint64 instruction)
12765 {
12766     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12767     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12768
12769     std::string ft = FPR(copy(ft_value));
12770     std::string fs = FPR(copy(fs_value));
12771
12772     return img::format("ROUND.L.S %s, %s", ft, fs);
12773 }
12774
12775
12776 /*
12777  *
12778  *
12779  *   3         2         1
12780  *  10987654321098765432109876543210
12781  *  001000               x1110000101
12782  *     rt -----
12783  *          rs -----
12784  *               rd -----
12785  */
12786 std::string NMD::ROUND_W_D(uint64 instruction)
12787 {
12788     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12789     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12790
12791     std::string ft = FPR(copy(ft_value));
12792     std::string fs = FPR(copy(fs_value));
12793
12794     return img::format("ROUND.W.D %s, %s", ft, fs);
12795 }
12796
12797
12798 /*
12799  *
12800  *
12801  *   3         2         1
12802  *  10987654321098765432109876543210
12803  *  001000               x1110000101
12804  *     rt -----
12805  *          rs -----
12806  *               rd -----
12807  */
12808 std::string NMD::ROUND_W_S(uint64 instruction)
12809 {
12810     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12811     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12812
12813     std::string ft = FPR(copy(ft_value));
12814     std::string fs = FPR(copy(fs_value));
12815
12816     return img::format("ROUND.W.S %s, %s", ft, fs);
12817 }
12818
12819
12820 /*
12821  *
12822  *
12823  *   3         2         1
12824  *  10987654321098765432109876543210
12825  *  001000               x1110000101
12826  *     rt -----
12827  *          rs -----
12828  *               rd -----
12829  */
12830 std::string NMD::RSQRT_D(uint64 instruction)
12831 {
12832     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12833     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12834
12835     std::string ft = FPR(copy(ft_value));
12836     std::string fs = FPR(copy(fs_value));
12837
12838     return img::format("RSQRT.D %s, %s", ft, fs);
12839 }
12840
12841
12842 /*
12843  *
12844  *
12845  *   3         2         1
12846  *  10987654321098765432109876543210
12847  *  001000               x1110000101
12848  *     rt -----
12849  *          rs -----
12850  *               rd -----
12851  */
12852 std::string NMD::RSQRT_S(uint64 instruction)
12853 {
12854     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
12855     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
12856
12857     std::string ft = FPR(copy(ft_value));
12858     std::string fs = FPR(copy(fs_value));
12859
12860     return img::format("RSQRT.S %s, %s", ft, fs);
12861 }
12862
12863
12864 /*
12865  *
12866  *
12867  *   3         2         1
12868  *  10987654321098765432109876543210
12869  *  001000               01001001101
12870  *     rt -----
12871  *          rs -----
12872  *               rd -----
12873  */
12874 std::string NMD::SAVE_16_(uint64 instruction)
12875 {
12876     uint64 count_value = extract_count_3_2_1_0(instruction);
12877     uint64 rt1_value = extract_rtl_11(instruction);
12878     uint64 u_value = extr_uil4il4bs4Fmsb7(instruction);
12879
12880     std::string u = IMMEDIATE(copy(u_value));
12881     return img::format("SAVE %s%s", u,
12882         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12883 }
12884
12885
12886 /*
12887  *
12888  *
12889  *   3         2         1
12890  *  10987654321098765432109876543210
12891  *  001000               01001001101
12892  *     rt -----
12893  *          rs -----
12894  *               rd -----
12895  */
12896 std::string NMD::SAVE_32_(uint64 instruction)
12897 {
12898     uint64 count_value = extract_count_19_18_17_16(instruction);
12899     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12900     uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);
12901     uint64 gp_value = extract_gp_2(instruction);
12902
12903     std::string u = IMMEDIATE(copy(u_value));
12904     return img::format("SAVE %s%s", u,
12905                save_restore_list(rt_value, count_value, gp_value));
12906 }
12907
12908
12909 /*
12910  *
12911  *
12912  *   3         2         1
12913  *  10987654321098765432109876543210
12914  *  001000               01001001101
12915  *     rt -----
12916  *          rs -----
12917  *               rd -----
12918  */
12919 std::string NMD::SAVEF(uint64 instruction)
12920 {
12921     uint64 count_value = extract_count_19_18_17_16(instruction);
12922     uint64 u_value = extr_uil3il3bs9Fmsb11(instruction);
12923
12924     std::string u = IMMEDIATE(copy(u_value));
12925     std::string count = IMMEDIATE(copy(count_value));
12926
12927     return img::format("SAVEF %s, %s", u, count);
12928 }
12929
12930
12931 /*
12932  *
12933  *
12934  *   3         2         1
12935  *  10987654321098765432109876543210
12936  *  001000               01001001101
12937  *     rt -----
12938  *          rs -----
12939  *               rd -----
12940  */
12941 std::string NMD::SB_16_(uint64 instruction)
12942 {
12943     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
12944     uint64 u_value = extract_u_1_0(instruction);
12945     uint64 rs3_value = extract_rs3_6_5_4(instruction);
12946
12947     std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));
12948     std::string u = IMMEDIATE(copy(u_value));
12949     std::string rs3 = GPR(encode_gpr3(rs3_value));
12950
12951     return img::format("SB %s, %s(%s)", rtz3, u, rs3);
12952 }
12953
12954
12955 /*
12956  *
12957  *
12958  *   3         2         1
12959  *  10987654321098765432109876543210
12960  *  001000               01001001101
12961  *     rt -----
12962  *          rs -----
12963  *               rd -----
12964  */
12965 std::string NMD::SB_GP_(uint64 instruction)
12966 {
12967     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12968     uint64 u_value = extract_u_17_to_0(instruction);
12969
12970     std::string rt = GPR(copy(rt_value));
12971     std::string u = IMMEDIATE(copy(u_value));
12972
12973     return img::format("SB %s, %s($%d)", rt, u, 28);
12974 }
12975
12976
12977 /*
12978  *
12979  *
12980  *   3         2         1
12981  *  10987654321098765432109876543210
12982  *  001000               01001001101
12983  *     rt -----
12984  *          rs -----
12985  *               rd -----
12986  */
12987 std::string NMD::SB_S9_(uint64 instruction)
12988 {
12989     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12990     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
12991     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12992
12993     std::string rt = GPR(copy(rt_value));
12994     std::string s = IMMEDIATE(copy(s_value));
12995     std::string rs = GPR(copy(rs_value));
12996
12997     return img::format("SB %s, %s(%s)", rt, s, rs);
12998 }
12999
13000
13001 /*
13002  *
13003  *
13004  *   3         2         1
13005  *  10987654321098765432109876543210
13006  *  001000               01001001101
13007  *     rt -----
13008  *          rs -----
13009  *               rd -----
13010  */
13011 std::string NMD::SB_U12_(uint64 instruction)
13012 {
13013     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13014     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13015     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13016
13017     std::string rt = GPR(copy(rt_value));
13018     std::string u = IMMEDIATE(copy(u_value));
13019     std::string rs = GPR(copy(rs_value));
13020
13021     return img::format("SB %s, %s(%s)", rt, u, rs);
13022 }
13023
13024
13025 /*
13026  *
13027  *
13028  *   3         2         1
13029  *  10987654321098765432109876543210
13030  *  001000               01001001101
13031  *     rt -----
13032  *          rs -----
13033  *               rd -----
13034  */
13035 std::string NMD::SBE(uint64 instruction)
13036 {
13037     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13038     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13039     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13040
13041     std::string rt = GPR(copy(rt_value));
13042     std::string s = IMMEDIATE(copy(s_value));
13043     std::string rs = GPR(copy(rs_value));
13044
13045     return img::format("SBE %s, %s(%s)", rt, s, rs);
13046 }
13047
13048
13049 /*
13050  *
13051  *
13052  *   3         2         1
13053  *  10987654321098765432109876543210
13054  *  001000               01001001101
13055  *     rt -----
13056  *          rs -----
13057  *               rd -----
13058  */
13059 std::string NMD::SBX(uint64 instruction)
13060 {
13061     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13062     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
13063     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13064
13065     std::string rd = GPR(copy(rd_value));
13066     std::string rs = GPR(copy(rs_value));
13067     std::string rt = GPR(copy(rt_value));
13068
13069     return img::format("SBX %s, %s(%s)", rd, rs, rt);
13070 }
13071
13072
13073 /*
13074  *
13075  *
13076  *   3         2         1
13077  *  10987654321098765432109876543210
13078  *  001000               01001001101
13079  *     rt -----
13080  *          rs -----
13081  *               rd -----
13082  */
13083 std::string NMD::SC(uint64 instruction)
13084 {
13085     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13086     int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);
13087     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13088
13089     std::string rt = GPR(copy(rt_value));
13090     std::string s = IMMEDIATE(copy(s_value));
13091     std::string rs = GPR(copy(rs_value));
13092
13093     return img::format("SC %s, %s(%s)", rt, s, rs);
13094 }
13095
13096
13097 /*
13098  *
13099  *
13100  *   3         2         1
13101  *  10987654321098765432109876543210
13102  *  001000               01001001101
13103  *     rt -----
13104  *          rs -----
13105  *               rd -----
13106  */
13107 std::string NMD::SCD(uint64 instruction)
13108 {
13109     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13110     int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction);
13111     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13112
13113     std::string rt = GPR(copy(rt_value));
13114     std::string s = IMMEDIATE(copy(s_value));
13115     std::string rs = GPR(copy(rs_value));
13116
13117     return img::format("SCD %s, %s(%s)", rt, s, rs);
13118 }
13119
13120
13121 /*
13122  *
13123  *
13124  *   3         2         1
13125  *  10987654321098765432109876543210
13126  *  001000               01001001101
13127  *     rt -----
13128  *          rs -----
13129  *               rd -----
13130  */
13131 std::string NMD::SCDP(uint64 instruction)
13132 {
13133     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13134     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13135     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13136
13137     std::string rt = GPR(copy(rt_value));
13138     std::string ru = GPR(copy(ru_value));
13139     std::string rs = GPR(copy(rs_value));
13140
13141     return img::format("SCDP %s, %s, (%s)", rt, ru, rs);
13142 }
13143
13144
13145 /*
13146  *
13147  *
13148  *   3         2         1
13149  *  10987654321098765432109876543210
13150  *  001000               01001001101
13151  *     rt -----
13152  *          rs -----
13153  *               rd -----
13154  */
13155 std::string NMD::SCE(uint64 instruction)
13156 {
13157     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13158     int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction);
13159     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13160
13161     std::string rt = GPR(copy(rt_value));
13162     std::string s = IMMEDIATE(copy(s_value));
13163     std::string rs = GPR(copy(rs_value));
13164
13165     return img::format("SCE %s, %s(%s)", rt, s, rs);
13166 }
13167
13168
13169 /*
13170  *
13171  *
13172  *   3         2         1
13173  *  10987654321098765432109876543210
13174  *  001000               01001001101
13175  *     rt -----
13176  *          rs -----
13177  *               rd -----
13178  */
13179 std::string NMD::SCWP(uint64 instruction)
13180 {
13181     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13182     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13184
13185     std::string rt = GPR(copy(rt_value));
13186     std::string ru = GPR(copy(ru_value));
13187     std::string rs = GPR(copy(rs_value));
13188
13189     return img::format("SCWP %s, %s, (%s)", rt, ru, rs);
13190 }
13191
13192
13193 /*
13194  *
13195  *
13196  *   3         2         1
13197  *  10987654321098765432109876543210
13198  *  001000               01001001101
13199  *     rt -----
13200  *          rs -----
13201  *               rd -----
13202  */
13203 std::string NMD::SCWPE(uint64 instruction)
13204 {
13205     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13206     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13207     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13208
13209     std::string rt = GPR(copy(rt_value));
13210     std::string ru = GPR(copy(ru_value));
13211     std::string rs = GPR(copy(rs_value));
13212
13213     return img::format("SCWPE %s, %s, (%s)", rt, ru, rs);
13214 }
13215
13216
13217 /*
13218  *
13219  *
13220  *   3         2         1
13221  *  10987654321098765432109876543210
13222  *  001000               01001001101
13223  *     rt -----
13224  *          rs -----
13225  *               rd -----
13226  */
13227 std::string NMD::SD_GP_(uint64 instruction)
13228 {
13229     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13230     uint64 u_value = extr_uil3il3bs18Fmsb20(instruction);
13231
13232     std::string rt = GPR(copy(rt_value));
13233     std::string u = IMMEDIATE(copy(u_value));
13234
13235     return img::format("SD %s, %s($%d)", rt, u, 28);
13236 }
13237
13238
13239 /*
13240  *
13241  *
13242  *   3         2         1
13243  *  10987654321098765432109876543210
13244  *  001000               01001001101
13245  *     rt -----
13246  *          rs -----
13247  *               rd -----
13248  */
13249 std::string NMD::SD_S9_(uint64 instruction)
13250 {
13251     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13252     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13253     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13254
13255     std::string rt = GPR(copy(rt_value));
13256     std::string s = IMMEDIATE(copy(s_value));
13257     std::string rs = GPR(copy(rs_value));
13258
13259     return img::format("SD %s, %s(%s)", rt, s, rs);
13260 }
13261
13262
13263 /*
13264  *
13265  *
13266  *   3         2         1
13267  *  10987654321098765432109876543210
13268  *  001000               01001001101
13269  *     rt -----
13270  *          rs -----
13271  *               rd -----
13272  */
13273 std::string NMD::SD_U12_(uint64 instruction)
13274 {
13275     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13276     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13277     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13278
13279     std::string rt = GPR(copy(rt_value));
13280     std::string u = IMMEDIATE(copy(u_value));
13281     std::string rs = GPR(copy(rs_value));
13282
13283     return img::format("SD %s, %s(%s)", rt, u, rs);
13284 }
13285
13286
13287 /*
13288  *
13289  *
13290  *   3         2         1
13291  *  10987654321098765432109876543210
13292  *  001000               01001001101
13293  *     rt -----
13294  *          rs -----
13295  *               rd -----
13296  */
13297 std::string NMD::SDBBP_16_(uint64 instruction)
13298 {
13299     uint64 code_value = extract_code_2_1_0(instruction);
13300
13301     std::string code = IMMEDIATE(copy(code_value));
13302
13303     return img::format("SDBBP %s", code);
13304 }
13305
13306
13307 /*
13308  *
13309  *
13310  *   3         2         1
13311  *  10987654321098765432109876543210
13312  *  001000               01001001101
13313  *     rt -----
13314  *          rs -----
13315  *               rd -----
13316  */
13317 std::string NMD::SDBBP_32_(uint64 instruction)
13318 {
13319     uint64 code_value = extract_code_18_to_0(instruction);
13320
13321     std::string code = IMMEDIATE(copy(code_value));
13322
13323     return img::format("SDBBP %s", code);
13324 }
13325
13326
13327 /*
13328  *
13329  *
13330  *   3         2         1
13331  *  10987654321098765432109876543210
13332  *  001000               01001001101
13333  *     rt -----
13334  *          rs -----
13335  *               rd -----
13336  */
13337 std::string NMD::SDC1_GP_(uint64 instruction)
13338 {
13339     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13340     uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);
13341
13342     std::string ft = FPR(copy(ft_value));
13343     std::string u = IMMEDIATE(copy(u_value));
13344
13345     return img::format("SDC1 %s, %s($%d)", ft, u, 28);
13346 }
13347
13348
13349 /*
13350  *
13351  *
13352  *   3         2         1
13353  *  10987654321098765432109876543210
13354  *  001000               01001001101
13355  *     rt -----
13356  *          rs -----
13357  *               rd -----
13358  */
13359 std::string NMD::SDC1_S9_(uint64 instruction)
13360 {
13361     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13362     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13363     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13364
13365     std::string ft = FPR(copy(ft_value));
13366     std::string s = IMMEDIATE(copy(s_value));
13367     std::string rs = GPR(copy(rs_value));
13368
13369     return img::format("SDC1 %s, %s(%s)", ft, s, rs);
13370 }
13371
13372
13373 /*
13374  *
13375  *
13376  *   3         2         1
13377  *  10987654321098765432109876543210
13378  *  001000               01001001101
13379  *     rt -----
13380  *          rs -----
13381  *               rd -----
13382  */
13383 std::string NMD::SDC1_U12_(uint64 instruction)
13384 {
13385     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13386     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13387     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13388
13389     std::string ft = FPR(copy(ft_value));
13390     std::string u = IMMEDIATE(copy(u_value));
13391     std::string rs = GPR(copy(rs_value));
13392
13393     return img::format("SDC1 %s, %s(%s)", ft, u, rs);
13394 }
13395
13396
13397 /*
13398  *
13399  *
13400  *   3         2         1
13401  *  10987654321098765432109876543210
13402  *  001000               01001001101
13403  *     rt -----
13404  *          rs -----
13405  *               rd -----
13406  */
13407 std::string NMD::SDC1X(uint64 instruction)
13408 {
13409     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13410     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13411     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13412
13413     std::string ft = FPR(copy(ft_value));
13414     std::string rs = GPR(copy(rs_value));
13415     std::string rt = GPR(copy(rt_value));
13416
13417     return img::format("SDC1X %s, %s(%s)", ft, rs, rt);
13418 }
13419
13420
13421 /*
13422  *
13423  *
13424  *   3         2         1
13425  *  10987654321098765432109876543210
13426  *  001000               01001001101
13427  *     rt -----
13428  *          rs -----
13429  *               rd -----
13430  */
13431 std::string NMD::SDC1XS(uint64 instruction)
13432 {
13433     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13434     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13435     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13436
13437     std::string ft = FPR(copy(ft_value));
13438     std::string rs = GPR(copy(rs_value));
13439     std::string rt = GPR(copy(rt_value));
13440
13441     return img::format("SDC1XS %s, %s(%s)", ft, rs, rt);
13442 }
13443
13444
13445 /*
13446  *
13447  *
13448  *   3         2         1
13449  *  10987654321098765432109876543210
13450  *  001000               01001001101
13451  *     rt -----
13452  *          rs -----
13453  *               rd -----
13454  */
13455 std::string NMD::SDC2(uint64 instruction)
13456 {
13457     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
13458     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13459     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13460
13461     std::string cs = CPR(copy(cs_value));
13462     std::string s = IMMEDIATE(copy(s_value));
13463     std::string rs = GPR(copy(rs_value));
13464
13465     return img::format("SDC2 %s, %s(%s)", cs, s, rs);
13466 }
13467
13468
13469 /*
13470  *
13471  *
13472  *   3         2         1
13473  *  10987654321098765432109876543210
13474  *  001000               01001001101
13475  *     rt -----
13476  *          rs -----
13477  *               rd -----
13478  */
13479 std::string NMD::SDM(uint64 instruction)
13480 {
13481     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13482     uint64 count3_value = extract_count3_14_13_12(instruction);
13483     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13484     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13485
13486     std::string rt = GPR(copy(rt_value));
13487     std::string s = IMMEDIATE(copy(s_value));
13488     std::string rs = GPR(copy(rs_value));
13489     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
13490
13491     return img::format("SDM %s, %s(%s), %s", rt, s, rs, count3);
13492 }
13493
13494
13495 /*
13496  *
13497  *
13498  *   3         2         1
13499  *  10987654321098765432109876543210
13500  *  001000               01001001101
13501  *     rt -----
13502  *          rs -----
13503  *               rd -----
13504  */
13505 std::string NMD::SDPC_48_(uint64 instruction)
13506 {
13507     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
13508     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
13509
13510     std::string rt = GPR(copy(rt_value));
13511     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
13512
13513     return img::format("SDPC %s, %s", rt, s);
13514 }
13515
13516
13517 /*
13518  *
13519  *
13520  *   3         2         1
13521  *  10987654321098765432109876543210
13522  *  001000               01001001101
13523  *     rt -----
13524  *          rs -----
13525  *               rd -----
13526  */
13527 std::string NMD::SDXS(uint64 instruction)
13528 {
13529     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13530     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
13531     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13532
13533     std::string rd = GPR(copy(rd_value));
13534     std::string rs = GPR(copy(rs_value));
13535     std::string rt = GPR(copy(rt_value));
13536
13537     return img::format("SDXS %s, %s(%s)", rd, rs, rt);
13538 }
13539
13540
13541 /*
13542  *
13543  *
13544  *   3         2         1
13545  *  10987654321098765432109876543210
13546  *  001000               01001001101
13547  *     rt -----
13548  *          rs -----
13549  *               rd -----
13550  */
13551 std::string NMD::SDX(uint64 instruction)
13552 {
13553     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13554     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
13555     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13556
13557     std::string rd = GPR(copy(rd_value));
13558     std::string rs = GPR(copy(rs_value));
13559     std::string rt = GPR(copy(rt_value));
13560
13561     return img::format("SDX %s, %s(%s)", rd, rs, rt);
13562 }
13563
13564
13565 /*
13566  *
13567  *
13568  *   3         2         1
13569  *  10987654321098765432109876543210
13570  *  001000               01001001101
13571  *     rt -----
13572  *          rs -----
13573  *               rd -----
13574  */
13575 std::string NMD::SEB(uint64 instruction)
13576 {
13577     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13578     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13579
13580     std::string rt = GPR(copy(rt_value));
13581     std::string rs = GPR(copy(rs_value));
13582
13583     return img::format("SEB %s, %s", rt, rs);
13584 }
13585
13586
13587 /*
13588  *
13589  *
13590  *   3         2         1
13591  *  10987654321098765432109876543210
13592  *  001000               01001001101
13593  *     rt -----
13594  *          rs -----
13595  *               rd -----
13596  */
13597 std::string NMD::SEH(uint64 instruction)
13598 {
13599     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13600     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13601
13602     std::string rt = GPR(copy(rt_value));
13603     std::string rs = GPR(copy(rs_value));
13604
13605     return img::format("SEH %s, %s", rt, rs);
13606 }
13607
13608
13609 /*
13610  *
13611  *
13612  *   3         2         1
13613  *  10987654321098765432109876543210
13614  *  001000               01001001101
13615  *     rt -----
13616  *          rs -----
13617  *               rd -----
13618  */
13619 std::string NMD::SEL_D(uint64 instruction)
13620 {
13621     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13622     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13623     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13624
13625     std::string fd = FPR(copy(fd_value));
13626     std::string fs = FPR(copy(fs_value));
13627     std::string ft = FPR(copy(ft_value));
13628
13629     return img::format("SEL.D %s, %s, %s", fd, fs, ft);
13630 }
13631
13632
13633 /*
13634  *
13635  *
13636  *   3         2         1
13637  *  10987654321098765432109876543210
13638  *  001000               01001001101
13639  *     rt -----
13640  *          rs -----
13641  *               rd -----
13642  */
13643 std::string NMD::SEL_S(uint64 instruction)
13644 {
13645     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13646     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13647     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13648
13649     std::string fd = FPR(copy(fd_value));
13650     std::string fs = FPR(copy(fs_value));
13651     std::string ft = FPR(copy(ft_value));
13652
13653     return img::format("SEL.S %s, %s, %s", fd, fs, ft);
13654 }
13655
13656
13657 /*
13658  *
13659  *
13660  *   3         2         1
13661  *  10987654321098765432109876543210
13662  *  001000               01001001101
13663  *     rt -----
13664  *          rs -----
13665  *               rd -----
13666  */
13667 std::string NMD::SELEQZ_D(uint64 instruction)
13668 {
13669     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13670     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13671     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13672
13673     std::string fd = FPR(copy(fd_value));
13674     std::string fs = FPR(copy(fs_value));
13675     std::string ft = FPR(copy(ft_value));
13676
13677     return img::format("SELEQZ.D %s, %s, %s", fd, fs, ft);
13678 }
13679
13680
13681 /*
13682  *
13683  *
13684  *   3         2         1
13685  *  10987654321098765432109876543210
13686  *  001000               01001001101
13687  *     rt -----
13688  *          rs -----
13689  *               rd -----
13690  */
13691 std::string NMD::SELEQZ_S(uint64 instruction)
13692 {
13693     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13694     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13695     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13696
13697     std::string fd = FPR(copy(fd_value));
13698     std::string fs = FPR(copy(fs_value));
13699     std::string ft = FPR(copy(ft_value));
13700
13701     return img::format("SELEQZ.S %s, %s, %s", fd, fs, ft);
13702 }
13703
13704
13705 /*
13706  *
13707  *
13708  *   3         2         1
13709  *  10987654321098765432109876543210
13710  *  001000               01001001101
13711  *     rt -----
13712  *          rs -----
13713  *               rd -----
13714  */
13715 std::string NMD::SELNEZ_D(uint64 instruction)
13716 {
13717     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13718     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13719     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13720
13721     std::string fd = FPR(copy(fd_value));
13722     std::string fs = FPR(copy(fs_value));
13723     std::string ft = FPR(copy(ft_value));
13724
13725     return img::format("SELNEZ.D %s, %s, %s", fd, fs, ft);
13726 }
13727
13728
13729 /*
13730  *
13731  *
13732  *   3         2         1
13733  *  10987654321098765432109876543210
13734  *  001000               01001001101
13735  *     rt -----
13736  *          rs -----
13737  *               rd -----
13738  */
13739 std::string NMD::SELNEZ_S(uint64 instruction)
13740 {
13741     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
13742     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
13743     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
13744
13745     std::string fd = FPR(copy(fd_value));
13746     std::string fs = FPR(copy(fs_value));
13747     std::string ft = FPR(copy(ft_value));
13748
13749     return img::format("SELNEZ.S %s, %s, %s", fd, fs, ft);
13750 }
13751
13752
13753 /*
13754  *
13755  *
13756  *   3         2         1
13757  *  10987654321098765432109876543210
13758  *  001000               01001001101
13759  *     rt -----
13760  *          rs -----
13761  *               rd -----
13762  */
13763 std::string NMD::SEQI(uint64 instruction)
13764 {
13765     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13766     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13767     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13768
13769     std::string rt = GPR(copy(rt_value));
13770     std::string rs = GPR(copy(rs_value));
13771     std::string u = IMMEDIATE(copy(u_value));
13772
13773     return img::format("SEQI %s, %s, %s", rt, rs, u);
13774 }
13775
13776
13777 /*
13778  *
13779  *
13780  *   3         2         1
13781  *  10987654321098765432109876543210
13782  *  001000               01001001101
13783  *     rt -----
13784  *          rs -----
13785  *               rd -----
13786  */
13787 std::string NMD::SH_16_(uint64 instruction)
13788 {
13789     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
13790     uint64 u_value = extr_uil1il1bs2Fmsb2(instruction);
13791     uint64 rs3_value = extract_rs3_6_5_4(instruction);
13792
13793     std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));
13794     std::string u = IMMEDIATE(copy(u_value));
13795     std::string rs3 = GPR(encode_gpr3(rs3_value));
13796
13797     return img::format("SH %s, %s(%s)", rtz3, u, rs3);
13798 }
13799
13800
13801 /*
13802  *
13803  *
13804  *   3         2         1
13805  *  10987654321098765432109876543210
13806  *  001000               01001001101
13807  *     rt -----
13808  *          rs -----
13809  *               rd -----
13810  */
13811 std::string NMD::SH_GP_(uint64 instruction)
13812 {
13813     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13814     uint64 u_value = extr_uil1il1bs17Fmsb17(instruction);
13815
13816     std::string rt = GPR(copy(rt_value));
13817     std::string u = IMMEDIATE(copy(u_value));
13818
13819     return img::format("SH %s, %s($%d)", rt, u, 28);
13820 }
13821
13822
13823 /*
13824  *
13825  *
13826  *   3         2         1
13827  *  10987654321098765432109876543210
13828  *  001000               01001001101
13829  *     rt -----
13830  *          rs -----
13831  *               rd -----
13832  */
13833 std::string NMD::SH_S9_(uint64 instruction)
13834 {
13835     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13836     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13837     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13838
13839     std::string rt = GPR(copy(rt_value));
13840     std::string s = IMMEDIATE(copy(s_value));
13841     std::string rs = GPR(copy(rs_value));
13842
13843     return img::format("SH %s, %s(%s)", rt, s, rs);
13844 }
13845
13846
13847 /*
13848  *
13849  *
13850  *   3         2         1
13851  *  10987654321098765432109876543210
13852  *  001000               01001001101
13853  *     rt -----
13854  *          rs -----
13855  *               rd -----
13856  */
13857 std::string NMD::SH_U12_(uint64 instruction)
13858 {
13859     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13860     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13861     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13862
13863     std::string rt = GPR(copy(rt_value));
13864     std::string u = IMMEDIATE(copy(u_value));
13865     std::string rs = GPR(copy(rs_value));
13866
13867     return img::format("SH %s, %s(%s)", rt, u, rs);
13868 }
13869
13870
13871 /*
13872  *
13873  *
13874  *   3         2         1
13875  *  10987654321098765432109876543210
13876  *  001000               01001001101
13877  *     rt -----
13878  *          rs -----
13879  *               rd -----
13880  */
13881 std::string NMD::SHE(uint64 instruction)
13882 {
13883     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13884     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
13885     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13886
13887     std::string rt = GPR(copy(rt_value));
13888     std::string s = IMMEDIATE(copy(s_value));
13889     std::string rs = GPR(copy(rs_value));
13890
13891     return img::format("SHE %s, %s(%s)", rt, s, rs);
13892 }
13893
13894
13895 /*
13896  * SHILO ac, shift - Shift an Accumulator Value Leaving the Result in the Same
13897  *                     Accumulator
13898  *
13899  *   3         2         1
13900  *  10987654321098765432109876543210
13901  *  001000xxxx        xxxx0000011101
13902  *      shift ------
13903  *               ac --
13904  */
13905 std::string NMD::SHILO(uint64 instruction)
13906 {
13907     int64 shift_value = extract_shift_21_20_19_18_17_16(instruction);
13908     uint64 ac_value = extract_ac_13_12(instruction);
13909
13910     std::string shift = IMMEDIATE(copy(shift_value));
13911     std::string ac = AC(copy(ac_value));
13912
13913     return img::format("SHILO %s, %s", ac, shift);
13914 }
13915
13916
13917 /*
13918  * SHILOV ac, rs - Variable Shift of Accumulator Value Leaving the Result in
13919  *                   the Same Accumulator
13920  *
13921  *   3         2         1
13922  *  10987654321098765432109876543210
13923  *  001000xxxxx       01001001111111
13924  *          rs -----
13925  *               ac --
13926  */
13927 std::string NMD::SHILOV(uint64 instruction)
13928 {
13929     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13930     uint64 ac_value = extract_ac_13_12(instruction);
13931
13932     std::string rs = GPR(copy(rs_value));
13933     std::string ac = AC(copy(ac_value));
13934
13935     return img::format("SHILOV %s, %s", ac, rs);
13936 }
13937
13938
13939 /*
13940  * SHLL.PH rt, rs, sa - Shift Left Logical Vector Pair Halfwords
13941  *
13942  *   3         2         1
13943  *  10987654321098765432109876543210
13944  *  001000              001110110101
13945  *     rt -----
13946  *          rs -----
13947  *               sa ----
13948  */
13949 std::string NMD::SHLL_PH(uint64 instruction)
13950 {
13951     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13952     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13953     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13954
13955     std::string rt = GPR(copy(rt_value));
13956     std::string rs = GPR(copy(rs_value));
13957     std::string sa = IMMEDIATE(copy(sa_value));
13958
13959     return img::format("SHLL.PH %s, %s, %s", rt, rs, sa);
13960 }
13961
13962
13963 /*
13964  * SHLL.QB rt, rs, sa - Shift Left Logical Vector Quad Bytes
13965  *
13966  *   3         2         1
13967  *  10987654321098765432109876543210
13968  *  001000             0100001111111
13969  *     rt -----
13970  *          rs -----
13971  *               sa ---
13972  */
13973 std::string NMD::SHLL_QB(uint64 instruction)
13974 {
13975     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13976     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13977     uint64 sa_value = extract_sa_15_14_13(instruction);
13978
13979     std::string rt = GPR(copy(rt_value));
13980     std::string rs = GPR(copy(rs_value));
13981     std::string sa = IMMEDIATE(copy(sa_value));
13982
13983     return img::format("SHLL.QB %s, %s, %s", rt, rs, sa);
13984 }
13985
13986
13987 /*
13988  * SHLL_S.PH rt, rs, sa - Shift Left Logical Vector Pair Halfwords (saturated)
13989  *
13990  *   3         2         1
13991  *  10987654321098765432109876543210
13992  *  001000              001110110101
13993  *     rt -----
13994  *          rs -----
13995  *               sa ----
13996  */
13997 std::string NMD::SHLL_S_PH(uint64 instruction)
13998 {
13999     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14000     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14001     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14002
14003     std::string rt = GPR(copy(rt_value));
14004     std::string rs = GPR(copy(rs_value));
14005     std::string sa = IMMEDIATE(copy(sa_value));
14006
14007     return img::format("SHLL_S.PH %s, %s, %s", rt, rs, sa);
14008 }
14009
14010
14011 /*
14012  *
14013  *
14014  *   3         2         1
14015  *  10987654321098765432109876543210
14016  *  001000               01001001101
14017  *     rt -----
14018  *          rs -----
14019  *               rd -----
14020  */
14021 std::string NMD::SHLL_S_W(uint64 instruction)
14022 {
14023     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14024     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14025     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14026
14027     std::string rt = GPR(copy(rt_value));
14028     std::string rs = GPR(copy(rs_value));
14029     std::string sa = IMMEDIATE(copy(sa_value));
14030
14031     return img::format("SHLL_S.W %s, %s, %s", rt, rs, sa);
14032 }
14033
14034
14035 /*
14036  *
14037  *
14038  *   3         2         1
14039  *  10987654321098765432109876543210
14040  *  001000               01001001101
14041  *     rt -----
14042  *          rs -----
14043  *               rd -----
14044  */
14045 std::string NMD::SHLLV_PH(uint64 instruction)
14046 {
14047     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14048     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14049     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14050
14051     std::string rd = GPR(copy(rd_value));
14052     std::string rt = GPR(copy(rt_value));
14053     std::string rs = GPR(copy(rs_value));
14054
14055     return img::format("SHLLV.PH %s, %s, %s", rd, rt, rs);
14056 }
14057
14058
14059 /*
14060  *
14061  *
14062  *   3         2         1
14063  *  10987654321098765432109876543210
14064  *  001000               01001001101
14065  *     rt -----
14066  *          rs -----
14067  *               rd -----
14068  */
14069 std::string NMD::SHLLV_QB(uint64 instruction)
14070 {
14071     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14072     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14073     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14074
14075     std::string rd = GPR(copy(rd_value));
14076     std::string rt = GPR(copy(rt_value));
14077     std::string rs = GPR(copy(rs_value));
14078
14079     return img::format("SHLLV.QB %s, %s, %s", rd, rt, rs);
14080 }
14081
14082
14083 /*
14084  *
14085  *
14086  *   3         2         1
14087  *  10987654321098765432109876543210
14088  *  001000               01001001101
14089  *     rt -----
14090  *          rs -----
14091  *               rd -----
14092  */
14093 std::string NMD::SHLLV_S_PH(uint64 instruction)
14094 {
14095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14096     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14098
14099     std::string rd = GPR(copy(rd_value));
14100     std::string rt = GPR(copy(rt_value));
14101     std::string rs = GPR(copy(rs_value));
14102
14103     return img::format("SHLLV_S.PH %s, %s, %s", rd, rt, rs);
14104 }
14105
14106
14107 /*
14108  *
14109  *
14110  *   3         2         1
14111  *  10987654321098765432109876543210
14112  *  001000               01001001101
14113  *     rt -----
14114  *          rs -----
14115  *               rd -----
14116  */
14117 std::string NMD::SHLLV_S_W(uint64 instruction)
14118 {
14119     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14120     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14121     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14122
14123     std::string rd = GPR(copy(rd_value));
14124     std::string rt = GPR(copy(rt_value));
14125     std::string rs = GPR(copy(rs_value));
14126
14127     return img::format("SHLLV_S.W %s, %s, %s", rd, rt, rs);
14128 }
14129
14130
14131 /*
14132  *
14133  *
14134  *   3         2         1
14135  *  10987654321098765432109876543210
14136  *  001000               01001001101
14137  *     rt -----
14138  *          rs -----
14139  *               rd -----
14140  */
14141 std::string NMD::SHRA_PH(uint64 instruction)
14142 {
14143     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14144     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14145     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14146
14147     std::string rt = GPR(copy(rt_value));
14148     std::string rs = GPR(copy(rs_value));
14149     std::string sa = IMMEDIATE(copy(sa_value));
14150
14151     return img::format("SHRA.PH %s, %s, %s", rt, rs, sa);
14152 }
14153
14154
14155 /*
14156  *
14157  *
14158  *   3         2         1
14159  *  10987654321098765432109876543210
14160  *  001000               01001001101
14161  *     rt -----
14162  *          rs -----
14163  *               rd -----
14164  */
14165 std::string NMD::SHRA_QB(uint64 instruction)
14166 {
14167     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14168     uint64 sa_value = extract_sa_15_14_13(instruction);
14169     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14170
14171     std::string rt = GPR(copy(rt_value));
14172     std::string rs = GPR(copy(rs_value));
14173     std::string sa = IMMEDIATE(copy(sa_value));
14174
14175     return img::format("SHRA.QB %s, %s, %s", rt, rs, sa);
14176 }
14177
14178
14179 /*
14180  *
14181  *
14182  *   3         2         1
14183  *  10987654321098765432109876543210
14184  *  001000               01001001101
14185  *     rt -----
14186  *          rs -----
14187  *               rd -----
14188  */
14189 std::string NMD::SHRA_R_PH(uint64 instruction)
14190 {
14191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14192     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14193     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14194
14195     std::string rt = GPR(copy(rt_value));
14196     std::string rs = GPR(copy(rs_value));
14197     std::string sa = IMMEDIATE(copy(sa_value));
14198
14199     return img::format("SHRA_R.PH %s, %s, %s", rt, rs, sa);
14200 }
14201
14202
14203 /*
14204  *
14205  *
14206  *   3         2         1
14207  *  10987654321098765432109876543210
14208  *  001000               01001001101
14209  *     rt -----
14210  *          rs -----
14211  *               rd -----
14212  */
14213 std::string NMD::SHRA_R_QB(uint64 instruction)
14214 {
14215     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14216     uint64 sa_value = extract_sa_15_14_13(instruction);
14217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14218
14219     std::string rt = GPR(copy(rt_value));
14220     std::string rs = GPR(copy(rs_value));
14221     std::string sa = IMMEDIATE(copy(sa_value));
14222
14223     return img::format("SHRA_R.QB %s, %s, %s", rt, rs, sa);
14224 }
14225
14226
14227 /*
14228  *
14229  *
14230  *   3         2         1
14231  *  10987654321098765432109876543210
14232  *  001000               01001001101
14233  *     rt -----
14234  *          rs -----
14235  *               rd -----
14236  */
14237 std::string NMD::SHRA_R_W(uint64 instruction)
14238 {
14239     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14240     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14242
14243     std::string rt = GPR(copy(rt_value));
14244     std::string rs = GPR(copy(rs_value));
14245     std::string sa = IMMEDIATE(copy(sa_value));
14246
14247     return img::format("SHRA_R.W %s, %s, %s", rt, rs, sa);
14248 }
14249
14250
14251 /*
14252  *
14253  *
14254  *   3         2         1
14255  *  10987654321098765432109876543210
14256  *  001000               01001001101
14257  *     rt -----
14258  *          rs -----
14259  *               rd -----
14260  */
14261 std::string NMD::SHRAV_PH(uint64 instruction)
14262 {
14263     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14264     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14266
14267     std::string rd = GPR(copy(rd_value));
14268     std::string rt = GPR(copy(rt_value));
14269     std::string rs = GPR(copy(rs_value));
14270
14271     return img::format("SHRAV.PH %s, %s, %s", rd, rt, rs);
14272 }
14273
14274
14275 /*
14276  *
14277  *
14278  *   3         2         1
14279  *  10987654321098765432109876543210
14280  *  001000               01001001101
14281  *     rt -----
14282  *          rs -----
14283  *               rd -----
14284  */
14285 std::string NMD::SHRAV_QB(uint64 instruction)
14286 {
14287     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14288     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14289     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14290
14291     std::string rd = GPR(copy(rd_value));
14292     std::string rt = GPR(copy(rt_value));
14293     std::string rs = GPR(copy(rs_value));
14294
14295     return img::format("SHRAV.QB %s, %s, %s", rd, rt, rs);
14296 }
14297
14298
14299 /*
14300  *
14301  *
14302  *   3         2         1
14303  *  10987654321098765432109876543210
14304  *  001000               01001001101
14305  *     rt -----
14306  *          rs -----
14307  *               rd -----
14308  */
14309 std::string NMD::SHRAV_R_PH(uint64 instruction)
14310 {
14311     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14312     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14313     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14314
14315     std::string rd = GPR(copy(rd_value));
14316     std::string rt = GPR(copy(rt_value));
14317     std::string rs = GPR(copy(rs_value));
14318
14319     return img::format("SHRAV_R.PH %s, %s, %s", rd, rt, rs);
14320 }
14321
14322
14323 /*
14324  *
14325  *
14326  *   3         2         1
14327  *  10987654321098765432109876543210
14328  *  001000               01001001101
14329  *     rt -----
14330  *          rs -----
14331  *               rd -----
14332  */
14333 std::string NMD::SHRAV_R_QB(uint64 instruction)
14334 {
14335     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14336     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14337     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14338
14339     std::string rd = GPR(copy(rd_value));
14340     std::string rt = GPR(copy(rt_value));
14341     std::string rs = GPR(copy(rs_value));
14342
14343     return img::format("SHRAV_R.QB %s, %s, %s", rd, rt, rs);
14344 }
14345
14346
14347 /*
14348  *
14349  *
14350  *   3         2         1
14351  *  10987654321098765432109876543210
14352  *  001000               01001001101
14353  *     rt -----
14354  *          rs -----
14355  *               rd -----
14356  */
14357 std::string NMD::SHRAV_R_W(uint64 instruction)
14358 {
14359     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14360     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14361     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14362
14363     std::string rd = GPR(copy(rd_value));
14364     std::string rt = GPR(copy(rt_value));
14365     std::string rs = GPR(copy(rs_value));
14366
14367     return img::format("SHRAV_R.W %s, %s, %s", rd, rt, rs);
14368 }
14369
14370
14371 /*
14372  *
14373  *
14374  *   3         2         1
14375  *  10987654321098765432109876543210
14376  *  001000               01001001101
14377  *     rt -----
14378  *          rs -----
14379  *               rd -----
14380  */
14381 std::string NMD::SHRL_PH(uint64 instruction)
14382 {
14383     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14384     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14385     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14386
14387     std::string rt = GPR(copy(rt_value));
14388     std::string rs = GPR(copy(rs_value));
14389     std::string sa = IMMEDIATE(copy(sa_value));
14390
14391     return img::format("SHRL.PH %s, %s, %s", rt, rs, sa);
14392 }
14393
14394
14395 /*
14396  *
14397  *
14398  *   3         2         1
14399  *  10987654321098765432109876543210
14400  *  001000               01001001101
14401  *     rt -----
14402  *          rs -----
14403  *               rd -----
14404  */
14405 std::string NMD::SHRL_QB(uint64 instruction)
14406 {
14407     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14408     uint64 sa_value = extract_sa_15_14_13(instruction);
14409     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14410
14411     std::string rt = GPR(copy(rt_value));
14412     std::string rs = GPR(copy(rs_value));
14413     std::string sa = IMMEDIATE(copy(sa_value));
14414
14415     return img::format("SHRL.QB %s, %s, %s", rt, rs, sa);
14416 }
14417
14418
14419 /*
14420  *
14421  *
14422  *   3         2         1
14423  *  10987654321098765432109876543210
14424  *  001000               01001001101
14425  *     rt -----
14426  *          rs -----
14427  *               rd -----
14428  */
14429 std::string NMD::SHRLV_PH(uint64 instruction)
14430 {
14431     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14432     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14433     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14434
14435     std::string rd = GPR(copy(rd_value));
14436     std::string rt = GPR(copy(rt_value));
14437     std::string rs = GPR(copy(rs_value));
14438
14439     return img::format("SHRLV.PH %s, %s, %s", rd, rt, rs);
14440 }
14441
14442
14443 /*
14444  *
14445  *
14446  *   3         2         1
14447  *  10987654321098765432109876543210
14448  *  001000               01001001101
14449  *     rt -----
14450  *          rs -----
14451  *               rd -----
14452  */
14453 std::string NMD::SHRLV_QB(uint64 instruction)
14454 {
14455     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14456     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14457     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14458
14459     std::string rd = GPR(copy(rd_value));
14460     std::string rt = GPR(copy(rt_value));
14461     std::string rs = GPR(copy(rs_value));
14462
14463     return img::format("SHRLV.QB %s, %s, %s", rd, rt, rs);
14464 }
14465
14466
14467 /*
14468  *
14469  *
14470  *   3         2         1
14471  *  10987654321098765432109876543210
14472  *  001000               01001001101
14473  *     rt -----
14474  *          rs -----
14475  *               rd -----
14476  */
14477 std::string NMD::SHX(uint64 instruction)
14478 {
14479     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14480     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14481     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14482
14483     std::string rd = GPR(copy(rd_value));
14484     std::string rs = GPR(copy(rs_value));
14485     std::string rt = GPR(copy(rt_value));
14486
14487     return img::format("SHX %s, %s(%s)", rd, rs, rt);
14488 }
14489
14490
14491 /*
14492  *
14493  *
14494  *   3         2         1
14495  *  10987654321098765432109876543210
14496  *  001000               01001001101
14497  *     rt -----
14498  *          rs -----
14499  *               rd -----
14500  */
14501 std::string NMD::SHXS(uint64 instruction)
14502 {
14503     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14504     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14505     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14506
14507     std::string rd = GPR(copy(rd_value));
14508     std::string rs = GPR(copy(rs_value));
14509     std::string rt = GPR(copy(rt_value));
14510
14511     return img::format("SHXS %s, %s(%s)", rd, rs, rt);
14512 }
14513
14514
14515 /*
14516  *
14517  *
14518  *   3         2         1
14519  *  10987654321098765432109876543210
14520  *  001000               01001001101
14521  *     rt -----
14522  *          rs -----
14523  *               rd -----
14524  */
14525 std::string NMD::SIGRIE(uint64 instruction)
14526 {
14527     uint64 code_value = extract_code_18_to_0(instruction);
14528
14529     std::string code = IMMEDIATE(copy(code_value));
14530
14531     return img::format("SIGRIE %s", code);
14532 }
14533
14534
14535 /*
14536  *
14537  *
14538  *   3         2         1
14539  *  10987654321098765432109876543210
14540  *  001000               01001001101
14541  *     rt -----
14542  *          rs -----
14543  *               rd -----
14544  */
14545 std::string NMD::SLL_16_(uint64 instruction)
14546 {
14547     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14548     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14549     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14550
14551     std::string rt3 = GPR(encode_gpr3(rt3_value));
14552     std::string rs3 = GPR(encode_gpr3(rs3_value));
14553     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14554
14555     return img::format("SLL %s, %s, %s", rt3, rs3, shift3);
14556 }
14557
14558
14559 /*
14560  *
14561  *
14562  *   3         2         1
14563  *  10987654321098765432109876543210
14564  *  001000               01001001101
14565  *     rt -----
14566  *          rs -----
14567  *               rd -----
14568  */
14569 std::string NMD::SLL_32_(uint64 instruction)
14570 {
14571     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14572     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14574
14575     std::string rt = GPR(copy(rt_value));
14576     std::string rs = GPR(copy(rs_value));
14577     std::string shift = IMMEDIATE(copy(shift_value));
14578
14579     return img::format("SLL %s, %s, %s", rt, rs, shift);
14580 }
14581
14582
14583 /*
14584  *
14585  *
14586  *   3         2         1
14587  *  10987654321098765432109876543210
14588  *  001000               01001001101
14589  *     rt -----
14590  *          rs -----
14591  *               rd -----
14592  */
14593 std::string NMD::SLLV(uint64 instruction)
14594 {
14595     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14596     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14597     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14598
14599     std::string rd = GPR(copy(rd_value));
14600     std::string rs = GPR(copy(rs_value));
14601     std::string rt = GPR(copy(rt_value));
14602
14603     return img::format("SLLV %s, %s, %s", rd, rs, rt);
14604 }
14605
14606
14607 /*
14608  *
14609  *
14610  *   3         2         1
14611  *  10987654321098765432109876543210
14612  *  001000               01001001101
14613  *     rt -----
14614  *          rs -----
14615  *               rd -----
14616  */
14617 std::string NMD::SLT(uint64 instruction)
14618 {
14619     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14620     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14621     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14622
14623     std::string rd = GPR(copy(rd_value));
14624     std::string rs = GPR(copy(rs_value));
14625     std::string rt = GPR(copy(rt_value));
14626
14627     return img::format("SLT %s, %s, %s", rd, rs, rt);
14628 }
14629
14630
14631 /*
14632  *
14633  *
14634  *   3         2         1
14635  *  10987654321098765432109876543210
14636  *  001000               01001001101
14637  *     rt -----
14638  *          rs -----
14639  *               rd -----
14640  */
14641 std::string NMD::SLTI(uint64 instruction)
14642 {
14643     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14644     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14645     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14646
14647     std::string rt = GPR(copy(rt_value));
14648     std::string rs = GPR(copy(rs_value));
14649     std::string u = IMMEDIATE(copy(u_value));
14650
14651     return img::format("SLTI %s, %s, %s", rt, rs, u);
14652 }
14653
14654
14655 /*
14656  *
14657  *
14658  *   3         2         1
14659  *  10987654321098765432109876543210
14660  *  001000               01001001101
14661  *     rt -----
14662  *          rs -----
14663  *               rd -----
14664  */
14665 std::string NMD::SLTIU(uint64 instruction)
14666 {
14667     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14668     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14669     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14670
14671     std::string rt = GPR(copy(rt_value));
14672     std::string rs = GPR(copy(rs_value));
14673     std::string u = IMMEDIATE(copy(u_value));
14674
14675     return img::format("SLTIU %s, %s, %s", rt, rs, u);
14676 }
14677
14678
14679 /*
14680  *
14681  *
14682  *   3         2         1
14683  *  10987654321098765432109876543210
14684  *  001000               01001001101
14685  *     rt -----
14686  *          rs -----
14687  *               rd -----
14688  */
14689 std::string NMD::SLTU(uint64 instruction)
14690 {
14691     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14692     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14693     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14694
14695     std::string rd = GPR(copy(rd_value));
14696     std::string rs = GPR(copy(rs_value));
14697     std::string rt = GPR(copy(rt_value));
14698
14699     return img::format("SLTU %s, %s, %s", rd, rs, rt);
14700 }
14701
14702
14703 /*
14704  *
14705  *
14706  *   3         2         1
14707  *  10987654321098765432109876543210
14708  *  001000               01001001101
14709  *     rt -----
14710  *          rs -----
14711  *               rd -----
14712  */
14713 std::string NMD::SOV(uint64 instruction)
14714 {
14715     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14716     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14717     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14718
14719     std::string rd = GPR(copy(rd_value));
14720     std::string rs = GPR(copy(rs_value));
14721     std::string rt = GPR(copy(rt_value));
14722
14723     return img::format("SOV %s, %s, %s", rd, rs, rt);
14724 }
14725
14726
14727 /*
14728  *
14729  *
14730  *   3         2         1
14731  *  10987654321098765432109876543210
14732  *  001000               01001001101
14733  *     rt -----
14734  *          rs -----
14735  *               rd -----
14736  */
14737 std::string NMD::SPECIAL2(uint64 instruction)
14738 {
14739     uint64 op_value = extract_op_25_to_3(instruction);
14740
14741     std::string op = IMMEDIATE(copy(op_value));
14742
14743     return img::format("SPECIAL2 %s", op);
14744 }
14745
14746
14747 /*
14748  *
14749  *
14750  *   3         2         1
14751  *  10987654321098765432109876543210
14752  *  001000               01001001101
14753  *     rt -----
14754  *          rs -----
14755  *               rd -----
14756  */
14757 std::string NMD::SQRT_D(uint64 instruction)
14758 {
14759     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
14760     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
14761
14762     std::string ft = FPR(copy(ft_value));
14763     std::string fs = FPR(copy(fs_value));
14764
14765     return img::format("SQRT.D %s, %s", ft, fs);
14766 }
14767
14768
14769 /*
14770  *
14771  *
14772  *   3         2         1
14773  *  10987654321098765432109876543210
14774  *  001000               01001001101
14775  *     rt -----
14776  *          rs -----
14777  *               rd -----
14778  */
14779 std::string NMD::SQRT_S(uint64 instruction)
14780 {
14781     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
14782     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
14783
14784     std::string ft = FPR(copy(ft_value));
14785     std::string fs = FPR(copy(fs_value));
14786
14787     return img::format("SQRT.S %s, %s", ft, fs);
14788 }
14789
14790
14791 /*
14792  * SRA rd, rt, sa - Shift Word Right Arithmetic
14793  *
14794  *   3         2         1
14795  *  10987654321098765432109876543210
14796  *  00000000000               000011
14797  *          rt -----
14798  *               rd -----
14799  *                    sa -----
14800  */
14801 std::string NMD::SRA(uint64 instruction)
14802 {
14803     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14804     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14805     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14806
14807     std::string rt = GPR(copy(rt_value));
14808     std::string rs = GPR(copy(rs_value));
14809     std::string shift = IMMEDIATE(copy(shift_value));
14810
14811     return img::format("SRA %s, %s, %s", rt, rs, shift);
14812 }
14813
14814
14815 /*
14816  * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14817  *
14818  *   3         2         1
14819  *  10987654321098765432109876543210
14820  *  001000               00000000111
14821  *     rs -----
14822  *          rt -----
14823  *               rd -----
14824  */
14825 std::string NMD::SRAV(uint64 instruction)
14826 {
14827     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14828     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14829     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14830
14831     std::string rd = GPR(copy(rd_value));
14832     std::string rs = GPR(copy(rs_value));
14833     std::string rt = GPR(copy(rt_value));
14834
14835     return img::format("SRAV %s, %s, %s", rd, rs, rt);
14836 }
14837
14838
14839 /*
14840  *
14841  *
14842  *   3         2         1
14843  *  10987654321098765432109876543210
14844  *  001000               00000000111
14845  *     rs -----
14846  *          rt -----
14847  *               rd -----
14848  */
14849 std::string NMD::SRL_16_(uint64 instruction)
14850 {
14851     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14852     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14853     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14854
14855     std::string rt3 = GPR(encode_gpr3(rt3_value));
14856     std::string rs3 = GPR(encode_gpr3(rs3_value));
14857     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14858
14859     return img::format("SRL %s, %s, %s", rt3, rs3, shift3);
14860 }
14861
14862
14863 /*
14864  *
14865  *
14866  *   3         2         1
14867  *  10987654321098765432109876543210
14868  *  001000               01001001101
14869  *     rt -----
14870  *          rs -----
14871  *               rd -----
14872  */
14873 std::string NMD::SRL_32_(uint64 instruction)
14874 {
14875     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14876     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14877     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14878
14879     std::string rt = GPR(copy(rt_value));
14880     std::string rs = GPR(copy(rs_value));
14881     std::string shift = IMMEDIATE(copy(shift_value));
14882
14883     return img::format("SRL %s, %s, %s", rt, rs, shift);
14884 }
14885
14886
14887 /*
14888  *
14889  *
14890  *   3         2         1
14891  *  10987654321098765432109876543210
14892  *  001000               01001001101
14893  *     rt -----
14894  *          rs -----
14895  *               rd -----
14896  */
14897 std::string NMD::SRLV(uint64 instruction)
14898 {
14899     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14900     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14901     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14902
14903     std::string rd = GPR(copy(rd_value));
14904     std::string rs = GPR(copy(rs_value));
14905     std::string rt = GPR(copy(rt_value));
14906
14907     return img::format("SRLV %s, %s, %s", rd, rs, rt);
14908 }
14909
14910
14911 /*
14912  *
14913  *
14914  *   3         2         1
14915  *  10987654321098765432109876543210
14916  *  001000               01001001101
14917  *     rt -----
14918  *          rs -----
14919  *               rd -----
14920  */
14921 std::string NMD::SUB(uint64 instruction)
14922 {
14923     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14924     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14925     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14926
14927     std::string rd = GPR(copy(rd_value));
14928     std::string rs = GPR(copy(rs_value));
14929     std::string rt = GPR(copy(rt_value));
14930
14931     return img::format("SUB %s, %s, %s", rd, rs, rt);
14932 }
14933
14934
14935 /*
14936  *
14937  *
14938  *   3         2         1
14939  *  10987654321098765432109876543210
14940  *  001000               01001001101
14941  *     rt -----
14942  *          rs -----
14943  *               rd -----
14944  */
14945 std::string NMD::SUB_D(uint64 instruction)
14946 {
14947     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
14948     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
14949     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
14950
14951     std::string fd = FPR(copy(fd_value));
14952     std::string fs = FPR(copy(fs_value));
14953     std::string ft = FPR(copy(ft_value));
14954
14955     return img::format("SUB.D %s, %s, %s", fd, fs, ft);
14956 }
14957
14958
14959 /*
14960  *
14961  *
14962  *   3         2         1
14963  *  10987654321098765432109876543210
14964  *  001000               01001001101
14965  *     rt -----
14966  *          rs -----
14967  *               rd -----
14968  */
14969 std::string NMD::SUB_S(uint64 instruction)
14970 {
14971     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
14972     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
14973     uint64 fd_value = extract_fd_10_9_8_7_6(instruction);
14974
14975     std::string fd = FPR(copy(fd_value));
14976     std::string fs = FPR(copy(fs_value));
14977     std::string ft = FPR(copy(ft_value));
14978
14979     return img::format("SUB.S %s, %s, %s", fd, fs, ft);
14980 }
14981
14982
14983 /*
14984  *
14985  *
14986  *   3         2         1
14987  *  10987654321098765432109876543210
14988  *  001000               01001001101
14989  *     rt -----
14990  *          rs -----
14991  *               rd -----
14992  */
14993 std::string NMD::SUBQ_PH(uint64 instruction)
14994 {
14995     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14996     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
14997     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14998
14999     std::string rd = GPR(copy(rd_value));
15000     std::string rs = GPR(copy(rs_value));
15001     std::string rt = GPR(copy(rt_value));
15002
15003     return img::format("SUBQ.PH %s, %s, %s", rd, rs, rt);
15004 }
15005
15006
15007 /*
15008  * SUBQH.PH rd, rt, rs - Subtract Fractional Halfword Vectors And Shift Right
15009  *                         to Halve Results
15010  *
15011  *   3         2         1
15012  *  10987654321098765432109876543210
15013  *  001000               01001001101
15014  *     rt -----
15015  *          rs -----
15016  *               rd -----
15017  */
15018 std::string NMD::SUBQ_S_PH(uint64 instruction)
15019 {
15020     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15021     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15022     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15023
15024     std::string rd = GPR(copy(rd_value));
15025     std::string rs = GPR(copy(rs_value));
15026     std::string rt = GPR(copy(rt_value));
15027
15028     return img::format("SUBQ_S.PH %s, %s, %s", rd, rs, rt);
15029 }
15030
15031
15032 /*
15033  * SUBQH.PH rd, rt, rs - Subtract Fractional Halfword Vectors And Shift Right
15034  *                         to Halve Results
15035  *
15036  *   3         2         1
15037  *  10987654321098765432109876543210
15038  *  001000               01001001101
15039  *     rt -----
15040  *          rs -----
15041  *               rd -----
15042  */
15043 std::string NMD::SUBQ_S_W(uint64 instruction)
15044 {
15045     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15046     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15047     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15048
15049     std::string rd = GPR(copy(rd_value));
15050     std::string rs = GPR(copy(rs_value));
15051     std::string rt = GPR(copy(rt_value));
15052
15053     return img::format("SUBQ_S.W %s, %s, %s", rd, rs, rt);
15054 }
15055
15056
15057 /*
15058  * SUBQH.PH rd, rt, rs - Subtract Fractional Halfword Vectors And Shift Right
15059  *                         to Halve Results
15060  *
15061  *   3         2         1
15062  *  10987654321098765432109876543210
15063  *  001000               01001001101
15064  *     rt -----
15065  *          rs -----
15066  *               rd -----
15067  */
15068 std::string NMD::SUBQH_PH(uint64 instruction)
15069 {
15070     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15071     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15072     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15073
15074     std::string rd = GPR(copy(rd_value));
15075     std::string rs = GPR(copy(rs_value));
15076     std::string rt = GPR(copy(rt_value));
15077
15078     return img::format("SUBQH.PH %s, %s, %s", rd, rs, rt);
15079 }
15080
15081
15082 /*
15083  * SUBQH.PH rd, rt, rs - Subtract Fractional Halfword Vectors And Shift Right
15084  *                         to Halve Results
15085  *
15086  *   3         2         1
15087  *  10987654321098765432109876543210
15088  *  001000               01001001101
15089  *     rt -----
15090  *          rs -----
15091  *               rd -----
15092  */
15093 std::string NMD::SUBQH_R_PH(uint64 instruction)
15094 {
15095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15096     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15098
15099     std::string rd = GPR(copy(rd_value));
15100     std::string rs = GPR(copy(rs_value));
15101     std::string rt = GPR(copy(rt_value));
15102
15103     return img::format("SUBQH_R.PH %s, %s, %s", rd, rs, rt);
15104 }
15105
15106
15107 /*
15108  * SUBQH_R.PH rd, rt, rs - Subtract Fractional Halfword Vectors And Shift Right
15109  *                           to Halve Results (rounding)
15110  *
15111  *   3         2         1
15112  *  10987654321098765432109876543210
15113  *  001000               11001001101
15114  *     rt -----
15115  *          rs -----
15116  *               rd -----
15117  */
15118 std::string NMD::SUBQH_R_W(uint64 instruction)
15119 {
15120     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15121     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15122     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15123
15124     std::string rd = GPR(copy(rd_value));
15125     std::string rs = GPR(copy(rs_value));
15126     std::string rt = GPR(copy(rt_value));
15127
15128     return img::format("SUBQH_R.W %s, %s, %s", rd, rs, rt);
15129 }
15130
15131
15132 /*
15133  * SUBQH.W rd, rs, rt - Subtract Fractional Words And Shift Right to Halve
15134  *                        Results
15135  *
15136  *   3         2         1
15137  *  10987654321098765432109876543210
15138  *  001000               01010001101
15139  *     rt -----
15140  *          rs -----
15141  *               rd -----
15142  */
15143 std::string NMD::SUBQH_W(uint64 instruction)
15144 {
15145     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15146     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15147     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15148
15149     std::string rd = GPR(copy(rd_value));
15150     std::string rs = GPR(copy(rs_value));
15151     std::string rt = GPR(copy(rt_value));
15152
15153     return img::format("SUBQH.W %s, %s, %s", rd, rs, rt);
15154 }
15155
15156
15157 /*
15158  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15159  *
15160  *   3         2         1
15161  *  10987654321098765432109876543210
15162  *  001000               00010001101
15163  *     rt -----
15164  *          rs -----
15165  *               rd -----
15166  */
15167 std::string NMD::SUBU_16_(uint64 instruction)
15168 {
15169     uint64 rd3_value = extract_rd3_3_2_1(instruction);
15170     uint64 rt3_value = extract_rt3_9_8_7(instruction);
15171     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15172
15173     std::string rd3 = GPR(encode_gpr3(rd3_value));
15174     std::string rs3 = GPR(encode_gpr3(rs3_value));
15175     std::string rt3 = GPR(encode_gpr3(rt3_value));
15176
15177     return img::format("SUBU %s, %s, %s", rd3, rs3, rt3);
15178 }
15179
15180
15181 /*
15182  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15183  *
15184  *   3         2         1
15185  *  10987654321098765432109876543210
15186  *  001000               00010001101
15187  *     rt -----
15188  *          rs -----
15189  *               rd -----
15190  */
15191 std::string NMD::SUBU_32_(uint64 instruction)
15192 {
15193     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15194     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15195     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15196
15197     std::string rd = GPR(copy(rd_value));
15198     std::string rs = GPR(copy(rs_value));
15199     std::string rt = GPR(copy(rt_value));
15200
15201     return img::format("SUBU %s, %s, %s", rd, rs, rt);
15202 }
15203
15204
15205 /*
15206  * SUBU.PH rd, rs, rt - Subtract Unsigned Integer Halfwords
15207  *
15208  *   3         2         1
15209  *  10987654321098765432109876543210
15210  *  001000               01100001101
15211  *     rt -----
15212  *          rs -----
15213  *               rd -----
15214  */
15215 std::string NMD::SUBU_PH(uint64 instruction)
15216 {
15217     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15218     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15219     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15220
15221     std::string rd = GPR(copy(rd_value));
15222     std::string rs = GPR(copy(rs_value));
15223     std::string rt = GPR(copy(rt_value));
15224
15225     return img::format("SUBU.PH %s, %s, %s", rd, rs, rt);
15226 }
15227
15228
15229 /*
15230  * SUBU.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector
15231  *
15232  *   3         2         1
15233  *  10987654321098765432109876543210
15234  *  001000               01011001101
15235  *     rt -----
15236  *          rs -----
15237  *               rd -----
15238  */
15239 std::string NMD::SUBU_QB(uint64 instruction)
15240 {
15241     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15242     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15243     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15244
15245     std::string rd = GPR(copy(rd_value));
15246     std::string rs = GPR(copy(rs_value));
15247     std::string rt = GPR(copy(rt_value));
15248
15249     return img::format("SUBU.QB %s, %s, %s", rd, rs, rt);
15250 }
15251
15252
15253 /*
15254  * SUBU_S.PH rd, rs, rt - Subtract Unsigned Integer Halfwords (saturating)
15255  *
15256  *   3         2         1
15257  *  10987654321098765432109876543210
15258  *  001000               11100001101
15259  *     rt -----
15260  *          rs -----
15261  *               rd -----
15262  */
15263 std::string NMD::SUBU_S_PH(uint64 instruction)
15264 {
15265     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15266     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15267     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15268
15269     std::string rd = GPR(copy(rd_value));
15270     std::string rs = GPR(copy(rs_value));
15271     std::string rt = GPR(copy(rt_value));
15272
15273     return img::format("SUBU_S.PH %s, %s, %s", rd, rs, rt);
15274 }
15275
15276
15277 /*
15278  * SUBU_S.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector (saturating)
15279  *
15280  *   3         2         1
15281  *  10987654321098765432109876543210
15282  *  001000               11011001101
15283  *     rt -----
15284  *          rs -----
15285  *               rd -----
15286  */
15287 std::string NMD::SUBU_S_QB(uint64 instruction)
15288 {
15289     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15290     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15291     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15292
15293     std::string rd = GPR(copy(rd_value));
15294     std::string rs = GPR(copy(rs_value));
15295     std::string rt = GPR(copy(rt_value));
15296
15297     return img::format("SUBU_S.QB %s, %s, %s", rd, rs, rt);
15298 }
15299
15300
15301 /*
15302  * SUBUH.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
15303  *                         Results
15304  *
15305  *   3         2         1
15306  *  10987654321098765432109876543210
15307  *  001000               01101001101
15308  *     rt -----
15309  *          rs -----
15310  *               rd -----
15311  */
15312 std::string NMD::SUBUH_QB(uint64 instruction)
15313 {
15314     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15315     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15316     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15317
15318     std::string rd = GPR(copy(rd_value));
15319     std::string rs = GPR(copy(rs_value));
15320     std::string rt = GPR(copy(rt_value));
15321
15322     return img::format("SUBUH.QB %s, %s, %s", rd, rs, rt);
15323 }
15324
15325
15326 /*
15327  * SUBUH_R.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
15328  *                           Results (rounding)
15329  *
15330  *   3         2         1
15331  *  10987654321098765432109876543210
15332  *  001000               11101001101
15333  *     rt -----
15334  *          rs -----
15335  *               rd -----
15336  */
15337 std::string NMD::SUBUH_R_QB(uint64 instruction)
15338 {
15339     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15340     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15341     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15342
15343     std::string rd = GPR(copy(rd_value));
15344     std::string rs = GPR(copy(rs_value));
15345     std::string rt = GPR(copy(rt_value));
15346
15347     return img::format("SUBUH_R.QB %s, %s, %s", rd, rs, rt);
15348 }
15349
15350
15351 /*
15352  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15353  *
15354  *   3         2         1
15355  *  10987654321098765432109876543210
15356  *  001000               00010001101
15357  *     rt -----
15358  *          rs -----
15359  *               rd -----
15360  */
15361 std::string NMD::SW_16_(uint64 instruction)
15362 {
15363     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15364     uint64 u_value = extr_uil0il2bs4Fmsb5(instruction);
15365     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15366
15367     std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));
15368     std::string u = IMMEDIATE(copy(u_value));
15369     std::string rs3 = GPR(encode_gpr3(rs3_value));
15370
15371     return img::format("SW %s, %s(%s)", rtz3, u, rs3);
15372 }
15373
15374
15375 /*
15376  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15377  *
15378  *   3         2         1
15379  *  10987654321098765432109876543210
15380  *  001000               00010001101
15381  *     rt -----
15382  *          rs -----
15383  *               rd -----
15384  */
15385 std::string NMD::SW_4X4_(uint64 instruction)
15386 {
15387     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
15388     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
15389     uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction);
15390
15391     std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value));
15392     std::string u = IMMEDIATE(copy(u_value));
15393     std::string rs4 = GPR(encode_gpr4(rs4_value));
15394
15395     return img::format("SW %s, %s(%s)", rtz4, u, rs4);
15396 }
15397
15398
15399 /*
15400  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15401  *
15402  *   3         2         1
15403  *  10987654321098765432109876543210
15404  *  001000               00010001101
15405  *     rt -----
15406  *          rs -----
15407  *               rd -----
15408  */
15409 std::string NMD::SW_GP16_(uint64 instruction)
15410 {
15411     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15412     uint64 u_value = extr_uil0il2bs7Fmsb8(instruction);
15413
15414     std::string rtz3 = GPR(encode_gpr3_store(rtz3_value));
15415     std::string u = IMMEDIATE(copy(u_value));
15416
15417     return img::format("SW %s, %s($%d)", rtz3, u, 28);
15418 }
15419
15420
15421 /*
15422  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15423  *
15424  *   3         2         1
15425  *  10987654321098765432109876543210
15426  *  001000               00010001101
15427  *     rt -----
15428  *          rs -----
15429  *               rd -----
15430  */
15431 std::string NMD::SW_GP_(uint64 instruction)
15432 {
15433     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15434     uint64 u_value = extr_uil2il2bs19Fmsb20(instruction);
15435
15436     std::string rt = GPR(copy(rt_value));
15437     std::string u = IMMEDIATE(copy(u_value));
15438
15439     return img::format("SW %s, %s($%d)", rt, u, 28);
15440 }
15441
15442
15443 /*
15444  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15445  *
15446  *   3         2         1
15447  *  10987654321098765432109876543210
15448  *  001000               00010001101
15449  *     rt -----
15450  *          rs -----
15451  *               rd -----
15452  */
15453 std::string NMD::SW_S9_(uint64 instruction)
15454 {
15455     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15456     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15457     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15458
15459     std::string rt = GPR(copy(rt_value));
15460     std::string s = IMMEDIATE(copy(s_value));
15461     std::string rs = GPR(copy(rs_value));
15462
15463     return img::format("SW %s, %s(%s)", rt, s, rs);
15464 }
15465
15466
15467 /*
15468  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15469  *
15470  *   3         2         1
15471  *  10987654321098765432109876543210
15472  *  001000               00010001101
15473  *     rt -----
15474  *          rs -----
15475  *               rd -----
15476  */
15477 std::string NMD::SW_SP_(uint64 instruction)
15478 {
15479     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
15480     uint64 u_value = extr_uil0il2bs5Fmsb6(instruction);
15481
15482     std::string rt = GPR(copy(rt_value));
15483     std::string u = IMMEDIATE(copy(u_value));
15484
15485     return img::format("SW %s, %s($%d)", rt, u, 29);
15486 }
15487
15488
15489 /*
15490  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15491  *
15492  *   3         2         1
15493  *  10987654321098765432109876543210
15494  *  001000               00010001101
15495  *     rt -----
15496  *          rs -----
15497  *               rd -----
15498  */
15499 std::string NMD::SW_U12_(uint64 instruction)
15500 {
15501     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15502     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15503     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15504
15505     std::string rt = GPR(copy(rt_value));
15506     std::string u = IMMEDIATE(copy(u_value));
15507     std::string rs = GPR(copy(rs_value));
15508
15509     return img::format("SW %s, %s(%s)", rt, u, rs);
15510 }
15511
15512
15513 /*
15514  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15515  *
15516  *   3         2         1
15517  *  10987654321098765432109876543210
15518  *  001000               00010001101
15519  *     rt -----
15520  *          rs -----
15521  *               rd -----
15522  */
15523 std::string NMD::SWC1_GP_(uint64 instruction)
15524 {
15525     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
15526     uint64 u_value = extr_uil2il2bs16Fmsb17(instruction);
15527
15528     std::string ft = FPR(copy(ft_value));
15529     std::string u = IMMEDIATE(copy(u_value));
15530
15531     return img::format("SWC1 %s, %s($%d)", ft, u, 28);
15532 }
15533
15534
15535 /*
15536  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15537  *
15538  *   3         2         1
15539  *  10987654321098765432109876543210
15540  *  001000               00010001101
15541  *     rt -----
15542  *          rs -----
15543  *               rd -----
15544  */
15545 std::string NMD::SWC1_S9_(uint64 instruction)
15546 {
15547     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15548     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
15549     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15550
15551     std::string ft = FPR(copy(ft_value));
15552     std::string s = IMMEDIATE(copy(s_value));
15553     std::string rs = GPR(copy(rs_value));
15554
15555     return img::format("SWC1 %s, %s(%s)", ft, s, rs);
15556 }
15557
15558
15559 /*
15560  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15561  *
15562  *   3         2         1
15563  *  10987654321098765432109876543210
15564  *  001000               00010001101
15565  *     rt -----
15566  *          rs -----
15567  *               rd -----
15568  */
15569 std::string NMD::SWC1_U12_(uint64 instruction)
15570 {
15571     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
15572     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15573     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15574
15575     std::string ft = FPR(copy(ft_value));
15576     std::string u = IMMEDIATE(copy(u_value));
15577     std::string rs = GPR(copy(rs_value));
15578
15579     return img::format("SWC1 %s, %s(%s)", ft, u, rs);
15580 }
15581
15582
15583 /*
15584  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15585  *
15586  *   3         2         1
15587  *  10987654321098765432109876543210
15588  *  001000               00010001101
15589  *     rt -----
15590  *          rs -----
15591  *               rd -----
15592  */
15593 std::string NMD::SWC1X(uint64 instruction)
15594 {
15595     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15596     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15597     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15598
15599     std::string ft = FPR(copy(ft_value));
15600     std::string rs = GPR(copy(rs_value));
15601     std::string rt = GPR(copy(rt_value));
15602
15603     return img::format("SWC1X %s, %s(%s)", ft, rs, rt);
15604 }
15605
15606
15607 /*
15608  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15609  *
15610  *   3         2         1
15611  *  10987654321098765432109876543210
15612  *  001000               00010001101
15613  *     rt -----
15614  *          rs -----
15615  *               rd -----
15616  */
15617 std::string NMD::SWC1XS(uint64 instruction)
15618 {
15619     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15620     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15621     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15622
15623     std::string ft = FPR(copy(ft_value));
15624     std::string rs = GPR(copy(rs_value));
15625     std::string rt = GPR(copy(rt_value));
15626
15627     return img::format("SWC1XS %s, %s(%s)", ft, rs, rt);
15628 }
15629
15630
15631 /*
15632  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15633  *
15634  *   3         2         1
15635  *  10987654321098765432109876543210
15636  *  001000               00010001101
15637  *     rt -----
15638  *          rs -----
15639  *               rd -----
15640  */
15641 std::string NMD::SWC2(uint64 instruction)
15642 {
15643     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
15644     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15645     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15646
15647     std::string cs = CPR(copy(cs_value));
15648     std::string s = IMMEDIATE(copy(s_value));
15649     std::string rs = GPR(copy(rs_value));
15650
15651     return img::format("SWC2 %s, %s(%s)", cs, s, rs);
15652 }
15653
15654
15655 /*
15656  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15657  *
15658  *   3         2         1
15659  *  10987654321098765432109876543210
15660  *  001000               00010001101
15661  *     rt -----
15662  *          rs -----
15663  *               rd -----
15664  */
15665 std::string NMD::SWE(uint64 instruction)
15666 {
15667     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15668     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15669     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15670
15671     std::string rt = GPR(copy(rt_value));
15672     std::string s = IMMEDIATE(copy(s_value));
15673     std::string rs = GPR(copy(rs_value));
15674
15675     return img::format("SWE %s, %s(%s)", rt, s, rs);
15676 }
15677
15678
15679 /*
15680  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15681  *
15682  *   3         2         1
15683  *  10987654321098765432109876543210
15684  *  001000               00010001101
15685  *     rt -----
15686  *          rs -----
15687  *               rd -----
15688  */
15689 std::string NMD::SWM(uint64 instruction)
15690 {
15691     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15692     uint64 count3_value = extract_count3_14_13_12(instruction);
15693     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15694     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15695
15696     std::string rt = GPR(copy(rt_value));
15697     std::string s = IMMEDIATE(copy(s_value));
15698     std::string rs = GPR(copy(rs_value));
15699     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
15700
15701     return img::format("SWM %s, %s(%s), %s", rt, s, rs, count3);
15702 }
15703
15704
15705 /*
15706  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15707  *
15708  *   3         2         1
15709  *  10987654321098765432109876543210
15710  *  001000               00010001101
15711  *     rt -----
15712  *          rs -----
15713  *               rd -----
15714  */
15715 std::string NMD::SWPC_48_(uint64 instruction)
15716 {
15717     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
15718     int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction);
15719
15720     std::string rt = GPR(copy(rt_value));
15721     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
15722
15723     return img::format("SWPC %s, %s", rt, s);
15724 }
15725
15726
15727 /*
15728  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15729  *
15730  *   3         2         1
15731  *  10987654321098765432109876543210
15732  *  001000               00010001101
15733  *     rt -----
15734  *          rs -----
15735  *               rd -----
15736  */
15737 std::string NMD::SWX(uint64 instruction)
15738 {
15739     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15740     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15741     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15742
15743     std::string rd = GPR(copy(rd_value));
15744     std::string rs = GPR(copy(rs_value));
15745     std::string rt = GPR(copy(rt_value));
15746
15747     return img::format("SWX %s, %s(%s)", rd, rs, rt);
15748 }
15749
15750
15751 /*
15752  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15753  *
15754  *   3         2         1
15755  *  10987654321098765432109876543210
15756  *  001000               00010001101
15757  *     rt -----
15758  *          rs -----
15759  *               rd -----
15760  */
15761 std::string NMD::SWXS(uint64 instruction)
15762 {
15763     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15764     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
15765     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15766
15767     std::string rd = GPR(copy(rd_value));
15768     std::string rs = GPR(copy(rs_value));
15769     std::string rt = GPR(copy(rt_value));
15770
15771     return img::format("SWXS %s, %s(%s)", rd, rs, rt);
15772 }
15773
15774
15775 /*
15776  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15777  *
15778  *   3         2         1
15779  *  10987654321098765432109876543210
15780  *  001000               00010001101
15781  *     rt -----
15782  *          rs -----
15783  *               rd -----
15784  */
15785 std::string NMD::SYNC(uint64 instruction)
15786 {
15787     uint64 stype_value = extract_stype_20_19_18_17_16(instruction);
15788
15789     std::string stype = IMMEDIATE(copy(stype_value));
15790
15791     return img::format("SYNC %s", stype);
15792 }
15793
15794
15795 /*
15796  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15797  *
15798  *   3         2         1
15799  *  10987654321098765432109876543210
15800  *  001000               00010001101
15801  *     rt -----
15802  *          rs -----
15803  *               rd -----
15804  */
15805 std::string NMD::SYNCI(uint64 instruction)
15806 {
15807     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15808     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15809
15810     std::string s = IMMEDIATE(copy(s_value));
15811     std::string rs = GPR(copy(rs_value));
15812
15813     return img::format("SYNCI %s(%s)", s, rs);
15814 }
15815
15816
15817 /*
15818  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15819  *
15820  *   3         2         1
15821  *  10987654321098765432109876543210
15822  *  001000               00010001101
15823  *     rt -----
15824  *          rs -----
15825  *               rd -----
15826  */
15827 std::string NMD::SYNCIE(uint64 instruction)
15828 {
15829     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
15830     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15831
15832     std::string s = IMMEDIATE(copy(s_value));
15833     std::string rs = GPR(copy(rs_value));
15834
15835     return img::format("SYNCIE %s(%s)", s, rs);
15836 }
15837
15838
15839 /*
15840  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15841  *
15842  *   3         2         1
15843  *  10987654321098765432109876543210
15844  *  001000               00010001101
15845  *     rt -----
15846  *          rs -----
15847  *               rd -----
15848  */
15849 std::string NMD::SYSCALL_16_(uint64 instruction)
15850 {
15851     uint64 code_value = extract_code_1_0(instruction);
15852
15853     std::string code = IMMEDIATE(copy(code_value));
15854
15855     return img::format("SYSCALL %s", code);
15856 }
15857
15858
15859 /*
15860  * SYSCALL code - System Call. Cause a System Call Exception
15861  *
15862  *   3         2         1
15863  *  10987654321098765432109876543210
15864  *  00000000000010
15865  *           code ------------------
15866  */
15867 std::string NMD::SYSCALL_32_(uint64 instruction)
15868 {
15869     uint64 code_value = extract_code_17_to_0(instruction);
15870
15871     std::string code = IMMEDIATE(copy(code_value));
15872
15873     return img::format("SYSCALL %s", code);
15874 }
15875
15876
15877 /*
15878  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15879  *
15880  *   3         2         1
15881  *  10987654321098765432109876543210
15882  *  001000               00010001101
15883  *     rt -----
15884  *          rs -----
15885  *               rd -----
15886  */
15887 std::string NMD::TEQ(uint64 instruction)
15888 {
15889     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15890     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15891
15892     std::string rs = GPR(copy(rs_value));
15893     std::string rt = GPR(copy(rt_value));
15894
15895     return img::format("TEQ %s, %s", rs, rt);
15896 }
15897
15898
15899 /*
15900  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15901  *
15902  *   3         2         1
15903  *  10987654321098765432109876543210
15904  *  001000               00010001101
15905  *     rt -----
15906  *          rs -----
15907  *               rd -----
15908  */
15909 std::string NMD::TLBGINV(uint64 instruction)
15910 {
15911     (void)instruction;
15912
15913     return "TLBGINV ";
15914 }
15915
15916
15917 /*
15918  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15919  *
15920  *   3         2         1
15921  *  10987654321098765432109876543210
15922  *  001000               00010001101
15923  *     rt -----
15924  *          rs -----
15925  *               rd -----
15926  */
15927 std::string NMD::TLBGINVF(uint64 instruction)
15928 {
15929     (void)instruction;
15930
15931     return "TLBGINVF ";
15932 }
15933
15934
15935 /*
15936  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15937  *
15938  *   3         2         1
15939  *  10987654321098765432109876543210
15940  *  001000               00010001101
15941  *     rt -----
15942  *          rs -----
15943  *               rd -----
15944  */
15945 std::string NMD::TLBGP(uint64 instruction)
15946 {
15947     (void)instruction;
15948
15949     return "TLBGP ";
15950 }
15951
15952
15953 /*
15954  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15955  *
15956  *   3         2         1
15957  *  10987654321098765432109876543210
15958  *  001000               00010001101
15959  *     rt -----
15960  *          rs -----
15961  *               rd -----
15962  */
15963 std::string NMD::TLBGR(uint64 instruction)
15964 {
15965     (void)instruction;
15966
15967     return "TLBGR ";
15968 }
15969
15970
15971 /*
15972  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15973  *
15974  *   3         2         1
15975  *  10987654321098765432109876543210
15976  *  001000               00010001101
15977  *     rt -----
15978  *          rs -----
15979  *               rd -----
15980  */
15981 std::string NMD::TLBGWI(uint64 instruction)
15982 {
15983     (void)instruction;
15984
15985     return "TLBGWI ";
15986 }
15987
15988
15989 /*
15990  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15991  *
15992  *   3         2         1
15993  *  10987654321098765432109876543210
15994  *  001000               00010001101
15995  *     rt -----
15996  *          rs -----
15997  *               rd -----
15998  */
15999 std::string NMD::TLBGWR(uint64 instruction)
16000 {
16001     (void)instruction;
16002
16003     return "TLBGWR ";
16004 }
16005
16006
16007 /*
16008  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16009  *
16010  *   3         2         1
16011  *  10987654321098765432109876543210
16012  *  001000               00010001101
16013  *     rt -----
16014  *          rs -----
16015  *               rd -----
16016  */
16017 std::string NMD::TLBINV(uint64 instruction)
16018 {
16019     (void)instruction;
16020
16021     return "TLBINV ";
16022 }
16023
16024
16025 /*
16026  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16027  *
16028  *   3         2         1
16029  *  10987654321098765432109876543210
16030  *  001000               00010001101
16031  *     rt -----
16032  *          rs -----
16033  *               rd -----
16034  */
16035 std::string NMD::TLBINVF(uint64 instruction)
16036 {
16037     (void)instruction;
16038
16039     return "TLBINVF ";
16040 }
16041
16042
16043 /*
16044  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16045  *
16046  *   3         2         1
16047  *  10987654321098765432109876543210
16048  *  001000               00010001101
16049  *     rt -----
16050  *          rs -----
16051  *               rd -----
16052  */
16053 std::string NMD::TLBP(uint64 instruction)
16054 {
16055     (void)instruction;
16056
16057     return "TLBP ";
16058 }
16059
16060
16061 /*
16062  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16063  *
16064  *   3         2         1
16065  *  10987654321098765432109876543210
16066  *  001000               00010001101
16067  *     rt -----
16068  *          rs -----
16069  *               rd -----
16070  */
16071 std::string NMD::TLBR(uint64 instruction)
16072 {
16073     (void)instruction;
16074
16075     return "TLBR ";
16076 }
16077
16078
16079 /*
16080  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16081  *
16082  *   3         2         1
16083  *  10987654321098765432109876543210
16084  *  001000               00010001101
16085  *     rt -----
16086  *          rs -----
16087  *               rd -----
16088  */
16089 std::string NMD::TLBWI(uint64 instruction)
16090 {
16091     (void)instruction;
16092
16093     return "TLBWI ";
16094 }
16095
16096
16097 /*
16098  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16099  *
16100  *   3         2         1
16101  *  10987654321098765432109876543210
16102  *  001000               00010001101
16103  *     rt -----
16104  *          rs -----
16105  *               rd -----
16106  */
16107 std::string NMD::TLBWR(uint64 instruction)
16108 {
16109     (void)instruction;
16110
16111     return "TLBWR ";
16112 }
16113
16114
16115 /*
16116  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16117  *
16118  *   3         2         1
16119  *  10987654321098765432109876543210
16120  *  001000               00010001101
16121  *     rt -----
16122  *          rs -----
16123  *               rd -----
16124  */
16125 std::string NMD::TNE(uint64 instruction)
16126 {
16127     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16128     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16129
16130     std::string rs = GPR(copy(rs_value));
16131     std::string rt = GPR(copy(rt_value));
16132
16133     return img::format("TNE %s, %s", rs, rt);
16134 }
16135
16136
16137 /*
16138  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16139  *
16140  *   3         2         1
16141  *  10987654321098765432109876543210
16142  *  001000               00010001101
16143  *     rt -----
16144  *          rs -----
16145  *               rd -----
16146  */
16147 std::string NMD::TRUNC_L_D(uint64 instruction)
16148 {
16149     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
16150     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
16151
16152     std::string ft = FPR(copy(ft_value));
16153     std::string fs = FPR(copy(fs_value));
16154
16155     return img::format("TRUNC.L.D %s, %s", ft, fs);
16156 }
16157
16158
16159 /*
16160  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16161  *
16162  *   3         2         1
16163  *  10987654321098765432109876543210
16164  *  001000               00010001101
16165  *     rt -----
16166  *          rs -----
16167  *               rd -----
16168  */
16169 std::string NMD::TRUNC_L_S(uint64 instruction)
16170 {
16171     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
16172     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
16173
16174     std::string ft = FPR(copy(ft_value));
16175     std::string fs = FPR(copy(fs_value));
16176
16177     return img::format("TRUNC.L.S %s, %s", ft, fs);
16178 }
16179
16180
16181 /*
16182  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16183  *
16184  *   3         2         1
16185  *  10987654321098765432109876543210
16186  *  001000               00010001101
16187  *     rt -----
16188  *          rs -----
16189  *               rd -----
16190  */
16191 std::string NMD::TRUNC_W_D(uint64 instruction)
16192 {
16193     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
16194     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
16195
16196     std::string ft = FPR(copy(ft_value));
16197     std::string fs = FPR(copy(fs_value));
16198
16199     return img::format("TRUNC.W.D %s, %s", ft, fs);
16200 }
16201
16202
16203 /*
16204  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16205  *
16206  *   3         2         1
16207  *  10987654321098765432109876543210
16208  *  001000               00010001101
16209  *     rt -----
16210  *          rs -----
16211  *               rd -----
16212  */
16213 std::string NMD::TRUNC_W_S(uint64 instruction)
16214 {
16215     uint64 fs_value = extract_fs_15_14_13_12_11(instruction);
16216     uint64 ft_value = extract_ft_20_19_18_17_16(instruction);
16217
16218     std::string ft = FPR(copy(ft_value));
16219     std::string fs = FPR(copy(fs_value));
16220
16221     return img::format("TRUNC.W.S %s, %s", ft, fs);
16222 }
16223
16224
16225 /*
16226  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16227  *
16228  *   3         2         1
16229  *  10987654321098765432109876543210
16230  *  001000               00010001101
16231  *     rt -----
16232  *          rs -----
16233  *               rd -----
16234  */
16235 std::string NMD::UALDM(uint64 instruction)
16236 {
16237     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16238     uint64 count3_value = extract_count3_14_13_12(instruction);
16239     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16240     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16241
16242     std::string rt = GPR(copy(rt_value));
16243     std::string s = IMMEDIATE(copy(s_value));
16244     std::string rs = GPR(copy(rs_value));
16245     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16246
16247     return img::format("UALDM %s, %s(%s), %s", rt, s, rs, count3);
16248 }
16249
16250
16251 /*
16252  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16253  *
16254  *   3         2         1
16255  *  10987654321098765432109876543210
16256  *  001000               00010001101
16257  *     rt -----
16258  *          rs -----
16259  *               rd -----
16260  */
16261 std::string NMD::UALH(uint64 instruction)
16262 {
16263     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16264     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16266
16267     std::string rt = GPR(copy(rt_value));
16268     std::string s = IMMEDIATE(copy(s_value));
16269     std::string rs = GPR(copy(rs_value));
16270
16271     return img::format("UALH %s, %s(%s)", rt, s, rs);
16272 }
16273
16274
16275 /*
16276  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16277  *
16278  *   3         2         1
16279  *  10987654321098765432109876543210
16280  *  001000               00010001101
16281  *     rt -----
16282  *          rs -----
16283  *               rd -----
16284  */
16285 std::string NMD::UALWM(uint64 instruction)
16286 {
16287     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16288     uint64 count3_value = extract_count3_14_13_12(instruction);
16289     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16290     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16291
16292     std::string rt = GPR(copy(rt_value));
16293     std::string s = IMMEDIATE(copy(s_value));
16294     std::string rs = GPR(copy(rs_value));
16295     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16296
16297     return img::format("UALWM %s, %s(%s), %s", rt, s, rs, count3);
16298 }
16299
16300
16301 /*
16302  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16303  *
16304  *   3         2         1
16305  *  10987654321098765432109876543210
16306  *  001000               00010001101
16307  *     rt -----
16308  *          rs -----
16309  *               rd -----
16310  */
16311 std::string NMD::UASDM(uint64 instruction)
16312 {
16313     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16314     uint64 count3_value = extract_count3_14_13_12(instruction);
16315     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16316     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16317
16318     std::string rt = GPR(copy(rt_value));
16319     std::string s = IMMEDIATE(copy(s_value));
16320     std::string rs = GPR(copy(rs_value));
16321     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16322
16323     return img::format("UASDM %s, %s(%s), %s", rt, s, rs, count3);
16324 }
16325
16326
16327 /*
16328  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16329  *
16330  *   3         2         1
16331  *  10987654321098765432109876543210
16332  *  001000               00010001101
16333  *     rt -----
16334  *          rs -----
16335  *               rd -----
16336  */
16337 std::string NMD::UASH(uint64 instruction)
16338 {
16339     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16340     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16341     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16342
16343     std::string rt = GPR(copy(rt_value));
16344     std::string s = IMMEDIATE(copy(s_value));
16345     std::string rs = GPR(copy(rs_value));
16346
16347     return img::format("UASH %s, %s(%s)", rt, s, rs);
16348 }
16349
16350
16351 /*
16352  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16353  *
16354  *   3         2         1
16355  *  10987654321098765432109876543210
16356  *  001000               00010001101
16357  *     rt -----
16358  *          rs -----
16359  *               rd -----
16360  */
16361 std::string NMD::UASWM(uint64 instruction)
16362 {
16363     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16364     uint64 count3_value = extract_count3_14_13_12(instruction);
16365     int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction);
16366     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16367
16368     std::string rt = GPR(copy(rt_value));
16369     std::string s = IMMEDIATE(copy(s_value));
16370     std::string rs = GPR(copy(rs_value));
16371     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16372
16373     return img::format("UASWM %s, %s(%s), %s", rt, s, rs, count3);
16374 }
16375
16376
16377 /*
16378  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16379  *
16380  *   3         2         1
16381  *  10987654321098765432109876543210
16382  *  001000               00010001101
16383  *     rt -----
16384  *          rs -----
16385  *               rd -----
16386  */
16387 std::string NMD::UDI(uint64 instruction)
16388 {
16389     uint64 op_value = extract_op_25_to_3(instruction);
16390
16391     std::string op = IMMEDIATE(copy(op_value));
16392
16393     return img::format("UDI %s", op);
16394 }
16395
16396
16397 /*
16398  * WAIT code - Enter Wait State
16399  *
16400  *   3         2         1
16401  *  10987654321098765432109876543210
16402  *  001000          1100001101111111
16403  *   code ----------
16404  */
16405 std::string NMD::WAIT(uint64 instruction)
16406 {
16407     uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction);
16408
16409     std::string code = IMMEDIATE(copy(code_value));
16410
16411     return img::format("WAIT %s", code);
16412 }
16413
16414
16415 /*
16416  * WRDSP rt, mask - Write Fields to DSPControl Register from a GPR
16417  *
16418  *   3         2         1
16419  *  10987654321098765432109876543210
16420  *  001000            01011001111111
16421  *     rt -----
16422  *        mask -------
16423  */
16424 std::string NMD::WRDSP(uint64 instruction)
16425 {
16426     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16427     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
16428
16429     std::string rt = GPR(copy(rt_value));
16430     std::string mask = IMMEDIATE(copy(mask_value));
16431
16432     return img::format("WRDSP %s, %s", rt, mask);
16433 }
16434
16435
16436 /*
16437  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16438  *
16439  *   3         2         1
16440  *  10987654321098765432109876543210
16441  *  001000               00010001101
16442  *     rt -----
16443  *          rs -----
16444  *               rd -----
16445  */
16446 std::string NMD::WRPGPR(uint64 instruction)
16447 {
16448     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16449     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16450
16451     std::string rt = GPR(copy(rt_value));
16452     std::string rs = GPR(copy(rs_value));
16453
16454     return img::format("WRPGPR %s, %s", rt, rs);
16455 }
16456
16457
16458 /*
16459  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16460  *
16461  *   3         2         1
16462  *  10987654321098765432109876543210
16463  *  001000               00010001101
16464  *     rt -----
16465  *          rs -----
16466  *               rd -----
16467  */
16468 std::string NMD::XOR_16_(uint64 instruction)
16469 {
16470     uint64 rt3_value = extract_rt3_9_8_7(instruction);
16471     uint64 rs3_value = extract_rs3_6_5_4(instruction);
16472
16473     std::string rs3 = GPR(encode_gpr3(rs3_value));
16474     std::string rt3 = GPR(encode_gpr3(rt3_value));
16475
16476     return img::format("XOR %s, %s", rs3, rt3);
16477 }
16478
16479
16480 /*
16481  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16482  *
16483  *   3         2         1
16484  *  10987654321098765432109876543210
16485  *  001000               00010001101
16486  *     rt -----
16487  *          rs -----
16488  *               rd -----
16489  */
16490 std::string NMD::XOR_32_(uint64 instruction)
16491 {
16492     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16493     uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
16494     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16495
16496     std::string rd = GPR(copy(rd_value));
16497     std::string rs = GPR(copy(rs_value));
16498     std::string rt = GPR(copy(rt_value));
16499
16500     return img::format("XOR %s, %s, %s", rd, rs, rt);
16501 }
16502
16503
16504 /*
16505  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16506  *
16507  *   3         2         1
16508  *  10987654321098765432109876543210
16509  *  001000               00010001101
16510  *     rt -----
16511  *          rs -----
16512  *               rd -----
16513  */
16514 std::string NMD::XORI(uint64 instruction)
16515 {
16516     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16517     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
16518     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16519
16520     std::string rt = GPR(copy(rt_value));
16521     std::string rs = GPR(copy(rs_value));
16522     std::string u = IMMEDIATE(copy(u_value));
16523
16524     return img::format("XORI %s, %s, %s", rt, rs, u);
16525 }
16526
16527
16528 /*
16529  * YIELD rt, rs -
16530  *
16531  *   3         2         1
16532  *  10987654321098765432109876543210
16533  *  001000               00010001101
16534  *     rt -----
16535  *          rs -----
16536  */
16537 std::string NMD::YIELD(uint64 instruction)
16538 {
16539     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16540     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16541
16542     std::string rt = GPR(copy(rt_value));
16543     std::string rs = GPR(copy(rs_value));
16544
16545     return img::format("YIELD %s, %s", rt, rs);
16546 }
16547
16548
16549
16550 NMD::Pool NMD::P_SYSCALL[2] = {
16551     { instruction         , 0                   , 0   , 32,
16552        0xfffc0000, 0x00080000, &NMD::SYSCALL_32_      , 0,
16553        0x0                 },        /* SYSCALL[32] */
16554     { instruction         , 0                   , 0   , 32,
16555        0xfffc0000, 0x000c0000, &NMD::HYPCALL          , 0,
16556        CP0_ | VZ_          },        /* HYPCALL */
16557 };
16558
16559
16560 NMD::Pool NMD::P_RI[4] = {
16561     { instruction         , 0                   , 0   , 32,
16562        0xfff80000, 0x00000000, &NMD::SIGRIE           , 0,
16563        0x0                 },        /* SIGRIE */
16564     { pool                , P_SYSCALL           , 2   , 32,
16565        0xfff80000, 0x00080000, 0                      , 0,
16566        0x0                 },        /* P.SYSCALL */
16567     { instruction         , 0                   , 0   , 32,
16568        0xfff80000, 0x00100000, &NMD::BREAK_32_        , 0,
16569        0x0                 },        /* BREAK[32] */
16570     { instruction         , 0                   , 0   , 32,
16571        0xfff80000, 0x00180000, &NMD::SDBBP_32_        , 0,
16572        EJTAG_              },        /* SDBBP[32] */
16573 };
16574
16575
16576 NMD::Pool NMD::P_ADDIU[2] = {
16577     { pool                , P_RI                , 4   , 32,
16578        0xffe00000, 0x00000000, 0                      , 0,
16579        0x0                 },        /* P.RI */
16580     { instruction         , 0                   , 0   , 32,
16581        0xfc000000, 0x00000000, &NMD::ADDIU_32_        , &NMD::ADDIU_32__cond   ,
16582        0x0                 },        /* ADDIU[32] */
16583 };
16584
16585
16586 NMD::Pool NMD::P_TRAP[2] = {
16587     { instruction         , 0                   , 0   , 32,
16588        0xfc0007ff, 0x20000000, &NMD::TEQ              , 0,
16589        XMMS_               },        /* TEQ */
16590     { instruction         , 0                   , 0   , 32,
16591        0xfc0007ff, 0x20000400, &NMD::TNE              , 0,
16592        XMMS_               },        /* TNE */
16593 };
16594
16595
16596 NMD::Pool NMD::P_CMOVE[2] = {
16597     { instruction         , 0                   , 0   , 32,
16598        0xfc0007ff, 0x20000210, &NMD::MOVZ             , 0,
16599        0x0                 },        /* MOVZ */
16600     { instruction         , 0                   , 0   , 32,
16601        0xfc0007ff, 0x20000610, &NMD::MOVN             , 0,
16602        0x0                 },        /* MOVN */
16603 };
16604
16605
16606 NMD::Pool NMD::P_D_MT_VPE[2] = {
16607     { instruction         , 0                   , 0   , 32,
16608        0xfc1f3fff, 0x20010ab0, &NMD::DMT              , 0,
16609        MT_                 },        /* DMT */
16610     { instruction         , 0                   , 0   , 32,
16611        0xfc1f3fff, 0x20000ab0, &NMD::DVPE             , 0,
16612        MT_                 },        /* DVPE */
16613 };
16614
16615
16616 NMD::Pool NMD::P_E_MT_VPE[2] = {
16617     { instruction         , 0                   , 0   , 32,
16618        0xfc1f3fff, 0x20010eb0, &NMD::EMT              , 0,
16619        MT_                 },        /* EMT */
16620     { instruction         , 0                   , 0   , 32,
16621        0xfc1f3fff, 0x20000eb0, &NMD::EVPE             , 0,
16622        MT_                 },        /* EVPE */
16623 };
16624
16625
16626 NMD::Pool NMD::_P_MT_VPE[2] = {
16627     { pool                , P_D_MT_VPE          , 2   , 32,
16628        0xfc003fff, 0x20000ab0, 0                      , 0,
16629        0x0                 },        /* P.D_MT_VPE */
16630     { pool                , P_E_MT_VPE          , 2   , 32,
16631        0xfc003fff, 0x20000eb0, 0                      , 0,
16632        0x0                 },        /* P.E_MT_VPE */
16633 };
16634
16635
16636 NMD::Pool NMD::P_MT_VPE[8] = {
16637     { reserved_block      , 0                   , 0   , 32,
16638        0xfc003bff, 0x200002b0, 0                      , 0,
16639        0x0                 },        /* P.MT_VPE~*(0) */
16640     { pool                , _P_MT_VPE           , 2   , 32,
16641        0xfc003bff, 0x20000ab0, 0                      , 0,
16642        0x0                 },        /* _P.MT_VPE */
16643     { reserved_block      , 0                   , 0   , 32,
16644        0xfc003bff, 0x200012b0, 0                      , 0,
16645        0x0                 },        /* P.MT_VPE~*(2) */
16646     { reserved_block      , 0                   , 0   , 32,
16647        0xfc003bff, 0x20001ab0, 0                      , 0,
16648        0x0                 },        /* P.MT_VPE~*(3) */
16649     { reserved_block      , 0                   , 0   , 32,
16650        0xfc003bff, 0x200022b0, 0                      , 0,
16651        0x0                 },        /* P.MT_VPE~*(4) */
16652     { reserved_block      , 0                   , 0   , 32,
16653        0xfc003bff, 0x20002ab0, 0                      , 0,
16654        0x0                 },        /* P.MT_VPE~*(5) */
16655     { reserved_block      , 0                   , 0   , 32,
16656        0xfc003bff, 0x200032b0, 0                      , 0,
16657        0x0                 },        /* P.MT_VPE~*(6) */
16658     { reserved_block      , 0                   , 0   , 32,
16659        0xfc003bff, 0x20003ab0, 0                      , 0,
16660        0x0                 },        /* P.MT_VPE~*(7) */
16661 };
16662
16663
16664 NMD::Pool NMD::P_DVP[2] = {
16665     { instruction         , 0                   , 0   , 32,
16666        0xfc00ffff, 0x20000390, &NMD::DVP              , 0,
16667        0x0                 },        /* DVP */
16668     { instruction         , 0                   , 0   , 32,
16669        0xfc00ffff, 0x20000790, &NMD::EVP              , 0,
16670        0x0                 },        /* EVP */
16671 };
16672
16673
16674 NMD::Pool NMD::P_SLTU[2] = {
16675     { pool                , P_DVP               , 2   , 32,
16676        0xfc00fbff, 0x20000390, 0                      , 0,
16677        0x0                 },        /* P.DVP */
16678     { instruction         , 0                   , 0   , 32,
16679        0xfc0003ff, 0x20000390, &NMD::SLTU             , &NMD::SLTU_cond        ,
16680        0x0                 },        /* SLTU */
16681 };
16682
16683
16684 NMD::Pool NMD::_POOL32A0[128] = {
16685     { pool                , P_TRAP              , 2   , 32,
16686        0xfc0003ff, 0x20000000, 0                      , 0,
16687        0x0                 },        /* P.TRAP */
16688     { instruction         , 0                   , 0   , 32,
16689        0xfc0003ff, 0x20000008, &NMD::SEB              , 0,
16690        XMMS_               },        /* SEB */
16691     { instruction         , 0                   , 0   , 32,
16692        0xfc0003ff, 0x20000010, &NMD::SLLV             , 0,
16693        0x0                 },        /* SLLV */
16694     { instruction         , 0                   , 0   , 32,
16695        0xfc0003ff, 0x20000018, &NMD::MUL_32_          , 0,
16696        0x0                 },        /* MUL[32] */
16697     { reserved_block      , 0                   , 0   , 32,
16698        0xfc0003ff, 0x20000020, 0                      , 0,
16699        0x0                 },        /* _POOL32A0~*(4) */
16700     { reserved_block      , 0                   , 0   , 32,
16701        0xfc0003ff, 0x20000028, 0                      , 0,
16702        0x0                 },        /* _POOL32A0~*(5) */
16703     { instruction         , 0                   , 0   , 32,
16704        0xfc0003ff, 0x20000030, &NMD::MFC0             , 0,
16705        0x0                 },        /* MFC0 */
16706     { instruction         , 0                   , 0   , 32,
16707        0xfc0003ff, 0x20000038, &NMD::MFHC0            , 0,
16708        CP0_ | MVH_         },        /* MFHC0 */
16709     { reserved_block      , 0                   , 0   , 32,
16710        0xfc0003ff, 0x20000040, 0                      , 0,
16711        0x0                 },        /* _POOL32A0~*(8) */
16712     { instruction         , 0                   , 0   , 32,
16713        0xfc0003ff, 0x20000048, &NMD::SEH              , 0,
16714        0x0                 },        /* SEH */
16715     { instruction         , 0                   , 0   , 32,
16716        0xfc0003ff, 0x20000050, &NMD::SRLV             , 0,
16717        0x0                 },        /* SRLV */
16718     { instruction         , 0                   , 0   , 32,
16719        0xfc0003ff, 0x20000058, &NMD::MUH              , 0,
16720        0x0                 },        /* MUH */
16721     { reserved_block      , 0                   , 0   , 32,
16722        0xfc0003ff, 0x20000060, 0                      , 0,
16723        0x0                 },        /* _POOL32A0~*(12) */
16724     { reserved_block      , 0                   , 0   , 32,
16725        0xfc0003ff, 0x20000068, 0                      , 0,
16726        0x0                 },        /* _POOL32A0~*(13) */
16727     { instruction         , 0                   , 0   , 32,
16728        0xfc0003ff, 0x20000070, &NMD::MTC0             , 0,
16729        CP0_                },        /* MTC0 */
16730     { instruction         , 0                   , 0   , 32,
16731        0xfc0003ff, 0x20000078, &NMD::MTHC0            , 0,
16732        CP0_ | MVH_         },        /* MTHC0 */
16733     { reserved_block      , 0                   , 0   , 32,
16734        0xfc0003ff, 0x20000080, 0                      , 0,
16735        0x0                 },        /* _POOL32A0~*(16) */
16736     { reserved_block      , 0                   , 0   , 32,
16737        0xfc0003ff, 0x20000088, 0                      , 0,
16738        0x0                 },        /* _POOL32A0~*(17) */
16739     { instruction         , 0                   , 0   , 32,
16740        0xfc0003ff, 0x20000090, &NMD::SRAV             , 0,
16741        0x0                 },        /* SRAV */
16742     { instruction         , 0                   , 0   , 32,
16743        0xfc0003ff, 0x20000098, &NMD::MULU             , 0,
16744        0x0                 },        /* MULU */
16745     { reserved_block      , 0                   , 0   , 32,
16746        0xfc0003ff, 0x200000a0, 0                      , 0,
16747        0x0                 },        /* _POOL32A0~*(20) */
16748     { reserved_block      , 0                   , 0   , 32,
16749        0xfc0003ff, 0x200000a8, 0                      , 0,
16750        0x0                 },        /* _POOL32A0~*(21) */
16751     { instruction         , 0                   , 0   , 32,
16752        0xfc0003ff, 0x200000b0, &NMD::MFGC0            , 0,
16753        CP0_ | VZ_          },        /* MFGC0 */
16754     { instruction         , 0                   , 0   , 32,
16755        0xfc0003ff, 0x200000b8, &NMD::MFHGC0           , 0,
16756        CP0_ | VZ_ | MVH_   },        /* MFHGC0 */
16757     { reserved_block      , 0                   , 0   , 32,
16758        0xfc0003ff, 0x200000c0, 0                      , 0,
16759        0x0                 },        /* _POOL32A0~*(24) */
16760     { reserved_block      , 0                   , 0   , 32,
16761        0xfc0003ff, 0x200000c8, 0                      , 0,
16762        0x0                 },        /* _POOL32A0~*(25) */
16763     { instruction         , 0                   , 0   , 32,
16764        0xfc0003ff, 0x200000d0, &NMD::ROTRV            , 0,
16765        0x0                 },        /* ROTRV */
16766     { instruction         , 0                   , 0   , 32,
16767        0xfc0003ff, 0x200000d8, &NMD::MUHU             , 0,
16768        0x0                 },        /* MUHU */
16769     { reserved_block      , 0                   , 0   , 32,
16770        0xfc0003ff, 0x200000e0, 0                      , 0,
16771        0x0                 },        /* _POOL32A0~*(28) */
16772     { reserved_block      , 0                   , 0   , 32,
16773        0xfc0003ff, 0x200000e8, 0                      , 0,
16774        0x0                 },        /* _POOL32A0~*(29) */
16775     { instruction         , 0                   , 0   , 32,
16776        0xfc0003ff, 0x200000f0, &NMD::MTGC0            , 0,
16777        CP0_ | VZ_          },        /* MTGC0 */
16778     { instruction         , 0                   , 0   , 32,
16779        0xfc0003ff, 0x200000f8, &NMD::MTHGC0           , 0,
16780        CP0_ | VZ_ | MVH_   },        /* MTHGC0 */
16781     { reserved_block      , 0                   , 0   , 32,
16782        0xfc0003ff, 0x20000100, 0                      , 0,
16783        0x0                 },        /* _POOL32A0~*(32) */
16784     { reserved_block      , 0                   , 0   , 32,
16785        0xfc0003ff, 0x20000108, 0                      , 0,
16786        0x0                 },        /* _POOL32A0~*(33) */
16787     { instruction         , 0                   , 0   , 32,
16788        0xfc0003ff, 0x20000110, &NMD::ADD              , 0,
16789        XMMS_               },        /* ADD */
16790     { instruction         , 0                   , 0   , 32,
16791        0xfc0003ff, 0x20000118, &NMD::DIV              , 0,
16792        0x0                 },        /* DIV */
16793     { reserved_block      , 0                   , 0   , 32,
16794        0xfc0003ff, 0x20000120, 0                      , 0,
16795        0x0                 },        /* _POOL32A0~*(36) */
16796     { reserved_block      , 0                   , 0   , 32,
16797        0xfc0003ff, 0x20000128, 0                      , 0,
16798        0x0                 },        /* _POOL32A0~*(37) */
16799     { instruction         , 0                   , 0   , 32,
16800        0xfc0003ff, 0x20000130, &NMD::DMFC0            , 0,
16801        CP0_ | MIPS64_      },        /* DMFC0 */
16802     { reserved_block      , 0                   , 0   , 32,
16803        0xfc0003ff, 0x20000138, 0                      , 0,
16804        0x0                 },        /* _POOL32A0~*(39) */
16805     { reserved_block      , 0                   , 0   , 32,
16806        0xfc0003ff, 0x20000140, 0                      , 0,
16807        0x0                 },        /* _POOL32A0~*(40) */
16808     { reserved_block      , 0                   , 0   , 32,
16809        0xfc0003ff, 0x20000148, 0                      , 0,
16810        0x0                 },        /* _POOL32A0~*(41) */
16811     { instruction         , 0                   , 0   , 32,
16812        0xfc0003ff, 0x20000150, &NMD::ADDU_32_         , 0,
16813        0x0                 },        /* ADDU[32] */
16814     { instruction         , 0                   , 0   , 32,
16815        0xfc0003ff, 0x20000158, &NMD::MOD              , 0,
16816        0x0                 },        /* MOD */
16817     { reserved_block      , 0                   , 0   , 32,
16818        0xfc0003ff, 0x20000160, 0                      , 0,
16819        0x0                 },        /* _POOL32A0~*(44) */
16820     { reserved_block      , 0                   , 0   , 32,
16821        0xfc0003ff, 0x20000168, 0                      , 0,
16822        0x0                 },        /* _POOL32A0~*(45) */
16823     { instruction         , 0                   , 0   , 32,
16824        0xfc0003ff, 0x20000170, &NMD::DMTC0            , 0,
16825        CP0_ | MIPS64_      },        /* DMTC0 */
16826     { reserved_block      , 0                   , 0   , 32,
16827        0xfc0003ff, 0x20000178, 0                      , 0,
16828        0x0                 },        /* _POOL32A0~*(47) */
16829     { reserved_block      , 0                   , 0   , 32,
16830        0xfc0003ff, 0x20000180, 0                      , 0,
16831        0x0                 },        /* _POOL32A0~*(48) */
16832     { reserved_block      , 0                   , 0   , 32,
16833        0xfc0003ff, 0x20000188, 0                      , 0,
16834        0x0                 },        /* _POOL32A0~*(49) */
16835     { instruction         , 0                   , 0   , 32,
16836        0xfc0003ff, 0x20000190, &NMD::SUB              , 0,
16837        XMMS_               },        /* SUB */
16838     { instruction         , 0                   , 0   , 32,
16839        0xfc0003ff, 0x20000198, &NMD::DIVU             , 0,
16840        0x0                 },        /* DIVU */
16841     { reserved_block      , 0                   , 0   , 32,
16842        0xfc0003ff, 0x200001a0, 0                      , 0,
16843        0x0                 },        /* _POOL32A0~*(52) */
16844     { reserved_block      , 0                   , 0   , 32,
16845        0xfc0003ff, 0x200001a8, 0                      , 0,
16846        0x0                 },        /* _POOL32A0~*(53) */
16847     { instruction         , 0                   , 0   , 32,
16848        0xfc0003ff, 0x200001b0, &NMD::DMFGC0           , 0,
16849        CP0_ | MIPS64_ | VZ_},        /* DMFGC0 */
16850     { reserved_block      , 0                   , 0   , 32,
16851        0xfc0003ff, 0x200001b8, 0                      , 0,
16852        0x0                 },        /* _POOL32A0~*(55) */
16853     { instruction         , 0                   , 0   , 32,
16854        0xfc0003ff, 0x200001c0, &NMD::RDHWR            , 0,
16855        XMMS_               },        /* RDHWR */
16856     { reserved_block      , 0                   , 0   , 32,
16857        0xfc0003ff, 0x200001c8, 0                      , 0,
16858        0x0                 },        /* _POOL32A0~*(57) */
16859     { instruction         , 0                   , 0   , 32,
16860        0xfc0003ff, 0x200001d0, &NMD::SUBU_32_         , 0,
16861        0x0                 },        /* SUBU[32] */
16862     { instruction         , 0                   , 0   , 32,
16863        0xfc0003ff, 0x200001d8, &NMD::MODU             , 0,
16864        0x0                 },        /* MODU */
16865     { reserved_block      , 0                   , 0   , 32,
16866        0xfc0003ff, 0x200001e0, 0                      , 0,
16867        0x0                 },        /* _POOL32A0~*(60) */
16868     { reserved_block      , 0                   , 0   , 32,
16869        0xfc0003ff, 0x200001e8, 0                      , 0,
16870        0x0                 },        /* _POOL32A0~*(61) */
16871     { instruction         , 0                   , 0   , 32,
16872        0xfc0003ff, 0x200001f0, &NMD::DMTGC0           , 0,
16873        CP0_ | MIPS64_ | VZ_},        /* DMTGC0 */
16874     { reserved_block      , 0                   , 0   , 32,
16875        0xfc0003ff, 0x200001f8, 0                      , 0,
16876        0x0                 },        /* _POOL32A0~*(63) */
16877     { reserved_block      , 0                   , 0   , 32,
16878        0xfc0003ff, 0x20000200, 0                      , 0,
16879        0x0                 },        /* _POOL32A0~*(64) */
16880     { reserved_block      , 0                   , 0   , 32,
16881        0xfc0003ff, 0x20000208, 0                      , 0,
16882        0x0                 },        /* _POOL32A0~*(65) */
16883     { pool                , P_CMOVE             , 2   , 32,
16884        0xfc0003ff, 0x20000210, 0                      , 0,
16885        0x0                 },        /* P.CMOVE */
16886     { reserved_block      , 0                   , 0   , 32,
16887        0xfc0003ff, 0x20000218, 0                      , 0,
16888        0x0                 },        /* _POOL32A0~*(67) */
16889     { reserved_block      , 0                   , 0   , 32,
16890        0xfc0003ff, 0x20000220, 0                      , 0,
16891        0x0                 },        /* _POOL32A0~*(68) */
16892     { instruction         , 0                   , 0   , 32,
16893        0xfc0003ff, 0x20000228, &NMD::FORK             , 0,
16894        MT_                 },        /* FORK */
16895     { instruction         , 0                   , 0   , 32,
16896        0xfc0003ff, 0x20000230, &NMD::MFTR             , 0,
16897        MT_                 },        /* MFTR */
16898     { instruction         , 0                   , 0   , 32,
16899        0xfc0003ff, 0x20000238, &NMD::MFHTR            , 0,
16900        MT_                 },        /* MFHTR */
16901     { reserved_block      , 0                   , 0   , 32,
16902        0xfc0003ff, 0x20000240, 0                      , 0,
16903        0x0                 },        /* _POOL32A0~*(72) */
16904     { reserved_block      , 0                   , 0   , 32,
16905        0xfc0003ff, 0x20000248, 0                      , 0,
16906        0x0                 },        /* _POOL32A0~*(73) */
16907     { instruction         , 0                   , 0   , 32,
16908        0xfc0003ff, 0x20000250, &NMD::AND_32_          , 0,
16909        0x0                 },        /* AND[32] */
16910     { reserved_block      , 0                   , 0   , 32,
16911        0xfc0003ff, 0x20000258, 0                      , 0,
16912        0x0                 },        /* _POOL32A0~*(75) */
16913     { reserved_block      , 0                   , 0   , 32,
16914        0xfc0003ff, 0x20000260, 0                      , 0,
16915        0x0                 },        /* _POOL32A0~*(76) */
16916     { instruction         , 0                   , 0   , 32,
16917        0xfc0003ff, 0x20000268, &NMD::YIELD            , 0,
16918        MT_                 },        /* YIELD */
16919     { instruction         , 0                   , 0   , 32,
16920        0xfc0003ff, 0x20000270, &NMD::MTTR             , 0,
16921        MT_                 },        /* MTTR */
16922     { instruction         , 0                   , 0   , 32,
16923        0xfc0003ff, 0x20000278, &NMD::MTHTR            , 0,
16924        MT_                 },        /* MTHTR */
16925     { reserved_block      , 0                   , 0   , 32,
16926        0xfc0003ff, 0x20000280, 0                      , 0,
16927        0x0                 },        /* _POOL32A0~*(80) */
16928     { reserved_block      , 0                   , 0   , 32,
16929        0xfc0003ff, 0x20000288, 0                      , 0,
16930        0x0                 },        /* _POOL32A0~*(81) */
16931     { instruction         , 0                   , 0   , 32,
16932        0xfc0003ff, 0x20000290, &NMD::OR_32_           , 0,
16933        0x0                 },        /* OR[32] */
16934     { reserved_block      , 0                   , 0   , 32,
16935        0xfc0003ff, 0x20000298, 0                      , 0,
16936        0x0                 },        /* _POOL32A0~*(83) */
16937     { reserved_block      , 0                   , 0   , 32,
16938        0xfc0003ff, 0x200002a0, 0                      , 0,
16939        0x0                 },        /* _POOL32A0~*(84) */
16940     { reserved_block      , 0                   , 0   , 32,
16941        0xfc0003ff, 0x200002a8, 0                      , 0,
16942        0x0                 },        /* _POOL32A0~*(85) */
16943     { pool                , P_MT_VPE            , 8   , 32,
16944        0xfc0003ff, 0x200002b0, 0                      , 0,
16945        0x0                 },        /* P.MT_VPE */
16946     { reserved_block      , 0                   , 0   , 32,
16947        0xfc0003ff, 0x200002b8, 0                      , 0,
16948        0x0                 },        /* _POOL32A0~*(87) */
16949     { reserved_block      , 0                   , 0   , 32,
16950        0xfc0003ff, 0x200002c0, 0                      , 0,
16951        0x0                 },        /* _POOL32A0~*(88) */
16952     { reserved_block      , 0                   , 0   , 32,
16953        0xfc0003ff, 0x200002c8, 0                      , 0,
16954        0x0                 },        /* _POOL32A0~*(89) */
16955     { instruction         , 0                   , 0   , 32,
16956        0xfc0003ff, 0x200002d0, &NMD::NOR              , 0,
16957        0x0                 },        /* NOR */
16958     { reserved_block      , 0                   , 0   , 32,
16959        0xfc0003ff, 0x200002d8, 0                      , 0,
16960        0x0                 },        /* _POOL32A0~*(91) */
16961     { reserved_block      , 0                   , 0   , 32,
16962        0xfc0003ff, 0x200002e0, 0                      , 0,
16963        0x0                 },        /* _POOL32A0~*(92) */
16964     { reserved_block      , 0                   , 0   , 32,
16965        0xfc0003ff, 0x200002e8, 0                      , 0,
16966        0x0                 },        /* _POOL32A0~*(93) */
16967     { reserved_block      , 0                   , 0   , 32,
16968        0xfc0003ff, 0x200002f0, 0                      , 0,
16969        0x0                 },        /* _POOL32A0~*(94) */
16970     { reserved_block      , 0                   , 0   , 32,
16971        0xfc0003ff, 0x200002f8, 0                      , 0,
16972        0x0                 },        /* _POOL32A0~*(95) */
16973     { reserved_block      , 0                   , 0   , 32,
16974        0xfc0003ff, 0x20000300, 0                      , 0,
16975        0x0                 },        /* _POOL32A0~*(96) */
16976     { reserved_block      , 0                   , 0   , 32,
16977        0xfc0003ff, 0x20000308, 0                      , 0,
16978        0x0                 },        /* _POOL32A0~*(97) */
16979     { instruction         , 0                   , 0   , 32,
16980        0xfc0003ff, 0x20000310, &NMD::XOR_32_          , 0,
16981        0x0                 },        /* XOR[32] */
16982     { reserved_block      , 0                   , 0   , 32,
16983        0xfc0003ff, 0x20000318, 0                      , 0,
16984        0x0                 },        /* _POOL32A0~*(99) */
16985     { reserved_block      , 0                   , 0   , 32,
16986        0xfc0003ff, 0x20000320, 0                      , 0,
16987        0x0                 },        /* _POOL32A0~*(100) */
16988     { reserved_block      , 0                   , 0   , 32,
16989        0xfc0003ff, 0x20000328, 0                      , 0,
16990        0x0                 },        /* _POOL32A0~*(101) */
16991     { reserved_block      , 0                   , 0   , 32,
16992        0xfc0003ff, 0x20000330, 0                      , 0,
16993        0x0                 },        /* _POOL32A0~*(102) */
16994     { reserved_block      , 0                   , 0   , 32,
16995        0xfc0003ff, 0x20000338, 0                      , 0,
16996        0x0                 },        /* _POOL32A0~*(103) */
16997     { reserved_block      , 0                   , 0   , 32,
16998        0xfc0003ff, 0x20000340, 0                      , 0,
16999        0x0                 },        /* _POOL32A0~*(104) */
17000     { reserved_block      , 0                   , 0   , 32,
17001        0xfc0003ff, 0x20000348, 0                      , 0,
17002        0x0                 },        /* _POOL32A0~*(105) */
17003     { instruction         , 0                   , 0   , 32,
17004        0xfc0003ff, 0x20000350, &NMD::SLT              , 0,
17005        0x0                 },        /* SLT */
17006     { reserved_block      , 0                   , 0   , 32,
17007        0xfc0003ff, 0x20000358, 0                      , 0,
17008        0x0                 },        /* _POOL32A0~*(107) */
17009     { reserved_block      , 0                   , 0   , 32,
17010        0xfc0003ff, 0x20000360, 0                      , 0,
17011        0x0                 },        /* _POOL32A0~*(108) */
17012     { reserved_block      , 0                   , 0   , 32,
17013        0xfc0003ff, 0x20000368, 0                      , 0,
17014        0x0                 },        /* _POOL32A0~*(109) */
17015     { reserved_block      , 0                   , 0   , 32,
17016        0xfc0003ff, 0x20000370, 0                      , 0,
17017        0x0                 },        /* _POOL32A0~*(110) */
17018     { reserved_block      , 0                   , 0   , 32,
17019        0xfc0003ff, 0x20000378, 0                      , 0,
17020        0x0                 },        /* _POOL32A0~*(111) */
17021     { reserved_block      , 0                   , 0   , 32,
17022        0xfc0003ff, 0x20000380, 0                      , 0,
17023        0x0                 },        /* _POOL32A0~*(112) */
17024     { reserved_block      , 0                   , 0   , 32,
17025        0xfc0003ff, 0x20000388, 0                      , 0,
17026        0x0                 },        /* _POOL32A0~*(113) */
17027     { pool                , P_SLTU              , 2   , 32,
17028        0xfc0003ff, 0x20000390, 0                      , 0,
17029        0x0                 },        /* P.SLTU */
17030     { reserved_block      , 0                   , 0   , 32,
17031        0xfc0003ff, 0x20000398, 0                      , 0,
17032        0x0                 },        /* _POOL32A0~*(115) */
17033     { reserved_block      , 0                   , 0   , 32,
17034        0xfc0003ff, 0x200003a0, 0                      , 0,
17035        0x0                 },        /* _POOL32A0~*(116) */
17036     { reserved_block      , 0                   , 0   , 32,
17037        0xfc0003ff, 0x200003a8, 0                      , 0,
17038        0x0                 },        /* _POOL32A0~*(117) */
17039     { reserved_block      , 0                   , 0   , 32,
17040        0xfc0003ff, 0x200003b0, 0                      , 0,
17041        0x0                 },        /* _POOL32A0~*(118) */
17042     { reserved_block      , 0                   , 0   , 32,
17043        0xfc0003ff, 0x200003b8, 0                      , 0,
17044        0x0                 },        /* _POOL32A0~*(119) */
17045     { reserved_block      , 0                   , 0   , 32,
17046        0xfc0003ff, 0x200003c0, 0                      , 0,
17047        0x0                 },        /* _POOL32A0~*(120) */
17048     { reserved_block      , 0                   , 0   , 32,
17049        0xfc0003ff, 0x200003c8, 0                      , 0,
17050        0x0                 },        /* _POOL32A0~*(121) */
17051     { instruction         , 0                   , 0   , 32,
17052        0xfc0003ff, 0x200003d0, &NMD::SOV              , 0,
17053        0x0                 },        /* SOV */
17054     { reserved_block      , 0                   , 0   , 32,
17055        0xfc0003ff, 0x200003d8, 0                      , 0,
17056        0x0                 },        /* _POOL32A0~*(123) */
17057     { reserved_block      , 0                   , 0   , 32,
17058        0xfc0003ff, 0x200003e0, 0                      , 0,
17059        0x0                 },        /* _POOL32A0~*(124) */
17060     { reserved_block      , 0                   , 0   , 32,
17061        0xfc0003ff, 0x200003e8, 0                      , 0,
17062        0x0                 },        /* _POOL32A0~*(125) */
17063     { reserved_block      , 0                   , 0   , 32,
17064        0xfc0003ff, 0x200003f0, 0                      , 0,
17065        0x0                 },        /* _POOL32A0~*(126) */
17066     { reserved_block      , 0                   , 0   , 32,
17067        0xfc0003ff, 0x200003f8, 0                      , 0,
17068        0x0                 },        /* _POOL32A0~*(127) */
17069 };
17070
17071
17072 NMD::Pool NMD::ADDQ__S__PH[2] = {
17073     { instruction         , 0                   , 0   , 32,
17074        0xfc0007ff, 0x2000000d, &NMD::ADDQ_PH          , 0,
17075        DSP_                },        /* ADDQ.PH */
17076     { instruction         , 0                   , 0   , 32,
17077        0xfc0007ff, 0x2000040d, &NMD::ADDQ_S_PH        , 0,
17078        DSP_                },        /* ADDQ_S.PH */
17079 };
17080
17081
17082 NMD::Pool NMD::MUL__S__PH[2] = {
17083     { instruction         , 0                   , 0   , 32,
17084        0xfc0007ff, 0x2000002d, &NMD::MUL_PH           , 0,
17085        DSP_                },        /* MUL.PH */
17086     { instruction         , 0                   , 0   , 32,
17087        0xfc0007ff, 0x2000042d, &NMD::MUL_S_PH         , 0,
17088        DSP_                },        /* MUL_S.PH */
17089 };
17090
17091
17092 NMD::Pool NMD::ADDQH__R__PH[2] = {
17093     { instruction         , 0                   , 0   , 32,
17094        0xfc0007ff, 0x2000004d, &NMD::ADDQH_PH         , 0,
17095        DSP_                },        /* ADDQH.PH */
17096     { instruction         , 0                   , 0   , 32,
17097        0xfc0007ff, 0x2000044d, &NMD::ADDQH_R_PH       , 0,
17098        DSP_                },        /* ADDQH_R.PH */
17099 };
17100
17101
17102 NMD::Pool NMD::ADDQH__R__W[2] = {
17103     { instruction         , 0                   , 0   , 32,
17104        0xfc0007ff, 0x2000008d, &NMD::ADDQH_W          , 0,
17105        DSP_                },        /* ADDQH.W */
17106     { instruction         , 0                   , 0   , 32,
17107        0xfc0007ff, 0x2000048d, &NMD::ADDQH_R_W        , 0,
17108        DSP_                },        /* ADDQH_R.W */
17109 };
17110
17111
17112 NMD::Pool NMD::ADDU__S__QB[2] = {
17113     { instruction         , 0                   , 0   , 32,
17114        0xfc0007ff, 0x200000cd, &NMD::ADDU_QB          , 0,
17115        DSP_                },        /* ADDU.QB */
17116     { instruction         , 0                   , 0   , 32,
17117        0xfc0007ff, 0x200004cd, &NMD::ADDU_S_QB        , 0,
17118        DSP_                },        /* ADDU_S.QB */
17119 };
17120
17121
17122 NMD::Pool NMD::ADDU__S__PH[2] = {
17123     { instruction         , 0                   , 0   , 32,
17124        0xfc0007ff, 0x2000010d, &NMD::ADDU_PH          , 0,
17125        DSP_                },        /* ADDU.PH */
17126     { instruction         , 0                   , 0   , 32,
17127        0xfc0007ff, 0x2000050d, &NMD::ADDU_S_PH        , 0,
17128        DSP_                },        /* ADDU_S.PH */
17129 };
17130
17131
17132 NMD::Pool NMD::ADDUH__R__QB[2] = {
17133     { instruction         , 0                   , 0   , 32,
17134        0xfc0007ff, 0x2000014d, &NMD::ADDUH_QB         , 0,
17135        DSP_                },        /* ADDUH.QB */
17136     { instruction         , 0                   , 0   , 32,
17137        0xfc0007ff, 0x2000054d, &NMD::ADDUH_R_QB       , 0,
17138        DSP_                },        /* ADDUH_R.QB */
17139 };
17140
17141
17142 NMD::Pool NMD::SHRAV__R__PH[2] = {
17143     { instruction         , 0                   , 0   , 32,
17144        0xfc0007ff, 0x2000018d, &NMD::SHRAV_PH         , 0,
17145        DSP_                },        /* SHRAV.PH */
17146     { instruction         , 0                   , 0   , 32,
17147        0xfc0007ff, 0x2000058d, &NMD::SHRAV_R_PH       , 0,
17148        DSP_                },        /* SHRAV_R.PH */
17149 };
17150
17151
17152 NMD::Pool NMD::SHRAV__R__QB[2] = {
17153     { instruction         , 0                   , 0   , 32,
17154        0xfc0007ff, 0x200001cd, &NMD::SHRAV_QB         , 0,
17155        DSP_                },        /* SHRAV.QB */
17156     { instruction         , 0                   , 0   , 32,
17157        0xfc0007ff, 0x200005cd, &NMD::SHRAV_R_QB       , 0,
17158        DSP_                },        /* SHRAV_R.QB */
17159 };
17160
17161
17162 NMD::Pool NMD::SUBQ__S__PH[2] = {
17163     { instruction         , 0                   , 0   , 32,
17164        0xfc0007ff, 0x2000020d, &NMD::SUBQ_PH          , 0,
17165        DSP_                },        /* SUBQ.PH */
17166     { instruction         , 0                   , 0   , 32,
17167        0xfc0007ff, 0x2000060d, &NMD::SUBQ_S_PH        , 0,
17168        DSP_                },        /* SUBQ_S.PH */
17169 };
17170
17171
17172 NMD::Pool NMD::SUBQH__R__PH[2] = {
17173     { instruction         , 0                   , 0   , 32,
17174        0xfc0007ff, 0x2000024d, &NMD::SUBQH_PH         , 0,
17175        DSP_                },        /* SUBQH.PH */
17176     { instruction         , 0                   , 0   , 32,
17177        0xfc0007ff, 0x2000064d, &NMD::SUBQH_R_PH       , 0,
17178        DSP_                },        /* SUBQH_R.PH */
17179 };
17180
17181
17182 NMD::Pool NMD::SUBQH__R__W[2] = {
17183     { instruction         , 0                   , 0   , 32,
17184        0xfc0007ff, 0x2000028d, &NMD::SUBQH_W          , 0,
17185        DSP_                },        /* SUBQH.W */
17186     { instruction         , 0                   , 0   , 32,
17187        0xfc0007ff, 0x2000068d, &NMD::SUBQH_R_W        , 0,
17188        DSP_                },        /* SUBQH_R.W */
17189 };
17190
17191
17192 NMD::Pool NMD::SUBU__S__QB[2] = {
17193     { instruction         , 0                   , 0   , 32,
17194        0xfc0007ff, 0x200002cd, &NMD::SUBU_QB          , 0,
17195        DSP_                },        /* SUBU.QB */
17196     { instruction         , 0                   , 0   , 32,
17197        0xfc0007ff, 0x200006cd, &NMD::SUBU_S_QB        , 0,
17198        DSP_                },        /* SUBU_S.QB */
17199 };
17200
17201
17202 NMD::Pool NMD::SUBU__S__PH[2] = {
17203     { instruction         , 0                   , 0   , 32,
17204        0xfc0007ff, 0x2000030d, &NMD::SUBU_PH          , 0,
17205        DSP_                },        /* SUBU.PH */
17206     { instruction         , 0                   , 0   , 32,
17207        0xfc0007ff, 0x2000070d, &NMD::SUBU_S_PH        , 0,
17208        DSP_                },        /* SUBU_S.PH */
17209 };
17210
17211
17212 NMD::Pool NMD::SHRA__R__PH[2] = {
17213     { instruction         , 0                   , 0   , 32,
17214        0xfc0007ff, 0x20000335, &NMD::SHRA_PH          , 0,
17215        DSP_                },        /* SHRA.PH */
17216     { instruction         , 0                   , 0   , 32,
17217        0xfc0007ff, 0x20000735, &NMD::SHRA_R_PH        , 0,
17218        DSP_                },        /* SHRA_R.PH */
17219 };
17220
17221
17222 NMD::Pool NMD::SUBUH__R__QB[2] = {
17223     { instruction         , 0                   , 0   , 32,
17224        0xfc0007ff, 0x2000034d, &NMD::SUBUH_QB         , 0,
17225        DSP_                },        /* SUBUH.QB */
17226     { instruction         , 0                   , 0   , 32,
17227        0xfc0007ff, 0x2000074d, &NMD::SUBUH_R_QB       , 0,
17228        DSP_                },        /* SUBUH_R.QB */
17229 };
17230
17231
17232 NMD::Pool NMD::SHLLV__S__PH[2] = {
17233     { instruction         , 0                   , 0   , 32,
17234        0xfc0007ff, 0x2000038d, &NMD::SHLLV_PH         , 0,
17235        DSP_                },        /* SHLLV.PH */
17236     { instruction         , 0                   , 0   , 32,
17237        0xfc0007ff, 0x2000078d, &NMD::SHLLV_S_PH       , 0,
17238        DSP_                },        /* SHLLV_S.PH */
17239 };
17240
17241
17242 NMD::Pool NMD::SHLL__S__PH[4] = {
17243     { instruction         , 0                   , 0   , 32,
17244        0xfc000fff, 0x200003b5, &NMD::SHLL_PH          , 0,
17245        DSP_                },        /* SHLL.PH */
17246     { reserved_block      , 0                   , 0   , 32,
17247        0xfc000fff, 0x200007b5, 0                      , 0,
17248        0x0                 },        /* SHLL[_S].PH~*(1) */
17249     { instruction         , 0                   , 0   , 32,
17250        0xfc000fff, 0x20000bb5, &NMD::SHLL_S_PH        , 0,
17251        DSP_                },        /* SHLL_S.PH */
17252     { reserved_block      , 0                   , 0   , 32,
17253        0xfc000fff, 0x20000fb5, 0                      , 0,
17254        0x0                 },        /* SHLL[_S].PH~*(3) */
17255 };
17256
17257
17258 NMD::Pool NMD::PRECR_SRA__R__PH_W[2] = {
17259     { instruction         , 0                   , 0   , 32,
17260        0xfc0007ff, 0x200003cd, &NMD::PRECR_SRA_PH_W   , 0,
17261        DSP_                },        /* PRECR_SRA.PH.W */
17262     { instruction         , 0                   , 0   , 32,
17263        0xfc0007ff, 0x200007cd, &NMD::PRECR_SRA_R_PH_W , 0,
17264        DSP_                },        /* PRECR_SRA_R.PH.W */
17265 };
17266
17267
17268 NMD::Pool NMD::_POOL32A5[128] = {
17269     { instruction         , 0                   , 0   , 32,
17270        0xfc0003ff, 0x20000005, &NMD::CMP_EQ_PH        , 0,
17271        DSP_                },        /* CMP.EQ.PH */
17272     { pool                , ADDQ__S__PH         , 2   , 32,
17273        0xfc0003ff, 0x2000000d, 0                      , 0,
17274        0x0                 },        /* ADDQ[_S].PH */
17275     { reserved_block      , 0                   , 0   , 32,
17276        0xfc0003ff, 0x20000015, 0                      , 0,
17277        0x0                 },        /* _POOL32A5~*(2) */
17278     { instruction         , 0                   , 0   , 32,
17279        0xfc0003ff, 0x2000001d, &NMD::SHILO            , 0,
17280        DSP_                },        /* SHILO */
17281     { instruction         , 0                   , 0   , 32,
17282        0xfc0003ff, 0x20000025, &NMD::MULEQ_S_W_PHL    , 0,
17283        DSP_                },        /* MULEQ_S.W.PHL */
17284     { pool                , MUL__S__PH          , 2   , 32,
17285        0xfc0003ff, 0x2000002d, 0                      , 0,
17286        0x0                 },        /* MUL[_S].PH */
17287     { reserved_block      , 0                   , 0   , 32,
17288        0xfc0003ff, 0x20000035, 0                      , 0,
17289        0x0                 },        /* _POOL32A5~*(6) */
17290     { instruction         , 0                   , 0   , 32,
17291        0xfc0003ff, 0x2000003d, &NMD::REPL_PH          , 0,
17292        DSP_                },        /* REPL.PH */
17293     { instruction         , 0                   , 0   , 32,
17294        0xfc0003ff, 0x20000045, &NMD::CMP_LT_PH        , 0,
17295        DSP_                },        /* CMP.LT.PH */
17296     { pool                , ADDQH__R__PH        , 2   , 32,
17297        0xfc0003ff, 0x2000004d, 0                      , 0,
17298        0x0                 },        /* ADDQH[_R].PH */
17299     { reserved_block      , 0                   , 0   , 32,
17300        0xfc0003ff, 0x20000055, 0                      , 0,
17301        0x0                 },        /* _POOL32A5~*(10) */
17302     { reserved_block      , 0                   , 0   , 32,
17303        0xfc0003ff, 0x2000005d, 0                      , 0,
17304        0x0                 },        /* _POOL32A5~*(11) */
17305     { instruction         , 0                   , 0   , 32,
17306        0xfc0003ff, 0x20000065, &NMD::MULEQ_S_W_PHR    , 0,
17307        DSP_                },        /* MULEQ_S.W.PHR */
17308     { instruction         , 0                   , 0   , 32,
17309        0xfc0003ff, 0x2000006d, &NMD::PRECR_QB_PH      , 0,
17310        DSP_                },        /* PRECR.QB.PH */
17311     { reserved_block      , 0                   , 0   , 32,
17312        0xfc0003ff, 0x20000075, 0                      , 0,
17313        0x0                 },        /* _POOL32A5~*(14) */
17314     { reserved_block      , 0                   , 0   , 32,
17315        0xfc0003ff, 0x2000007d, 0                      , 0,
17316        0x0                 },        /* _POOL32A5~*(15) */
17317     { instruction         , 0                   , 0   , 32,
17318        0xfc0003ff, 0x20000085, &NMD::CMP_LE_PH        , 0,
17319        DSP_                },        /* CMP.LE.PH */
17320     { pool                , ADDQH__R__W         , 2   , 32,
17321        0xfc0003ff, 0x2000008d, 0                      , 0,
17322        0x0                 },        /* ADDQH[_R].W */
17323     { instruction         , 0                   , 0   , 32,
17324        0xfc0003ff, 0x20000095, &NMD::MULEU_S_PH_QBL   , 0,
17325        DSP_                },        /* MULEU_S.PH.QBL */
17326     { reserved_block      , 0                   , 0   , 32,
17327        0xfc0003ff, 0x2000009d, 0                      , 0,
17328        0x0                 },        /* _POOL32A5~*(19) */
17329     { reserved_block      , 0                   , 0   , 32,
17330        0xfc0003ff, 0x200000a5, 0                      , 0,
17331        0x0                 },        /* _POOL32A5~*(20) */
17332     { instruction         , 0                   , 0   , 32,
17333        0xfc0003ff, 0x200000ad, &NMD::PRECRQ_QB_PH     , 0,
17334        DSP_                },        /* PRECRQ.QB.PH */
17335     { reserved_block      , 0                   , 0   , 32,
17336        0xfc0003ff, 0x200000b5, 0                      , 0,
17337        0x0                 },        /* _POOL32A5~*(22) */
17338     { reserved_block      , 0                   , 0   , 32,
17339        0xfc0003ff, 0x200000bd, 0                      , 0,
17340        0x0                 },        /* _POOL32A5~*(23) */
17341     { instruction         , 0                   , 0   , 32,
17342        0xfc0003ff, 0x200000c5, &NMD::CMPGU_EQ_QB      , 0,
17343        DSP_                },        /* CMPGU.EQ.QB */
17344     { pool                , ADDU__S__QB         , 2   , 32,
17345        0xfc0003ff, 0x200000cd, 0                      , 0,
17346        0x0                 },        /* ADDU[_S].QB */
17347     { instruction         , 0                   , 0   , 32,
17348        0xfc0003ff, 0x200000d5, &NMD::MULEU_S_PH_QBR   , 0,
17349        DSP_                },        /* MULEU_S.PH.QBR */
17350     { reserved_block      , 0                   , 0   , 32,
17351        0xfc0003ff, 0x200000dd, 0                      , 0,
17352        0x0                 },        /* _POOL32A5~*(27) */
17353     { reserved_block      , 0                   , 0   , 32,
17354        0xfc0003ff, 0x200000e5, 0                      , 0,
17355        0x0                 },        /* _POOL32A5~*(28) */
17356     { instruction         , 0                   , 0   , 32,
17357        0xfc0003ff, 0x200000ed, &NMD::PRECRQ_PH_W      , 0,
17358        DSP_                },        /* PRECRQ.PH.W */
17359     { reserved_block      , 0                   , 0   , 32,
17360        0xfc0003ff, 0x200000f5, 0                      , 0,
17361        0x0                 },        /* _POOL32A5~*(30) */
17362     { reserved_block      , 0                   , 0   , 32,
17363        0xfc0003ff, 0x200000fd, 0                      , 0,
17364        0x0                 },        /* _POOL32A5~*(31) */
17365     { instruction         , 0                   , 0   , 32,
17366        0xfc0003ff, 0x20000105, &NMD::CMPGU_LT_QB      , 0,
17367        DSP_                },        /* CMPGU.LT.QB */
17368     { pool                , ADDU__S__PH         , 2   , 32,
17369        0xfc0003ff, 0x2000010d, 0                      , 0,
17370        0x0                 },        /* ADDU[_S].PH */
17371     { instruction         , 0                   , 0   , 32,
17372        0xfc0003ff, 0x20000115, &NMD::MULQ_RS_PH       , 0,
17373        DSP_                },        /* MULQ_RS.PH */
17374     { reserved_block      , 0                   , 0   , 32,
17375        0xfc0003ff, 0x2000011d, 0                      , 0,
17376        0x0                 },        /* _POOL32A5~*(35) */
17377     { reserved_block      , 0                   , 0   , 32,
17378        0xfc0003ff, 0x20000125, 0                      , 0,
17379        0x0                 },        /* _POOL32A5~*(36) */
17380     { instruction         , 0                   , 0   , 32,
17381        0xfc0003ff, 0x2000012d, &NMD::PRECRQ_RS_PH_W   , 0,
17382        DSP_                },        /* PRECRQ_RS.PH.W */
17383     { reserved_block      , 0                   , 0   , 32,
17384        0xfc0003ff, 0x20000135, 0                      , 0,
17385        0x0                 },        /* _POOL32A5~*(38) */
17386     { reserved_block      , 0                   , 0   , 32,
17387        0xfc0003ff, 0x2000013d, 0                      , 0,
17388        0x0                 },        /* _POOL32A5~*(39) */
17389     { instruction         , 0                   , 0   , 32,
17390        0xfc0003ff, 0x20000145, &NMD::CMPGU_LE_QB      , 0,
17391        DSP_                },        /* CMPGU.LE.QB */
17392     { pool                , ADDUH__R__QB        , 2   , 32,
17393        0xfc0003ff, 0x2000014d, 0                      , 0,
17394        0x0                 },        /* ADDUH[_R].QB */
17395     { instruction         , 0                   , 0   , 32,
17396        0xfc0003ff, 0x20000155, &NMD::MULQ_S_PH        , 0,
17397        DSP_                },        /* MULQ_S.PH */
17398     { reserved_block      , 0                   , 0   , 32,
17399        0xfc0003ff, 0x2000015d, 0                      , 0,
17400        0x0                 },        /* _POOL32A5~*(43) */
17401     { reserved_block      , 0                   , 0   , 32,
17402        0xfc0003ff, 0x20000165, 0                      , 0,
17403        0x0                 },        /* _POOL32A5~*(44) */
17404     { instruction         , 0                   , 0   , 32,
17405        0xfc0003ff, 0x2000016d, &NMD::PRECRQU_S_QB_PH  , 0,
17406        DSP_                },        /* PRECRQU_S.QB.PH */
17407     { reserved_block      , 0                   , 0   , 32,
17408        0xfc0003ff, 0x20000175, 0                      , 0,
17409        0x0                 },        /* _POOL32A5~*(46) */
17410     { reserved_block      , 0                   , 0   , 32,
17411        0xfc0003ff, 0x2000017d, 0                      , 0,
17412        0x0                 },        /* _POOL32A5~*(47) */
17413     { instruction         , 0                   , 0   , 32,
17414        0xfc0003ff, 0x20000185, &NMD::CMPGDU_EQ_QB     , 0,
17415        DSP_                },        /* CMPGDU.EQ.QB */
17416     { pool                , SHRAV__R__PH        , 2   , 32,
17417        0xfc0003ff, 0x2000018d, 0                      , 0,
17418        0x0                 },        /* SHRAV[_R].PH */
17419     { instruction         , 0                   , 0   , 32,
17420        0xfc0003ff, 0x20000195, &NMD::MULQ_RS_W        , 0,
17421        DSP_                },        /* MULQ_RS.W */
17422     { reserved_block      , 0                   , 0   , 32,
17423        0xfc0003ff, 0x2000019d, 0                      , 0,
17424        0x0                 },        /* _POOL32A5~*(51) */
17425     { reserved_block      , 0                   , 0   , 32,
17426        0xfc0003ff, 0x200001a5, 0                      , 0,
17427        0x0                 },        /* _POOL32A5~*(52) */
17428     { instruction         , 0                   , 0   , 32,
17429        0xfc0003ff, 0x200001ad, &NMD::PACKRL_PH        , 0,
17430        DSP_                },        /* PACKRL.PH */
17431     { reserved_block      , 0                   , 0   , 32,
17432        0xfc0003ff, 0x200001b5, 0                      , 0,
17433        0x0                 },        /* _POOL32A5~*(54) */
17434     { reserved_block      , 0                   , 0   , 32,
17435        0xfc0003ff, 0x200001bd, 0                      , 0,
17436        0x0                 },        /* _POOL32A5~*(55) */
17437     { instruction         , 0                   , 0   , 32,
17438        0xfc0003ff, 0x200001c5, &NMD::CMPGDU_LT_QB     , 0,
17439        DSP_                },        /* CMPGDU.LT.QB */
17440     { pool                , SHRAV__R__QB        , 2   , 32,
17441        0xfc0003ff, 0x200001cd, 0                      , 0,
17442        0x0                 },        /* SHRAV[_R].QB */
17443     { instruction         , 0                   , 0   , 32,
17444        0xfc0003ff, 0x200001d5, &NMD::MULQ_S_W         , 0,
17445        DSP_                },        /* MULQ_S.W */
17446     { reserved_block      , 0                   , 0   , 32,
17447        0xfc0003ff, 0x200001dd, 0                      , 0,
17448        0x0                 },        /* _POOL32A5~*(59) */
17449     { reserved_block      , 0                   , 0   , 32,
17450        0xfc0003ff, 0x200001e5, 0                      , 0,
17451        0x0                 },        /* _POOL32A5~*(60) */
17452     { instruction         , 0                   , 0   , 32,
17453        0xfc0003ff, 0x200001ed, &NMD::PICK_QB          , 0,
17454        DSP_                },        /* PICK.QB */
17455     { reserved_block      , 0                   , 0   , 32,
17456        0xfc0003ff, 0x200001f5, 0                      , 0,
17457        0x0                 },        /* _POOL32A5~*(62) */
17458     { reserved_block      , 0                   , 0   , 32,
17459        0xfc0003ff, 0x200001fd, 0                      , 0,
17460        0x0                 },        /* _POOL32A5~*(63) */
17461     { instruction         , 0                   , 0   , 32,
17462        0xfc0003ff, 0x20000205, &NMD::CMPGDU_LE_QB     , 0,
17463        DSP_                },        /* CMPGDU.LE.QB */
17464     { pool                , SUBQ__S__PH         , 2   , 32,
17465        0xfc0003ff, 0x2000020d, 0                      , 0,
17466        0x0                 },        /* SUBQ[_S].PH */
17467     { instruction         , 0                   , 0   , 32,
17468        0xfc0003ff, 0x20000215, &NMD::APPEND           , 0,
17469        DSP_                },        /* APPEND */
17470     { reserved_block      , 0                   , 0   , 32,
17471        0xfc0003ff, 0x2000021d, 0                      , 0,
17472        0x0                 },        /* _POOL32A5~*(67) */
17473     { reserved_block      , 0                   , 0   , 32,
17474        0xfc0003ff, 0x20000225, 0                      , 0,
17475        0x0                 },        /* _POOL32A5~*(68) */
17476     { instruction         , 0                   , 0   , 32,
17477        0xfc0003ff, 0x2000022d, &NMD::PICK_PH          , 0,
17478        DSP_                },        /* PICK.PH */
17479     { reserved_block      , 0                   , 0   , 32,
17480        0xfc0003ff, 0x20000235, 0                      , 0,
17481        0x0                 },        /* _POOL32A5~*(70) */
17482     { reserved_block      , 0                   , 0   , 32,
17483        0xfc0003ff, 0x2000023d, 0                      , 0,
17484        0x0                 },        /* _POOL32A5~*(71) */
17485     { instruction         , 0                   , 0   , 32,
17486        0xfc0003ff, 0x20000245, &NMD::CMPU_EQ_QB       , 0,
17487        DSP_                },        /* CMPU.EQ.QB */
17488     { pool                , SUBQH__R__PH        , 2   , 32,
17489        0xfc0003ff, 0x2000024d, 0                      , 0,
17490        0x0                 },        /* SUBQH[_R].PH */
17491     { instruction         , 0                   , 0   , 32,
17492        0xfc0003ff, 0x20000255, &NMD::PREPEND          , 0,
17493        DSP_                },        /* PREPEND */
17494     { reserved_block      , 0                   , 0   , 32,
17495        0xfc0003ff, 0x2000025d, 0                      , 0,
17496        0x0                 },        /* _POOL32A5~*(75) */
17497     { reserved_block      , 0                   , 0   , 32,
17498        0xfc0003ff, 0x20000265, 0                      , 0,
17499        0x0                 },        /* _POOL32A5~*(76) */
17500     { reserved_block      , 0                   , 0   , 32,
17501        0xfc0003ff, 0x2000026d, 0                      , 0,
17502        0x0                 },        /* _POOL32A5~*(77) */
17503     { reserved_block      , 0                   , 0   , 32,
17504        0xfc0003ff, 0x20000275, 0                      , 0,
17505        0x0                 },        /* _POOL32A5~*(78) */
17506     { reserved_block      , 0                   , 0   , 32,
17507        0xfc0003ff, 0x2000027d, 0                      , 0,
17508        0x0                 },        /* _POOL32A5~*(79) */
17509     { instruction         , 0                   , 0   , 32,
17510        0xfc0003ff, 0x20000285, &NMD::CMPU_LT_QB       , 0,
17511        DSP_                },        /* CMPU.LT.QB */
17512     { pool                , SUBQH__R__W         , 2   , 32,
17513        0xfc0003ff, 0x2000028d, 0                      , 0,
17514        0x0                 },        /* SUBQH[_R].W */
17515     { instruction         , 0                   , 0   , 32,
17516        0xfc0003ff, 0x20000295, &NMD::MODSUB           , 0,
17517        DSP_                },        /* MODSUB */
17518     { reserved_block      , 0                   , 0   , 32,
17519        0xfc0003ff, 0x2000029d, 0                      , 0,
17520        0x0                 },        /* _POOL32A5~*(83) */
17521     { reserved_block      , 0                   , 0   , 32,
17522        0xfc0003ff, 0x200002a5, 0                      , 0,
17523        0x0                 },        /* _POOL32A5~*(84) */
17524     { reserved_block      , 0                   , 0   , 32,
17525        0xfc0003ff, 0x200002ad, 0                      , 0,
17526        0x0                 },        /* _POOL32A5~*(85) */
17527     { reserved_block      , 0                   , 0   , 32,
17528        0xfc0003ff, 0x200002b5, 0                      , 0,
17529        0x0                 },        /* _POOL32A5~*(86) */
17530     { reserved_block      , 0                   , 0   , 32,
17531        0xfc0003ff, 0x200002bd, 0                      , 0,
17532        0x0                 },        /* _POOL32A5~*(87) */
17533     { instruction         , 0                   , 0   , 32,
17534        0xfc0003ff, 0x200002c5, &NMD::CMPU_LE_QB       , 0,
17535        DSP_                },        /* CMPU.LE.QB */
17536     { pool                , SUBU__S__QB         , 2   , 32,
17537        0xfc0003ff, 0x200002cd, 0                      , 0,
17538        0x0                 },        /* SUBU[_S].QB */
17539     { instruction         , 0                   , 0   , 32,
17540        0xfc0003ff, 0x200002d5, &NMD::SHRAV_R_W        , 0,
17541        DSP_                },        /* SHRAV_R.W */
17542     { reserved_block      , 0                   , 0   , 32,
17543        0xfc0003ff, 0x200002dd, 0                      , 0,
17544        0x0                 },        /* _POOL32A5~*(91) */
17545     { reserved_block      , 0                   , 0   , 32,
17546        0xfc0003ff, 0x200002e5, 0                      , 0,
17547        0x0                 },        /* _POOL32A5~*(92) */
17548     { reserved_block      , 0                   , 0   , 32,
17549        0xfc0003ff, 0x200002ed, 0                      , 0,
17550        0x0                 },        /* _POOL32A5~*(93) */
17551     { instruction         , 0                   , 0   , 32,
17552        0xfc0003ff, 0x200002f5, &NMD::SHRA_R_W         , 0,
17553        DSP_                },        /* SHRA_R.W */
17554     { reserved_block      , 0                   , 0   , 32,
17555        0xfc0003ff, 0x200002fd, 0                      , 0,
17556        0x0                 },        /* _POOL32A5~*(95) */
17557     { instruction         , 0                   , 0   , 32,
17558        0xfc0003ff, 0x20000305, &NMD::ADDQ_S_W         , 0,
17559        DSP_                },        /* ADDQ_S.W */
17560     { pool                , SUBU__S__PH         , 2   , 32,
17561        0xfc0003ff, 0x2000030d, 0                      , 0,
17562        0x0                 },        /* SUBU[_S].PH */
17563     { instruction         , 0                   , 0   , 32,
17564        0xfc0003ff, 0x20000315, &NMD::SHRLV_PH         , 0,
17565        DSP_                },        /* SHRLV.PH */
17566     { reserved_block      , 0                   , 0   , 32,
17567        0xfc0003ff, 0x2000031d, 0                      , 0,
17568        0x0                 },        /* _POOL32A5~*(99) */
17569     { reserved_block      , 0                   , 0   , 32,
17570        0xfc0003ff, 0x20000325, 0                      , 0,
17571        0x0                 },        /* _POOL32A5~*(100) */
17572     { reserved_block      , 0                   , 0   , 32,
17573        0xfc0003ff, 0x2000032d, 0                      , 0,
17574        0x0                 },        /* _POOL32A5~*(101) */
17575     { pool                , SHRA__R__PH         , 2   , 32,
17576        0xfc0003ff, 0x20000335, 0                      , 0,
17577        0x0                 },        /* SHRA[_R].PH */
17578     { reserved_block      , 0                   , 0   , 32,
17579        0xfc0003ff, 0x2000033d, 0                      , 0,
17580        0x0                 },        /* _POOL32A5~*(103) */
17581     { instruction         , 0                   , 0   , 32,
17582        0xfc0003ff, 0x20000345, &NMD::SUBQ_S_W         , 0,
17583        DSP_                },        /* SUBQ_S.W */
17584     { pool                , SUBUH__R__QB        , 2   , 32,
17585        0xfc0003ff, 0x2000034d, 0                      , 0,
17586        0x0                 },        /* SUBUH[_R].QB */
17587     { instruction         , 0                   , 0   , 32,
17588        0xfc0003ff, 0x20000355, &NMD::SHRLV_QB         , 0,
17589        DSP_                },        /* SHRLV.QB */
17590     { reserved_block      , 0                   , 0   , 32,
17591        0xfc0003ff, 0x2000035d, 0                      , 0,
17592        0x0                 },        /* _POOL32A5~*(107) */
17593     { reserved_block      , 0                   , 0   , 32,
17594        0xfc0003ff, 0x20000365, 0                      , 0,
17595        0x0                 },        /* _POOL32A5~*(108) */
17596     { reserved_block      , 0                   , 0   , 32,
17597        0xfc0003ff, 0x2000036d, 0                      , 0,
17598        0x0                 },        /* _POOL32A5~*(109) */
17599     { reserved_block      , 0                   , 0   , 32,
17600        0xfc0003ff, 0x20000375, 0                      , 0,
17601        0x0                 },        /* _POOL32A5~*(110) */
17602     { reserved_block      , 0                   , 0   , 32,
17603        0xfc0003ff, 0x2000037d, 0                      , 0,
17604        0x0                 },        /* _POOL32A5~*(111) */
17605     { instruction         , 0                   , 0   , 32,
17606        0xfc0003ff, 0x20000385, &NMD::ADDSC            , 0,
17607        DSP_                },        /* ADDSC */
17608     { pool                , SHLLV__S__PH        , 2   , 32,
17609        0xfc0003ff, 0x2000038d, 0                      , 0,
17610        0x0                 },        /* SHLLV[_S].PH */
17611     { instruction         , 0                   , 0   , 32,
17612        0xfc0003ff, 0x20000395, &NMD::SHLLV_QB         , 0,
17613        DSP_                },        /* SHLLV.QB */
17614     { reserved_block      , 0                   , 0   , 32,
17615        0xfc0003ff, 0x2000039d, 0                      , 0,
17616        0x0                 },        /* _POOL32A5~*(115) */
17617     { reserved_block      , 0                   , 0   , 32,
17618        0xfc0003ff, 0x200003a5, 0                      , 0,
17619        0x0                 },        /* _POOL32A5~*(116) */
17620     { reserved_block      , 0                   , 0   , 32,
17621        0xfc0003ff, 0x200003ad, 0                      , 0,
17622        0x0                 },        /* _POOL32A5~*(117) */
17623     { pool                , SHLL__S__PH         , 4   , 32,
17624        0xfc0003ff, 0x200003b5, 0                      , 0,
17625        0x0                 },        /* SHLL[_S].PH */
17626     { reserved_block      , 0                   , 0   , 32,
17627        0xfc0003ff, 0x200003bd, 0                      , 0,
17628        0x0                 },        /* _POOL32A5~*(119) */
17629     { instruction         , 0                   , 0   , 32,
17630        0xfc0003ff, 0x200003c5, &NMD::ADDWC            , 0,
17631        DSP_                },        /* ADDWC */
17632     { pool                , PRECR_SRA__R__PH_W  , 2   , 32,
17633        0xfc0003ff, 0x200003cd, 0                      , 0,
17634        0x0                 },        /* PRECR_SRA[_R].PH.W */
17635     { instruction         , 0                   , 0   , 32,
17636        0xfc0003ff, 0x200003d5, &NMD::SHLLV_S_W        , 0,
17637        DSP_                },        /* SHLLV_S.W */
17638     { reserved_block      , 0                   , 0   , 32,
17639        0xfc0003ff, 0x200003dd, 0                      , 0,
17640        0x0                 },        /* _POOL32A5~*(123) */
17641     { reserved_block      , 0                   , 0   , 32,
17642        0xfc0003ff, 0x200003e5, 0                      , 0,
17643        0x0                 },        /* _POOL32A5~*(124) */
17644     { reserved_block      , 0                   , 0   , 32,
17645        0xfc0003ff, 0x200003ed, 0                      , 0,
17646        0x0                 },        /* _POOL32A5~*(125) */
17647     { instruction         , 0                   , 0   , 32,
17648        0xfc0003ff, 0x200003f5, &NMD::SHLL_S_W         , 0,
17649        DSP_                },        /* SHLL_S.W */
17650     { reserved_block      , 0                   , 0   , 32,
17651        0xfc0003ff, 0x200003fd, 0                      , 0,
17652        0x0                 },        /* _POOL32A5~*(127) */
17653 };
17654
17655
17656 NMD::Pool NMD::PP_LSX[16] = {
17657     { instruction         , 0                   , 0   , 32,
17658        0xfc0007ff, 0x20000007, &NMD::LBX              , 0,
17659        0x0                 },        /* LBX */
17660     { instruction         , 0                   , 0   , 32,
17661        0xfc0007ff, 0x20000087, &NMD::SBX              , 0,
17662        XMMS_               },        /* SBX */
17663     { instruction         , 0                   , 0   , 32,
17664        0xfc0007ff, 0x20000107, &NMD::LBUX             , 0,
17665        0x0                 },        /* LBUX */
17666     { reserved_block      , 0                   , 0   , 32,
17667        0xfc0007ff, 0x20000187, 0                      , 0,
17668        0x0                 },        /* PP.LSX~*(3) */
17669     { instruction         , 0                   , 0   , 32,
17670        0xfc0007ff, 0x20000207, &NMD::LHX              , 0,
17671        0x0                 },        /* LHX */
17672     { instruction         , 0                   , 0   , 32,
17673        0xfc0007ff, 0x20000287, &NMD::SHX              , 0,
17674        XMMS_               },        /* SHX */
17675     { instruction         , 0                   , 0   , 32,
17676        0xfc0007ff, 0x20000307, &NMD::LHUX             , 0,
17677        0x0                 },        /* LHUX */
17678     { instruction         , 0                   , 0   , 32,
17679        0xfc0007ff, 0x20000387, &NMD::LWUX             , 0,
17680        MIPS64_             },        /* LWUX */
17681     { instruction         , 0                   , 0   , 32,
17682        0xfc0007ff, 0x20000407, &NMD::LWX              , 0,
17683        0x0                 },        /* LWX */
17684     { instruction         , 0                   , 0   , 32,
17685        0xfc0007ff, 0x20000487, &NMD::SWX              , 0,
17686        XMMS_               },        /* SWX */
17687     { instruction         , 0                   , 0   , 32,
17688        0xfc0007ff, 0x20000507, &NMD::LWC1X            , 0,
17689        CP1_                },        /* LWC1X */
17690     { instruction         , 0                   , 0   , 32,
17691        0xfc0007ff, 0x20000587, &NMD::SWC1X            , 0,
17692        CP1_                },        /* SWC1X */
17693     { instruction         , 0                   , 0   , 32,
17694        0xfc0007ff, 0x20000607, &NMD::LDX              , 0,
17695        MIPS64_             },        /* LDX */
17696     { instruction         , 0                   , 0   , 32,
17697        0xfc0007ff, 0x20000687, &NMD::SDX              , 0,
17698        MIPS64_             },        /* SDX */
17699     { instruction         , 0                   , 0   , 32,
17700        0xfc0007ff, 0x20000707, &NMD::LDC1X            , 0,
17701        CP1_                },        /* LDC1X */
17702     { instruction         , 0                   , 0   , 32,
17703        0xfc0007ff, 0x20000787, &NMD::SDC1X            , 0,
17704        CP1_                },        /* SDC1X */
17705 };
17706
17707
17708 NMD::Pool NMD::PP_LSXS[16] = {
17709     { reserved_block      , 0                   , 0   , 32,
17710        0xfc0007ff, 0x20000047, 0                      , 0,
17711        0x0                 },        /* PP.LSXS~*(0) */
17712     { reserved_block      , 0                   , 0   , 32,
17713        0xfc0007ff, 0x200000c7, 0                      , 0,
17714        0x0                 },        /* PP.LSXS~*(1) */
17715     { reserved_block      , 0                   , 0   , 32,
17716        0xfc0007ff, 0x20000147, 0                      , 0,
17717        0x0                 },        /* PP.LSXS~*(2) */
17718     { reserved_block      , 0                   , 0   , 32,
17719        0xfc0007ff, 0x200001c7, 0                      , 0,
17720        0x0                 },        /* PP.LSXS~*(3) */
17721     { instruction         , 0                   , 0   , 32,
17722        0xfc0007ff, 0x20000247, &NMD::LHXS             , 0,
17723        0x0                 },        /* LHXS */
17724     { instruction         , 0                   , 0   , 32,
17725        0xfc0007ff, 0x200002c7, &NMD::SHXS             , 0,
17726        XMMS_               },        /* SHXS */
17727     { instruction         , 0                   , 0   , 32,
17728        0xfc0007ff, 0x20000347, &NMD::LHUXS            , 0,
17729        0x0                 },        /* LHUXS */
17730     { instruction         , 0                   , 0   , 32,
17731        0xfc0007ff, 0x200003c7, &NMD::LWUXS            , 0,
17732        MIPS64_             },        /* LWUXS */
17733     { instruction         , 0                   , 0   , 32,
17734        0xfc0007ff, 0x20000447, &NMD::LWXS_32_         , 0,
17735        0x0                 },        /* LWXS[32] */
17736     { instruction         , 0                   , 0   , 32,
17737        0xfc0007ff, 0x200004c7, &NMD::SWXS             , 0,
17738        XMMS_               },        /* SWXS */
17739     { instruction         , 0                   , 0   , 32,
17740        0xfc0007ff, 0x20000547, &NMD::LWC1XS           , 0,
17741        CP1_                },        /* LWC1XS */
17742     { instruction         , 0                   , 0   , 32,
17743        0xfc0007ff, 0x200005c7, &NMD::SWC1XS           , 0,
17744        CP1_                },        /* SWC1XS */
17745     { instruction         , 0                   , 0   , 32,
17746        0xfc0007ff, 0x20000647, &NMD::LDXS             , 0,
17747        MIPS64_             },        /* LDXS */
17748     { instruction         , 0                   , 0   , 32,
17749        0xfc0007ff, 0x200006c7, &NMD::SDXS             , 0,
17750        MIPS64_             },        /* SDXS */
17751     { instruction         , 0                   , 0   , 32,
17752        0xfc0007ff, 0x20000747, &NMD::LDC1XS           , 0,
17753        CP1_                },        /* LDC1XS */
17754     { instruction         , 0                   , 0   , 32,
17755        0xfc0007ff, 0x200007c7, &NMD::SDC1XS           , 0,
17756        CP1_                },        /* SDC1XS */
17757 };
17758
17759
17760 NMD::Pool NMD::P_LSX[2] = {
17761     { pool                , PP_LSX              , 16  , 32,
17762        0xfc00007f, 0x20000007, 0                      , 0,
17763        0x0                 },        /* PP.LSX */
17764     { pool                , PP_LSXS             , 16  , 32,
17765        0xfc00007f, 0x20000047, 0                      , 0,
17766        0x0                 },        /* PP.LSXS */
17767 };
17768
17769
17770 NMD::Pool NMD::POOL32Axf_1_0[4] = {
17771     { instruction         , 0                   , 0   , 32,
17772        0xfc003fff, 0x2000007f, &NMD::MFHI_DSP_        , 0,
17773        DSP_                },        /* MFHI[DSP] */
17774     { instruction         , 0                   , 0   , 32,
17775        0xfc003fff, 0x2000107f, &NMD::MFLO_DSP_        , 0,
17776        DSP_                },        /* MFLO[DSP] */
17777     { instruction         , 0                   , 0   , 32,
17778        0xfc003fff, 0x2000207f, &NMD::MTHI_DSP_        , 0,
17779        DSP_                },        /* MTHI[DSP] */
17780     { instruction         , 0                   , 0   , 32,
17781        0xfc003fff, 0x2000307f, &NMD::MTLO_DSP_        , 0,
17782        DSP_                },        /* MTLO[DSP] */
17783 };
17784
17785
17786 NMD::Pool NMD::POOL32Axf_1_1[4] = {
17787     { instruction         , 0                   , 0   , 32,
17788        0xfc003fff, 0x2000027f, &NMD::MTHLIP           , 0,
17789        DSP_                },        /* MTHLIP */
17790     { instruction         , 0                   , 0   , 32,
17791        0xfc003fff, 0x2000127f, &NMD::SHILOV           , 0,
17792        DSP_                },        /* SHILOV */
17793     { reserved_block      , 0                   , 0   , 32,
17794        0xfc003fff, 0x2000227f, 0                      , 0,
17795        0x0                 },        /* POOL32Axf_1_1~*(2) */
17796     { reserved_block      , 0                   , 0   , 32,
17797        0xfc003fff, 0x2000327f, 0                      , 0,
17798        0x0                 },        /* POOL32Axf_1_1~*(3) */
17799 };
17800
17801
17802 NMD::Pool NMD::POOL32Axf_1_3[4] = {
17803     { instruction         , 0                   , 0   , 32,
17804        0xfc003fff, 0x2000067f, &NMD::RDDSP            , 0,
17805        DSP_                },        /* RDDSP */
17806     { instruction         , 0                   , 0   , 32,
17807        0xfc003fff, 0x2000167f, &NMD::WRDSP            , 0,
17808        DSP_                },        /* WRDSP */
17809     { instruction         , 0                   , 0   , 32,
17810        0xfc003fff, 0x2000267f, &NMD::EXTP             , 0,
17811        DSP_                },        /* EXTP */
17812     { instruction         , 0                   , 0   , 32,
17813        0xfc003fff, 0x2000367f, &NMD::EXTPDP           , 0,
17814        DSP_                },        /* EXTPDP */
17815 };
17816
17817
17818 NMD::Pool NMD::POOL32Axf_1_4[2] = {
17819     { instruction         , 0                   , 0   , 32,
17820        0xfc001fff, 0x2000087f, &NMD::SHLL_QB          , 0,
17821        DSP_                },        /* SHLL.QB */
17822     { instruction         , 0                   , 0   , 32,
17823        0xfc001fff, 0x2000187f, &NMD::SHRL_QB          , 0,
17824        DSP_                },        /* SHRL.QB */
17825 };
17826
17827
17828 NMD::Pool NMD::MAQ_S_A__W_PHR[2] = {
17829     { instruction         , 0                   , 0   , 32,
17830        0xfc003fff, 0x20000a7f, &NMD::MAQ_S_W_PHR      , 0,
17831        DSP_                },        /* MAQ_S.W.PHR */
17832     { instruction         , 0                   , 0   , 32,
17833        0xfc003fff, 0x20002a7f, &NMD::MAQ_SA_W_PHR     , 0,
17834        DSP_                },        /* MAQ_SA.W.PHR */
17835 };
17836
17837
17838 NMD::Pool NMD::MAQ_S_A__W_PHL[2] = {
17839     { instruction         , 0                   , 0   , 32,
17840        0xfc003fff, 0x20001a7f, &NMD::MAQ_S_W_PHL      , 0,
17841        DSP_                },        /* MAQ_S.W.PHL */
17842     { instruction         , 0                   , 0   , 32,
17843        0xfc003fff, 0x20003a7f, &NMD::MAQ_SA_W_PHL     , 0,
17844        DSP_                },        /* MAQ_SA.W.PHL */
17845 };
17846
17847
17848 NMD::Pool NMD::POOL32Axf_1_5[2] = {
17849     { pool                , MAQ_S_A__W_PHR      , 2   , 32,
17850        0xfc001fff, 0x20000a7f, 0                      , 0,
17851        0x0                 },        /* MAQ_S[A].W.PHR */
17852     { pool                , MAQ_S_A__W_PHL      , 2   , 32,
17853        0xfc001fff, 0x20001a7f, 0                      , 0,
17854        0x0                 },        /* MAQ_S[A].W.PHL */
17855 };
17856
17857
17858 NMD::Pool NMD::POOL32Axf_1_7[4] = {
17859     { instruction         , 0                   , 0   , 32,
17860        0xfc003fff, 0x20000e7f, &NMD::EXTR_W           , 0,
17861        DSP_                },        /* EXTR.W */
17862     { instruction         , 0                   , 0   , 32,
17863        0xfc003fff, 0x20001e7f, &NMD::EXTR_R_W         , 0,
17864        DSP_                },        /* EXTR_R.W */
17865     { instruction         , 0                   , 0   , 32,
17866        0xfc003fff, 0x20002e7f, &NMD::EXTR_RS_W        , 0,
17867        DSP_                },        /* EXTR_RS.W */
17868     { instruction         , 0                   , 0   , 32,
17869        0xfc003fff, 0x20003e7f, &NMD::EXTR_S_H         , 0,
17870        DSP_                },        /* EXTR_S.H */
17871 };
17872
17873
17874 NMD::Pool NMD::POOL32Axf_1[8] = {
17875     { pool                , POOL32Axf_1_0       , 4   , 32,
17876        0xfc000fff, 0x2000007f, 0                      , 0,
17877        0x0                 },        /* POOL32Axf_1_0 */
17878     { pool                , POOL32Axf_1_1       , 4   , 32,
17879        0xfc000fff, 0x2000027f, 0                      , 0,
17880        0x0                 },        /* POOL32Axf_1_1 */
17881     { reserved_block      , 0                   , 0   , 32,
17882        0xfc000fff, 0x2000047f, 0                      , 0,
17883        0x0                 },        /* POOL32Axf_1~*(2) */
17884     { pool                , POOL32Axf_1_3       , 4   , 32,
17885        0xfc000fff, 0x2000067f, 0                      , 0,
17886        0x0                 },        /* POOL32Axf_1_3 */
17887     { pool                , POOL32Axf_1_4       , 2   , 32,
17888        0xfc000fff, 0x2000087f, 0                      , 0,
17889        0x0                 },        /* POOL32Axf_1_4 */
17890     { pool                , POOL32Axf_1_5       , 2   , 32,
17891        0xfc000fff, 0x20000a7f, 0                      , 0,
17892        0x0                 },        /* POOL32Axf_1_5 */
17893     { reserved_block      , 0                   , 0   , 32,
17894        0xfc000fff, 0x20000c7f, 0                      , 0,
17895        0x0                 },        /* POOL32Axf_1~*(6) */
17896     { pool                , POOL32Axf_1_7       , 4   , 32,
17897        0xfc000fff, 0x20000e7f, 0                      , 0,
17898        0x0                 },        /* POOL32Axf_1_7 */
17899 };
17900
17901
17902 NMD::Pool NMD::POOL32Axf_2_DSP__0_7[8] = {
17903     { instruction         , 0                   , 0   , 32,
17904        0xfc003fff, 0x200000bf, &NMD::DPA_W_PH         , 0,
17905        DSP_                },        /* DPA.W.PH */
17906     { instruction         , 0                   , 0   , 32,
17907        0xfc003fff, 0x200002bf, &NMD::DPAQ_S_W_PH      , 0,
17908        DSP_                },        /* DPAQ_S.W.PH */
17909     { instruction         , 0                   , 0   , 32,
17910        0xfc003fff, 0x200004bf, &NMD::DPS_W_PH         , 0,
17911        DSP_                },        /* DPS.W.PH */
17912     { instruction         , 0                   , 0   , 32,
17913        0xfc003fff, 0x200006bf, &NMD::DPSQ_S_W_PH      , 0,
17914        DSP_                },        /* DPSQ_S.W.PH */
17915     { reserved_block      , 0                   , 0   , 32,
17916        0xfc003fff, 0x200008bf, 0                      , 0,
17917        0x0                 },        /* POOL32Axf_2(DSP)_0_7~*(4) */
17918     { instruction         , 0                   , 0   , 32,
17919        0xfc003fff, 0x20000abf, &NMD::MADD_DSP_        , 0,
17920        DSP_                },        /* MADD[DSP] */
17921     { instruction         , 0                   , 0   , 32,
17922        0xfc003fff, 0x20000cbf, &NMD::MULT_DSP_        , 0,
17923        DSP_                },        /* MULT[DSP] */
17924     { instruction         , 0                   , 0   , 32,
17925        0xfc003fff, 0x20000ebf, &NMD::EXTRV_W          , 0,
17926        DSP_                },        /* EXTRV.W */
17927 };
17928
17929
17930 NMD::Pool NMD::POOL32Axf_2_DSP__8_15[8] = {
17931     { instruction         , 0                   , 0   , 32,
17932        0xfc003fff, 0x200010bf, &NMD::DPAX_W_PH        , 0,
17933        DSP_                },        /* DPAX.W.PH */
17934     { instruction         , 0                   , 0   , 32,
17935        0xfc003fff, 0x200012bf, &NMD::DPAQ_SA_L_W      , 0,
17936        DSP_                },        /* DPAQ_SA.L.W */
17937     { instruction         , 0                   , 0   , 32,
17938        0xfc003fff, 0x200014bf, &NMD::DPSX_W_PH        , 0,
17939        DSP_                },        /* DPSX.W.PH */
17940     { instruction         , 0                   , 0   , 32,
17941        0xfc003fff, 0x200016bf, &NMD::DPSQ_SA_L_W      , 0,
17942        DSP_                },        /* DPSQ_SA.L.W */
17943     { reserved_block      , 0                   , 0   , 32,
17944        0xfc003fff, 0x200018bf, 0                      , 0,
17945        0x0                 },        /* POOL32Axf_2(DSP)_8_15~*(4) */
17946     { instruction         , 0                   , 0   , 32,
17947        0xfc003fff, 0x20001abf, &NMD::MADDU_DSP_       , 0,
17948        DSP_                },        /* MADDU[DSP] */
17949     { instruction         , 0                   , 0   , 32,
17950        0xfc003fff, 0x20001cbf, &NMD::MULTU_DSP_       , 0,
17951        DSP_                },        /* MULTU[DSP] */
17952     { instruction         , 0                   , 0   , 32,
17953        0xfc003fff, 0x20001ebf, &NMD::EXTRV_R_W        , 0,
17954        DSP_                },        /* EXTRV_R.W */
17955 };
17956
17957
17958 NMD::Pool NMD::POOL32Axf_2_DSP__16_23[8] = {
17959     { instruction         , 0                   , 0   , 32,
17960        0xfc003fff, 0x200020bf, &NMD::DPAU_H_QBL       , 0,
17961        DSP_                },        /* DPAU.H.QBL */
17962     { instruction         , 0                   , 0   , 32,
17963        0xfc003fff, 0x200022bf, &NMD::DPAQX_S_W_PH     , 0,
17964        DSP_                },        /* DPAQX_S.W.PH */
17965     { instruction         , 0                   , 0   , 32,
17966        0xfc003fff, 0x200024bf, &NMD::DPSU_H_QBL       , 0,
17967        DSP_                },        /* DPSU.H.QBL */
17968     { instruction         , 0                   , 0   , 32,
17969        0xfc003fff, 0x200026bf, &NMD::DPSQX_S_W_PH     , 0,
17970        DSP_                },        /* DPSQX_S.W.PH */
17971     { instruction         , 0                   , 0   , 32,
17972        0xfc003fff, 0x200028bf, &NMD::EXTPV            , 0,
17973        DSP_                },        /* EXTPV */
17974     { instruction         , 0                   , 0   , 32,
17975        0xfc003fff, 0x20002abf, &NMD::MSUB_DSP_        , 0,
17976        DSP_                },        /* MSUB[DSP] */
17977     { instruction         , 0                   , 0   , 32,
17978        0xfc003fff, 0x20002cbf, &NMD::MULSA_W_PH       , 0,
17979        DSP_                },        /* MULSA.W.PH */
17980     { instruction         , 0                   , 0   , 32,
17981        0xfc003fff, 0x20002ebf, &NMD::EXTRV_RS_W       , 0,
17982        DSP_                },        /* EXTRV_RS.W */
17983 };
17984
17985
17986 NMD::Pool NMD::POOL32Axf_2_DSP__24_31[8] = {
17987     { instruction         , 0                   , 0   , 32,
17988        0xfc003fff, 0x200030bf, &NMD::DPAU_H_QBR       , 0,
17989        DSP_                },        /* DPAU.H.QBR */
17990     { instruction         , 0                   , 0   , 32,
17991        0xfc003fff, 0x200032bf, &NMD::DPAQX_SA_W_PH    , 0,
17992        DSP_                },        /* DPAQX_SA.W.PH */
17993     { instruction         , 0                   , 0   , 32,
17994        0xfc003fff, 0x200034bf, &NMD::DPSU_H_QBR       , 0,
17995        DSP_                },        /* DPSU.H.QBR */
17996     { instruction         , 0                   , 0   , 32,
17997        0xfc003fff, 0x200036bf, &NMD::DPSQX_SA_W_PH    , 0,
17998        DSP_                },        /* DPSQX_SA.W.PH */
17999     { instruction         , 0                   , 0   , 32,
18000        0xfc003fff, 0x200038bf, &NMD::EXTPDPV          , 0,
18001        DSP_                },        /* EXTPDPV */
18002     { instruction         , 0                   , 0   , 32,
18003        0xfc003fff, 0x20003abf, &NMD::MSUBU_DSP_       , 0,
18004        DSP_                },        /* MSUBU[DSP] */
18005     { instruction         , 0                   , 0   , 32,
18006        0xfc003fff, 0x20003cbf, &NMD::MULSAQ_S_W_PH    , 0,
18007        DSP_                },        /* MULSAQ_S.W.PH */
18008     { instruction         , 0                   , 0   , 32,
18009        0xfc003fff, 0x20003ebf, &NMD::EXTRV_S_H        , 0,
18010        DSP_                },        /* EXTRV_S.H */
18011 };
18012
18013
18014 NMD::Pool NMD::POOL32Axf_2[4] = {
18015     { pool                , POOL32Axf_2_DSP__0_7, 8   , 32,
18016        0xfc0031ff, 0x200000bf, 0                      , 0,
18017        0x0                 },        /* POOL32Axf_2(DSP)_0_7 */
18018     { pool                , POOL32Axf_2_DSP__8_15, 8   , 32,
18019        0xfc0031ff, 0x200010bf, 0                      , 0,
18020        0x0                 },        /* POOL32Axf_2(DSP)_8_15 */
18021     { pool                , POOL32Axf_2_DSP__16_23, 8   , 32,
18022        0xfc0031ff, 0x200020bf, 0                      , 0,
18023        0x0                 },        /* POOL32Axf_2(DSP)_16_23 */
18024     { pool                , POOL32Axf_2_DSP__24_31, 8   , 32,
18025        0xfc0031ff, 0x200030bf, 0                      , 0,
18026        0x0                 },        /* POOL32Axf_2(DSP)_24_31 */
18027 };
18028
18029
18030 NMD::Pool NMD::POOL32Axf_4[128] = {
18031     { instruction         , 0                   , 0   , 32,
18032        0xfc00ffff, 0x2000013f, &NMD::ABSQ_S_QB        , 0,
18033        DSP_                },        /* ABSQ_S.QB */
18034     { instruction         , 0                   , 0   , 32,
18035        0xfc00ffff, 0x2000033f, &NMD::REPLV_PH         , 0,
18036        DSP_                },        /* REPLV.PH */
18037     { reserved_block      , 0                   , 0   , 32,
18038        0xfc00ffff, 0x2000053f, 0                      , 0,
18039        0x0                 },        /* POOL32Axf_4~*(2) */
18040     { reserved_block      , 0                   , 0   , 32,
18041        0xfc00ffff, 0x2000073f, 0                      , 0,
18042        0x0                 },        /* POOL32Axf_4~*(3) */
18043     { reserved_block      , 0                   , 0   , 32,
18044        0xfc00ffff, 0x2000093f, 0                      , 0,
18045        0x0                 },        /* POOL32Axf_4~*(4) */
18046     { reserved_block      , 0                   , 0   , 32,
18047        0xfc00ffff, 0x20000b3f, 0                      , 0,
18048        0x0                 },        /* POOL32Axf_4~*(5) */
18049     { reserved_block      , 0                   , 0   , 32,
18050        0xfc00ffff, 0x20000d3f, 0                      , 0,
18051        0x0                 },        /* POOL32Axf_4~*(6) */
18052     { reserved_block      , 0                   , 0   , 32,
18053        0xfc00ffff, 0x20000f3f, 0                      , 0,
18054        0x0                 },        /* POOL32Axf_4~*(7) */
18055     { instruction         , 0                   , 0   , 32,
18056        0xfc00ffff, 0x2000113f, &NMD::ABSQ_S_PH        , 0,
18057        DSP_                },        /* ABSQ_S.PH */
18058     { instruction         , 0                   , 0   , 32,
18059        0xfc00ffff, 0x2000133f, &NMD::REPLV_QB         , 0,
18060        DSP_                },        /* REPLV.QB */
18061     { reserved_block      , 0                   , 0   , 32,
18062        0xfc00ffff, 0x2000153f, 0                      , 0,
18063        0x0                 },        /* POOL32Axf_4~*(10) */
18064     { reserved_block      , 0                   , 0   , 32,
18065        0xfc00ffff, 0x2000173f, 0                      , 0,
18066        0x0                 },        /* POOL32Axf_4~*(11) */
18067     { reserved_block      , 0                   , 0   , 32,
18068        0xfc00ffff, 0x2000193f, 0                      , 0,
18069        0x0                 },        /* POOL32Axf_4~*(12) */
18070     { reserved_block      , 0                   , 0   , 32,
18071        0xfc00ffff, 0x20001b3f, 0                      , 0,
18072        0x0                 },        /* POOL32Axf_4~*(13) */
18073     { reserved_block      , 0                   , 0   , 32,
18074        0xfc00ffff, 0x20001d3f, 0                      , 0,
18075        0x0                 },        /* POOL32Axf_4~*(14) */
18076     { reserved_block      , 0                   , 0   , 32,
18077        0xfc00ffff, 0x20001f3f, 0                      , 0,
18078        0x0                 },        /* POOL32Axf_4~*(15) */
18079     { instruction         , 0                   , 0   , 32,
18080        0xfc00ffff, 0x2000213f, &NMD::ABSQ_S_W         , 0,
18081        DSP_                },        /* ABSQ_S.W */
18082     { reserved_block      , 0                   , 0   , 32,
18083        0xfc00ffff, 0x2000233f, 0                      , 0,
18084        0x0                 },        /* POOL32Axf_4~*(17) */
18085     { reserved_block      , 0                   , 0   , 32,
18086        0xfc00ffff, 0x2000253f, 0                      , 0,
18087        0x0                 },        /* POOL32Axf_4~*(18) */
18088     { reserved_block      , 0                   , 0   , 32,
18089        0xfc00ffff, 0x2000273f, 0                      , 0,
18090        0x0                 },        /* POOL32Axf_4~*(19) */
18091     { reserved_block      , 0                   , 0   , 32,
18092        0xfc00ffff, 0x2000293f, 0                      , 0,
18093        0x0                 },        /* POOL32Axf_4~*(20) */
18094     { reserved_block      , 0                   , 0   , 32,
18095        0xfc00ffff, 0x20002b3f, 0                      , 0,
18096        0x0                 },        /* POOL32Axf_4~*(21) */
18097     { reserved_block      , 0                   , 0   , 32,
18098        0xfc00ffff, 0x20002d3f, 0                      , 0,
18099        0x0                 },        /* POOL32Axf_4~*(22) */
18100     { reserved_block      , 0                   , 0   , 32,
18101        0xfc00ffff, 0x20002f3f, 0                      , 0,
18102        0x0                 },        /* POOL32Axf_4~*(23) */
18103     { reserved_block      , 0                   , 0   , 32,
18104        0xfc00ffff, 0x2000313f, 0                      , 0,
18105        0x0                 },        /* POOL32Axf_4~*(24) */
18106     { reserved_block      , 0                   , 0   , 32,
18107        0xfc00ffff, 0x2000333f, 0                      , 0,
18108        0x0                 },        /* POOL32Axf_4~*(25) */
18109     { reserved_block      , 0                   , 0   , 32,
18110        0xfc00ffff, 0x2000353f, 0                      , 0,
18111        0x0                 },        /* POOL32Axf_4~*(26) */
18112     { reserved_block      , 0                   , 0   , 32,
18113        0xfc00ffff, 0x2000373f, 0                      , 0,
18114        0x0                 },        /* POOL32Axf_4~*(27) */
18115     { reserved_block      , 0                   , 0   , 32,
18116        0xfc00ffff, 0x2000393f, 0                      , 0,
18117        0x0                 },        /* POOL32Axf_4~*(28) */
18118     { reserved_block      , 0                   , 0   , 32,
18119        0xfc00ffff, 0x20003b3f, 0                      , 0,
18120        0x0                 },        /* POOL32Axf_4~*(29) */
18121     { reserved_block      , 0                   , 0   , 32,
18122        0xfc00ffff, 0x20003d3f, 0                      , 0,
18123        0x0                 },        /* POOL32Axf_4~*(30) */
18124     { reserved_block      , 0                   , 0   , 32,
18125        0xfc00ffff, 0x20003f3f, 0                      , 0,
18126        0x0                 },        /* POOL32Axf_4~*(31) */
18127     { instruction         , 0                   , 0   , 32,
18128        0xfc00ffff, 0x2000413f, &NMD::INSV             , 0,
18129        DSP_                },        /* INSV */
18130     { reserved_block      , 0                   , 0   , 32,
18131        0xfc00ffff, 0x2000433f, 0                      , 0,
18132        0x0                 },        /* POOL32Axf_4~*(33) */
18133     { reserved_block      , 0                   , 0   , 32,
18134        0xfc00ffff, 0x2000453f, 0                      , 0,
18135        0x0                 },        /* POOL32Axf_4~*(34) */
18136     { reserved_block      , 0                   , 0   , 32,
18137        0xfc00ffff, 0x2000473f, 0                      , 0,
18138        0x0                 },        /* POOL32Axf_4~*(35) */
18139     { reserved_block      , 0                   , 0   , 32,
18140        0xfc00ffff, 0x2000493f, 0                      , 0,
18141        0x0                 },        /* POOL32Axf_4~*(36) */
18142     { instruction         , 0                   , 0   , 32,
18143        0xfc00ffff, 0x20004b3f, &NMD::CLO              , 0,
18144        XMMS_               },        /* CLO */
18145     { instruction         , 0                   , 0   , 32,
18146        0xfc00ffff, 0x20004d3f, &NMD::MFC2             , 0,
18147        CP2_                },        /* MFC2 */
18148     { reserved_block      , 0                   , 0   , 32,
18149        0xfc00ffff, 0x20004f3f, 0                      , 0,
18150        0x0                 },        /* POOL32Axf_4~*(39) */
18151     { instruction         , 0                   , 0   , 32,
18152        0xfc00ffff, 0x2000513f, &NMD::PRECEQ_W_PHL     , 0,
18153        DSP_                },        /* PRECEQ.W.PHL */
18154     { reserved_block      , 0                   , 0   , 32,
18155        0xfc00ffff, 0x2000533f, 0                      , 0,
18156        0x0                 },        /* POOL32Axf_4~*(41) */
18157     { reserved_block      , 0                   , 0   , 32,
18158        0xfc00ffff, 0x2000553f, 0                      , 0,
18159        0x0                 },        /* POOL32Axf_4~*(42) */
18160     { reserved_block      , 0                   , 0   , 32,
18161        0xfc00ffff, 0x2000573f, 0                      , 0,
18162        0x0                 },        /* POOL32Axf_4~*(43) */
18163     { reserved_block      , 0                   , 0   , 32,
18164        0xfc00ffff, 0x2000593f, 0                      , 0,
18165        0x0                 },        /* POOL32Axf_4~*(44) */
18166     { instruction         , 0                   , 0   , 32,
18167        0xfc00ffff, 0x20005b3f, &NMD::CLZ              , 0,
18168        XMMS_               },        /* CLZ */
18169     { instruction         , 0                   , 0   , 32,
18170        0xfc00ffff, 0x20005d3f, &NMD::MTC2             , 0,
18171        CP2_                },        /* MTC2 */
18172     { reserved_block      , 0                   , 0   , 32,
18173        0xfc00ffff, 0x20005f3f, 0                      , 0,
18174        0x0                 },        /* POOL32Axf_4~*(47) */
18175     { instruction         , 0                   , 0   , 32,
18176        0xfc00ffff, 0x2000613f, &NMD::PRECEQ_W_PHR     , 0,
18177        DSP_                },        /* PRECEQ.W.PHR */
18178     { reserved_block      , 0                   , 0   , 32,
18179        0xfc00ffff, 0x2000633f, 0                      , 0,
18180        0x0                 },        /* POOL32Axf_4~*(49) */
18181     { reserved_block      , 0                   , 0   , 32,
18182        0xfc00ffff, 0x2000653f, 0                      , 0,
18183        0x0                 },        /* POOL32Axf_4~*(50) */
18184     { reserved_block      , 0                   , 0   , 32,
18185        0xfc00ffff, 0x2000673f, 0                      , 0,
18186        0x0                 },        /* POOL32Axf_4~*(51) */
18187     { reserved_block      , 0                   , 0   , 32,
18188        0xfc00ffff, 0x2000693f, 0                      , 0,
18189        0x0                 },        /* POOL32Axf_4~*(52) */
18190     { reserved_block      , 0                   , 0   , 32,
18191        0xfc00ffff, 0x20006b3f, 0                      , 0,
18192        0x0                 },        /* POOL32Axf_4~*(53) */
18193     { instruction         , 0                   , 0   , 32,
18194        0xfc00ffff, 0x20006d3f, &NMD::DMFC2            , 0,
18195        CP2_                },        /* DMFC2 */
18196     { reserved_block      , 0                   , 0   , 32,
18197        0xfc00ffff, 0x20006f3f, 0                      , 0,
18198        0x0                 },        /* POOL32Axf_4~*(55) */
18199     { instruction         , 0                   , 0   , 32,
18200        0xfc00ffff, 0x2000713f, &NMD::PRECEQU_PH_QBL   , 0,
18201        DSP_                },        /* PRECEQU.PH.QBL */
18202     { instruction         , 0                   , 0   , 32,
18203        0xfc00ffff, 0x2000733f, &NMD::PRECEQU_PH_QBLA  , 0,
18204        DSP_                },        /* PRECEQU.PH.QBLA */
18205     { reserved_block      , 0                   , 0   , 32,
18206        0xfc00ffff, 0x2000753f, 0                      , 0,
18207        0x0                 },        /* POOL32Axf_4~*(58) */
18208     { reserved_block      , 0                   , 0   , 32,
18209        0xfc00ffff, 0x2000773f, 0                      , 0,
18210        0x0                 },        /* POOL32Axf_4~*(59) */
18211     { reserved_block      , 0                   , 0   , 32,
18212        0xfc00ffff, 0x2000793f, 0                      , 0,
18213        0x0                 },        /* POOL32Axf_4~*(60) */
18214     { reserved_block      , 0                   , 0   , 32,
18215        0xfc00ffff, 0x20007b3f, 0                      , 0,
18216        0x0                 },        /* POOL32Axf_4~*(61) */
18217     { instruction         , 0                   , 0   , 32,
18218        0xfc00ffff, 0x20007d3f, &NMD::DMTC2            , 0,
18219        CP2_                },        /* DMTC2 */
18220     { reserved_block      , 0                   , 0   , 32,
18221        0xfc00ffff, 0x20007f3f, 0                      , 0,
18222        0x0                 },        /* POOL32Axf_4~*(63) */
18223     { reserved_block      , 0                   , 0   , 32,
18224        0xfc00ffff, 0x2000813f, 0                      , 0,
18225        0x0                 },        /* POOL32Axf_4~*(64) */
18226     { reserved_block      , 0                   , 0   , 32,
18227        0xfc00ffff, 0x2000833f, 0                      , 0,
18228        0x0                 },        /* POOL32Axf_4~*(65) */
18229     { reserved_block      , 0                   , 0   , 32,
18230        0xfc00ffff, 0x2000853f, 0                      , 0,
18231        0x0                 },        /* POOL32Axf_4~*(66) */
18232     { reserved_block      , 0                   , 0   , 32,
18233        0xfc00ffff, 0x2000873f, 0                      , 0,
18234        0x0                 },        /* POOL32Axf_4~*(67) */
18235     { reserved_block      , 0                   , 0   , 32,
18236        0xfc00ffff, 0x2000893f, 0                      , 0,
18237        0x0                 },        /* POOL32Axf_4~*(68) */
18238     { reserved_block      , 0                   , 0   , 32,
18239        0xfc00ffff, 0x20008b3f, 0                      , 0,
18240        0x0                 },        /* POOL32Axf_4~*(69) */
18241     { instruction         , 0                   , 0   , 32,
18242        0xfc00ffff, 0x20008d3f, &NMD::MFHC2            , 0,
18243        CP2_                },        /* MFHC2 */
18244     { reserved_block      , 0                   , 0   , 32,
18245        0xfc00ffff, 0x20008f3f, 0                      , 0,
18246        0x0                 },        /* POOL32Axf_4~*(71) */
18247     { instruction         , 0                   , 0   , 32,
18248        0xfc00ffff, 0x2000913f, &NMD::PRECEQU_PH_QBR   , 0,
18249        DSP_                },        /* PRECEQU.PH.QBR */
18250     { instruction         , 0                   , 0   , 32,
18251        0xfc00ffff, 0x2000933f, &NMD::PRECEQU_PH_QBRA  , 0,
18252        DSP_                },        /* PRECEQU.PH.QBRA */
18253     { reserved_block      , 0                   , 0   , 32,
18254        0xfc00ffff, 0x2000953f, 0                      , 0,
18255        0x0                 },        /* POOL32Axf_4~*(74) */
18256     { reserved_block      , 0                   , 0   , 32,
18257        0xfc00ffff, 0x2000973f, 0                      , 0,
18258        0x0                 },        /* POOL32Axf_4~*(75) */
18259     { reserved_block      , 0                   , 0   , 32,
18260        0xfc00ffff, 0x2000993f, 0                      , 0,
18261        0x0                 },        /* POOL32Axf_4~*(76) */
18262     { reserved_block      , 0                   , 0   , 32,
18263        0xfc00ffff, 0x20009b3f, 0                      , 0,
18264        0x0                 },        /* POOL32Axf_4~*(77) */
18265     { instruction         , 0                   , 0   , 32,
18266        0xfc00ffff, 0x20009d3f, &NMD::MTHC2            , 0,
18267        CP2_                },        /* MTHC2 */
18268     { reserved_block      , 0                   , 0   , 32,
18269        0xfc00ffff, 0x20009f3f, 0                      , 0,
18270        0x0                 },        /* POOL32Axf_4~*(79) */
18271     { reserved_block      , 0                   , 0   , 32,
18272        0xfc00ffff, 0x2000a13f, 0                      , 0,
18273        0x0                 },        /* POOL32Axf_4~*(80) */
18274     { reserved_block      , 0                   , 0   , 32,
18275        0xfc00ffff, 0x2000a33f, 0                      , 0,
18276        0x0                 },        /* POOL32Axf_4~*(81) */
18277     { reserved_block      , 0                   , 0   , 32,
18278        0xfc00ffff, 0x2000a53f, 0                      , 0,
18279        0x0                 },        /* POOL32Axf_4~*(82) */
18280     { reserved_block      , 0                   , 0   , 32,
18281        0xfc00ffff, 0x2000a73f, 0                      , 0,
18282        0x0                 },        /* POOL32Axf_4~*(83) */
18283     { reserved_block      , 0                   , 0   , 32,
18284        0xfc00ffff, 0x2000a93f, 0                      , 0,
18285        0x0                 },        /* POOL32Axf_4~*(84) */
18286     { reserved_block      , 0                   , 0   , 32,
18287        0xfc00ffff, 0x2000ab3f, 0                      , 0,
18288        0x0                 },        /* POOL32Axf_4~*(85) */
18289     { reserved_block      , 0                   , 0   , 32,
18290        0xfc00ffff, 0x2000ad3f, 0                      , 0,
18291        0x0                 },        /* POOL32Axf_4~*(86) */
18292     { reserved_block      , 0                   , 0   , 32,
18293        0xfc00ffff, 0x2000af3f, 0                      , 0,
18294        0x0                 },        /* POOL32Axf_4~*(87) */
18295     { instruction         , 0                   , 0   , 32,
18296        0xfc00ffff, 0x2000b13f, &NMD::PRECEU_PH_QBL    , 0,
18297        DSP_                },        /* PRECEU.PH.QBL */
18298     { instruction         , 0                   , 0   , 32,
18299        0xfc00ffff, 0x2000b33f, &NMD::PRECEU_PH_QBLA   , 0,
18300        DSP_                },        /* PRECEU.PH.QBLA */
18301     { reserved_block      , 0                   , 0   , 32,
18302        0xfc00ffff, 0x2000b53f, 0                      , 0,
18303        0x0                 },        /* POOL32Axf_4~*(90) */
18304     { reserved_block      , 0                   , 0   , 32,
18305        0xfc00ffff, 0x2000b73f, 0                      , 0,
18306        0x0                 },        /* POOL32Axf_4~*(91) */
18307     { reserved_block      , 0                   , 0   , 32,
18308        0xfc00ffff, 0x2000b93f, 0                      , 0,
18309        0x0                 },        /* POOL32Axf_4~*(92) */
18310     { reserved_block      , 0                   , 0   , 32,
18311        0xfc00ffff, 0x2000bb3f, 0                      , 0,
18312        0x0                 },        /* POOL32Axf_4~*(93) */
18313     { reserved_block      , 0                   , 0   , 32,
18314        0xfc00ffff, 0x2000bd3f, 0                      , 0,
18315        0x0                 },        /* POOL32Axf_4~*(94) */
18316     { reserved_block      , 0                   , 0   , 32,
18317        0xfc00ffff, 0x2000bf3f, 0                      , 0,
18318        0x0                 },        /* POOL32Axf_4~*(95) */
18319     { reserved_block      , 0                   , 0   , 32,
18320        0xfc00ffff, 0x2000c13f, 0                      , 0,
18321        0x0                 },        /* POOL32Axf_4~*(96) */
18322     { reserved_block      , 0                   , 0   , 32,
18323        0xfc00ffff, 0x2000c33f, 0                      , 0,
18324        0x0                 },        /* POOL32Axf_4~*(97) */
18325     { reserved_block      , 0                   , 0   , 32,
18326        0xfc00ffff, 0x2000c53f, 0                      , 0,
18327        0x0                 },        /* POOL32Axf_4~*(98) */
18328     { reserved_block      , 0                   , 0   , 32,
18329        0xfc00ffff, 0x2000c73f, 0                      , 0,
18330        0x0                 },        /* POOL32Axf_4~*(99) */
18331     { reserved_block      , 0                   , 0   , 32,
18332        0xfc00ffff, 0x2000c93f, 0                      , 0,
18333        0x0                 },        /* POOL32Axf_4~*(100) */
18334     { reserved_block      , 0                   , 0   , 32,
18335        0xfc00ffff, 0x2000cb3f, 0                      , 0,
18336        0x0                 },        /* POOL32Axf_4~*(101) */
18337     { instruction         , 0                   , 0   , 32,
18338        0xfc00ffff, 0x2000cd3f, &NMD::CFC2             , 0,
18339        CP2_                },        /* CFC2 */
18340     { reserved_block      , 0                   , 0   , 32,
18341        0xfc00ffff, 0x2000cf3f, 0                      , 0,
18342        0x0                 },        /* POOL32Axf_4~*(103) */
18343     { instruction         , 0                   , 0   , 32,
18344        0xfc00ffff, 0x2000d13f, &NMD::PRECEU_PH_QBR    , 0,
18345        DSP_                },        /* PRECEU.PH.QBR */
18346     { instruction         , 0                   , 0   , 32,
18347        0xfc00ffff, 0x2000d33f, &NMD::PRECEU_PH_QBRA   , 0,
18348        DSP_                },        /* PRECEU.PH.QBRA */
18349     { reserved_block      , 0                   , 0   , 32,
18350        0xfc00ffff, 0x2000d53f, 0                      , 0,
18351        0x0                 },        /* POOL32Axf_4~*(106) */
18352     { reserved_block      , 0                   , 0   , 32,
18353        0xfc00ffff, 0x2000d73f, 0                      , 0,
18354        0x0                 },        /* POOL32Axf_4~*(107) */
18355     { reserved_block      , 0                   , 0   , 32,
18356        0xfc00ffff, 0x2000d93f, 0                      , 0,
18357        0x0                 },        /* POOL32Axf_4~*(108) */
18358     { reserved_block      , 0                   , 0   , 32,
18359        0xfc00ffff, 0x2000db3f, 0                      , 0,
18360        0x0                 },        /* POOL32Axf_4~*(109) */
18361     { instruction         , 0                   , 0   , 32,
18362        0xfc00ffff, 0x2000dd3f, &NMD::CTC2             , 0,
18363        CP2_                },        /* CTC2 */
18364     { reserved_block      , 0                   , 0   , 32,
18365        0xfc00ffff, 0x2000df3f, 0                      , 0,
18366        0x0                 },        /* POOL32Axf_4~*(111) */
18367     { reserved_block      , 0                   , 0   , 32,
18368        0xfc00ffff, 0x2000e13f, 0                      , 0,
18369        0x0                 },        /* POOL32Axf_4~*(112) */
18370     { reserved_block      , 0                   , 0   , 32,
18371        0xfc00ffff, 0x2000e33f, 0                      , 0,
18372        0x0                 },        /* POOL32Axf_4~*(113) */
18373     { reserved_block      , 0                   , 0   , 32,
18374        0xfc00ffff, 0x2000e53f, 0                      , 0,
18375        0x0                 },        /* POOL32Axf_4~*(114) */
18376     { reserved_block      , 0                   , 0   , 32,
18377        0xfc00ffff, 0x2000e73f, 0                      , 0,
18378        0x0                 },        /* POOL32Axf_4~*(115) */
18379     { reserved_block      , 0                   , 0   , 32,
18380        0xfc00ffff, 0x2000e93f, 0                      , 0,
18381        0x0                 },        /* POOL32Axf_4~*(116) */
18382     { reserved_block      , 0                   , 0   , 32,
18383        0xfc00ffff, 0x2000eb3f, 0                      , 0,
18384        0x0                 },        /* POOL32Axf_4~*(117) */
18385     { reserved_block      , 0                   , 0   , 32,
18386        0xfc00ffff, 0x2000ed3f, 0                      , 0,
18387        0x0                 },        /* POOL32Axf_4~*(118) */
18388     { reserved_block      , 0                   , 0   , 32,
18389        0xfc00ffff, 0x2000ef3f, 0                      , 0,
18390        0x0                 },        /* POOL32Axf_4~*(119) */
18391     { instruction         , 0                   , 0   , 32,
18392        0xfc00ffff, 0x2000f13f, &NMD::RADDU_W_QB       , 0,
18393        DSP_                },        /* RADDU.W.QB */
18394     { reserved_block      , 0                   , 0   , 32,
18395        0xfc00ffff, 0x2000f33f, 0                      , 0,
18396        0x0                 },        /* POOL32Axf_4~*(121) */
18397     { reserved_block      , 0                   , 0   , 32,
18398        0xfc00ffff, 0x2000f53f, 0                      , 0,
18399        0x0                 },        /* POOL32Axf_4~*(122) */
18400     { reserved_block      , 0                   , 0   , 32,
18401        0xfc00ffff, 0x2000f73f, 0                      , 0,
18402        0x0                 },        /* POOL32Axf_4~*(123) */
18403     { reserved_block      , 0                   , 0   , 32,
18404        0xfc00ffff, 0x2000f93f, 0                      , 0,
18405        0x0                 },        /* POOL32Axf_4~*(124) */
18406     { reserved_block      , 0                   , 0   , 32,
18407        0xfc00ffff, 0x2000fb3f, 0                      , 0,
18408        0x0                 },        /* POOL32Axf_4~*(125) */
18409     { reserved_block      , 0                   , 0   , 32,
18410        0xfc00ffff, 0x2000fd3f, 0                      , 0,
18411        0x0                 },        /* POOL32Axf_4~*(126) */
18412     { reserved_block      , 0                   , 0   , 32,
18413        0xfc00ffff, 0x2000ff3f, 0                      , 0,
18414        0x0                 },        /* POOL32Axf_4~*(127) */
18415 };
18416
18417
18418 NMD::Pool NMD::POOL32Axf_5_group0[32] = {
18419     { instruction         , 0                   , 0   , 32,
18420        0xfc00ffff, 0x2000017f, &NMD::TLBGP            , 0,
18421        CP0_ | VZ_ | TLB_   },        /* TLBGP */
18422     { instruction         , 0                   , 0   , 32,
18423        0xfc00ffff, 0x2000037f, &NMD::TLBP             , 0,
18424        CP0_ | TLB_         },        /* TLBP */
18425     { instruction         , 0                   , 0   , 32,
18426        0xfc00ffff, 0x2000057f, &NMD::TLBGINV          , 0,
18427        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINV */
18428     { instruction         , 0                   , 0   , 32,
18429        0xfc00ffff, 0x2000077f, &NMD::TLBINV           , 0,
18430        CP0_ | TLB_ | TLBINV_},        /* TLBINV */
18431     { reserved_block      , 0                   , 0   , 32,
18432        0xfc00ffff, 0x2000097f, 0                      , 0,
18433        0x0                 },        /* POOL32Axf_5_group0~*(4) */
18434     { reserved_block      , 0                   , 0   , 32,
18435        0xfc00ffff, 0x20000b7f, 0                      , 0,
18436        0x0                 },        /* POOL32Axf_5_group0~*(5) */
18437     { reserved_block      , 0                   , 0   , 32,
18438        0xfc00ffff, 0x20000d7f, 0                      , 0,
18439        0x0                 },        /* POOL32Axf_5_group0~*(6) */
18440     { reserved_block      , 0                   , 0   , 32,
18441        0xfc00ffff, 0x20000f7f, 0                      , 0,
18442        0x0                 },        /* POOL32Axf_5_group0~*(7) */
18443     { instruction         , 0                   , 0   , 32,
18444        0xfc00ffff, 0x2000117f, &NMD::TLBGR            , 0,
18445        CP0_ | VZ_ | TLB_   },        /* TLBGR */
18446     { instruction         , 0                   , 0   , 32,
18447        0xfc00ffff, 0x2000137f, &NMD::TLBR             , 0,
18448        CP0_ | TLB_         },        /* TLBR */
18449     { instruction         , 0                   , 0   , 32,
18450        0xfc00ffff, 0x2000157f, &NMD::TLBGINVF         , 0,
18451        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINVF */
18452     { instruction         , 0                   , 0   , 32,
18453        0xfc00ffff, 0x2000177f, &NMD::TLBINVF          , 0,
18454        CP0_ | TLB_ | TLBINV_},        /* TLBINVF */
18455     { reserved_block      , 0                   , 0   , 32,
18456        0xfc00ffff, 0x2000197f, 0                      , 0,
18457        0x0                 },        /* POOL32Axf_5_group0~*(12) */
18458     { reserved_block      , 0                   , 0   , 32,
18459        0xfc00ffff, 0x20001b7f, 0                      , 0,
18460        0x0                 },        /* POOL32Axf_5_group0~*(13) */
18461     { reserved_block      , 0                   , 0   , 32,
18462        0xfc00ffff, 0x20001d7f, 0                      , 0,
18463        0x0                 },        /* POOL32Axf_5_group0~*(14) */
18464     { reserved_block      , 0                   , 0   , 32,
18465        0xfc00ffff, 0x20001f7f, 0                      , 0,
18466        0x0                 },        /* POOL32Axf_5_group0~*(15) */
18467     { instruction         , 0                   , 0   , 32,
18468        0xfc00ffff, 0x2000217f, &NMD::TLBGWI           , 0,
18469        CP0_ | VZ_ | TLB_   },        /* TLBGWI */
18470     { instruction         , 0                   , 0   , 32,
18471        0xfc00ffff, 0x2000237f, &NMD::TLBWI            , 0,
18472        CP0_ | TLB_         },        /* TLBWI */
18473     { reserved_block      , 0                   , 0   , 32,
18474        0xfc00ffff, 0x2000257f, 0                      , 0,
18475        0x0                 },        /* POOL32Axf_5_group0~*(18) */
18476     { reserved_block      , 0                   , 0   , 32,
18477        0xfc00ffff, 0x2000277f, 0                      , 0,
18478        0x0                 },        /* POOL32Axf_5_group0~*(19) */
18479     { reserved_block      , 0                   , 0   , 32,
18480        0xfc00ffff, 0x2000297f, 0                      , 0,
18481        0x0                 },        /* POOL32Axf_5_group0~*(20) */
18482     { reserved_block      , 0                   , 0   , 32,
18483        0xfc00ffff, 0x20002b7f, 0                      , 0,
18484        0x0                 },        /* POOL32Axf_5_group0~*(21) */
18485     { reserved_block      , 0                   , 0   , 32,
18486        0xfc00ffff, 0x20002d7f, 0                      , 0,
18487        0x0                 },        /* POOL32Axf_5_group0~*(22) */
18488     { reserved_block      , 0                   , 0   , 32,
18489        0xfc00ffff, 0x20002f7f, 0                      , 0,
18490        0x0                 },        /* POOL32Axf_5_group0~*(23) */
18491     { instruction         , 0                   , 0   , 32,
18492        0xfc00ffff, 0x2000317f, &NMD::TLBGWR           , 0,
18493        CP0_ | VZ_ | TLB_   },        /* TLBGWR */
18494     { instruction         , 0                   , 0   , 32,
18495        0xfc00ffff, 0x2000337f, &NMD::TLBWR            , 0,
18496        CP0_ | TLB_         },        /* TLBWR */
18497     { reserved_block      , 0                   , 0   , 32,
18498        0xfc00ffff, 0x2000357f, 0                      , 0,
18499        0x0                 },        /* POOL32Axf_5_group0~*(26) */
18500     { reserved_block      , 0                   , 0   , 32,
18501        0xfc00ffff, 0x2000377f, 0                      , 0,
18502        0x0                 },        /* POOL32Axf_5_group0~*(27) */
18503     { reserved_block      , 0                   , 0   , 32,
18504        0xfc00ffff, 0x2000397f, 0                      , 0,
18505        0x0                 },        /* POOL32Axf_5_group0~*(28) */
18506     { reserved_block      , 0                   , 0   , 32,
18507        0xfc00ffff, 0x20003b7f, 0                      , 0,
18508        0x0                 },        /* POOL32Axf_5_group0~*(29) */
18509     { reserved_block      , 0                   , 0   , 32,
18510        0xfc00ffff, 0x20003d7f, 0                      , 0,
18511        0x0                 },        /* POOL32Axf_5_group0~*(30) */
18512     { reserved_block      , 0                   , 0   , 32,
18513        0xfc00ffff, 0x20003f7f, 0                      , 0,
18514        0x0                 },        /* POOL32Axf_5_group0~*(31) */
18515 };
18516
18517
18518 NMD::Pool NMD::POOL32Axf_5_group1[32] = {
18519     { reserved_block      , 0                   , 0   , 32,
18520        0xfc00ffff, 0x2000417f, 0                      , 0,
18521        0x0                 },        /* POOL32Axf_5_group1~*(0) */
18522     { reserved_block      , 0                   , 0   , 32,
18523        0xfc00ffff, 0x2000437f, 0                      , 0,
18524        0x0                 },        /* POOL32Axf_5_group1~*(1) */
18525     { reserved_block      , 0                   , 0   , 32,
18526        0xfc00ffff, 0x2000457f, 0                      , 0,
18527        0x0                 },        /* POOL32Axf_5_group1~*(2) */
18528     { instruction         , 0                   , 0   , 32,
18529        0xfc00ffff, 0x2000477f, &NMD::DI               , 0,
18530        0x0                 },        /* DI */
18531     { reserved_block      , 0                   , 0   , 32,
18532        0xfc00ffff, 0x2000497f, 0                      , 0,
18533        0x0                 },        /* POOL32Axf_5_group1~*(4) */
18534     { reserved_block      , 0                   , 0   , 32,
18535        0xfc00ffff, 0x20004b7f, 0                      , 0,
18536        0x0                 },        /* POOL32Axf_5_group1~*(5) */
18537     { reserved_block      , 0                   , 0   , 32,
18538        0xfc00ffff, 0x20004d7f, 0                      , 0,
18539        0x0                 },        /* POOL32Axf_5_group1~*(6) */
18540     { reserved_block      , 0                   , 0   , 32,
18541        0xfc00ffff, 0x20004f7f, 0                      , 0,
18542        0x0                 },        /* POOL32Axf_5_group1~*(7) */
18543     { reserved_block      , 0                   , 0   , 32,
18544        0xfc00ffff, 0x2000517f, 0                      , 0,
18545        0x0                 },        /* POOL32Axf_5_group1~*(8) */
18546     { reserved_block      , 0                   , 0   , 32,
18547        0xfc00ffff, 0x2000537f, 0                      , 0,
18548        0x0                 },        /* POOL32Axf_5_group1~*(9) */
18549     { reserved_block      , 0                   , 0   , 32,
18550        0xfc00ffff, 0x2000557f, 0                      , 0,
18551        0x0                 },        /* POOL32Axf_5_group1~*(10) */
18552     { instruction         , 0                   , 0   , 32,
18553        0xfc00ffff, 0x2000577f, &NMD::EI               , 0,
18554        0x0                 },        /* EI */
18555     { reserved_block      , 0                   , 0   , 32,
18556        0xfc00ffff, 0x2000597f, 0                      , 0,
18557        0x0                 },        /* POOL32Axf_5_group1~*(12) */
18558     { reserved_block      , 0                   , 0   , 32,
18559        0xfc00ffff, 0x20005b7f, 0                      , 0,
18560        0x0                 },        /* POOL32Axf_5_group1~*(13) */
18561     { reserved_block      , 0                   , 0   , 32,
18562        0xfc00ffff, 0x20005d7f, 0                      , 0,
18563        0x0                 },        /* POOL32Axf_5_group1~*(14) */
18564     { reserved_block      , 0                   , 0   , 32,
18565        0xfc00ffff, 0x20005f7f, 0                      , 0,
18566        0x0                 },        /* POOL32Axf_5_group1~*(15) */
18567     { reserved_block      , 0                   , 0   , 32,
18568        0xfc00ffff, 0x2000617f, 0                      , 0,
18569        0x0                 },        /* POOL32Axf_5_group1~*(16) */
18570     { reserved_block      , 0                   , 0   , 32,
18571        0xfc00ffff, 0x2000637f, 0                      , 0,
18572        0x0                 },        /* POOL32Axf_5_group1~*(17) */
18573     { reserved_block      , 0                   , 0   , 32,
18574        0xfc00ffff, 0x2000657f, 0                      , 0,
18575        0x0                 },        /* POOL32Axf_5_group1~*(18) */
18576     { reserved_block      , 0                   , 0   , 32,
18577        0xfc00ffff, 0x2000677f, 0                      , 0,
18578        0x0                 },        /* POOL32Axf_5_group1~*(19) */
18579     { reserved_block      , 0                   , 0   , 32,
18580        0xfc00ffff, 0x2000697f, 0                      , 0,
18581        0x0                 },        /* POOL32Axf_5_group1~*(20) */
18582     { reserved_block      , 0                   , 0   , 32,
18583        0xfc00ffff, 0x20006b7f, 0                      , 0,
18584        0x0                 },        /* POOL32Axf_5_group1~*(21) */
18585     { reserved_block      , 0                   , 0   , 32,
18586        0xfc00ffff, 0x20006d7f, 0                      , 0,
18587        0x0                 },        /* POOL32Axf_5_group1~*(22) */
18588     { reserved_block      , 0                   , 0   , 32,
18589        0xfc00ffff, 0x20006f7f, 0                      , 0,
18590        0x0                 },        /* POOL32Axf_5_group1~*(23) */
18591     { reserved_block      , 0                   , 0   , 32,
18592        0xfc00ffff, 0x2000717f, 0                      , 0,
18593        0x0                 },        /* POOL32Axf_5_group1~*(24) */
18594     { reserved_block      , 0                   , 0   , 32,
18595        0xfc00ffff, 0x2000737f, 0                      , 0,
18596        0x0                 },        /* POOL32Axf_5_group1~*(25) */
18597     { reserved_block      , 0                   , 0   , 32,
18598        0xfc00ffff, 0x2000757f, 0                      , 0,
18599        0x0                 },        /* POOL32Axf_5_group1~*(26) */
18600     { reserved_block      , 0                   , 0   , 32,
18601        0xfc00ffff, 0x2000777f, 0                      , 0,
18602        0x0                 },        /* POOL32Axf_5_group1~*(27) */
18603     { reserved_block      , 0                   , 0   , 32,
18604        0xfc00ffff, 0x2000797f, 0                      , 0,
18605        0x0                 },        /* POOL32Axf_5_group1~*(28) */
18606     { reserved_block      , 0                   , 0   , 32,
18607        0xfc00ffff, 0x20007b7f, 0                      , 0,
18608        0x0                 },        /* POOL32Axf_5_group1~*(29) */
18609     { reserved_block      , 0                   , 0   , 32,
18610        0xfc00ffff, 0x20007d7f, 0                      , 0,
18611        0x0                 },        /* POOL32Axf_5_group1~*(30) */
18612     { reserved_block      , 0                   , 0   , 32,
18613        0xfc00ffff, 0x20007f7f, 0                      , 0,
18614        0x0                 },        /* POOL32Axf_5_group1~*(31) */
18615 };
18616
18617
18618 NMD::Pool NMD::ERETx[2] = {
18619     { instruction         , 0                   , 0   , 32,
18620        0xfc01ffff, 0x2000f37f, &NMD::ERET             , 0,
18621        0x0                 },        /* ERET */
18622     { instruction         , 0                   , 0   , 32,
18623        0xfc01ffff, 0x2001f37f, &NMD::ERETNC           , 0,
18624        0x0                 },        /* ERETNC */
18625 };
18626
18627
18628 NMD::Pool NMD::POOL32Axf_5_group3[32] = {
18629     { reserved_block      , 0                   , 0   , 32,
18630        0xfc00ffff, 0x2000c17f, 0                      , 0,
18631        0x0                 },        /* POOL32Axf_5_group3~*(0) */
18632     { instruction         , 0                   , 0   , 32,
18633        0xfc00ffff, 0x2000c37f, &NMD::WAIT             , 0,
18634        0x0                 },        /* WAIT */
18635     { reserved_block      , 0                   , 0   , 32,
18636        0xfc00ffff, 0x2000c57f, 0                      , 0,
18637        0x0                 },        /* POOL32Axf_5_group3~*(2) */
18638     { reserved_block      , 0                   , 0   , 32,
18639        0xfc00ffff, 0x2000c77f, 0                      , 0,
18640        0x0                 },        /* POOL32Axf_5_group3~*(3) */
18641     { reserved_block      , 0                   , 0   , 32,
18642        0xfc00ffff, 0x2000c97f, 0                      , 0,
18643        0x0                 },        /* POOL32Axf_5_group3~*(4) */
18644     { reserved_block      , 0                   , 0   , 32,
18645        0xfc00ffff, 0x2000cb7f, 0                      , 0,
18646        0x0                 },        /* POOL32Axf_5_group3~*(5) */
18647     { reserved_block      , 0                   , 0   , 32,
18648        0xfc00ffff, 0x2000cd7f, 0                      , 0,
18649        0x0                 },        /* POOL32Axf_5_group3~*(6) */
18650     { reserved_block      , 0                   , 0   , 32,
18651        0xfc00ffff, 0x2000cf7f, 0                      , 0,
18652        0x0                 },        /* POOL32Axf_5_group3~*(7) */
18653     { reserved_block      , 0                   , 0   , 32,
18654        0xfc00ffff, 0x2000d17f, 0                      , 0,
18655        0x0                 },        /* POOL32Axf_5_group3~*(8) */
18656     { instruction         , 0                   , 0   , 32,
18657        0xfc00ffff, 0x2000d37f, &NMD::IRET             , 0,
18658        MCU_                },        /* IRET */
18659     { reserved_block      , 0                   , 0   , 32,
18660        0xfc00ffff, 0x2000d57f, 0                      , 0,
18661        0x0                 },        /* POOL32Axf_5_group3~*(10) */
18662     { reserved_block      , 0                   , 0   , 32,
18663        0xfc00ffff, 0x2000d77f, 0                      , 0,
18664        0x0                 },        /* POOL32Axf_5_group3~*(11) */
18665     { reserved_block      , 0                   , 0   , 32,
18666        0xfc00ffff, 0x2000d97f, 0                      , 0,
18667        0x0                 },        /* POOL32Axf_5_group3~*(12) */
18668     { reserved_block      , 0                   , 0   , 32,
18669        0xfc00ffff, 0x2000db7f, 0                      , 0,
18670        0x0                 },        /* POOL32Axf_5_group3~*(13) */
18671     { reserved_block      , 0                   , 0   , 32,
18672        0xfc00ffff, 0x2000dd7f, 0                      , 0,
18673        0x0                 },        /* POOL32Axf_5_group3~*(14) */
18674     { reserved_block      , 0                   , 0   , 32,
18675        0xfc00ffff, 0x2000df7f, 0                      , 0,
18676        0x0                 },        /* POOL32Axf_5_group3~*(15) */
18677     { instruction         , 0                   , 0   , 32,
18678        0xfc00ffff, 0x2000e17f, &NMD::RDPGPR           , 0,
18679        CP0_                },        /* RDPGPR */
18680     { instruction         , 0                   , 0   , 32,
18681        0xfc00ffff, 0x2000e37f, &NMD::DERET            , 0,
18682        EJTAG_              },        /* DERET */
18683     { reserved_block      , 0                   , 0   , 32,
18684        0xfc00ffff, 0x2000e57f, 0                      , 0,
18685        0x0                 },        /* POOL32Axf_5_group3~*(18) */
18686     { reserved_block      , 0                   , 0   , 32,
18687        0xfc00ffff, 0x2000e77f, 0                      , 0,
18688        0x0                 },        /* POOL32Axf_5_group3~*(19) */
18689     { reserved_block      , 0                   , 0   , 32,
18690        0xfc00ffff, 0x2000e97f, 0                      , 0,
18691        0x0                 },        /* POOL32Axf_5_group3~*(20) */
18692     { reserved_block      , 0                   , 0   , 32,
18693        0xfc00ffff, 0x2000eb7f, 0                      , 0,
18694        0x0                 },        /* POOL32Axf_5_group3~*(21) */
18695     { reserved_block      , 0                   , 0   , 32,
18696        0xfc00ffff, 0x2000ed7f, 0                      , 0,
18697        0x0                 },        /* POOL32Axf_5_group3~*(22) */
18698     { reserved_block      , 0                   , 0   , 32,
18699        0xfc00ffff, 0x2000ef7f, 0                      , 0,
18700        0x0                 },        /* POOL32Axf_5_group3~*(23) */
18701     { instruction         , 0                   , 0   , 32,
18702        0xfc00ffff, 0x2000f17f, &NMD::WRPGPR           , 0,
18703        CP0_                },        /* WRPGPR */
18704     { pool                , ERETx               , 2   , 32,
18705        0xfc00ffff, 0x2000f37f, 0                      , 0,
18706        0x0                 },        /* ERETx */
18707     { reserved_block      , 0                   , 0   , 32,
18708        0xfc00ffff, 0x2000f57f, 0                      , 0,
18709        0x0                 },        /* POOL32Axf_5_group3~*(26) */
18710     { reserved_block      , 0                   , 0   , 32,
18711        0xfc00ffff, 0x2000f77f, 0                      , 0,
18712        0x0                 },        /* POOL32Axf_5_group3~*(27) */
18713     { reserved_block      , 0                   , 0   , 32,
18714        0xfc00ffff, 0x2000f97f, 0                      , 0,
18715        0x0                 },        /* POOL32Axf_5_group3~*(28) */
18716     { reserved_block      , 0                   , 0   , 32,
18717        0xfc00ffff, 0x2000fb7f, 0                      , 0,
18718        0x0                 },        /* POOL32Axf_5_group3~*(29) */
18719     { reserved_block      , 0                   , 0   , 32,
18720        0xfc00ffff, 0x2000fd7f, 0                      , 0,
18721        0x0                 },        /* POOL32Axf_5_group3~*(30) */
18722     { reserved_block      , 0                   , 0   , 32,
18723        0xfc00ffff, 0x2000ff7f, 0                      , 0,
18724        0x0                 },        /* POOL32Axf_5_group3~*(31) */
18725 };
18726
18727
18728 NMD::Pool NMD::POOL32Axf_5[4] = {
18729     { pool                , POOL32Axf_5_group0  , 32  , 32,
18730        0xfc00c1ff, 0x2000017f, 0                      , 0,
18731        0x0                 },        /* POOL32Axf_5_group0 */
18732     { pool                , POOL32Axf_5_group1  , 32  , 32,
18733        0xfc00c1ff, 0x2000417f, 0                      , 0,
18734        0x0                 },        /* POOL32Axf_5_group1 */
18735     { reserved_block      , 0                   , 0   , 32,
18736        0xfc00c1ff, 0x2000817f, 0                      , 0,
18737        0x0                 },        /* POOL32Axf_5~*(2) */
18738     { pool                , POOL32Axf_5_group3  , 32  , 32,
18739        0xfc00c1ff, 0x2000c17f, 0                      , 0,
18740        0x0                 },        /* POOL32Axf_5_group3 */
18741 };
18742
18743
18744 NMD::Pool NMD::SHRA__R__QB[2] = {
18745     { instruction         , 0                   , 0   , 32,
18746        0xfc001fff, 0x200001ff, &NMD::SHRA_QB          , 0,
18747        DSP_                },        /* SHRA.QB */
18748     { instruction         , 0                   , 0   , 32,
18749        0xfc001fff, 0x200011ff, &NMD::SHRA_R_QB        , 0,
18750        DSP_                },        /* SHRA_R.QB */
18751 };
18752
18753
18754 NMD::Pool NMD::POOL32Axf_7[8] = {
18755     { pool                , SHRA__R__QB         , 2   , 32,
18756        0xfc000fff, 0x200001ff, 0                      , 0,
18757        0x0                 },        /* SHRA[_R].QB */
18758     { instruction         , 0                   , 0   , 32,
18759        0xfc000fff, 0x200003ff, &NMD::SHRL_PH          , 0,
18760        DSP_                },        /* SHRL.PH */
18761     { instruction         , 0                   , 0   , 32,
18762        0xfc000fff, 0x200005ff, &NMD::REPL_QB          , 0,
18763        DSP_                },        /* REPL.QB */
18764     { reserved_block      , 0                   , 0   , 32,
18765        0xfc000fff, 0x200007ff, 0                      , 0,
18766        0x0                 },        /* POOL32Axf_7~*(3) */
18767     { reserved_block      , 0                   , 0   , 32,
18768        0xfc000fff, 0x200009ff, 0                      , 0,
18769        0x0                 },        /* POOL32Axf_7~*(4) */
18770     { reserved_block      , 0                   , 0   , 32,
18771        0xfc000fff, 0x20000bff, 0                      , 0,
18772        0x0                 },        /* POOL32Axf_7~*(5) */
18773     { reserved_block      , 0                   , 0   , 32,
18774        0xfc000fff, 0x20000dff, 0                      , 0,
18775        0x0                 },        /* POOL32Axf_7~*(6) */
18776     { reserved_block      , 0                   , 0   , 32,
18777        0xfc000fff, 0x20000fff, 0                      , 0,
18778        0x0                 },        /* POOL32Axf_7~*(7) */
18779 };
18780
18781
18782 NMD::Pool NMD::POOL32Axf[8] = {
18783     { reserved_block      , 0                   , 0   , 32,
18784        0xfc0001ff, 0x2000003f, 0                      , 0,
18785        0x0                 },        /* POOL32Axf~*(0) */
18786     { pool                , POOL32Axf_1         , 8   , 32,
18787        0xfc0001ff, 0x2000007f, 0                      , 0,
18788        0x0                 },        /* POOL32Axf_1 */
18789     { pool                , POOL32Axf_2         , 4   , 32,
18790        0xfc0001ff, 0x200000bf, 0                      , 0,
18791        0x0                 },        /* POOL32Axf_2 */
18792     { reserved_block      , 0                   , 0   , 32,
18793        0xfc0001ff, 0x200000ff, 0                      , 0,
18794        0x0                 },        /* POOL32Axf~*(3) */
18795     { pool                , POOL32Axf_4         , 128 , 32,
18796        0xfc0001ff, 0x2000013f, 0                      , 0,
18797        0x0                 },        /* POOL32Axf_4 */
18798     { pool                , POOL32Axf_5         , 4   , 32,
18799        0xfc0001ff, 0x2000017f, 0                      , 0,
18800        0x0                 },        /* POOL32Axf_5 */
18801     { reserved_block      , 0                   , 0   , 32,
18802        0xfc0001ff, 0x200001bf, 0                      , 0,
18803        0x0                 },        /* POOL32Axf~*(6) */
18804     { pool                , POOL32Axf_7         , 8   , 32,
18805        0xfc0001ff, 0x200001ff, 0                      , 0,
18806        0x0                 },        /* POOL32Axf_7 */
18807 };
18808
18809
18810 NMD::Pool NMD::_POOL32A7[8] = {
18811     { pool                , P_LSX               , 2   , 32,
18812        0xfc00003f, 0x20000007, 0                      , 0,
18813        0x0                 },        /* P.LSX */
18814     { instruction         , 0                   , 0   , 32,
18815        0xfc00003f, 0x2000000f, &NMD::LSA              , 0,
18816        0x0                 },        /* LSA */
18817     { reserved_block      , 0                   , 0   , 32,
18818        0xfc00003f, 0x20000017, 0                      , 0,
18819        0x0                 },        /* _POOL32A7~*(2) */
18820     { instruction         , 0                   , 0   , 32,
18821        0xfc00003f, 0x2000001f, &NMD::EXTW             , 0,
18822        0x0                 },        /* EXTW */
18823     { reserved_block      , 0                   , 0   , 32,
18824        0xfc00003f, 0x20000027, 0                      , 0,
18825        0x0                 },        /* _POOL32A7~*(4) */
18826     { reserved_block      , 0                   , 0   , 32,
18827        0xfc00003f, 0x2000002f, 0                      , 0,
18828        0x0                 },        /* _POOL32A7~*(5) */
18829     { reserved_block      , 0                   , 0   , 32,
18830        0xfc00003f, 0x20000037, 0                      , 0,
18831        0x0                 },        /* _POOL32A7~*(6) */
18832     { pool                , POOL32Axf           , 8   , 32,
18833        0xfc00003f, 0x2000003f, 0                      , 0,
18834        0x0                 },        /* POOL32Axf */
18835 };
18836
18837
18838 NMD::Pool NMD::P32A[8] = {
18839     { pool                , _POOL32A0           , 128 , 32,
18840        0xfc000007, 0x20000000, 0                      , 0,
18841        0x0                 },        /* _POOL32A0 */
18842     { instruction         , 0                   , 0   , 32,
18843        0xfc000007, 0x20000001, &NMD::SPECIAL2         , 0,
18844        UDI_                },        /* SPECIAL2 */
18845     { instruction         , 0                   , 0   , 32,
18846        0xfc000007, 0x20000002, &NMD::COP2_1           , 0,
18847        CP2_                },        /* COP2_1 */
18848     { instruction         , 0                   , 0   , 32,
18849        0xfc000007, 0x20000003, &NMD::UDI              , 0,
18850        UDI_                },        /* UDI */
18851     { reserved_block      , 0                   , 0   , 32,
18852        0xfc000007, 0x20000004, 0                      , 0,
18853        0x0                 },        /* P32A~*(4) */
18854     { pool                , _POOL32A5           , 128 , 32,
18855        0xfc000007, 0x20000005, 0                      , 0,
18856        0x0                 },        /* _POOL32A5 */
18857     { reserved_block      , 0                   , 0   , 32,
18858        0xfc000007, 0x20000006, 0                      , 0,
18859        0x0                 },        /* P32A~*(6) */
18860     { pool                , _POOL32A7           , 8   , 32,
18861        0xfc000007, 0x20000007, 0                      , 0,
18862        0x0                 },        /* _POOL32A7 */
18863 };
18864
18865
18866 NMD::Pool NMD::P_GP_D[2] = {
18867     { instruction         , 0                   , 0   , 32,
18868        0xfc000007, 0x40000001, &NMD::LD_GP_           , 0,
18869        MIPS64_             },        /* LD[GP] */
18870     { instruction         , 0                   , 0   , 32,
18871        0xfc000007, 0x40000005, &NMD::SD_GP_           , 0,
18872        MIPS64_             },        /* SD[GP] */
18873 };
18874
18875
18876 NMD::Pool NMD::P_GP_W[4] = {
18877     { instruction         , 0                   , 0   , 32,
18878        0xfc000003, 0x40000000, &NMD::ADDIU_GP_W_      , 0,
18879        0x0                 },        /* ADDIU[GP.W] */
18880     { pool                , P_GP_D              , 2   , 32,
18881        0xfc000003, 0x40000001, 0                      , 0,
18882        0x0                 },        /* P.GP.D */
18883     { instruction         , 0                   , 0   , 32,
18884        0xfc000003, 0x40000002, &NMD::LW_GP_           , 0,
18885        0x0                 },        /* LW[GP] */
18886     { instruction         , 0                   , 0   , 32,
18887        0xfc000003, 0x40000003, &NMD::SW_GP_           , 0,
18888        0x0                 },        /* SW[GP] */
18889 };
18890
18891
18892 NMD::Pool NMD::POOL48I[32] = {
18893     { instruction         , 0                   , 0   , 48,
18894        0xfc1f00000000ull, 0x600000000000ull, &NMD::LI_48_           , 0,
18895        XMMS_               },        /* LI[48] */
18896     { instruction         , 0                   , 0   , 48,
18897        0xfc1f00000000ull, 0x600100000000ull, &NMD::ADDIU_48_        , 0,
18898        XMMS_               },        /* ADDIU[48] */
18899     { instruction         , 0                   , 0   , 48,
18900        0xfc1f00000000ull, 0x600200000000ull, &NMD::ADDIU_GP48_      , 0,
18901        XMMS_               },        /* ADDIU[GP48] */
18902     { instruction         , 0                   , 0   , 48,
18903        0xfc1f00000000ull, 0x600300000000ull, &NMD::ADDIUPC_48_      , 0,
18904        XMMS_               },        /* ADDIUPC[48] */
18905     { reserved_block      , 0                   , 0   , 48,
18906        0xfc1f00000000ull, 0x600400000000ull, 0                      , 0,
18907        0x0                 },        /* POOL48I~*(4) */
18908     { reserved_block      , 0                   , 0   , 48,
18909        0xfc1f00000000ull, 0x600500000000ull, 0                      , 0,
18910        0x0                 },        /* POOL48I~*(5) */
18911     { reserved_block      , 0                   , 0   , 48,
18912        0xfc1f00000000ull, 0x600600000000ull, 0                      , 0,
18913        0x0                 },        /* POOL48I~*(6) */
18914     { reserved_block      , 0                   , 0   , 48,
18915        0xfc1f00000000ull, 0x600700000000ull, 0                      , 0,
18916        0x0                 },        /* POOL48I~*(7) */
18917     { reserved_block      , 0                   , 0   , 48,
18918        0xfc1f00000000ull, 0x600800000000ull, 0                      , 0,
18919        0x0                 },        /* POOL48I~*(8) */
18920     { reserved_block      , 0                   , 0   , 48,
18921        0xfc1f00000000ull, 0x600900000000ull, 0                      , 0,
18922        0x0                 },        /* POOL48I~*(9) */
18923     { reserved_block      , 0                   , 0   , 48,
18924        0xfc1f00000000ull, 0x600a00000000ull, 0                      , 0,
18925        0x0                 },        /* POOL48I~*(10) */
18926     { instruction         , 0                   , 0   , 48,
18927        0xfc1f00000000ull, 0x600b00000000ull, &NMD::LWPC_48_         , 0,
18928        XMMS_               },        /* LWPC[48] */
18929     { reserved_block      , 0                   , 0   , 48,
18930        0xfc1f00000000ull, 0x600c00000000ull, 0                      , 0,
18931        0x0                 },        /* POOL48I~*(12) */
18932     { reserved_block      , 0                   , 0   , 48,
18933        0xfc1f00000000ull, 0x600d00000000ull, 0                      , 0,
18934        0x0                 },        /* POOL48I~*(13) */
18935     { reserved_block      , 0                   , 0   , 48,
18936        0xfc1f00000000ull, 0x600e00000000ull, 0                      , 0,
18937        0x0                 },        /* POOL48I~*(14) */
18938     { instruction         , 0                   , 0   , 48,
18939        0xfc1f00000000ull, 0x600f00000000ull, &NMD::SWPC_48_         , 0,
18940        XMMS_               },        /* SWPC[48] */
18941     { reserved_block      , 0                   , 0   , 48,
18942        0xfc1f00000000ull, 0x601000000000ull, 0                      , 0,
18943        0x0                 },        /* POOL48I~*(16) */
18944     { instruction         , 0                   , 0   , 48,
18945        0xfc1f00000000ull, 0x601100000000ull, &NMD::DADDIU_48_       , 0,
18946        MIPS64_             },        /* DADDIU[48] */
18947     { reserved_block      , 0                   , 0   , 48,
18948        0xfc1f00000000ull, 0x601200000000ull, 0                      , 0,
18949        0x0                 },        /* POOL48I~*(18) */
18950     { reserved_block      , 0                   , 0   , 48,
18951        0xfc1f00000000ull, 0x601300000000ull, 0                      , 0,
18952        0x0                 },        /* POOL48I~*(19) */
18953     { instruction         , 0                   , 0   , 48,
18954        0xfc1f00000000ull, 0x601400000000ull, &NMD::DLUI_48_         , 0,
18955        MIPS64_             },        /* DLUI[48] */
18956     { reserved_block      , 0                   , 0   , 48,
18957        0xfc1f00000000ull, 0x601500000000ull, 0                      , 0,
18958        0x0                 },        /* POOL48I~*(21) */
18959     { reserved_block      , 0                   , 0   , 48,
18960        0xfc1f00000000ull, 0x601600000000ull, 0                      , 0,
18961        0x0                 },        /* POOL48I~*(22) */
18962     { reserved_block      , 0                   , 0   , 48,
18963        0xfc1f00000000ull, 0x601700000000ull, 0                      , 0,
18964        0x0                 },        /* POOL48I~*(23) */
18965     { reserved_block      , 0                   , 0   , 48,
18966        0xfc1f00000000ull, 0x601800000000ull, 0                      , 0,
18967        0x0                 },        /* POOL48I~*(24) */
18968     { reserved_block      , 0                   , 0   , 48,
18969        0xfc1f00000000ull, 0x601900000000ull, 0                      , 0,
18970        0x0                 },        /* POOL48I~*(25) */
18971     { reserved_block      , 0                   , 0   , 48,
18972        0xfc1f00000000ull, 0x601a00000000ull, 0                      , 0,
18973        0x0                 },        /* POOL48I~*(26) */
18974     { instruction         , 0                   , 0   , 48,
18975        0xfc1f00000000ull, 0x601b00000000ull, &NMD::LDPC_48_         , 0,
18976        MIPS64_             },        /* LDPC[48] */
18977     { reserved_block      , 0                   , 0   , 48,
18978        0xfc1f00000000ull, 0x601c00000000ull, 0                      , 0,
18979        0x0                 },        /* POOL48I~*(28) */
18980     { reserved_block      , 0                   , 0   , 48,
18981        0xfc1f00000000ull, 0x601d00000000ull, 0                      , 0,
18982        0x0                 },        /* POOL48I~*(29) */
18983     { reserved_block      , 0                   , 0   , 48,
18984        0xfc1f00000000ull, 0x601e00000000ull, 0                      , 0,
18985        0x0                 },        /* POOL48I~*(30) */
18986     { instruction         , 0                   , 0   , 48,
18987        0xfc1f00000000ull, 0x601f00000000ull, &NMD::SDPC_48_         , 0,
18988        MIPS64_             },        /* SDPC[48] */
18989 };
18990
18991
18992 NMD::Pool NMD::PP_SR[4] = {
18993     { instruction         , 0                   , 0   , 32,
18994        0xfc10f003, 0x80003000, &NMD::SAVE_32_         , 0,
18995        0x0                 },        /* SAVE[32] */
18996     { reserved_block      , 0                   , 0   , 32,
18997        0xfc10f003, 0x80003001, 0                      , 0,
18998        0x0                 },        /* PP.SR~*(1) */
18999     { instruction         , 0                   , 0   , 32,
19000        0xfc10f003, 0x80003002, &NMD::RESTORE_32_      , 0,
19001        0x0                 },        /* RESTORE[32] */
19002     { return_instruction  , 0                   , 0   , 32,
19003        0xfc10f003, 0x80003003, &NMD::RESTORE_JRC_32_  , 0,
19004        0x0                 },        /* RESTORE.JRC[32] */
19005 };
19006
19007
19008 NMD::Pool NMD::P_SR_F[8] = {
19009     { instruction         , 0                   , 0   , 32,
19010        0xfc10f007, 0x80103000, &NMD::SAVEF            , 0,
19011        CP1_                },        /* SAVEF */
19012     { instruction         , 0                   , 0   , 32,
19013        0xfc10f007, 0x80103001, &NMD::RESTOREF         , 0,
19014        CP1_                },        /* RESTOREF */
19015     { reserved_block      , 0                   , 0   , 32,
19016        0xfc10f007, 0x80103002, 0                      , 0,
19017        0x0                 },        /* P.SR.F~*(2) */
19018     { reserved_block      , 0                   , 0   , 32,
19019        0xfc10f007, 0x80103003, 0                      , 0,
19020        0x0                 },        /* P.SR.F~*(3) */
19021     { reserved_block      , 0                   , 0   , 32,
19022        0xfc10f007, 0x80103004, 0                      , 0,
19023        0x0                 },        /* P.SR.F~*(4) */
19024     { reserved_block      , 0                   , 0   , 32,
19025        0xfc10f007, 0x80103005, 0                      , 0,
19026        0x0                 },        /* P.SR.F~*(5) */
19027     { reserved_block      , 0                   , 0   , 32,
19028        0xfc10f007, 0x80103006, 0                      , 0,
19029        0x0                 },        /* P.SR.F~*(6) */
19030     { reserved_block      , 0                   , 0   , 32,
19031        0xfc10f007, 0x80103007, 0                      , 0,
19032        0x0                 },        /* P.SR.F~*(7) */
19033 };
19034
19035
19036 NMD::Pool NMD::P_SR[2] = {
19037     { pool                , PP_SR               , 4   , 32,
19038        0xfc10f000, 0x80003000, 0                      , 0,
19039        0x0                 },        /* PP.SR */
19040     { pool                , P_SR_F              , 8   , 32,
19041        0xfc10f000, 0x80103000, 0                      , 0,
19042        0x0                 },        /* P.SR.F */
19043 };
19044
19045
19046 NMD::Pool NMD::P_SLL[5] = {
19047     { instruction         , 0                   , 0   , 32,
19048        0xffe0f1ff, 0x8000c000, &NMD::NOP_32_          , 0,
19049        0x0                 },        /* NOP[32] */
19050     { instruction         , 0                   , 0   , 32,
19051        0xffe0f1ff, 0x8000c003, &NMD::EHB              , 0,
19052        0x0                 },        /* EHB */
19053     { instruction         , 0                   , 0   , 32,
19054        0xffe0f1ff, 0x8000c005, &NMD::PAUSE            , 0,
19055        0x0                 },        /* PAUSE */
19056     { instruction         , 0                   , 0   , 32,
19057        0xffe0f1ff, 0x8000c006, &NMD::SYNC             , 0,
19058        0x0                 },        /* SYNC */
19059     { instruction         , 0                   , 0   , 32,
19060        0xfc00f1e0, 0x8000c000, &NMD::SLL_32_          , 0,
19061        0x0                 },        /* SLL[32] */
19062 };
19063
19064
19065 NMD::Pool NMD::P_SHIFT[16] = {
19066     { pool                , P_SLL               , 5   , 32,
19067        0xfc00f1e0, 0x8000c000, 0                      , 0,
19068        0x0                 },        /* P.SLL */
19069     { reserved_block      , 0                   , 0   , 32,
19070        0xfc00f1e0, 0x8000c020, 0                      , 0,
19071        0x0                 },        /* P.SHIFT~*(1) */
19072     { instruction         , 0                   , 0   , 32,
19073        0xfc00f1e0, 0x8000c040, &NMD::SRL_32_          , 0,
19074        0x0                 },        /* SRL[32] */
19075     { reserved_block      , 0                   , 0   , 32,
19076        0xfc00f1e0, 0x8000c060, 0                      , 0,
19077        0x0                 },        /* P.SHIFT~*(3) */
19078     { instruction         , 0                   , 0   , 32,
19079        0xfc00f1e0, 0x8000c080, &NMD::SRA              , 0,
19080        0x0                 },        /* SRA */
19081     { reserved_block      , 0                   , 0   , 32,
19082        0xfc00f1e0, 0x8000c0a0, 0                      , 0,
19083        0x0                 },        /* P.SHIFT~*(5) */
19084     { instruction         , 0                   , 0   , 32,
19085        0xfc00f1e0, 0x8000c0c0, &NMD::ROTR             , 0,
19086        0x0                 },        /* ROTR */
19087     { reserved_block      , 0                   , 0   , 32,
19088        0xfc00f1e0, 0x8000c0e0, 0                      , 0,
19089        0x0                 },        /* P.SHIFT~*(7) */
19090     { instruction         , 0                   , 0   , 32,
19091        0xfc00f1e0, 0x8000c100, &NMD::DSLL             , 0,
19092        MIPS64_             },        /* DSLL */
19093     { instruction         , 0                   , 0   , 32,
19094        0xfc00f1e0, 0x8000c120, &NMD::DSLL32           , 0,
19095        MIPS64_             },        /* DSLL32 */
19096     { instruction         , 0                   , 0   , 32,
19097        0xfc00f1e0, 0x8000c140, &NMD::DSRL             , 0,
19098        MIPS64_             },        /* DSRL */
19099     { instruction         , 0                   , 0   , 32,
19100        0xfc00f1e0, 0x8000c160, &NMD::DSRL32           , 0,
19101        MIPS64_             },        /* DSRL32 */
19102     { instruction         , 0                   , 0   , 32,
19103        0xfc00f1e0, 0x8000c180, &NMD::DSRA             , 0,
19104        MIPS64_             },        /* DSRA */
19105     { instruction         , 0                   , 0   , 32,
19106        0xfc00f1e0, 0x8000c1a0, &NMD::DSRA32           , 0,
19107        MIPS64_             },        /* DSRA32 */
19108     { instruction         , 0                   , 0   , 32,
19109        0xfc00f1e0, 0x8000c1c0, &NMD::DROTR            , 0,
19110        MIPS64_             },        /* DROTR */
19111     { instruction         , 0                   , 0   , 32,
19112        0xfc00f1e0, 0x8000c1e0, &NMD::DROTR32          , 0,
19113        MIPS64_             },        /* DROTR32 */
19114 };
19115
19116
19117 NMD::Pool NMD::P_ROTX[4] = {
19118     { instruction         , 0                   , 0   , 32,
19119        0xfc00f820, 0x8000d000, &NMD::ROTX             , 0,
19120        XMMS_               },        /* ROTX */
19121     { reserved_block      , 0                   , 0   , 32,
19122        0xfc00f820, 0x8000d020, 0                      , 0,
19123        0x0                 },        /* P.ROTX~*(1) */
19124     { reserved_block      , 0                   , 0   , 32,
19125        0xfc00f820, 0x8000d800, 0                      , 0,
19126        0x0                 },        /* P.ROTX~*(2) */
19127     { reserved_block      , 0                   , 0   , 32,
19128        0xfc00f820, 0x8000d820, 0                      , 0,
19129        0x0                 },        /* P.ROTX~*(3) */
19130 };
19131
19132
19133 NMD::Pool NMD::P_INS[4] = {
19134     { instruction         , 0                   , 0   , 32,
19135        0xfc00f820, 0x8000e000, &NMD::INS              , 0,
19136        XMMS_               },        /* INS */
19137     { instruction         , 0                   , 0   , 32,
19138        0xfc00f820, 0x8000e020, &NMD::DINSU            , 0,
19139        MIPS64_             },        /* DINSU */
19140     { instruction         , 0                   , 0   , 32,
19141        0xfc00f820, 0x8000e800, &NMD::DINSM            , 0,
19142        MIPS64_             },        /* DINSM */
19143     { instruction         , 0                   , 0   , 32,
19144        0xfc00f820, 0x8000e820, &NMD::DINS             , 0,
19145        MIPS64_             },        /* DINS */
19146 };
19147
19148
19149 NMD::Pool NMD::P_EXT[4] = {
19150     { instruction         , 0                   , 0   , 32,
19151        0xfc00f820, 0x8000f000, &NMD::EXT              , 0,
19152        XMMS_               },        /* EXT */
19153     { instruction         , 0                   , 0   , 32,
19154        0xfc00f820, 0x8000f020, &NMD::DEXTU            , 0,
19155        MIPS64_             },        /* DEXTU */
19156     { instruction         , 0                   , 0   , 32,
19157        0xfc00f820, 0x8000f800, &NMD::DEXTM            , 0,
19158        MIPS64_             },        /* DEXTM */
19159     { instruction         , 0                   , 0   , 32,
19160        0xfc00f820, 0x8000f820, &NMD::DEXT             , 0,
19161        MIPS64_             },        /* DEXT */
19162 };
19163
19164
19165 NMD::Pool NMD::P_U12[16] = {
19166     { instruction         , 0                   , 0   , 32,
19167        0xfc00f000, 0x80000000, &NMD::ORI              , 0,
19168        0x0                 },        /* ORI */
19169     { instruction         , 0                   , 0   , 32,
19170        0xfc00f000, 0x80001000, &NMD::XORI             , 0,
19171        0x0                 },        /* XORI */
19172     { instruction         , 0                   , 0   , 32,
19173        0xfc00f000, 0x80002000, &NMD::ANDI_32_         , 0,
19174        0x0                 },        /* ANDI[32] */
19175     { pool                , P_SR                , 2   , 32,
19176        0xfc00f000, 0x80003000, 0                      , 0,
19177        0x0                 },        /* P.SR */
19178     { instruction         , 0                   , 0   , 32,
19179        0xfc00f000, 0x80004000, &NMD::SLTI             , 0,
19180        0x0                 },        /* SLTI */
19181     { instruction         , 0                   , 0   , 32,
19182        0xfc00f000, 0x80005000, &NMD::SLTIU            , 0,
19183        0x0                 },        /* SLTIU */
19184     { instruction         , 0                   , 0   , 32,
19185        0xfc00f000, 0x80006000, &NMD::SEQI             , 0,
19186        0x0                 },        /* SEQI */
19187     { reserved_block      , 0                   , 0   , 32,
19188        0xfc00f000, 0x80007000, 0                      , 0,
19189        0x0                 },        /* P.U12~*(7) */
19190     { instruction         , 0                   , 0   , 32,
19191        0xfc00f000, 0x80008000, &NMD::ADDIU_NEG_       , 0,
19192        0x0                 },        /* ADDIU[NEG] */
19193     { instruction         , 0                   , 0   , 32,
19194        0xfc00f000, 0x80009000, &NMD::DADDIU_U12_      , 0,
19195        MIPS64_             },        /* DADDIU[U12] */
19196     { instruction         , 0                   , 0   , 32,
19197        0xfc00f000, 0x8000a000, &NMD::DADDIU_NEG_      , 0,
19198        MIPS64_             },        /* DADDIU[NEG] */
19199     { instruction         , 0                   , 0   , 32,
19200        0xfc00f000, 0x8000b000, &NMD::DROTX            , 0,
19201        MIPS64_             },        /* DROTX */
19202     { pool                , P_SHIFT             , 16  , 32,
19203        0xfc00f000, 0x8000c000, 0                      , 0,
19204        0x0                 },        /* P.SHIFT */
19205     { pool                , P_ROTX              , 4   , 32,
19206        0xfc00f000, 0x8000d000, 0                      , 0,
19207        0x0                 },        /* P.ROTX */
19208     { pool                , P_INS               , 4   , 32,
19209        0xfc00f000, 0x8000e000, 0                      , 0,
19210        0x0                 },        /* P.INS */
19211     { pool                , P_EXT               , 4   , 32,
19212        0xfc00f000, 0x8000f000, 0                      , 0,
19213        0x0                 },        /* P.EXT */
19214 };
19215
19216
19217 NMD::Pool NMD::RINT_fmt[2] = {
19218     { instruction         , 0                   , 0   , 32,
19219        0xfc0003ff, 0xa0000020, &NMD::RINT_S           , 0,
19220        CP1_                },        /* RINT.S */
19221     { instruction         , 0                   , 0   , 32,
19222        0xfc0003ff, 0xa0000220, &NMD::RINT_D           , 0,
19223        CP1_                },        /* RINT.D */
19224 };
19225
19226
19227 NMD::Pool NMD::ADD_fmt0[2] = {
19228     { instruction         , 0                   , 0   , 32,
19229        0xfc0003ff, 0xa0000030, &NMD::ADD_S            , 0,
19230        CP1_                },        /* ADD.S */
19231     { reserved_block      , 0                   , 0   , 32,
19232        0xfc0003ff, 0xa0000230, 0                      , 0,
19233        CP1_                },        /* ADD.fmt0~*(1) */
19234 };
19235
19236
19237 NMD::Pool NMD::SELEQZ_fmt[2] = {
19238     { instruction         , 0                   , 0   , 32,
19239        0xfc0003ff, 0xa0000038, &NMD::SELEQZ_S         , 0,
19240        CP1_                },        /* SELEQZ.S */
19241     { instruction         , 0                   , 0   , 32,
19242        0xfc0003ff, 0xa0000238, &NMD::SELEQZ_D         , 0,
19243        CP1_                },        /* SELEQZ.D */
19244 };
19245
19246
19247 NMD::Pool NMD::CLASS_fmt[2] = {
19248     { instruction         , 0                   , 0   , 32,
19249        0xfc0003ff, 0xa0000060, &NMD::CLASS_S          , 0,
19250        CP1_                },        /* CLASS.S */
19251     { instruction         , 0                   , 0   , 32,
19252        0xfc0003ff, 0xa0000260, &NMD::CLASS_D          , 0,
19253        CP1_                },        /* CLASS.D */
19254 };
19255
19256
19257 NMD::Pool NMD::SUB_fmt0[2] = {
19258     { instruction         , 0                   , 0   , 32,
19259        0xfc0003ff, 0xa0000070, &NMD::SUB_S            , 0,
19260        CP1_                },        /* SUB.S */
19261     { reserved_block      , 0                   , 0   , 32,
19262        0xfc0003ff, 0xa0000270, 0                      , 0,
19263        CP1_                },        /* SUB.fmt0~*(1) */
19264 };
19265
19266
19267 NMD::Pool NMD::SELNEZ_fmt[2] = {
19268     { instruction         , 0                   , 0   , 32,
19269        0xfc0003ff, 0xa0000078, &NMD::SELNEZ_S         , 0,
19270        CP1_                },        /* SELNEZ.S */
19271     { instruction         , 0                   , 0   , 32,
19272        0xfc0003ff, 0xa0000278, &NMD::SELNEZ_D         , 0,
19273        CP1_                },        /* SELNEZ.D */
19274 };
19275
19276
19277 NMD::Pool NMD::MUL_fmt0[2] = {
19278     { instruction         , 0                   , 0   , 32,
19279        0xfc0003ff, 0xa00000b0, &NMD::MUL_S            , 0,
19280        CP1_                },        /* MUL.S */
19281     { reserved_block      , 0                   , 0   , 32,
19282        0xfc0003ff, 0xa00002b0, 0                      , 0,
19283        CP1_                },        /* MUL.fmt0~*(1) */
19284 };
19285
19286
19287 NMD::Pool NMD::SEL_fmt[2] = {
19288     { instruction         , 0                   , 0   , 32,
19289        0xfc0003ff, 0xa00000b8, &NMD::SEL_S            , 0,
19290        CP1_                },        /* SEL.S */
19291     { instruction         , 0                   , 0   , 32,
19292        0xfc0003ff, 0xa00002b8, &NMD::SEL_D            , 0,
19293        CP1_                },        /* SEL.D */
19294 };
19295
19296
19297 NMD::Pool NMD::DIV_fmt0[2] = {
19298     { instruction         , 0                   , 0   , 32,
19299        0xfc0003ff, 0xa00000f0, &NMD::DIV_S            , 0,
19300        CP1_                },        /* DIV.S */
19301     { reserved_block      , 0                   , 0   , 32,
19302        0xfc0003ff, 0xa00002f0, 0                      , 0,
19303        CP1_                },        /* DIV.fmt0~*(1) */
19304 };
19305
19306
19307 NMD::Pool NMD::ADD_fmt1[2] = {
19308     { instruction         , 0                   , 0   , 32,
19309        0xfc0003ff, 0xa0000130, &NMD::ADD_D            , 0,
19310        CP1_                },        /* ADD.D */
19311     { reserved_block      , 0                   , 0   , 32,
19312        0xfc0003ff, 0xa0000330, 0                      , 0,
19313        CP1_                },        /* ADD.fmt1~*(1) */
19314 };
19315
19316
19317 NMD::Pool NMD::SUB_fmt1[2] = {
19318     { instruction         , 0                   , 0   , 32,
19319        0xfc0003ff, 0xa0000170, &NMD::SUB_D            , 0,
19320        CP1_                },        /* SUB.D */
19321     { reserved_block      , 0                   , 0   , 32,
19322        0xfc0003ff, 0xa0000370, 0                      , 0,
19323        CP1_                },        /* SUB.fmt1~*(1) */
19324 };
19325
19326
19327 NMD::Pool NMD::MUL_fmt1[2] = {
19328     { instruction         , 0                   , 0   , 32,
19329        0xfc0003ff, 0xa00001b0, &NMD::MUL_D            , 0,
19330        CP1_                },        /* MUL.D */
19331     { reserved_block      , 0                   , 0   , 32,
19332        0xfc0003ff, 0xa00003b0, 0                      , 0,
19333        CP1_                },        /* MUL.fmt1~*(1) */
19334 };
19335
19336
19337 NMD::Pool NMD::MADDF_fmt[2] = {
19338     { instruction         , 0                   , 0   , 32,
19339        0xfc0003ff, 0xa00001b8, &NMD::MADDF_S          , 0,
19340        CP1_                },        /* MADDF.S */
19341     { instruction         , 0                   , 0   , 32,
19342        0xfc0003ff, 0xa00003b8, &NMD::MADDF_D          , 0,
19343        CP1_                },        /* MADDF.D */
19344 };
19345
19346
19347 NMD::Pool NMD::DIV_fmt1[2] = {
19348     { instruction         , 0                   , 0   , 32,
19349        0xfc0003ff, 0xa00001f0, &NMD::DIV_D            , 0,
19350        CP1_                },        /* DIV.D */
19351     { reserved_block      , 0                   , 0   , 32,
19352        0xfc0003ff, 0xa00003f0, 0                      , 0,
19353        CP1_                },        /* DIV.fmt1~*(1) */
19354 };
19355
19356
19357 NMD::Pool NMD::MSUBF_fmt[2] = {
19358     { instruction         , 0                   , 0   , 32,
19359        0xfc0003ff, 0xa00001f8, &NMD::MSUBF_S          , 0,
19360        CP1_                },        /* MSUBF.S */
19361     { instruction         , 0                   , 0   , 32,
19362        0xfc0003ff, 0xa00003f8, &NMD::MSUBF_D          , 0,
19363        CP1_                },        /* MSUBF.D */
19364 };
19365
19366
19367 NMD::Pool NMD::POOL32F_0[64] = {
19368     { reserved_block      , 0                   , 0   , 32,
19369        0xfc0001ff, 0xa0000000, 0                      , 0,
19370        CP1_                },        /* POOL32F_0~*(0) */
19371     { reserved_block      , 0                   , 0   , 32,
19372        0xfc0001ff, 0xa0000008, 0                      , 0,
19373        CP1_                },        /* POOL32F_0~*(1) */
19374     { reserved_block      , 0                   , 0   , 32,
19375        0xfc0001ff, 0xa0000010, 0                      , 0,
19376        CP1_                },        /* POOL32F_0~*(2) */
19377     { reserved_block      , 0                   , 0   , 32,
19378        0xfc0001ff, 0xa0000018, 0                      , 0,
19379        CP1_                },        /* POOL32F_0~*(3) */
19380     { pool                , RINT_fmt            , 2   , 32,
19381        0xfc0001ff, 0xa0000020, 0                      , 0,
19382        CP1_                },        /* RINT.fmt */
19383     { reserved_block      , 0                   , 0   , 32,
19384        0xfc0001ff, 0xa0000028, 0                      , 0,
19385        CP1_                },        /* POOL32F_0~*(5) */
19386     { pool                , ADD_fmt0            , 2   , 32,
19387        0xfc0001ff, 0xa0000030, 0                      , 0,
19388        CP1_                },        /* ADD.fmt0 */
19389     { pool                , SELEQZ_fmt          , 2   , 32,
19390        0xfc0001ff, 0xa0000038, 0                      , 0,
19391        CP1_                },        /* SELEQZ.fmt */
19392     { reserved_block      , 0                   , 0   , 32,
19393        0xfc0001ff, 0xa0000040, 0                      , 0,
19394        CP1_                },        /* POOL32F_0~*(8) */
19395     { reserved_block      , 0                   , 0   , 32,
19396        0xfc0001ff, 0xa0000048, 0                      , 0,
19397        CP1_                },        /* POOL32F_0~*(9) */
19398     { reserved_block      , 0                   , 0   , 32,
19399        0xfc0001ff, 0xa0000050, 0                      , 0,
19400        CP1_                },        /* POOL32F_0~*(10) */
19401     { reserved_block      , 0                   , 0   , 32,
19402        0xfc0001ff, 0xa0000058, 0                      , 0,
19403        CP1_                },        /* POOL32F_0~*(11) */
19404     { pool                , CLASS_fmt           , 2   , 32,
19405        0xfc0001ff, 0xa0000060, 0                      , 0,
19406        CP1_                },        /* CLASS.fmt */
19407     { reserved_block      , 0                   , 0   , 32,
19408        0xfc0001ff, 0xa0000068, 0                      , 0,
19409        CP1_                },        /* POOL32F_0~*(13) */
19410     { pool                , SUB_fmt0            , 2   , 32,
19411        0xfc0001ff, 0xa0000070, 0                      , 0,
19412        CP1_                },        /* SUB.fmt0 */
19413     { pool                , SELNEZ_fmt          , 2   , 32,
19414        0xfc0001ff, 0xa0000078, 0                      , 0,
19415        CP1_                },        /* SELNEZ.fmt */
19416     { reserved_block      , 0                   , 0   , 32,
19417        0xfc0001ff, 0xa0000080, 0                      , 0,
19418        CP1_                },        /* POOL32F_0~*(16) */
19419     { reserved_block      , 0                   , 0   , 32,
19420        0xfc0001ff, 0xa0000088, 0                      , 0,
19421        CP1_                },        /* POOL32F_0~*(17) */
19422     { reserved_block      , 0                   , 0   , 32,
19423        0xfc0001ff, 0xa0000090, 0                      , 0,
19424        CP1_                },        /* POOL32F_0~*(18) */
19425     { reserved_block      , 0                   , 0   , 32,
19426        0xfc0001ff, 0xa0000098, 0                      , 0,
19427        CP1_                },        /* POOL32F_0~*(19) */
19428     { reserved_block      , 0                   , 0   , 32,
19429        0xfc0001ff, 0xa00000a0, 0                      , 0,
19430        CP1_                },        /* POOL32F_0~*(20) */
19431     { reserved_block      , 0                   , 0   , 32,
19432        0xfc0001ff, 0xa00000a8, 0                      , 0,
19433        CP1_                },        /* POOL32F_0~*(21) */
19434     { pool                , MUL_fmt0            , 2   , 32,
19435        0xfc0001ff, 0xa00000b0, 0                      , 0,
19436        CP1_                },        /* MUL.fmt0 */
19437     { pool                , SEL_fmt             , 2   , 32,
19438        0xfc0001ff, 0xa00000b8, 0                      , 0,
19439        CP1_                },        /* SEL.fmt */
19440     { reserved_block      , 0                   , 0   , 32,
19441        0xfc0001ff, 0xa00000c0, 0                      , 0,
19442        CP1_                },        /* POOL32F_0~*(24) */
19443     { reserved_block      , 0                   , 0   , 32,
19444        0xfc0001ff, 0xa00000c8, 0                      , 0,
19445        CP1_                },        /* POOL32F_0~*(25) */
19446     { reserved_block      , 0                   , 0   , 32,
19447        0xfc0001ff, 0xa00000d0, 0                      , 0,
19448        CP1_                },        /* POOL32F_0~*(26) */
19449     { reserved_block      , 0                   , 0   , 32,
19450        0xfc0001ff, 0xa00000d8, 0                      , 0,
19451        CP1_                },        /* POOL32F_0~*(27) */
19452     { reserved_block      , 0                   , 0   , 32,
19453        0xfc0001ff, 0xa00000e0, 0                      , 0,
19454        CP1_                },        /* POOL32F_0~*(28) */
19455     { reserved_block      , 0                   , 0   , 32,
19456        0xfc0001ff, 0xa00000e8, 0                      , 0,
19457        CP1_                },        /* POOL32F_0~*(29) */
19458     { pool                , DIV_fmt0            , 2   , 32,
19459        0xfc0001ff, 0xa00000f0, 0                      , 0,
19460        CP1_                },        /* DIV.fmt0 */
19461     { reserved_block      , 0                   , 0   , 32,
19462        0xfc0001ff, 0xa00000f8, 0                      , 0,
19463        CP1_                },        /* POOL32F_0~*(31) */
19464     { reserved_block      , 0                   , 0   , 32,
19465        0xfc0001ff, 0xa0000100, 0                      , 0,
19466        CP1_                },        /* POOL32F_0~*(32) */
19467     { reserved_block      , 0                   , 0   , 32,
19468        0xfc0001ff, 0xa0000108, 0                      , 0,
19469        CP1_                },        /* POOL32F_0~*(33) */
19470     { reserved_block      , 0                   , 0   , 32,
19471        0xfc0001ff, 0xa0000110, 0                      , 0,
19472        CP1_                },        /* POOL32F_0~*(34) */
19473     { reserved_block      , 0                   , 0   , 32,
19474        0xfc0001ff, 0xa0000118, 0                      , 0,
19475        CP1_                },        /* POOL32F_0~*(35) */
19476     { reserved_block      , 0                   , 0   , 32,
19477        0xfc0001ff, 0xa0000120, 0                      , 0,
19478        CP1_                },        /* POOL32F_0~*(36) */
19479     { reserved_block      , 0                   , 0   , 32,
19480        0xfc0001ff, 0xa0000128, 0                      , 0,
19481        CP1_                },        /* POOL32F_0~*(37) */
19482     { pool                , ADD_fmt1            , 2   , 32,
19483        0xfc0001ff, 0xa0000130, 0                      , 0,
19484        CP1_                },        /* ADD.fmt1 */
19485     { reserved_block      , 0                   , 0   , 32,
19486        0xfc0001ff, 0xa0000138, 0                      , 0,
19487        CP1_                },        /* POOL32F_0~*(39) */
19488     { reserved_block      , 0                   , 0   , 32,
19489        0xfc0001ff, 0xa0000140, 0                      , 0,
19490        CP1_                },        /* POOL32F_0~*(40) */
19491     { reserved_block      , 0                   , 0   , 32,
19492        0xfc0001ff, 0xa0000148, 0                      , 0,
19493        CP1_                },        /* POOL32F_0~*(41) */
19494     { reserved_block      , 0                   , 0   , 32,
19495        0xfc0001ff, 0xa0000150, 0                      , 0,
19496        CP1_                },        /* POOL32F_0~*(42) */
19497     { reserved_block      , 0                   , 0   , 32,
19498        0xfc0001ff, 0xa0000158, 0                      , 0,
19499        CP1_                },        /* POOL32F_0~*(43) */
19500     { reserved_block      , 0                   , 0   , 32,
19501        0xfc0001ff, 0xa0000160, 0                      , 0,
19502        CP1_                },        /* POOL32F_0~*(44) */
19503     { reserved_block      , 0                   , 0   , 32,
19504        0xfc0001ff, 0xa0000168, 0                      , 0,
19505        CP1_                },        /* POOL32F_0~*(45) */
19506     { pool                , SUB_fmt1            , 2   , 32,
19507        0xfc0001ff, 0xa0000170, 0                      , 0,
19508        CP1_                },        /* SUB.fmt1 */
19509     { reserved_block      , 0                   , 0   , 32,
19510        0xfc0001ff, 0xa0000178, 0                      , 0,
19511        CP1_                },        /* POOL32F_0~*(47) */
19512     { reserved_block      , 0                   , 0   , 32,
19513        0xfc0001ff, 0xa0000180, 0                      , 0,
19514        CP1_                },        /* POOL32F_0~*(48) */
19515     { reserved_block      , 0                   , 0   , 32,
19516        0xfc0001ff, 0xa0000188, 0                      , 0,
19517        CP1_                },        /* POOL32F_0~*(49) */
19518     { reserved_block      , 0                   , 0   , 32,
19519        0xfc0001ff, 0xa0000190, 0                      , 0,
19520        CP1_                },        /* POOL32F_0~*(50) */
19521     { reserved_block      , 0                   , 0   , 32,
19522        0xfc0001ff, 0xa0000198, 0                      , 0,
19523        CP1_                },        /* POOL32F_0~*(51) */
19524     { reserved_block      , 0                   , 0   , 32,
19525        0xfc0001ff, 0xa00001a0, 0                      , 0,
19526        CP1_                },        /* POOL32F_0~*(52) */
19527     { reserved_block      , 0                   , 0   , 32,
19528        0xfc0001ff, 0xa00001a8, 0                      , 0,
19529        CP1_                },        /* POOL32F_0~*(53) */
19530     { pool                , MUL_fmt1            , 2   , 32,
19531        0xfc0001ff, 0xa00001b0, 0                      , 0,
19532        CP1_                },        /* MUL.fmt1 */
19533     { pool                , MADDF_fmt           , 2   , 32,
19534        0xfc0001ff, 0xa00001b8, 0                      , 0,
19535        CP1_                },        /* MADDF.fmt */
19536     { reserved_block      , 0                   , 0   , 32,
19537        0xfc0001ff, 0xa00001c0, 0                      , 0,
19538        CP1_                },        /* POOL32F_0~*(56) */
19539     { reserved_block      , 0                   , 0   , 32,
19540        0xfc0001ff, 0xa00001c8, 0                      , 0,
19541        CP1_                },        /* POOL32F_0~*(57) */
19542     { reserved_block      , 0                   , 0   , 32,
19543        0xfc0001ff, 0xa00001d0, 0                      , 0,
19544        CP1_                },        /* POOL32F_0~*(58) */
19545     { reserved_block      , 0                   , 0   , 32,
19546        0xfc0001ff, 0xa00001d8, 0                      , 0,
19547        CP1_                },        /* POOL32F_0~*(59) */
19548     { reserved_block      , 0                   , 0   , 32,
19549        0xfc0001ff, 0xa00001e0, 0                      , 0,
19550        CP1_                },        /* POOL32F_0~*(60) */
19551     { reserved_block      , 0                   , 0   , 32,
19552        0xfc0001ff, 0xa00001e8, 0                      , 0,
19553        CP1_                },        /* POOL32F_0~*(61) */
19554     { pool                , DIV_fmt1            , 2   , 32,
19555        0xfc0001ff, 0xa00001f0, 0                      , 0,
19556        CP1_                },        /* DIV.fmt1 */
19557     { pool                , MSUBF_fmt           , 2   , 32,
19558        0xfc0001ff, 0xa00001f8, 0                      , 0,
19559        CP1_                },        /* MSUBF.fmt */
19560 };
19561
19562
19563 NMD::Pool NMD::MIN_fmt[2] = {
19564     { instruction         , 0                   , 0   , 32,
19565        0xfc00023f, 0xa0000003, &NMD::MIN_S            , 0,
19566        CP1_                },        /* MIN.S */
19567     { instruction         , 0                   , 0   , 32,
19568        0xfc00023f, 0xa0000203, &NMD::MIN_D            , 0,
19569        CP1_                },        /* MIN.D */
19570 };
19571
19572
19573 NMD::Pool NMD::MAX_fmt[2] = {
19574     { instruction         , 0                   , 0   , 32,
19575        0xfc00023f, 0xa000000b, &NMD::MAX_S            , 0,
19576        CP1_                },        /* MAX.S */
19577     { instruction         , 0                   , 0   , 32,
19578        0xfc00023f, 0xa000020b, &NMD::MAX_D            , 0,
19579        CP1_                },        /* MAX.D */
19580 };
19581
19582
19583 NMD::Pool NMD::MINA_fmt[2] = {
19584     { instruction         , 0                   , 0   , 32,
19585        0xfc00023f, 0xa0000023, &NMD::MINA_S           , 0,
19586        CP1_                },        /* MINA.S */
19587     { instruction         , 0                   , 0   , 32,
19588        0xfc00023f, 0xa0000223, &NMD::MINA_D           , 0,
19589        CP1_                },        /* MINA.D */
19590 };
19591
19592
19593 NMD::Pool NMD::MAXA_fmt[2] = {
19594     { instruction         , 0                   , 0   , 32,
19595        0xfc00023f, 0xa000002b, &NMD::MAXA_S           , 0,
19596        CP1_                },        /* MAXA.S */
19597     { instruction         , 0                   , 0   , 32,
19598        0xfc00023f, 0xa000022b, &NMD::MAXA_D           , 0,
19599        CP1_                },        /* MAXA.D */
19600 };
19601
19602
19603 NMD::Pool NMD::CVT_L_fmt[2] = {
19604     { instruction         , 0                   , 0   , 32,
19605        0xfc007fff, 0xa000013b, &NMD::CVT_L_S          , 0,
19606        CP1_                },        /* CVT.L.S */
19607     { instruction         , 0                   , 0   , 32,
19608        0xfc007fff, 0xa000413b, &NMD::CVT_L_D          , 0,
19609        CP1_                },        /* CVT.L.D */
19610 };
19611
19612
19613 NMD::Pool NMD::RSQRT_fmt[2] = {
19614     { instruction         , 0                   , 0   , 32,
19615        0xfc007fff, 0xa000023b, &NMD::RSQRT_S          , 0,
19616        CP1_                },        /* RSQRT.S */
19617     { instruction         , 0                   , 0   , 32,
19618        0xfc007fff, 0xa000423b, &NMD::RSQRT_D          , 0,
19619        CP1_                },        /* RSQRT.D */
19620 };
19621
19622
19623 NMD::Pool NMD::FLOOR_L_fmt[2] = {
19624     { instruction         , 0                   , 0   , 32,
19625        0xfc007fff, 0xa000033b, &NMD::FLOOR_L_S        , 0,
19626        CP1_                },        /* FLOOR.L.S */
19627     { instruction         , 0                   , 0   , 32,
19628        0xfc007fff, 0xa000433b, &NMD::FLOOR_L_D        , 0,
19629        CP1_                },        /* FLOOR.L.D */
19630 };
19631
19632
19633 NMD::Pool NMD::CVT_W_fmt[2] = {
19634     { instruction         , 0                   , 0   , 32,
19635        0xfc007fff, 0xa000093b, &NMD::CVT_W_S          , 0,
19636        CP1_                },        /* CVT.W.S */
19637     { instruction         , 0                   , 0   , 32,
19638        0xfc007fff, 0xa000493b, &NMD::CVT_W_D          , 0,
19639        CP1_                },        /* CVT.W.D */
19640 };
19641
19642
19643 NMD::Pool NMD::SQRT_fmt[2] = {
19644     { instruction         , 0                   , 0   , 32,
19645        0xfc007fff, 0xa0000a3b, &NMD::SQRT_S           , 0,
19646        CP1_                },        /* SQRT.S */
19647     { instruction         , 0                   , 0   , 32,
19648        0xfc007fff, 0xa0004a3b, &NMD::SQRT_D           , 0,
19649        CP1_                },        /* SQRT.D */
19650 };
19651
19652
19653 NMD::Pool NMD::FLOOR_W_fmt[2] = {
19654     { instruction         , 0                   , 0   , 32,
19655        0xfc007fff, 0xa0000b3b, &NMD::FLOOR_W_S        , 0,
19656        CP1_                },        /* FLOOR.W.S */
19657     { instruction         , 0                   , 0   , 32,
19658        0xfc007fff, 0xa0004b3b, &NMD::FLOOR_W_D        , 0,
19659        CP1_                },        /* FLOOR.W.D */
19660 };
19661
19662
19663 NMD::Pool NMD::RECIP_fmt[2] = {
19664     { instruction         , 0                   , 0   , 32,
19665        0xfc007fff, 0xa000123b, &NMD::RECIP_S          , 0,
19666        CP1_                },        /* RECIP.S */
19667     { instruction         , 0                   , 0   , 32,
19668        0xfc007fff, 0xa000523b, &NMD::RECIP_D          , 0,
19669        CP1_                },        /* RECIP.D */
19670 };
19671
19672
19673 NMD::Pool NMD::CEIL_L_fmt[2] = {
19674     { instruction         , 0                   , 0   , 32,
19675        0xfc007fff, 0xa000133b, &NMD::CEIL_L_S         , 0,
19676        CP1_                },        /* CEIL.L.S */
19677     { instruction         , 0                   , 0   , 32,
19678        0xfc007fff, 0xa000533b, &NMD::CEIL_L_D         , 0,
19679        CP1_                },        /* CEIL.L.D */
19680 };
19681
19682
19683 NMD::Pool NMD::CEIL_W_fmt[2] = {
19684     { instruction         , 0                   , 0   , 32,
19685        0xfc007fff, 0xa0001b3b, &NMD::CEIL_W_S         , 0,
19686        CP1_                },        /* CEIL.W.S */
19687     { instruction         , 0                   , 0   , 32,
19688        0xfc007fff, 0xa0005b3b, &NMD::CEIL_W_D         , 0,
19689        CP1_                },        /* CEIL.W.D */
19690 };
19691
19692
19693 NMD::Pool NMD::TRUNC_L_fmt[2] = {
19694     { instruction         , 0                   , 0   , 32,
19695        0xfc007fff, 0xa000233b, &NMD::TRUNC_L_S        , 0,
19696        CP1_                },        /* TRUNC.L.S */
19697     { instruction         , 0                   , 0   , 32,
19698        0xfc007fff, 0xa000633b, &NMD::TRUNC_L_D        , 0,
19699        CP1_                },        /* TRUNC.L.D */
19700 };
19701
19702
19703 NMD::Pool NMD::TRUNC_W_fmt[2] = {
19704     { instruction         , 0                   , 0   , 32,
19705        0xfc007fff, 0xa0002b3b, &NMD::TRUNC_W_S        , 0,
19706        CP1_                },        /* TRUNC.W.S */
19707     { instruction         , 0                   , 0   , 32,
19708        0xfc007fff, 0xa0006b3b, &NMD::TRUNC_W_D        , 0,
19709        CP1_                },        /* TRUNC.W.D */
19710 };
19711
19712
19713 NMD::Pool NMD::ROUND_L_fmt[2] = {
19714     { instruction         , 0                   , 0   , 32,
19715        0xfc007fff, 0xa000333b, &NMD::ROUND_L_S        , 0,
19716        CP1_                },        /* ROUND.L.S */
19717     { instruction         , 0                   , 0   , 32,
19718        0xfc007fff, 0xa000733b, &NMD::ROUND_L_D        , 0,
19719        CP1_                },        /* ROUND.L.D */
19720 };
19721
19722
19723 NMD::Pool NMD::ROUND_W_fmt[2] = {
19724     { instruction         , 0                   , 0   , 32,
19725        0xfc007fff, 0xa0003b3b, &NMD::ROUND_W_S        , 0,
19726        CP1_                },        /* ROUND.W.S */
19727     { instruction         , 0                   , 0   , 32,
19728        0xfc007fff, 0xa0007b3b, &NMD::ROUND_W_D        , 0,
19729        CP1_                },        /* ROUND.W.D */
19730 };
19731
19732
19733 NMD::Pool NMD::POOL32Fxf_0[64] = {
19734     { reserved_block      , 0                   , 0   , 32,
19735        0xfc003fff, 0xa000003b, 0                      , 0,
19736        CP1_                },        /* POOL32Fxf_0~*(0) */
19737     { pool                , CVT_L_fmt           , 2   , 32,
19738        0xfc003fff, 0xa000013b, 0                      , 0,
19739        CP1_                },        /* CVT.L.fmt */
19740     { pool                , RSQRT_fmt           , 2   , 32,
19741        0xfc003fff, 0xa000023b, 0                      , 0,
19742        CP1_                },        /* RSQRT.fmt */
19743     { pool                , FLOOR_L_fmt         , 2   , 32,
19744        0xfc003fff, 0xa000033b, 0                      , 0,
19745        CP1_                },        /* FLOOR.L.fmt */
19746     { reserved_block      , 0                   , 0   , 32,
19747        0xfc003fff, 0xa000043b, 0                      , 0,
19748        CP1_                },        /* POOL32Fxf_0~*(4) */
19749     { reserved_block      , 0                   , 0   , 32,
19750        0xfc003fff, 0xa000053b, 0                      , 0,
19751        CP1_                },        /* POOL32Fxf_0~*(5) */
19752     { reserved_block      , 0                   , 0   , 32,
19753        0xfc003fff, 0xa000063b, 0                      , 0,
19754        CP1_                },        /* POOL32Fxf_0~*(6) */
19755     { reserved_block      , 0                   , 0   , 32,
19756        0xfc003fff, 0xa000073b, 0                      , 0,
19757        CP1_                },        /* POOL32Fxf_0~*(7) */
19758     { reserved_block      , 0                   , 0   , 32,
19759        0xfc003fff, 0xa000083b, 0                      , 0,
19760        CP1_                },        /* POOL32Fxf_0~*(8) */
19761     { pool                , CVT_W_fmt           , 2   , 32,
19762        0xfc003fff, 0xa000093b, 0                      , 0,
19763        CP1_                },        /* CVT.W.fmt */
19764     { pool                , SQRT_fmt            , 2   , 32,
19765        0xfc003fff, 0xa0000a3b, 0                      , 0,
19766        CP1_                },        /* SQRT.fmt */
19767     { pool                , FLOOR_W_fmt         , 2   , 32,
19768        0xfc003fff, 0xa0000b3b, 0                      , 0,
19769        CP1_                },        /* FLOOR.W.fmt */
19770     { reserved_block      , 0                   , 0   , 32,
19771        0xfc003fff, 0xa0000c3b, 0                      , 0,
19772        CP1_                },        /* POOL32Fxf_0~*(12) */
19773     { reserved_block      , 0                   , 0   , 32,
19774        0xfc003fff, 0xa0000d3b, 0                      , 0,
19775        CP1_                },        /* POOL32Fxf_0~*(13) */
19776     { reserved_block      , 0                   , 0   , 32,
19777        0xfc003fff, 0xa0000e3b, 0                      , 0,
19778        CP1_                },        /* POOL32Fxf_0~*(14) */
19779     { reserved_block      , 0                   , 0   , 32,
19780        0xfc003fff, 0xa0000f3b, 0                      , 0,
19781        CP1_                },        /* POOL32Fxf_0~*(15) */
19782     { instruction         , 0                   , 0   , 32,
19783        0xfc003fff, 0xa000103b, &NMD::CFC1             , 0,
19784        CP1_                },        /* CFC1 */
19785     { reserved_block      , 0                   , 0   , 32,
19786        0xfc003fff, 0xa000113b, 0                      , 0,
19787        CP1_                },        /* POOL32Fxf_0~*(17) */
19788     { pool                , RECIP_fmt           , 2   , 32,
19789        0xfc003fff, 0xa000123b, 0                      , 0,
19790        CP1_                },        /* RECIP.fmt */
19791     { pool                , CEIL_L_fmt          , 2   , 32,
19792        0xfc003fff, 0xa000133b, 0                      , 0,
19793        CP1_                },        /* CEIL.L.fmt */
19794     { reserved_block      , 0                   , 0   , 32,
19795        0xfc003fff, 0xa000143b, 0                      , 0,
19796        CP1_                },        /* POOL32Fxf_0~*(20) */
19797     { reserved_block      , 0                   , 0   , 32,
19798        0xfc003fff, 0xa000153b, 0                      , 0,
19799        CP1_                },        /* POOL32Fxf_0~*(21) */
19800     { reserved_block      , 0                   , 0   , 32,
19801        0xfc003fff, 0xa000163b, 0                      , 0,
19802        CP1_                },        /* POOL32Fxf_0~*(22) */
19803     { reserved_block      , 0                   , 0   , 32,
19804        0xfc003fff, 0xa000173b, 0                      , 0,
19805        CP1_                },        /* POOL32Fxf_0~*(23) */
19806     { instruction         , 0                   , 0   , 32,
19807        0xfc003fff, 0xa000183b, &NMD::CTC1             , 0,
19808        CP1_                },        /* CTC1 */
19809     { reserved_block      , 0                   , 0   , 32,
19810        0xfc003fff, 0xa000193b, 0                      , 0,
19811        CP1_                },        /* POOL32Fxf_0~*(25) */
19812     { reserved_block      , 0                   , 0   , 32,
19813        0xfc003fff, 0xa0001a3b, 0                      , 0,
19814        CP1_                },        /* POOL32Fxf_0~*(26) */
19815     { pool                , CEIL_W_fmt          , 2   , 32,
19816        0xfc003fff, 0xa0001b3b, 0                      , 0,
19817        CP1_                },        /* CEIL.W.fmt */
19818     { reserved_block      , 0                   , 0   , 32,
19819        0xfc003fff, 0xa0001c3b, 0                      , 0,
19820        CP1_                },        /* POOL32Fxf_0~*(28) */
19821     { reserved_block      , 0                   , 0   , 32,
19822        0xfc003fff, 0xa0001d3b, 0                      , 0,
19823        CP1_                },        /* POOL32Fxf_0~*(29) */
19824     { reserved_block      , 0                   , 0   , 32,
19825        0xfc003fff, 0xa0001e3b, 0                      , 0,
19826        CP1_                },        /* POOL32Fxf_0~*(30) */
19827     { reserved_block      , 0                   , 0   , 32,
19828        0xfc003fff, 0xa0001f3b, 0                      , 0,
19829        CP1_                },        /* POOL32Fxf_0~*(31) */
19830     { instruction         , 0                   , 0   , 32,
19831        0xfc003fff, 0xa000203b, &NMD::MFC1             , 0,
19832        CP1_                },        /* MFC1 */
19833     { instruction         , 0                   , 0   , 32,
19834        0xfc003fff, 0xa000213b, &NMD::CVT_S_PL         , 0,
19835        CP1_                },        /* CVT.S.PL */
19836     { reserved_block      , 0                   , 0   , 32,
19837        0xfc003fff, 0xa000223b, 0                      , 0,
19838        CP1_                },        /* POOL32Fxf_0~*(34) */
19839     { pool                , TRUNC_L_fmt         , 2   , 32,
19840        0xfc003fff, 0xa000233b, 0                      , 0,
19841        CP1_                },        /* TRUNC.L.fmt */
19842     { instruction         , 0                   , 0   , 32,
19843        0xfc003fff, 0xa000243b, &NMD::DMFC1            , 0,
19844        CP1_ | MIPS64_      },        /* DMFC1 */
19845     { reserved_block      , 0                   , 0   , 32,
19846        0xfc003fff, 0xa000253b, 0                      , 0,
19847        CP1_                },        /* POOL32Fxf_0~*(37) */
19848     { reserved_block      , 0                   , 0   , 32,
19849        0xfc003fff, 0xa000263b, 0                      , 0,
19850        CP1_                },        /* POOL32Fxf_0~*(38) */
19851     { reserved_block      , 0                   , 0   , 32,
19852        0xfc003fff, 0xa000273b, 0                      , 0,
19853        CP1_                },        /* POOL32Fxf_0~*(39) */
19854     { instruction         , 0                   , 0   , 32,
19855        0xfc003fff, 0xa000283b, &NMD::MTC1             , 0,
19856        CP1_                },        /* MTC1 */
19857     { instruction         , 0                   , 0   , 32,
19858        0xfc003fff, 0xa000293b, &NMD::CVT_S_PU         , 0,
19859        CP1_                },        /* CVT.S.PU */
19860     { reserved_block      , 0                   , 0   , 32,
19861        0xfc003fff, 0xa0002a3b, 0                      , 0,
19862        CP1_                },        /* POOL32Fxf_0~*(42) */
19863     { pool                , TRUNC_W_fmt         , 2   , 32,
19864        0xfc003fff, 0xa0002b3b, 0                      , 0,
19865        CP1_                },        /* TRUNC.W.fmt */
19866     { instruction         , 0                   , 0   , 32,
19867        0xfc003fff, 0xa0002c3b, &NMD::DMTC1            , 0,
19868        CP1_ | MIPS64_      },        /* DMTC1 */
19869     { reserved_block      , 0                   , 0   , 32,
19870        0xfc003fff, 0xa0002d3b, 0                      , 0,
19871        CP1_                },        /* POOL32Fxf_0~*(45) */
19872     { reserved_block      , 0                   , 0   , 32,
19873        0xfc003fff, 0xa0002e3b, 0                      , 0,
19874        CP1_                },        /* POOL32Fxf_0~*(46) */
19875     { reserved_block      , 0                   , 0   , 32,
19876        0xfc003fff, 0xa0002f3b, 0                      , 0,
19877        CP1_                },        /* POOL32Fxf_0~*(47) */
19878     { instruction         , 0                   , 0   , 32,
19879        0xfc003fff, 0xa000303b, &NMD::MFHC1            , 0,
19880        CP1_                },        /* MFHC1 */
19881     { reserved_block      , 0                   , 0   , 32,
19882        0xfc003fff, 0xa000313b, 0                      , 0,
19883        CP1_                },        /* POOL32Fxf_0~*(49) */
19884     { reserved_block      , 0                   , 0   , 32,
19885        0xfc003fff, 0xa000323b, 0                      , 0,
19886        CP1_                },        /* POOL32Fxf_0~*(50) */
19887     { pool                , ROUND_L_fmt         , 2   , 32,
19888        0xfc003fff, 0xa000333b, 0                      , 0,
19889        CP1_                },        /* ROUND.L.fmt */
19890     { reserved_block      , 0                   , 0   , 32,
19891        0xfc003fff, 0xa000343b, 0                      , 0,
19892        CP1_                },        /* POOL32Fxf_0~*(52) */
19893     { reserved_block      , 0                   , 0   , 32,
19894        0xfc003fff, 0xa000353b, 0                      , 0,
19895        CP1_                },        /* POOL32Fxf_0~*(53) */
19896     { reserved_block      , 0                   , 0   , 32,
19897        0xfc003fff, 0xa000363b, 0                      , 0,
19898        CP1_                },        /* POOL32Fxf_0~*(54) */
19899     { reserved_block      , 0                   , 0   , 32,
19900        0xfc003fff, 0xa000373b, 0                      , 0,
19901        CP1_                },        /* POOL32Fxf_0~*(55) */
19902     { instruction         , 0                   , 0   , 32,
19903        0xfc003fff, 0xa000383b, &NMD::MTHC1            , 0,
19904        CP1_                },        /* MTHC1 */
19905     { reserved_block      , 0                   , 0   , 32,
19906        0xfc003fff, 0xa000393b, 0                      , 0,
19907        CP1_                },        /* POOL32Fxf_0~*(57) */
19908     { reserved_block      , 0                   , 0   , 32,
19909        0xfc003fff, 0xa0003a3b, 0                      , 0,
19910        CP1_                },        /* POOL32Fxf_0~*(58) */
19911     { pool                , ROUND_W_fmt         , 2   , 32,
19912        0xfc003fff, 0xa0003b3b, 0                      , 0,
19913        CP1_                },        /* ROUND.W.fmt */
19914     { reserved_block      , 0                   , 0   , 32,
19915        0xfc003fff, 0xa0003c3b, 0                      , 0,
19916        CP1_                },        /* POOL32Fxf_0~*(60) */
19917     { reserved_block      , 0                   , 0   , 32,
19918        0xfc003fff, 0xa0003d3b, 0                      , 0,
19919        CP1_                },        /* POOL32Fxf_0~*(61) */
19920     { reserved_block      , 0                   , 0   , 32,
19921        0xfc003fff, 0xa0003e3b, 0                      , 0,
19922        CP1_                },        /* POOL32Fxf_0~*(62) */
19923     { reserved_block      , 0                   , 0   , 32,
19924        0xfc003fff, 0xa0003f3b, 0                      , 0,
19925        CP1_                },        /* POOL32Fxf_0~*(63) */
19926 };
19927
19928
19929 NMD::Pool NMD::MOV_fmt[4] = {
19930     { instruction         , 0                   , 0   , 32,
19931        0xfc007fff, 0xa000007b, &NMD::MOV_S            , 0,
19932        CP1_                },        /* MOV.S */
19933     { instruction         , 0                   , 0   , 32,
19934        0xfc007fff, 0xa000207b, &NMD::MOV_D            , 0,
19935        CP1_                },        /* MOV.D */
19936     { reserved_block      , 0                   , 0   , 32,
19937        0xfc007fff, 0xa000407b, 0                      , 0,
19938        CP1_                },        /* MOV.fmt~*(2) */
19939     { reserved_block      , 0                   , 0   , 32,
19940        0xfc007fff, 0xa000607b, 0                      , 0,
19941        CP1_                },        /* MOV.fmt~*(3) */
19942 };
19943
19944
19945 NMD::Pool NMD::ABS_fmt[4] = {
19946     { instruction         , 0                   , 0   , 32,
19947        0xfc007fff, 0xa000037b, &NMD::ABS_S            , 0,
19948        CP1_                },        /* ABS.S */
19949     { instruction         , 0                   , 0   , 32,
19950        0xfc007fff, 0xa000237b, &NMD::ABS_D            , 0,
19951        CP1_                },        /* ABS.D */
19952     { reserved_block      , 0                   , 0   , 32,
19953        0xfc007fff, 0xa000437b, 0                      , 0,
19954        CP1_                },        /* ABS.fmt~*(2) */
19955     { reserved_block      , 0                   , 0   , 32,
19956        0xfc007fff, 0xa000637b, 0                      , 0,
19957        CP1_                },        /* ABS.fmt~*(3) */
19958 };
19959
19960
19961 NMD::Pool NMD::NEG_fmt[4] = {
19962     { instruction         , 0                   , 0   , 32,
19963        0xfc007fff, 0xa0000b7b, &NMD::NEG_S            , 0,
19964        CP1_                },        /* NEG.S */
19965     { instruction         , 0                   , 0   , 32,
19966        0xfc007fff, 0xa0002b7b, &NMD::NEG_D            , 0,
19967        CP1_                },        /* NEG.D */
19968     { reserved_block      , 0                   , 0   , 32,
19969        0xfc007fff, 0xa0004b7b, 0                      , 0,
19970        CP1_                },        /* NEG.fmt~*(2) */
19971     { reserved_block      , 0                   , 0   , 32,
19972        0xfc007fff, 0xa0006b7b, 0                      , 0,
19973        CP1_                },        /* NEG.fmt~*(3) */
19974 };
19975
19976
19977 NMD::Pool NMD::CVT_D_fmt[4] = {
19978     { instruction         , 0                   , 0   , 32,
19979        0xfc007fff, 0xa000137b, &NMD::CVT_D_S          , 0,
19980        CP1_                },        /* CVT.D.S */
19981     { instruction         , 0                   , 0   , 32,
19982        0xfc007fff, 0xa000337b, &NMD::CVT_D_W          , 0,
19983        CP1_                },        /* CVT.D.W */
19984     { instruction         , 0                   , 0   , 32,
19985        0xfc007fff, 0xa000537b, &NMD::CVT_D_L          , 0,
19986        CP1_                },        /* CVT.D.L */
19987     { reserved_block      , 0                   , 0   , 32,
19988        0xfc007fff, 0xa000737b, 0                      , 0,
19989        CP1_                },        /* CVT.D.fmt~*(3) */
19990 };
19991
19992
19993 NMD::Pool NMD::CVT_S_fmt[4] = {
19994     { instruction         , 0                   , 0   , 32,
19995        0xfc007fff, 0xa0001b7b, &NMD::CVT_S_D          , 0,
19996        CP1_                },        /* CVT.S.D */
19997     { instruction         , 0                   , 0   , 32,
19998        0xfc007fff, 0xa0003b7b, &NMD::CVT_S_W          , 0,
19999        CP1_                },        /* CVT.S.W */
20000     { instruction         , 0                   , 0   , 32,
20001        0xfc007fff, 0xa0005b7b, &NMD::CVT_S_L          , 0,
20002        CP1_                },        /* CVT.S.L */
20003     { reserved_block      , 0                   , 0   , 32,
20004        0xfc007fff, 0xa0007b7b, 0                      , 0,
20005        CP1_                },        /* CVT.S.fmt~*(3) */
20006 };
20007
20008
20009 NMD::Pool NMD::POOL32Fxf_1[32] = {
20010     { pool                , MOV_fmt             , 4   , 32,
20011        0xfc001fff, 0xa000007b, 0                      , 0,
20012        CP1_                },        /* MOV.fmt */
20013     { reserved_block      , 0                   , 0   , 32,
20014        0xfc001fff, 0xa000017b, 0                      , 0,
20015        CP1_                },        /* POOL32Fxf_1~*(1) */
20016     { reserved_block      , 0                   , 0   , 32,
20017        0xfc001fff, 0xa000027b, 0                      , 0,
20018        CP1_                },        /* POOL32Fxf_1~*(2) */
20019     { pool                , ABS_fmt             , 4   , 32,
20020        0xfc001fff, 0xa000037b, 0                      , 0,
20021        CP1_                },        /* ABS.fmt */
20022     { reserved_block      , 0                   , 0   , 32,
20023        0xfc001fff, 0xa000047b, 0                      , 0,
20024        CP1_                },        /* POOL32Fxf_1~*(4) */
20025     { reserved_block      , 0                   , 0   , 32,
20026        0xfc001fff, 0xa000057b, 0                      , 0,
20027        CP1_                },        /* POOL32Fxf_1~*(5) */
20028     { reserved_block      , 0                   , 0   , 32,
20029        0xfc001fff, 0xa000067b, 0                      , 0,
20030        CP1_                },        /* POOL32Fxf_1~*(6) */
20031     { reserved_block      , 0                   , 0   , 32,
20032        0xfc001fff, 0xa000077b, 0                      , 0,
20033        CP1_                },        /* POOL32Fxf_1~*(7) */
20034     { reserved_block      , 0                   , 0   , 32,
20035        0xfc001fff, 0xa000087b, 0                      , 0,
20036        CP1_                },        /* POOL32Fxf_1~*(8) */
20037     { reserved_block      , 0                   , 0   , 32,
20038        0xfc001fff, 0xa000097b, 0                      , 0,
20039        CP1_                },        /* POOL32Fxf_1~*(9) */
20040     { reserved_block      , 0                   , 0   , 32,
20041        0xfc001fff, 0xa0000a7b, 0                      , 0,
20042        CP1_                },        /* POOL32Fxf_1~*(10) */
20043     { pool                , NEG_fmt             , 4   , 32,
20044        0xfc001fff, 0xa0000b7b, 0                      , 0,
20045        CP1_                },        /* NEG.fmt */
20046     { reserved_block      , 0                   , 0   , 32,
20047        0xfc001fff, 0xa0000c7b, 0                      , 0,
20048        CP1_                },        /* POOL32Fxf_1~*(12) */
20049     { reserved_block      , 0                   , 0   , 32,
20050        0xfc001fff, 0xa0000d7b, 0                      , 0,
20051        CP1_                },        /* POOL32Fxf_1~*(13) */
20052     { reserved_block      , 0                   , 0   , 32,
20053        0xfc001fff, 0xa0000e7b, 0                      , 0,
20054        CP1_                },        /* POOL32Fxf_1~*(14) */
20055     { reserved_block      , 0                   , 0   , 32,
20056        0xfc001fff, 0xa0000f7b, 0                      , 0,
20057        CP1_                },        /* POOL32Fxf_1~*(15) */
20058     { reserved_block      , 0                   , 0   , 32,
20059        0xfc001fff, 0xa000107b, 0                      , 0,
20060        CP1_                },        /* POOL32Fxf_1~*(16) */
20061     { reserved_block      , 0                   , 0   , 32,
20062        0xfc001fff, 0xa000117b, 0                      , 0,
20063        CP1_                },        /* POOL32Fxf_1~*(17) */
20064     { reserved_block      , 0                   , 0   , 32,
20065        0xfc001fff, 0xa000127b, 0                      , 0,
20066        CP1_                },        /* POOL32Fxf_1~*(18) */
20067     { pool                , CVT_D_fmt           , 4   , 32,
20068        0xfc001fff, 0xa000137b, 0                      , 0,
20069        CP1_                },        /* CVT.D.fmt */
20070     { reserved_block      , 0                   , 0   , 32,
20071        0xfc001fff, 0xa000147b, 0                      , 0,
20072        CP1_                },        /* POOL32Fxf_1~*(20) */
20073     { reserved_block      , 0                   , 0   , 32,
20074        0xfc001fff, 0xa000157b, 0                      , 0,
20075        CP1_                },        /* POOL32Fxf_1~*(21) */
20076     { reserved_block      , 0                   , 0   , 32,
20077        0xfc001fff, 0xa000167b, 0                      , 0,
20078        CP1_                },        /* POOL32Fxf_1~*(22) */
20079     { reserved_block      , 0                   , 0   , 32,
20080        0xfc001fff, 0xa000177b, 0                      , 0,
20081        CP1_                },        /* POOL32Fxf_1~*(23) */
20082     { reserved_block      , 0                   , 0   , 32,
20083        0xfc001fff, 0xa000187b, 0                      , 0,
20084        CP1_                },        /* POOL32Fxf_1~*(24) */
20085     { reserved_block      , 0                   , 0   , 32,
20086        0xfc001fff, 0xa000197b, 0                      , 0,
20087        CP1_                },        /* POOL32Fxf_1~*(25) */
20088     { reserved_block      , 0                   , 0   , 32,
20089        0xfc001fff, 0xa0001a7b, 0                      , 0,
20090        CP1_                },        /* POOL32Fxf_1~*(26) */
20091     { pool                , CVT_S_fmt           , 4   , 32,
20092        0xfc001fff, 0xa0001b7b, 0                      , 0,
20093        CP1_                },        /* CVT.S.fmt */
20094     { reserved_block      , 0                   , 0   , 32,
20095        0xfc001fff, 0xa0001c7b, 0                      , 0,
20096        CP1_                },        /* POOL32Fxf_1~*(28) */
20097     { reserved_block      , 0                   , 0   , 32,
20098        0xfc001fff, 0xa0001d7b, 0                      , 0,
20099        CP1_                },        /* POOL32Fxf_1~*(29) */
20100     { reserved_block      , 0                   , 0   , 32,
20101        0xfc001fff, 0xa0001e7b, 0                      , 0,
20102        CP1_                },        /* POOL32Fxf_1~*(30) */
20103     { reserved_block      , 0                   , 0   , 32,
20104        0xfc001fff, 0xa0001f7b, 0                      , 0,
20105        CP1_                },        /* POOL32Fxf_1~*(31) */
20106 };
20107
20108
20109 NMD::Pool NMD::POOL32Fxf[4] = {
20110     { pool                , POOL32Fxf_0         , 64  , 32,
20111        0xfc0000ff, 0xa000003b, 0                      , 0,
20112        CP1_                },        /* POOL32Fxf_0 */
20113     { pool                , POOL32Fxf_1         , 32  , 32,
20114        0xfc0000ff, 0xa000007b, 0                      , 0,
20115        CP1_                },        /* POOL32Fxf_1 */
20116     { reserved_block      , 0                   , 0   , 32,
20117        0xfc0000ff, 0xa00000bb, 0                      , 0,
20118        CP1_                },        /* POOL32Fxf~*(2) */
20119     { reserved_block      , 0                   , 0   , 32,
20120        0xfc0000ff, 0xa00000fb, 0                      , 0,
20121        CP1_                },        /* POOL32Fxf~*(3) */
20122 };
20123
20124
20125 NMD::Pool NMD::POOL32F_3[8] = {
20126     { pool                , MIN_fmt             , 2   , 32,
20127        0xfc00003f, 0xa0000003, 0                      , 0,
20128        CP1_                },        /* MIN.fmt */
20129     { pool                , MAX_fmt             , 2   , 32,
20130        0xfc00003f, 0xa000000b, 0                      , 0,
20131        CP1_                },        /* MAX.fmt */
20132     { reserved_block      , 0                   , 0   , 32,
20133        0xfc00003f, 0xa0000013, 0                      , 0,
20134        CP1_                },        /* POOL32F_3~*(2) */
20135     { reserved_block      , 0                   , 0   , 32,
20136        0xfc00003f, 0xa000001b, 0                      , 0,
20137        CP1_                },        /* POOL32F_3~*(3) */
20138     { pool                , MINA_fmt            , 2   , 32,
20139        0xfc00003f, 0xa0000023, 0                      , 0,
20140        CP1_                },        /* MINA.fmt */
20141     { pool                , MAXA_fmt            , 2   , 32,
20142        0xfc00003f, 0xa000002b, 0                      , 0,
20143        CP1_                },        /* MAXA.fmt */
20144     { reserved_block      , 0                   , 0   , 32,
20145        0xfc00003f, 0xa0000033, 0                      , 0,
20146        CP1_                },        /* POOL32F_3~*(6) */
20147     { pool                , POOL32Fxf           , 4   , 32,
20148        0xfc00003f, 0xa000003b, 0                      , 0,
20149        CP1_                },        /* POOL32Fxf */
20150 };
20151
20152
20153 NMD::Pool NMD::CMP_condn_S[32] = {
20154     { instruction         , 0                   , 0   , 32,
20155        0xfc0007ff, 0xa0000005, &NMD::CMP_AF_S         , 0,
20156        CP1_                },        /* CMP.AF.S */
20157     { instruction         , 0                   , 0   , 32,
20158        0xfc0007ff, 0xa0000045, &NMD::CMP_UN_S         , 0,
20159        CP1_                },        /* CMP.UN.S */
20160     { instruction         , 0                   , 0   , 32,
20161        0xfc0007ff, 0xa0000085, &NMD::CMP_EQ_S         , 0,
20162        CP1_                },        /* CMP.EQ.S */
20163     { instruction         , 0                   , 0   , 32,
20164        0xfc0007ff, 0xa00000c5, &NMD::CMP_UEQ_S        , 0,
20165        CP1_                },        /* CMP.UEQ.S */
20166     { instruction         , 0                   , 0   , 32,
20167        0xfc0007ff, 0xa0000105, &NMD::CMP_LT_S         , 0,
20168        CP1_                },        /* CMP.LT.S */
20169     { instruction         , 0                   , 0   , 32,
20170        0xfc0007ff, 0xa0000145, &NMD::CMP_ULT_S        , 0,
20171        CP1_                },        /* CMP.ULT.S */
20172     { instruction         , 0                   , 0   , 32,
20173        0xfc0007ff, 0xa0000185, &NMD::CMP_LE_S         , 0,
20174        CP1_                },        /* CMP.LE.S */
20175     { instruction         , 0                   , 0   , 32,
20176        0xfc0007ff, 0xa00001c5, &NMD::CMP_ULE_S        , 0,
20177        CP1_                },        /* CMP.ULE.S */
20178     { instruction         , 0                   , 0   , 32,
20179        0xfc0007ff, 0xa0000205, &NMD::CMP_SAF_S        , 0,
20180        CP1_                },        /* CMP.SAF.S */
20181     { instruction         , 0                   , 0   , 32,
20182        0xfc0007ff, 0xa0000245, &NMD::CMP_SUN_S        , 0,
20183        CP1_                },        /* CMP.SUN.S */
20184     { instruction         , 0                   , 0   , 32,
20185        0xfc0007ff, 0xa0000285, &NMD::CMP_SEQ_S        , 0,
20186        CP1_                },        /* CMP.SEQ.S */
20187     { instruction         , 0                   , 0   , 32,
20188        0xfc0007ff, 0xa00002c5, &NMD::CMP_SUEQ_S       , 0,
20189        CP1_                },        /* CMP.SUEQ.S */
20190     { instruction         , 0                   , 0   , 32,
20191        0xfc0007ff, 0xa0000305, &NMD::CMP_SLT_S        , 0,
20192        CP1_                },        /* CMP.SLT.S */
20193     { instruction         , 0                   , 0   , 32,
20194        0xfc0007ff, 0xa0000345, &NMD::CMP_SULT_S       , 0,
20195        CP1_                },        /* CMP.SULT.S */
20196     { instruction         , 0                   , 0   , 32,
20197        0xfc0007ff, 0xa0000385, &NMD::CMP_SLE_S        , 0,
20198        CP1_                },        /* CMP.SLE.S */
20199     { instruction         , 0                   , 0   , 32,
20200        0xfc0007ff, 0xa00003c5, &NMD::CMP_SULE_S       , 0,
20201        CP1_                },        /* CMP.SULE.S */
20202     { reserved_block      , 0                   , 0   , 32,
20203        0xfc0007ff, 0xa0000405, 0                      , 0,
20204        CP1_                },        /* CMP.condn.S~*(16) */
20205     { instruction         , 0                   , 0   , 32,
20206        0xfc0007ff, 0xa0000445, &NMD::CMP_OR_S         , 0,
20207        CP1_                },        /* CMP.OR.S */
20208     { instruction         , 0                   , 0   , 32,
20209        0xfc0007ff, 0xa0000485, &NMD::CMP_UNE_S        , 0,
20210        CP1_                },        /* CMP.UNE.S */
20211     { instruction         , 0                   , 0   , 32,
20212        0xfc0007ff, 0xa00004c5, &NMD::CMP_NE_S         , 0,
20213        CP1_                },        /* CMP.NE.S */
20214     { reserved_block      , 0                   , 0   , 32,
20215        0xfc0007ff, 0xa0000505, 0                      , 0,
20216        CP1_                },        /* CMP.condn.S~*(20) */
20217     { reserved_block      , 0                   , 0   , 32,
20218        0xfc0007ff, 0xa0000545, 0                      , 0,
20219        CP1_                },        /* CMP.condn.S~*(21) */
20220     { reserved_block      , 0                   , 0   , 32,
20221        0xfc0007ff, 0xa0000585, 0                      , 0,
20222        CP1_                },        /* CMP.condn.S~*(22) */
20223     { reserved_block      , 0                   , 0   , 32,
20224        0xfc0007ff, 0xa00005c5, 0                      , 0,
20225        CP1_                },        /* CMP.condn.S~*(23) */
20226     { reserved_block      , 0                   , 0   , 32,
20227        0xfc0007ff, 0xa0000605, 0                      , 0,
20228        CP1_                },        /* CMP.condn.S~*(24) */
20229     { instruction         , 0                   , 0   , 32,
20230        0xfc0007ff, 0xa0000645, &NMD::CMP_SOR_S        , 0,
20231        CP1_                },        /* CMP.SOR.S */
20232     { instruction         , 0                   , 0   , 32,
20233        0xfc0007ff, 0xa0000685, &NMD::CMP_SUNE_S       , 0,
20234        CP1_                },        /* CMP.SUNE.S */
20235     { instruction         , 0                   , 0   , 32,
20236        0xfc0007ff, 0xa00006c5, &NMD::CMP_SNE_S        , 0,
20237        CP1_                },        /* CMP.SNE.S */
20238     { reserved_block      , 0                   , 0   , 32,
20239        0xfc0007ff, 0xa0000705, 0                      , 0,
20240        CP1_                },        /* CMP.condn.S~*(28) */
20241     { reserved_block      , 0                   , 0   , 32,
20242        0xfc0007ff, 0xa0000745, 0                      , 0,
20243        CP1_                },        /* CMP.condn.S~*(29) */
20244     { reserved_block      , 0                   , 0   , 32,
20245        0xfc0007ff, 0xa0000785, 0                      , 0,
20246        CP1_                },        /* CMP.condn.S~*(30) */
20247     { reserved_block      , 0                   , 0   , 32,
20248        0xfc0007ff, 0xa00007c5, 0                      , 0,
20249        CP1_                },        /* CMP.condn.S~*(31) */
20250 };
20251
20252
20253 NMD::Pool NMD::CMP_condn_D[32] = {
20254     { instruction         , 0                   , 0   , 32,
20255        0xfc0007ff, 0xa0000015, &NMD::CMP_AF_D         , 0,
20256        CP1_                },        /* CMP.AF.D */
20257     { instruction         , 0                   , 0   , 32,
20258        0xfc0007ff, 0xa0000055, &NMD::CMP_UN_D         , 0,
20259        CP1_                },        /* CMP.UN.D */
20260     { instruction         , 0                   , 0   , 32,
20261        0xfc0007ff, 0xa0000095, &NMD::CMP_EQ_D         , 0,
20262        CP1_                },        /* CMP.EQ.D */
20263     { instruction         , 0                   , 0   , 32,
20264        0xfc0007ff, 0xa00000d5, &NMD::CMP_UEQ_D        , 0,
20265        CP1_                },        /* CMP.UEQ.D */
20266     { instruction         , 0                   , 0   , 32,
20267        0xfc0007ff, 0xa0000115, &NMD::CMP_LT_D         , 0,
20268        CP1_                },        /* CMP.LT.D */
20269     { instruction         , 0                   , 0   , 32,
20270        0xfc0007ff, 0xa0000155, &NMD::CMP_ULT_D        , 0,
20271        CP1_                },        /* CMP.ULT.D */
20272     { instruction         , 0                   , 0   , 32,
20273        0xfc0007ff, 0xa0000195, &NMD::CMP_LE_D         , 0,
20274        CP1_                },        /* CMP.LE.D */
20275     { instruction         , 0                   , 0   , 32,
20276        0xfc0007ff, 0xa00001d5, &NMD::CMP_ULE_D        , 0,
20277        CP1_                },        /* CMP.ULE.D */
20278     { instruction         , 0                   , 0   , 32,
20279        0xfc0007ff, 0xa0000215, &NMD::CMP_SAF_D        , 0,
20280        CP1_                },        /* CMP.SAF.D */
20281     { instruction         , 0                   , 0   , 32,
20282        0xfc0007ff, 0xa0000255, &NMD::CMP_SUN_D        , 0,
20283        CP1_                },        /* CMP.SUN.D */
20284     { instruction         , 0                   , 0   , 32,
20285        0xfc0007ff, 0xa0000295, &NMD::CMP_SEQ_D        , 0,
20286        CP1_                },        /* CMP.SEQ.D */
20287     { instruction         , 0                   , 0   , 32,
20288        0xfc0007ff, 0xa00002d5, &NMD::CMP_SUEQ_D       , 0,
20289        CP1_                },        /* CMP.SUEQ.D */
20290     { instruction         , 0                   , 0   , 32,
20291        0xfc0007ff, 0xa0000315, &NMD::CMP_SLT_D        , 0,
20292        CP1_                },        /* CMP.SLT.D */
20293     { instruction         , 0                   , 0   , 32,
20294        0xfc0007ff, 0xa0000355, &NMD::CMP_SULT_D       , 0,
20295        CP1_                },        /* CMP.SULT.D */
20296     { instruction         , 0                   , 0   , 32,
20297        0xfc0007ff, 0xa0000395, &NMD::CMP_SLE_D        , 0,
20298        CP1_                },        /* CMP.SLE.D */
20299     { instruction         , 0                   , 0   , 32,
20300        0xfc0007ff, 0xa00003d5, &NMD::CMP_SULE_D       , 0,
20301        CP1_                },        /* CMP.SULE.D */
20302     { reserved_block      , 0                   , 0   , 32,
20303        0xfc0007ff, 0xa0000415, 0                      , 0,
20304        CP1_                },        /* CMP.condn.D~*(16) */
20305     { instruction         , 0                   , 0   , 32,
20306        0xfc0007ff, 0xa0000455, &NMD::CMP_OR_D         , 0,
20307        CP1_                },        /* CMP.OR.D */
20308     { instruction         , 0                   , 0   , 32,
20309        0xfc0007ff, 0xa0000495, &NMD::CMP_UNE_D        , 0,
20310        CP1_                },        /* CMP.UNE.D */
20311     { instruction         , 0                   , 0   , 32,
20312        0xfc0007ff, 0xa00004d5, &NMD::CMP_NE_D         , 0,
20313        CP1_                },        /* CMP.NE.D */
20314     { reserved_block      , 0                   , 0   , 32,
20315        0xfc0007ff, 0xa0000515, 0                      , 0,
20316        CP1_                },        /* CMP.condn.D~*(20) */
20317     { reserved_block      , 0                   , 0   , 32,
20318        0xfc0007ff, 0xa0000555, 0                      , 0,
20319        CP1_                },        /* CMP.condn.D~*(21) */
20320     { reserved_block      , 0                   , 0   , 32,
20321        0xfc0007ff, 0xa0000595, 0                      , 0,
20322        CP1_                },        /* CMP.condn.D~*(22) */
20323     { reserved_block      , 0                   , 0   , 32,
20324        0xfc0007ff, 0xa00005d5, 0                      , 0,
20325        CP1_                },        /* CMP.condn.D~*(23) */
20326     { reserved_block      , 0                   , 0   , 32,
20327        0xfc0007ff, 0xa0000615, 0                      , 0,
20328        CP1_                },        /* CMP.condn.D~*(24) */
20329     { instruction         , 0                   , 0   , 32,
20330        0xfc0007ff, 0xa0000655, &NMD::CMP_SOR_D        , 0,
20331        CP1_                },        /* CMP.SOR.D */
20332     { instruction         , 0                   , 0   , 32,
20333        0xfc0007ff, 0xa0000695, &NMD::CMP_SUNE_D       , 0,
20334        CP1_                },        /* CMP.SUNE.D */
20335     { instruction         , 0                   , 0   , 32,
20336        0xfc0007ff, 0xa00006d5, &NMD::CMP_SNE_D        , 0,
20337        CP1_                },        /* CMP.SNE.D */
20338     { reserved_block      , 0                   , 0   , 32,
20339        0xfc0007ff, 0xa0000715, 0                      , 0,
20340        CP1_                },        /* CMP.condn.D~*(28) */
20341     { reserved_block      , 0                   , 0   , 32,
20342        0xfc0007ff, 0xa0000755, 0                      , 0,
20343        CP1_                },        /* CMP.condn.D~*(29) */
20344     { reserved_block      , 0                   , 0   , 32,
20345        0xfc0007ff, 0xa0000795, 0                      , 0,
20346        CP1_                },        /* CMP.condn.D~*(30) */
20347     { reserved_block      , 0                   , 0   , 32,
20348        0xfc0007ff, 0xa00007d5, 0                      , 0,
20349        CP1_                },        /* CMP.condn.D~*(31) */
20350 };
20351
20352
20353 NMD::Pool NMD::POOL32F_5[8] = {
20354     { pool                , CMP_condn_S         , 32  , 32,
20355        0xfc00003f, 0xa0000005, 0                      , 0,
20356        CP1_                },        /* CMP.condn.S */
20357     { reserved_block      , 0                   , 0   , 32,
20358        0xfc00003f, 0xa000000d, 0                      , 0,
20359        CP1_                },        /* POOL32F_5~*(1) */
20360     { pool                , CMP_condn_D         , 32  , 32,
20361        0xfc00003f, 0xa0000015, 0                      , 0,
20362        CP1_                },        /* CMP.condn.D */
20363     { reserved_block      , 0                   , 0   , 32,
20364        0xfc00003f, 0xa000001d, 0                      , 0,
20365        CP1_                },        /* POOL32F_5~*(3) */
20366     { reserved_block      , 0                   , 0   , 32,
20367        0xfc00003f, 0xa0000025, 0                      , 0,
20368        CP1_                },        /* POOL32F_5~*(4) */
20369     { reserved_block      , 0                   , 0   , 32,
20370        0xfc00003f, 0xa000002d, 0                      , 0,
20371        CP1_                },        /* POOL32F_5~*(5) */
20372     { reserved_block      , 0                   , 0   , 32,
20373        0xfc00003f, 0xa0000035, 0                      , 0,
20374        CP1_                },        /* POOL32F_5~*(6) */
20375     { reserved_block      , 0                   , 0   , 32,
20376        0xfc00003f, 0xa000003d, 0                      , 0,
20377        CP1_                },        /* POOL32F_5~*(7) */
20378 };
20379
20380
20381 NMD::Pool NMD::POOL32F[8] = {
20382     { pool                , POOL32F_0           , 64  , 32,
20383        0xfc000007, 0xa0000000, 0                      , 0,
20384        CP1_                },        /* POOL32F_0 */
20385     { reserved_block      , 0                   , 0   , 32,
20386        0xfc000007, 0xa0000001, 0                      , 0,
20387        CP1_                },        /* POOL32F~*(1) */
20388     { reserved_block      , 0                   , 0   , 32,
20389        0xfc000007, 0xa0000002, 0                      , 0,
20390        CP1_                },        /* POOL32F~*(2) */
20391     { pool                , POOL32F_3           , 8   , 32,
20392        0xfc000007, 0xa0000003, 0                      , 0,
20393        CP1_                },        /* POOL32F_3 */
20394     { reserved_block      , 0                   , 0   , 32,
20395        0xfc000007, 0xa0000004, 0                      , 0,
20396        CP1_                },        /* POOL32F~*(4) */
20397     { pool                , POOL32F_5           , 8   , 32,
20398        0xfc000007, 0xa0000005, 0                      , 0,
20399        CP1_                },        /* POOL32F_5 */
20400     { reserved_block      , 0                   , 0   , 32,
20401        0xfc000007, 0xa0000006, 0                      , 0,
20402        CP1_                },        /* POOL32F~*(6) */
20403     { reserved_block      , 0                   , 0   , 32,
20404        0xfc000007, 0xa0000007, 0                      , 0,
20405        CP1_                },        /* POOL32F~*(7) */
20406 };
20407
20408
20409 NMD::Pool NMD::POOL32S_0[64] = {
20410     { reserved_block      , 0                   , 0   , 32,
20411        0xfc0001ff, 0xc0000000, 0                      , 0,
20412        0x0                 },        /* POOL32S_0~*(0) */
20413     { instruction         , 0                   , 0   , 32,
20414        0xfc0001ff, 0xc0000008, &NMD::DLSA             , 0,
20415        MIPS64_             },        /* DLSA */
20416     { instruction         , 0                   , 0   , 32,
20417        0xfc0001ff, 0xc0000010, &NMD::DSLLV            , 0,
20418        MIPS64_             },        /* DSLLV */
20419     { instruction         , 0                   , 0   , 32,
20420        0xfc0001ff, 0xc0000018, &NMD::DMUL             , 0,
20421        MIPS64_             },        /* DMUL */
20422     { reserved_block      , 0                   , 0   , 32,
20423        0xfc0001ff, 0xc0000020, 0                      , 0,
20424        0x0                 },        /* POOL32S_0~*(4) */
20425     { reserved_block      , 0                   , 0   , 32,
20426        0xfc0001ff, 0xc0000028, 0                      , 0,
20427        0x0                 },        /* POOL32S_0~*(5) */
20428     { reserved_block      , 0                   , 0   , 32,
20429        0xfc0001ff, 0xc0000030, 0                      , 0,
20430        0x0                 },        /* POOL32S_0~*(6) */
20431     { reserved_block      , 0                   , 0   , 32,
20432        0xfc0001ff, 0xc0000038, 0                      , 0,
20433        0x0                 },        /* POOL32S_0~*(7) */
20434     { reserved_block      , 0                   , 0   , 32,
20435        0xfc0001ff, 0xc0000040, 0                      , 0,
20436        0x0                 },        /* POOL32S_0~*(8) */
20437     { reserved_block      , 0                   , 0   , 32,
20438        0xfc0001ff, 0xc0000048, 0                      , 0,
20439        0x0                 },        /* POOL32S_0~*(9) */
20440     { instruction         , 0                   , 0   , 32,
20441        0xfc0001ff, 0xc0000050, &NMD::DSRLV            , 0,
20442        MIPS64_             },        /* DSRLV */
20443     { instruction         , 0                   , 0   , 32,
20444        0xfc0001ff, 0xc0000058, &NMD::DMUH             , 0,
20445        MIPS64_             },        /* DMUH */
20446     { reserved_block      , 0                   , 0   , 32,
20447        0xfc0001ff, 0xc0000060, 0                      , 0,
20448        0x0                 },        /* POOL32S_0~*(12) */
20449     { reserved_block      , 0                   , 0   , 32,
20450        0xfc0001ff, 0xc0000068, 0                      , 0,
20451        0x0                 },        /* POOL32S_0~*(13) */
20452     { reserved_block      , 0                   , 0   , 32,
20453        0xfc0001ff, 0xc0000070, 0                      , 0,
20454        0x0                 },        /* POOL32S_0~*(14) */
20455     { reserved_block      , 0                   , 0   , 32,
20456        0xfc0001ff, 0xc0000078, 0                      , 0,
20457        0x0                 },        /* POOL32S_0~*(15) */
20458     { reserved_block      , 0                   , 0   , 32,
20459        0xfc0001ff, 0xc0000080, 0                      , 0,
20460        0x0                 },        /* POOL32S_0~*(16) */
20461     { reserved_block      , 0                   , 0   , 32,
20462        0xfc0001ff, 0xc0000088, 0                      , 0,
20463        0x0                 },        /* POOL32S_0~*(17) */
20464     { instruction         , 0                   , 0   , 32,
20465        0xfc0001ff, 0xc0000090, &NMD::DSRAV            , 0,
20466        MIPS64_             },        /* DSRAV */
20467     { instruction         , 0                   , 0   , 32,
20468        0xfc0001ff, 0xc0000098, &NMD::DMULU            , 0,
20469        MIPS64_             },        /* DMULU */
20470     { reserved_block      , 0                   , 0   , 32,
20471        0xfc0001ff, 0xc00000a0, 0                      , 0,
20472        0x0                 },        /* POOL32S_0~*(20) */
20473     { reserved_block      , 0                   , 0   , 32,
20474        0xfc0001ff, 0xc00000a8, 0                      , 0,
20475        0x0                 },        /* POOL32S_0~*(21) */
20476     { reserved_block      , 0                   , 0   , 32,
20477        0xfc0001ff, 0xc00000b0, 0                      , 0,
20478        0x0                 },        /* POOL32S_0~*(22) */
20479     { reserved_block      , 0                   , 0   , 32,
20480        0xfc0001ff, 0xc00000b8, 0                      , 0,
20481        0x0                 },        /* POOL32S_0~*(23) */
20482     { reserved_block      , 0                   , 0   , 32,
20483        0xfc0001ff, 0xc00000c0, 0                      , 0,
20484        0x0                 },        /* POOL32S_0~*(24) */
20485     { reserved_block      , 0                   , 0   , 32,
20486        0xfc0001ff, 0xc00000c8, 0                      , 0,
20487        0x0                 },        /* POOL32S_0~*(25) */
20488     { instruction         , 0                   , 0   , 32,
20489        0xfc0001ff, 0xc00000d0, &NMD::DROTRV           , 0,
20490        MIPS64_             },        /* DROTRV */
20491     { instruction         , 0                   , 0   , 32,
20492        0xfc0001ff, 0xc00000d8, &NMD::DMUHU            , 0,
20493        MIPS64_             },        /* DMUHU */
20494     { reserved_block      , 0                   , 0   , 32,
20495        0xfc0001ff, 0xc00000e0, 0                      , 0,
20496        0x0                 },        /* POOL32S_0~*(28) */
20497     { reserved_block      , 0                   , 0   , 32,
20498        0xfc0001ff, 0xc00000e8, 0                      , 0,
20499        0x0                 },        /* POOL32S_0~*(29) */
20500     { reserved_block      , 0                   , 0   , 32,
20501        0xfc0001ff, 0xc00000f0, 0                      , 0,
20502        0x0                 },        /* POOL32S_0~*(30) */
20503     { reserved_block      , 0                   , 0   , 32,
20504        0xfc0001ff, 0xc00000f8, 0                      , 0,
20505        0x0                 },        /* POOL32S_0~*(31) */
20506     { reserved_block      , 0                   , 0   , 32,
20507        0xfc0001ff, 0xc0000100, 0                      , 0,
20508        0x0                 },        /* POOL32S_0~*(32) */
20509     { reserved_block      , 0                   , 0   , 32,
20510        0xfc0001ff, 0xc0000108, 0                      , 0,
20511        0x0                 },        /* POOL32S_0~*(33) */
20512     { instruction         , 0                   , 0   , 32,
20513        0xfc0001ff, 0xc0000110, &NMD::DADD             , 0,
20514        MIPS64_             },        /* DADD */
20515     { instruction         , 0                   , 0   , 32,
20516        0xfc0001ff, 0xc0000118, &NMD::DDIV             , 0,
20517        MIPS64_             },        /* DDIV */
20518     { reserved_block      , 0                   , 0   , 32,
20519        0xfc0001ff, 0xc0000120, 0                      , 0,
20520        0x0                 },        /* POOL32S_0~*(36) */
20521     { reserved_block      , 0                   , 0   , 32,
20522        0xfc0001ff, 0xc0000128, 0                      , 0,
20523        0x0                 },        /* POOL32S_0~*(37) */
20524     { reserved_block      , 0                   , 0   , 32,
20525        0xfc0001ff, 0xc0000130, 0                      , 0,
20526        0x0                 },        /* POOL32S_0~*(38) */
20527     { reserved_block      , 0                   , 0   , 32,
20528        0xfc0001ff, 0xc0000138, 0                      , 0,
20529        0x0                 },        /* POOL32S_0~*(39) */
20530     { reserved_block      , 0                   , 0   , 32,
20531        0xfc0001ff, 0xc0000140, 0                      , 0,
20532        0x0                 },        /* POOL32S_0~*(40) */
20533     { reserved_block      , 0                   , 0   , 32,
20534        0xfc0001ff, 0xc0000148, 0                      , 0,
20535        0x0                 },        /* POOL32S_0~*(41) */
20536     { instruction         , 0                   , 0   , 32,
20537        0xfc0001ff, 0xc0000150, &NMD::DADDU            , 0,
20538        MIPS64_             },        /* DADDU */
20539     { instruction         , 0                   , 0   , 32,
20540        0xfc0001ff, 0xc0000158, &NMD::DMOD             , 0,
20541        MIPS64_             },        /* DMOD */
20542     { reserved_block      , 0                   , 0   , 32,
20543        0xfc0001ff, 0xc0000160, 0                      , 0,
20544        0x0                 },        /* POOL32S_0~*(44) */
20545     { reserved_block      , 0                   , 0   , 32,
20546        0xfc0001ff, 0xc0000168, 0                      , 0,
20547        0x0                 },        /* POOL32S_0~*(45) */
20548     { reserved_block      , 0                   , 0   , 32,
20549        0xfc0001ff, 0xc0000170, 0                      , 0,
20550        0x0                 },        /* POOL32S_0~*(46) */
20551     { reserved_block      , 0                   , 0   , 32,
20552        0xfc0001ff, 0xc0000178, 0                      , 0,
20553        0x0                 },        /* POOL32S_0~*(47) */
20554     { reserved_block      , 0                   , 0   , 32,
20555        0xfc0001ff, 0xc0000180, 0                      , 0,
20556        0x0                 },        /* POOL32S_0~*(48) */
20557     { reserved_block      , 0                   , 0   , 32,
20558        0xfc0001ff, 0xc0000188, 0                      , 0,
20559        0x0                 },        /* POOL32S_0~*(49) */
20560     { instruction         , 0                   , 0   , 32,
20561        0xfc0001ff, 0xc0000190, &NMD::DSUB             , 0,
20562        MIPS64_             },        /* DSUB */
20563     { instruction         , 0                   , 0   , 32,
20564        0xfc0001ff, 0xc0000198, &NMD::DDIVU            , 0,
20565        MIPS64_             },        /* DDIVU */
20566     { reserved_block      , 0                   , 0   , 32,
20567        0xfc0001ff, 0xc00001a0, 0                      , 0,
20568        0x0                 },        /* POOL32S_0~*(52) */
20569     { reserved_block      , 0                   , 0   , 32,
20570        0xfc0001ff, 0xc00001a8, 0                      , 0,
20571        0x0                 },        /* POOL32S_0~*(53) */
20572     { reserved_block      , 0                   , 0   , 32,
20573        0xfc0001ff, 0xc00001b0, 0                      , 0,
20574        0x0                 },        /* POOL32S_0~*(54) */
20575     { reserved_block      , 0                   , 0   , 32,
20576        0xfc0001ff, 0xc00001b8, 0                      , 0,
20577        0x0                 },        /* POOL32S_0~*(55) */
20578     { reserved_block      , 0                   , 0   , 32,
20579        0xfc0001ff, 0xc00001c0, 0                      , 0,
20580        0x0                 },        /* POOL32S_0~*(56) */
20581     { reserved_block      , 0                   , 0   , 32,
20582        0xfc0001ff, 0xc00001c8, 0                      , 0,
20583        0x0                 },        /* POOL32S_0~*(57) */
20584     { instruction         , 0                   , 0   , 32,
20585        0xfc0001ff, 0xc00001d0, &NMD::DSUBU            , 0,
20586        MIPS64_             },        /* DSUBU */
20587     { instruction         , 0                   , 0   , 32,
20588        0xfc0001ff, 0xc00001d8, &NMD::DMODU            , 0,
20589        MIPS64_             },        /* DMODU */
20590     { reserved_block      , 0                   , 0   , 32,
20591        0xfc0001ff, 0xc00001e0, 0                      , 0,
20592        0x0                 },        /* POOL32S_0~*(60) */
20593     { reserved_block      , 0                   , 0   , 32,
20594        0xfc0001ff, 0xc00001e8, 0                      , 0,
20595        0x0                 },        /* POOL32S_0~*(61) */
20596     { reserved_block      , 0                   , 0   , 32,
20597        0xfc0001ff, 0xc00001f0, 0                      , 0,
20598        0x0                 },        /* POOL32S_0~*(62) */
20599     { reserved_block      , 0                   , 0   , 32,
20600        0xfc0001ff, 0xc00001f8, 0                      , 0,
20601        0x0                 },        /* POOL32S_0~*(63) */
20602 };
20603
20604
20605 NMD::Pool NMD::POOL32Sxf_4[128] = {
20606     { reserved_block      , 0                   , 0   , 32,
20607        0xfc00ffff, 0xc000013c, 0                      , 0,
20608        0x0                 },        /* POOL32Sxf_4~*(0) */
20609     { reserved_block      , 0                   , 0   , 32,
20610        0xfc00ffff, 0xc000033c, 0                      , 0,
20611        0x0                 },        /* POOL32Sxf_4~*(1) */
20612     { reserved_block      , 0                   , 0   , 32,
20613        0xfc00ffff, 0xc000053c, 0                      , 0,
20614        0x0                 },        /* POOL32Sxf_4~*(2) */
20615     { reserved_block      , 0                   , 0   , 32,
20616        0xfc00ffff, 0xc000073c, 0                      , 0,
20617        0x0                 },        /* POOL32Sxf_4~*(3) */
20618     { reserved_block      , 0                   , 0   , 32,
20619        0xfc00ffff, 0xc000093c, 0                      , 0,
20620        0x0                 },        /* POOL32Sxf_4~*(4) */
20621     { reserved_block      , 0                   , 0   , 32,
20622        0xfc00ffff, 0xc0000b3c, 0                      , 0,
20623        0x0                 },        /* POOL32Sxf_4~*(5) */
20624     { reserved_block      , 0                   , 0   , 32,
20625        0xfc00ffff, 0xc0000d3c, 0                      , 0,
20626        0x0                 },        /* POOL32Sxf_4~*(6) */
20627     { reserved_block      , 0                   , 0   , 32,
20628        0xfc00ffff, 0xc0000f3c, 0                      , 0,
20629        0x0                 },        /* POOL32Sxf_4~*(7) */
20630     { reserved_block      , 0                   , 0   , 32,
20631        0xfc00ffff, 0xc000113c, 0                      , 0,
20632        0x0                 },        /* POOL32Sxf_4~*(8) */
20633     { reserved_block      , 0                   , 0   , 32,
20634        0xfc00ffff, 0xc000133c, 0                      , 0,
20635        0x0                 },        /* POOL32Sxf_4~*(9) */
20636     { reserved_block      , 0                   , 0   , 32,
20637        0xfc00ffff, 0xc000153c, 0                      , 0,
20638        0x0                 },        /* POOL32Sxf_4~*(10) */
20639     { reserved_block      , 0                   , 0   , 32,
20640        0xfc00ffff, 0xc000173c, 0                      , 0,
20641        0x0                 },        /* POOL32Sxf_4~*(11) */
20642     { reserved_block      , 0                   , 0   , 32,
20643        0xfc00ffff, 0xc000193c, 0                      , 0,
20644        0x0                 },        /* POOL32Sxf_4~*(12) */
20645     { reserved_block      , 0                   , 0   , 32,
20646        0xfc00ffff, 0xc0001b3c, 0                      , 0,
20647        0x0                 },        /* POOL32Sxf_4~*(13) */
20648     { reserved_block      , 0                   , 0   , 32,
20649        0xfc00ffff, 0xc0001d3c, 0                      , 0,
20650        0x0                 },        /* POOL32Sxf_4~*(14) */
20651     { reserved_block      , 0                   , 0   , 32,
20652        0xfc00ffff, 0xc0001f3c, 0                      , 0,
20653        0x0                 },        /* POOL32Sxf_4~*(15) */
20654     { reserved_block      , 0                   , 0   , 32,
20655        0xfc00ffff, 0xc000213c, 0                      , 0,
20656        0x0                 },        /* POOL32Sxf_4~*(16) */
20657     { reserved_block      , 0                   , 0   , 32,
20658        0xfc00ffff, 0xc000233c, 0                      , 0,
20659        0x0                 },        /* POOL32Sxf_4~*(17) */
20660     { reserved_block      , 0                   , 0   , 32,
20661        0xfc00ffff, 0xc000253c, 0                      , 0,
20662        0x0                 },        /* POOL32Sxf_4~*(18) */
20663     { reserved_block      , 0                   , 0   , 32,
20664        0xfc00ffff, 0xc000273c, 0                      , 0,
20665        0x0                 },        /* POOL32Sxf_4~*(19) */
20666     { reserved_block      , 0                   , 0   , 32,
20667        0xfc00ffff, 0xc000293c, 0                      , 0,
20668        0x0                 },        /* POOL32Sxf_4~*(20) */
20669     { reserved_block      , 0                   , 0   , 32,
20670        0xfc00ffff, 0xc0002b3c, 0                      , 0,
20671        0x0                 },        /* POOL32Sxf_4~*(21) */
20672     { reserved_block      , 0                   , 0   , 32,
20673        0xfc00ffff, 0xc0002d3c, 0                      , 0,
20674        0x0                 },        /* POOL32Sxf_4~*(22) */
20675     { reserved_block      , 0                   , 0   , 32,
20676        0xfc00ffff, 0xc0002f3c, 0                      , 0,
20677        0x0                 },        /* POOL32Sxf_4~*(23) */
20678     { reserved_block      , 0                   , 0   , 32,
20679        0xfc00ffff, 0xc000313c, 0                      , 0,
20680        0x0                 },        /* POOL32Sxf_4~*(24) */
20681     { reserved_block      , 0                   , 0   , 32,
20682        0xfc00ffff, 0xc000333c, 0                      , 0,
20683        0x0                 },        /* POOL32Sxf_4~*(25) */
20684     { reserved_block      , 0                   , 0   , 32,
20685        0xfc00ffff, 0xc000353c, 0                      , 0,
20686        0x0                 },        /* POOL32Sxf_4~*(26) */
20687     { reserved_block      , 0                   , 0   , 32,
20688        0xfc00ffff, 0xc000373c, 0                      , 0,
20689        0x0                 },        /* POOL32Sxf_4~*(27) */
20690     { reserved_block      , 0                   , 0   , 32,
20691        0xfc00ffff, 0xc000393c, 0                      , 0,
20692        0x0                 },        /* POOL32Sxf_4~*(28) */
20693     { reserved_block      , 0                   , 0   , 32,
20694        0xfc00ffff, 0xc0003b3c, 0                      , 0,
20695        0x0                 },        /* POOL32Sxf_4~*(29) */
20696     { reserved_block      , 0                   , 0   , 32,
20697        0xfc00ffff, 0xc0003d3c, 0                      , 0,
20698        0x0                 },        /* POOL32Sxf_4~*(30) */
20699     { reserved_block      , 0                   , 0   , 32,
20700        0xfc00ffff, 0xc0003f3c, 0                      , 0,
20701        0x0                 },        /* POOL32Sxf_4~*(31) */
20702     { reserved_block      , 0                   , 0   , 32,
20703        0xfc00ffff, 0xc000413c, 0                      , 0,
20704        0x0                 },        /* POOL32Sxf_4~*(32) */
20705     { reserved_block      , 0                   , 0   , 32,
20706        0xfc00ffff, 0xc000433c, 0                      , 0,
20707        0x0                 },        /* POOL32Sxf_4~*(33) */
20708     { reserved_block      , 0                   , 0   , 32,
20709        0xfc00ffff, 0xc000453c, 0                      , 0,
20710        0x0                 },        /* POOL32Sxf_4~*(34) */
20711     { reserved_block      , 0                   , 0   , 32,
20712        0xfc00ffff, 0xc000473c, 0                      , 0,
20713        0x0                 },        /* POOL32Sxf_4~*(35) */
20714     { reserved_block      , 0                   , 0   , 32,
20715        0xfc00ffff, 0xc000493c, 0                      , 0,
20716        0x0                 },        /* POOL32Sxf_4~*(36) */
20717     { instruction         , 0                   , 0   , 32,
20718        0xfc00ffff, 0xc0004b3c, &NMD::DCLO             , 0,
20719        MIPS64_             },        /* DCLO */
20720     { reserved_block      , 0                   , 0   , 32,
20721        0xfc00ffff, 0xc0004d3c, 0                      , 0,
20722        0x0                 },        /* POOL32Sxf_4~*(38) */
20723     { reserved_block      , 0                   , 0   , 32,
20724        0xfc00ffff, 0xc0004f3c, 0                      , 0,
20725        0x0                 },        /* POOL32Sxf_4~*(39) */
20726     { reserved_block      , 0                   , 0   , 32,
20727        0xfc00ffff, 0xc000513c, 0                      , 0,
20728        0x0                 },        /* POOL32Sxf_4~*(40) */
20729     { reserved_block      , 0                   , 0   , 32,
20730        0xfc00ffff, 0xc000533c, 0                      , 0,
20731        0x0                 },        /* POOL32Sxf_4~*(41) */
20732     { reserved_block      , 0                   , 0   , 32,
20733        0xfc00ffff, 0xc000553c, 0                      , 0,
20734        0x0                 },        /* POOL32Sxf_4~*(42) */
20735     { reserved_block      , 0                   , 0   , 32,
20736        0xfc00ffff, 0xc000573c, 0                      , 0,
20737        0x0                 },        /* POOL32Sxf_4~*(43) */
20738     { reserved_block      , 0                   , 0   , 32,
20739        0xfc00ffff, 0xc000593c, 0                      , 0,
20740        0x0                 },        /* POOL32Sxf_4~*(44) */
20741     { instruction         , 0                   , 0   , 32,
20742        0xfc00ffff, 0xc0005b3c, &NMD::DCLZ             , 0,
20743        MIPS64_             },        /* DCLZ */
20744     { reserved_block      , 0                   , 0   , 32,
20745        0xfc00ffff, 0xc0005d3c, 0                      , 0,
20746        0x0                 },        /* POOL32Sxf_4~*(46) */
20747     { reserved_block      , 0                   , 0   , 32,
20748        0xfc00ffff, 0xc0005f3c, 0                      , 0,
20749        0x0                 },        /* POOL32Sxf_4~*(47) */
20750     { reserved_block      , 0                   , 0   , 32,
20751        0xfc00ffff, 0xc000613c, 0                      , 0,
20752        0x0                 },        /* POOL32Sxf_4~*(48) */
20753     { reserved_block      , 0                   , 0   , 32,
20754        0xfc00ffff, 0xc000633c, 0                      , 0,
20755        0x0                 },        /* POOL32Sxf_4~*(49) */
20756     { reserved_block      , 0                   , 0   , 32,
20757        0xfc00ffff, 0xc000653c, 0                      , 0,
20758        0x0                 },        /* POOL32Sxf_4~*(50) */
20759     { reserved_block      , 0                   , 0   , 32,
20760        0xfc00ffff, 0xc000673c, 0                      , 0,
20761        0x0                 },        /* POOL32Sxf_4~*(51) */
20762     { reserved_block      , 0                   , 0   , 32,
20763        0xfc00ffff, 0xc000693c, 0                      , 0,
20764        0x0                 },        /* POOL32Sxf_4~*(52) */
20765     { reserved_block      , 0                   , 0   , 32,
20766        0xfc00ffff, 0xc0006b3c, 0                      , 0,
20767        0x0                 },        /* POOL32Sxf_4~*(53) */
20768     { reserved_block      , 0                   , 0   , 32,
20769        0xfc00ffff, 0xc0006d3c, 0                      , 0,
20770        0x0                 },        /* POOL32Sxf_4~*(54) */
20771     { reserved_block      , 0                   , 0   , 32,
20772        0xfc00ffff, 0xc0006f3c, 0                      , 0,
20773        0x0                 },        /* POOL32Sxf_4~*(55) */
20774     { reserved_block      , 0                   , 0   , 32,
20775        0xfc00ffff, 0xc000713c, 0                      , 0,
20776        0x0                 },        /* POOL32Sxf_4~*(56) */
20777     { reserved_block      , 0                   , 0   , 32,
20778        0xfc00ffff, 0xc000733c, 0                      , 0,
20779        0x0                 },        /* POOL32Sxf_4~*(57) */
20780     { reserved_block      , 0                   , 0   , 32,
20781        0xfc00ffff, 0xc000753c, 0                      , 0,
20782        0x0                 },        /* POOL32Sxf_4~*(58) */
20783     { reserved_block      , 0                   , 0   , 32,
20784        0xfc00ffff, 0xc000773c, 0                      , 0,
20785        0x0                 },        /* POOL32Sxf_4~*(59) */
20786     { reserved_block      , 0                   , 0   , 32,
20787        0xfc00ffff, 0xc000793c, 0                      , 0,
20788        0x0                 },        /* POOL32Sxf_4~*(60) */
20789     { reserved_block      , 0                   , 0   , 32,
20790        0xfc00ffff, 0xc0007b3c, 0                      , 0,
20791        0x0                 },        /* POOL32Sxf_4~*(61) */
20792     { reserved_block      , 0                   , 0   , 32,
20793        0xfc00ffff, 0xc0007d3c, 0                      , 0,
20794        0x0                 },        /* POOL32Sxf_4~*(62) */
20795     { reserved_block      , 0                   , 0   , 32,
20796        0xfc00ffff, 0xc0007f3c, 0                      , 0,
20797        0x0                 },        /* POOL32Sxf_4~*(63) */
20798     { reserved_block      , 0                   , 0   , 32,
20799        0xfc00ffff, 0xc000813c, 0                      , 0,
20800        0x0                 },        /* POOL32Sxf_4~*(64) */
20801     { reserved_block      , 0                   , 0   , 32,
20802        0xfc00ffff, 0xc000833c, 0                      , 0,
20803        0x0                 },        /* POOL32Sxf_4~*(65) */
20804     { reserved_block      , 0                   , 0   , 32,
20805        0xfc00ffff, 0xc000853c, 0                      , 0,
20806        0x0                 },        /* POOL32Sxf_4~*(66) */
20807     { reserved_block      , 0                   , 0   , 32,
20808        0xfc00ffff, 0xc000873c, 0                      , 0,
20809        0x0                 },        /* POOL32Sxf_4~*(67) */
20810     { reserved_block      , 0                   , 0   , 32,
20811        0xfc00ffff, 0xc000893c, 0                      , 0,
20812        0x0                 },        /* POOL32Sxf_4~*(68) */
20813     { reserved_block      , 0                   , 0   , 32,
20814        0xfc00ffff, 0xc0008b3c, 0                      , 0,
20815        0x0                 },        /* POOL32Sxf_4~*(69) */
20816     { reserved_block      , 0                   , 0   , 32,
20817        0xfc00ffff, 0xc0008d3c, 0                      , 0,
20818        0x0                 },        /* POOL32Sxf_4~*(70) */
20819     { reserved_block      , 0                   , 0   , 32,
20820        0xfc00ffff, 0xc0008f3c, 0                      , 0,
20821        0x0                 },        /* POOL32Sxf_4~*(71) */
20822     { reserved_block      , 0                   , 0   , 32,
20823        0xfc00ffff, 0xc000913c, 0                      , 0,
20824        0x0                 },        /* POOL32Sxf_4~*(72) */
20825     { reserved_block      , 0                   , 0   , 32,
20826        0xfc00ffff, 0xc000933c, 0                      , 0,
20827        0x0                 },        /* POOL32Sxf_4~*(73) */
20828     { reserved_block      , 0                   , 0   , 32,
20829        0xfc00ffff, 0xc000953c, 0                      , 0,
20830        0x0                 },        /* POOL32Sxf_4~*(74) */
20831     { reserved_block      , 0                   , 0   , 32,
20832        0xfc00ffff, 0xc000973c, 0                      , 0,
20833        0x0                 },        /* POOL32Sxf_4~*(75) */
20834     { reserved_block      , 0                   , 0   , 32,
20835        0xfc00ffff, 0xc000993c, 0                      , 0,
20836        0x0                 },        /* POOL32Sxf_4~*(76) */
20837     { reserved_block      , 0                   , 0   , 32,
20838        0xfc00ffff, 0xc0009b3c, 0                      , 0,
20839        0x0                 },        /* POOL32Sxf_4~*(77) */
20840     { reserved_block      , 0                   , 0   , 32,
20841        0xfc00ffff, 0xc0009d3c, 0                      , 0,
20842        0x0                 },        /* POOL32Sxf_4~*(78) */
20843     { reserved_block      , 0                   , 0   , 32,
20844        0xfc00ffff, 0xc0009f3c, 0                      , 0,
20845        0x0                 },        /* POOL32Sxf_4~*(79) */
20846     { reserved_block      , 0                   , 0   , 32,
20847        0xfc00ffff, 0xc000a13c, 0                      , 0,
20848        0x0                 },        /* POOL32Sxf_4~*(80) */
20849     { reserved_block      , 0                   , 0   , 32,
20850        0xfc00ffff, 0xc000a33c, 0                      , 0,
20851        0x0                 },        /* POOL32Sxf_4~*(81) */
20852     { reserved_block      , 0                   , 0   , 32,
20853        0xfc00ffff, 0xc000a53c, 0                      , 0,
20854        0x0                 },        /* POOL32Sxf_4~*(82) */
20855     { reserved_block      , 0                   , 0   , 32,
20856        0xfc00ffff, 0xc000a73c, 0                      , 0,
20857        0x0                 },        /* POOL32Sxf_4~*(83) */
20858     { reserved_block      , 0                   , 0   , 32,
20859        0xfc00ffff, 0xc000a93c, 0                      , 0,
20860        0x0                 },        /* POOL32Sxf_4~*(84) */
20861     { reserved_block      , 0                   , 0   , 32,
20862        0xfc00ffff, 0xc000ab3c, 0                      , 0,
20863        0x0                 },        /* POOL32Sxf_4~*(85) */
20864     { reserved_block      , 0                   , 0   , 32,
20865        0xfc00ffff, 0xc000ad3c, 0                      , 0,
20866        0x0                 },        /* POOL32Sxf_4~*(86) */
20867     { reserved_block      , 0                   , 0   , 32,
20868        0xfc00ffff, 0xc000af3c, 0                      , 0,
20869        0x0                 },        /* POOL32Sxf_4~*(87) */
20870     { reserved_block      , 0                   , 0   , 32,
20871        0xfc00ffff, 0xc000b13c, 0                      , 0,
20872        0x0                 },        /* POOL32Sxf_4~*(88) */
20873     { reserved_block      , 0                   , 0   , 32,
20874        0xfc00ffff, 0xc000b33c, 0                      , 0,
20875        0x0                 },        /* POOL32Sxf_4~*(89) */
20876     { reserved_block      , 0                   , 0   , 32,
20877        0xfc00ffff, 0xc000b53c, 0                      , 0,
20878        0x0                 },        /* POOL32Sxf_4~*(90) */
20879     { reserved_block      , 0                   , 0   , 32,
20880        0xfc00ffff, 0xc000b73c, 0                      , 0,
20881        0x0                 },        /* POOL32Sxf_4~*(91) */
20882     { reserved_block      , 0                   , 0   , 32,
20883        0xfc00ffff, 0xc000b93c, 0                      , 0,
20884        0x0                 },        /* POOL32Sxf_4~*(92) */
20885     { reserved_block      , 0                   , 0   , 32,
20886        0xfc00ffff, 0xc000bb3c, 0                      , 0,
20887        0x0                 },        /* POOL32Sxf_4~*(93) */
20888     { reserved_block      , 0                   , 0   , 32,
20889        0xfc00ffff, 0xc000bd3c, 0                      , 0,
20890        0x0                 },        /* POOL32Sxf_4~*(94) */
20891     { reserved_block      , 0                   , 0   , 32,
20892        0xfc00ffff, 0xc000bf3c, 0                      , 0,
20893        0x0                 },        /* POOL32Sxf_4~*(95) */
20894     { reserved_block      , 0                   , 0   , 32,
20895        0xfc00ffff, 0xc000c13c, 0                      , 0,
20896        0x0                 },        /* POOL32Sxf_4~*(96) */
20897     { reserved_block      , 0                   , 0   , 32,
20898        0xfc00ffff, 0xc000c33c, 0                      , 0,
20899        0x0                 },        /* POOL32Sxf_4~*(97) */
20900     { reserved_block      , 0                   , 0   , 32,
20901        0xfc00ffff, 0xc000c53c, 0                      , 0,
20902        0x0                 },        /* POOL32Sxf_4~*(98) */
20903     { reserved_block      , 0                   , 0   , 32,
20904        0xfc00ffff, 0xc000c73c, 0                      , 0,
20905        0x0                 },        /* POOL32Sxf_4~*(99) */
20906     { reserved_block      , 0                   , 0   , 32,
20907        0xfc00ffff, 0xc000c93c, 0                      , 0,
20908        0x0                 },        /* POOL32Sxf_4~*(100) */
20909     { reserved_block      , 0                   , 0   , 32,
20910        0xfc00ffff, 0xc000cb3c, 0                      , 0,
20911        0x0                 },        /* POOL32Sxf_4~*(101) */
20912     { reserved_block      , 0                   , 0   , 32,
20913        0xfc00ffff, 0xc000cd3c, 0                      , 0,
20914        0x0                 },        /* POOL32Sxf_4~*(102) */
20915     { reserved_block      , 0                   , 0   , 32,
20916        0xfc00ffff, 0xc000cf3c, 0                      , 0,
20917        0x0                 },        /* POOL32Sxf_4~*(103) */
20918     { reserved_block      , 0                   , 0   , 32,
20919        0xfc00ffff, 0xc000d13c, 0                      , 0,
20920        0x0                 },        /* POOL32Sxf_4~*(104) */
20921     { reserved_block      , 0                   , 0   , 32,
20922        0xfc00ffff, 0xc000d33c, 0                      , 0,
20923        0x0                 },        /* POOL32Sxf_4~*(105) */
20924     { reserved_block      , 0                   , 0   , 32,
20925        0xfc00ffff, 0xc000d53c, 0                      , 0,
20926        0x0                 },        /* POOL32Sxf_4~*(106) */
20927     { reserved_block      , 0                   , 0   , 32,
20928        0xfc00ffff, 0xc000d73c, 0                      , 0,
20929        0x0                 },        /* POOL32Sxf_4~*(107) */
20930     { reserved_block      , 0                   , 0   , 32,
20931        0xfc00ffff, 0xc000d93c, 0                      , 0,
20932        0x0                 },        /* POOL32Sxf_4~*(108) */
20933     { reserved_block      , 0                   , 0   , 32,
20934        0xfc00ffff, 0xc000db3c, 0                      , 0,
20935        0x0                 },        /* POOL32Sxf_4~*(109) */
20936     { reserved_block      , 0                   , 0   , 32,
20937        0xfc00ffff, 0xc000dd3c, 0                      , 0,
20938        0x0                 },        /* POOL32Sxf_4~*(110) */
20939     { reserved_block      , 0                   , 0   , 32,
20940        0xfc00ffff, 0xc000df3c, 0                      , 0,
20941        0x0                 },        /* POOL32Sxf_4~*(111) */
20942     { reserved_block      , 0                   , 0   , 32,
20943        0xfc00ffff, 0xc000e13c, 0                      , 0,
20944        0x0                 },        /* POOL32Sxf_4~*(112) */
20945     { reserved_block      , 0                   , 0   , 32,
20946        0xfc00ffff, 0xc000e33c, 0                      , 0,
20947        0x0                 },        /* POOL32Sxf_4~*(113) */
20948     { reserved_block      , 0                   , 0   , 32,
20949        0xfc00ffff, 0xc000e53c, 0                      , 0,
20950        0x0                 },        /* POOL32Sxf_4~*(114) */
20951     { reserved_block      , 0                   , 0   , 32,
20952        0xfc00ffff, 0xc000e73c, 0                      , 0,
20953        0x0                 },        /* POOL32Sxf_4~*(115) */
20954     { reserved_block      , 0                   , 0   , 32,
20955        0xfc00ffff, 0xc000e93c, 0                      , 0,
20956        0x0                 },        /* POOL32Sxf_4~*(116) */
20957     { reserved_block      , 0                   , 0   , 32,
20958        0xfc00ffff, 0xc000eb3c, 0                      , 0,
20959        0x0                 },        /* POOL32Sxf_4~*(117) */
20960     { reserved_block      , 0                   , 0   , 32,
20961        0xfc00ffff, 0xc000ed3c, 0                      , 0,
20962        0x0                 },        /* POOL32Sxf_4~*(118) */
20963     { reserved_block      , 0                   , 0   , 32,
20964        0xfc00ffff, 0xc000ef3c, 0                      , 0,
20965        0x0                 },        /* POOL32Sxf_4~*(119) */
20966     { reserved_block      , 0                   , 0   , 32,
20967        0xfc00ffff, 0xc000f13c, 0                      , 0,
20968        0x0                 },        /* POOL32Sxf_4~*(120) */
20969     { reserved_block      , 0                   , 0   , 32,
20970        0xfc00ffff, 0xc000f33c, 0                      , 0,
20971        0x0                 },        /* POOL32Sxf_4~*(121) */
20972     { reserved_block      , 0                   , 0   , 32,
20973        0xfc00ffff, 0xc000f53c, 0                      , 0,
20974        0x0                 },        /* POOL32Sxf_4~*(122) */
20975     { reserved_block      , 0                   , 0   , 32,
20976        0xfc00ffff, 0xc000f73c, 0                      , 0,
20977        0x0                 },        /* POOL32Sxf_4~*(123) */
20978     { reserved_block      , 0                   , 0   , 32,
20979        0xfc00ffff, 0xc000f93c, 0                      , 0,
20980        0x0                 },        /* POOL32Sxf_4~*(124) */
20981     { reserved_block      , 0                   , 0   , 32,
20982        0xfc00ffff, 0xc000fb3c, 0                      , 0,
20983        0x0                 },        /* POOL32Sxf_4~*(125) */
20984     { reserved_block      , 0                   , 0   , 32,
20985        0xfc00ffff, 0xc000fd3c, 0                      , 0,
20986        0x0                 },        /* POOL32Sxf_4~*(126) */
20987     { reserved_block      , 0                   , 0   , 32,
20988        0xfc00ffff, 0xc000ff3c, 0                      , 0,
20989        0x0                 },        /* POOL32Sxf_4~*(127) */
20990 };
20991
20992
20993 NMD::Pool NMD::POOL32Sxf[8] = {
20994     { reserved_block      , 0                   , 0   , 32,
20995        0xfc0001ff, 0xc000003c, 0                      , 0,
20996        0x0                 },        /* POOL32Sxf~*(0) */
20997     { reserved_block      , 0                   , 0   , 32,
20998        0xfc0001ff, 0xc000007c, 0                      , 0,
20999        0x0                 },        /* POOL32Sxf~*(1) */
21000     { reserved_block      , 0                   , 0   , 32,
21001        0xfc0001ff, 0xc00000bc, 0                      , 0,
21002        0x0                 },        /* POOL32Sxf~*(2) */
21003     { reserved_block      , 0                   , 0   , 32,
21004        0xfc0001ff, 0xc00000fc, 0                      , 0,
21005        0x0                 },        /* POOL32Sxf~*(3) */
21006     { pool                , POOL32Sxf_4         , 128 , 32,
21007        0xfc0001ff, 0xc000013c, 0                      , 0,
21008        0x0                 },        /* POOL32Sxf_4 */
21009     { reserved_block      , 0                   , 0   , 32,
21010        0xfc0001ff, 0xc000017c, 0                      , 0,
21011        0x0                 },        /* POOL32Sxf~*(5) */
21012     { reserved_block      , 0                   , 0   , 32,
21013        0xfc0001ff, 0xc00001bc, 0                      , 0,
21014        0x0                 },        /* POOL32Sxf~*(6) */
21015     { reserved_block      , 0                   , 0   , 32,
21016        0xfc0001ff, 0xc00001fc, 0                      , 0,
21017        0x0                 },        /* POOL32Sxf~*(7) */
21018 };
21019
21020
21021 NMD::Pool NMD::POOL32S_4[8] = {
21022     { instruction         , 0                   , 0   , 32,
21023        0xfc00003f, 0xc0000004, &NMD::EXTD             , 0,
21024        MIPS64_             },        /* EXTD */
21025     { instruction         , 0                   , 0   , 32,
21026        0xfc00003f, 0xc000000c, &NMD::EXTD32           , 0,
21027        MIPS64_             },        /* EXTD32 */
21028     { reserved_block      , 0                   , 0   , 32,
21029        0xfc00003f, 0xc0000014, 0                      , 0,
21030        0x0                 },        /* POOL32S_4~*(2) */
21031     { reserved_block      , 0                   , 0   , 32,
21032        0xfc00003f, 0xc000001c, 0                      , 0,
21033        0x0                 },        /* POOL32S_4~*(3) */
21034     { reserved_block      , 0                   , 0   , 32,
21035        0xfc00003f, 0xc0000024, 0                      , 0,
21036        0x0                 },        /* POOL32S_4~*(4) */
21037     { reserved_block      , 0                   , 0   , 32,
21038        0xfc00003f, 0xc000002c, 0                      , 0,
21039        0x0                 },        /* POOL32S_4~*(5) */
21040     { reserved_block      , 0                   , 0   , 32,
21041        0xfc00003f, 0xc0000034, 0                      , 0,
21042        0x0                 },        /* POOL32S_4~*(6) */
21043     { pool                , POOL32Sxf           , 8   , 32,
21044        0xfc00003f, 0xc000003c, 0                      , 0,
21045        0x0                 },        /* POOL32Sxf */
21046 };
21047
21048
21049 NMD::Pool NMD::POOL32S[8] = {
21050     { pool                , POOL32S_0           , 64  , 32,
21051        0xfc000007, 0xc0000000, 0                      , 0,
21052        0x0                 },        /* POOL32S_0 */
21053     { reserved_block      , 0                   , 0   , 32,
21054        0xfc000007, 0xc0000001, 0                      , 0,
21055        0x0                 },        /* POOL32S~*(1) */
21056     { reserved_block      , 0                   , 0   , 32,
21057        0xfc000007, 0xc0000002, 0                      , 0,
21058        0x0                 },        /* POOL32S~*(2) */
21059     { reserved_block      , 0                   , 0   , 32,
21060        0xfc000007, 0xc0000003, 0                      , 0,
21061        0x0                 },        /* POOL32S~*(3) */
21062     { pool                , POOL32S_4           , 8   , 32,
21063        0xfc000007, 0xc0000004, 0                      , 0,
21064        0x0                 },        /* POOL32S_4 */
21065     { reserved_block      , 0                   , 0   , 32,
21066        0xfc000007, 0xc0000005, 0                      , 0,
21067        0x0                 },        /* POOL32S~*(5) */
21068     { reserved_block      , 0                   , 0   , 32,
21069        0xfc000007, 0xc0000006, 0                      , 0,
21070        0x0                 },        /* POOL32S~*(6) */
21071     { reserved_block      , 0                   , 0   , 32,
21072        0xfc000007, 0xc0000007, 0                      , 0,
21073        0x0                 },        /* POOL32S~*(7) */
21074 };
21075
21076
21077 NMD::Pool NMD::P_LUI[2] = {
21078     { instruction         , 0                   , 0   , 32,
21079        0xfc000002, 0xe0000000, &NMD::LUI              , 0,
21080        0x0                 },        /* LUI */
21081     { instruction         , 0                   , 0   , 32,
21082        0xfc000002, 0xe0000002, &NMD::ALUIPC           , 0,
21083        0x0                 },        /* ALUIPC */
21084 };
21085
21086
21087 NMD::Pool NMD::P_GP_LH[2] = {
21088     { instruction         , 0                   , 0   , 32,
21089        0xfc1c0001, 0x44100000, &NMD::LH_GP_           , 0,
21090        0x0                 },        /* LH[GP] */
21091     { instruction         , 0                   , 0   , 32,
21092        0xfc1c0001, 0x44100001, &NMD::LHU_GP_          , 0,
21093        0x0                 },        /* LHU[GP] */
21094 };
21095
21096
21097 NMD::Pool NMD::P_GP_SH[2] = {
21098     { instruction         , 0                   , 0   , 32,
21099        0xfc1c0001, 0x44140000, &NMD::SH_GP_           , 0,
21100        0x0                 },        /* SH[GP] */
21101     { reserved_block      , 0                   , 0   , 32,
21102        0xfc1c0001, 0x44140001, 0                      , 0,
21103        0x0                 },        /* P.GP.SH~*(1) */
21104 };
21105
21106
21107 NMD::Pool NMD::P_GP_CP1[4] = {
21108     { instruction         , 0                   , 0   , 32,
21109        0xfc1c0003, 0x44180000, &NMD::LWC1_GP_         , 0,
21110        CP1_                },        /* LWC1[GP] */
21111     { instruction         , 0                   , 0   , 32,
21112        0xfc1c0003, 0x44180001, &NMD::SWC1_GP_         , 0,
21113        CP1_                },        /* SWC1[GP] */
21114     { instruction         , 0                   , 0   , 32,
21115        0xfc1c0003, 0x44180002, &NMD::LDC1_GP_         , 0,
21116        CP1_                },        /* LDC1[GP] */
21117     { instruction         , 0                   , 0   , 32,
21118        0xfc1c0003, 0x44180003, &NMD::SDC1_GP_         , 0,
21119        CP1_                },        /* SDC1[GP] */
21120 };
21121
21122
21123 NMD::Pool NMD::P_GP_M64[4] = {
21124     { instruction         , 0                   , 0   , 32,
21125        0xfc1c0003, 0x441c0000, &NMD::LWU_GP_          , 0,
21126        MIPS64_             },        /* LWU[GP] */
21127     { reserved_block      , 0                   , 0   , 32,
21128        0xfc1c0003, 0x441c0001, 0                      , 0,
21129        0x0                 },        /* P.GP.M64~*(1) */
21130     { reserved_block      , 0                   , 0   , 32,
21131        0xfc1c0003, 0x441c0002, 0                      , 0,
21132        0x0                 },        /* P.GP.M64~*(2) */
21133     { reserved_block      , 0                   , 0   , 32,
21134        0xfc1c0003, 0x441c0003, 0                      , 0,
21135        0x0                 },        /* P.GP.M64~*(3) */
21136 };
21137
21138
21139 NMD::Pool NMD::P_GP_BH[8] = {
21140     { instruction         , 0                   , 0   , 32,
21141        0xfc1c0000, 0x44000000, &NMD::LB_GP_           , 0,
21142        0x0                 },        /* LB[GP] */
21143     { instruction         , 0                   , 0   , 32,
21144        0xfc1c0000, 0x44040000, &NMD::SB_GP_           , 0,
21145        0x0                 },        /* SB[GP] */
21146     { instruction         , 0                   , 0   , 32,
21147        0xfc1c0000, 0x44080000, &NMD::LBU_GP_          , 0,
21148        0x0                 },        /* LBU[GP] */
21149     { instruction         , 0                   , 0   , 32,
21150        0xfc1c0000, 0x440c0000, &NMD::ADDIU_GP_B_      , 0,
21151        0x0                 },        /* ADDIU[GP.B] */
21152     { pool                , P_GP_LH             , 2   , 32,
21153        0xfc1c0000, 0x44100000, 0                      , 0,
21154        0x0                 },        /* P.GP.LH */
21155     { pool                , P_GP_SH             , 2   , 32,
21156        0xfc1c0000, 0x44140000, 0                      , 0,
21157        0x0                 },        /* P.GP.SH */
21158     { pool                , P_GP_CP1            , 4   , 32,
21159        0xfc1c0000, 0x44180000, 0                      , 0,
21160        0x0                 },        /* P.GP.CP1 */
21161     { pool                , P_GP_M64            , 4   , 32,
21162        0xfc1c0000, 0x441c0000, 0                      , 0,
21163        0x0                 },        /* P.GP.M64 */
21164 };
21165
21166
21167 NMD::Pool NMD::P_LS_U12[16] = {
21168     { instruction         , 0                   , 0   , 32,
21169        0xfc00f000, 0x84000000, &NMD::LB_U12_          , 0,
21170        0x0                 },        /* LB[U12] */
21171     { instruction         , 0                   , 0   , 32,
21172        0xfc00f000, 0x84001000, &NMD::SB_U12_          , 0,
21173        0x0                 },        /* SB[U12] */
21174     { instruction         , 0                   , 0   , 32,
21175        0xfc00f000, 0x84002000, &NMD::LBU_U12_         , 0,
21176        0x0                 },        /* LBU[U12] */
21177     { instruction         , 0                   , 0   , 32,
21178        0xfc00f000, 0x84003000, &NMD::PREF_U12_        , 0,
21179        0x0                 },        /* PREF[U12] */
21180     { instruction         , 0                   , 0   , 32,
21181        0xfc00f000, 0x84004000, &NMD::LH_U12_          , 0,
21182        0x0                 },        /* LH[U12] */
21183     { instruction         , 0                   , 0   , 32,
21184        0xfc00f000, 0x84005000, &NMD::SH_U12_          , 0,
21185        0x0                 },        /* SH[U12] */
21186     { instruction         , 0                   , 0   , 32,
21187        0xfc00f000, 0x84006000, &NMD::LHU_U12_         , 0,
21188        0x0                 },        /* LHU[U12] */
21189     { instruction         , 0                   , 0   , 32,
21190        0xfc00f000, 0x84007000, &NMD::LWU_U12_         , 0,
21191        MIPS64_             },        /* LWU[U12] */
21192     { instruction         , 0                   , 0   , 32,
21193        0xfc00f000, 0x84008000, &NMD::LW_U12_          , 0,
21194        0x0                 },        /* LW[U12] */
21195     { instruction         , 0                   , 0   , 32,
21196        0xfc00f000, 0x84009000, &NMD::SW_U12_          , 0,
21197        0x0                 },        /* SW[U12] */
21198     { instruction         , 0                   , 0   , 32,
21199        0xfc00f000, 0x8400a000, &NMD::LWC1_U12_        , 0,
21200        CP1_                },        /* LWC1[U12] */
21201     { instruction         , 0                   , 0   , 32,
21202        0xfc00f000, 0x8400b000, &NMD::SWC1_U12_        , 0,
21203        CP1_                },        /* SWC1[U12] */
21204     { instruction         , 0                   , 0   , 32,
21205        0xfc00f000, 0x8400c000, &NMD::LD_U12_          , 0,
21206        MIPS64_             },        /* LD[U12] */
21207     { instruction         , 0                   , 0   , 32,
21208        0xfc00f000, 0x8400d000, &NMD::SD_U12_          , 0,
21209        MIPS64_             },        /* SD[U12] */
21210     { instruction         , 0                   , 0   , 32,
21211        0xfc00f000, 0x8400e000, &NMD::LDC1_U12_        , 0,
21212        CP1_                },        /* LDC1[U12] */
21213     { instruction         , 0                   , 0   , 32,
21214        0xfc00f000, 0x8400f000, &NMD::SDC1_U12_        , 0,
21215        CP1_                },        /* SDC1[U12] */
21216 };
21217
21218
21219 NMD::Pool NMD::P_PREF_S9_[2] = {
21220     { instruction         , 0                   , 0   , 32,
21221        0xffe07f00, 0xa7e01800, &NMD::SYNCI            , 0,
21222        0x0                 },        /* SYNCI */
21223     { instruction         , 0                   , 0   , 32,
21224        0xfc007f00, 0xa4001800, &NMD::PREF_S9_         , &NMD::PREF_S9__cond    ,
21225        0x0                 },        /* PREF[S9] */
21226 };
21227
21228
21229 NMD::Pool NMD::P_LS_S0[16] = {
21230     { instruction         , 0                   , 0   , 32,
21231        0xfc007f00, 0xa4000000, &NMD::LB_S9_           , 0,
21232        0x0                 },        /* LB[S9] */
21233     { instruction         , 0                   , 0   , 32,
21234        0xfc007f00, 0xa4000800, &NMD::SB_S9_           , 0,
21235        0x0                 },        /* SB[S9] */
21236     { instruction         , 0                   , 0   , 32,
21237        0xfc007f00, 0xa4001000, &NMD::LBU_S9_          , 0,
21238        0x0                 },        /* LBU[S9] */
21239     { pool                , P_PREF_S9_          , 2   , 32,
21240        0xfc007f00, 0xa4001800, 0                      , 0,
21241        0x0                 },        /* P.PREF[S9] */
21242     { instruction         , 0                   , 0   , 32,
21243        0xfc007f00, 0xa4002000, &NMD::LH_S9_           , 0,
21244        0x0                 },        /* LH[S9] */
21245     { instruction         , 0                   , 0   , 32,
21246        0xfc007f00, 0xa4002800, &NMD::SH_S9_           , 0,
21247        0x0                 },        /* SH[S9] */
21248     { instruction         , 0                   , 0   , 32,
21249        0xfc007f00, 0xa4003000, &NMD::LHU_S9_          , 0,
21250        0x0                 },        /* LHU[S9] */
21251     { instruction         , 0                   , 0   , 32,
21252        0xfc007f00, 0xa4003800, &NMD::LWU_S9_          , 0,
21253        MIPS64_             },        /* LWU[S9] */
21254     { instruction         , 0                   , 0   , 32,
21255        0xfc007f00, 0xa4004000, &NMD::LW_S9_           , 0,
21256        0x0                 },        /* LW[S9] */
21257     { instruction         , 0                   , 0   , 32,
21258        0xfc007f00, 0xa4004800, &NMD::SW_S9_           , 0,
21259        0x0                 },        /* SW[S9] */
21260     { instruction         , 0                   , 0   , 32,
21261        0xfc007f00, 0xa4005000, &NMD::LWC1_S9_         , 0,
21262        CP1_                },        /* LWC1[S9] */
21263     { instruction         , 0                   , 0   , 32,
21264        0xfc007f00, 0xa4005800, &NMD::SWC1_S9_         , 0,
21265        CP1_                },        /* SWC1[S9] */
21266     { instruction         , 0                   , 0   , 32,
21267        0xfc007f00, 0xa4006000, &NMD::LD_S9_           , 0,
21268        MIPS64_             },        /* LD[S9] */
21269     { instruction         , 0                   , 0   , 32,
21270        0xfc007f00, 0xa4006800, &NMD::SD_S9_           , 0,
21271        MIPS64_             },        /* SD[S9] */
21272     { instruction         , 0                   , 0   , 32,
21273        0xfc007f00, 0xa4007000, &NMD::LDC1_S9_         , 0,
21274        CP1_                },        /* LDC1[S9] */
21275     { instruction         , 0                   , 0   , 32,
21276        0xfc007f00, 0xa4007800, &NMD::SDC1_S9_         , 0,
21277        CP1_                },        /* SDC1[S9] */
21278 };
21279
21280
21281 NMD::Pool NMD::ASET_ACLR[2] = {
21282     { instruction         , 0                   , 0   , 32,
21283        0xfe007f00, 0xa4001100, &NMD::ASET             , 0,
21284        MCU_                },        /* ASET */
21285     { instruction         , 0                   , 0   , 32,
21286        0xfe007f00, 0xa6001100, &NMD::ACLR             , 0,
21287        MCU_                },        /* ACLR */
21288 };
21289
21290
21291 NMD::Pool NMD::P_LL[4] = {
21292     { instruction         , 0                   , 0   , 32,
21293        0xfc007f03, 0xa4005100, &NMD::LL               , 0,
21294        0x0                 },        /* LL */
21295     { instruction         , 0                   , 0   , 32,
21296        0xfc007f03, 0xa4005101, &NMD::LLWP             , 0,
21297        XNP_                },        /* LLWP */
21298     { reserved_block      , 0                   , 0   , 32,
21299        0xfc007f03, 0xa4005102, 0                      , 0,
21300        0x0                 },        /* P.LL~*(2) */
21301     { reserved_block      , 0                   , 0   , 32,
21302        0xfc007f03, 0xa4005103, 0                      , 0,
21303        0x0                 },        /* P.LL~*(3) */
21304 };
21305
21306
21307 NMD::Pool NMD::P_SC[4] = {
21308     { instruction         , 0                   , 0   , 32,
21309        0xfc007f03, 0xa4005900, &NMD::SC               , 0,
21310        0x0                 },        /* SC */
21311     { instruction         , 0                   , 0   , 32,
21312        0xfc007f03, 0xa4005901, &NMD::SCWP             , 0,
21313        XNP_                },        /* SCWP */
21314     { reserved_block      , 0                   , 0   , 32,
21315        0xfc007f03, 0xa4005902, 0                      , 0,
21316        0x0                 },        /* P.SC~*(2) */
21317     { reserved_block      , 0                   , 0   , 32,
21318        0xfc007f03, 0xa4005903, 0                      , 0,
21319        0x0                 },        /* P.SC~*(3) */
21320 };
21321
21322
21323 NMD::Pool NMD::P_LLD[8] = {
21324     { instruction         , 0                   , 0   , 32,
21325        0xfc007f07, 0xa4007100, &NMD::LLD              , 0,
21326        MIPS64_             },        /* LLD */
21327     { instruction         , 0                   , 0   , 32,
21328        0xfc007f07, 0xa4007101, &NMD::LLDP             , 0,
21329        MIPS64_             },        /* LLDP */
21330     { reserved_block      , 0                   , 0   , 32,
21331        0xfc007f07, 0xa4007102, 0                      , 0,
21332        0x0                 },        /* P.LLD~*(2) */
21333     { reserved_block      , 0                   , 0   , 32,
21334        0xfc007f07, 0xa4007103, 0                      , 0,
21335        0x0                 },        /* P.LLD~*(3) */
21336     { reserved_block      , 0                   , 0   , 32,
21337        0xfc007f07, 0xa4007104, 0                      , 0,
21338        0x0                 },        /* P.LLD~*(4) */
21339     { reserved_block      , 0                   , 0   , 32,
21340        0xfc007f07, 0xa4007105, 0                      , 0,
21341        0x0                 },        /* P.LLD~*(5) */
21342     { reserved_block      , 0                   , 0   , 32,
21343        0xfc007f07, 0xa4007106, 0                      , 0,
21344        0x0                 },        /* P.LLD~*(6) */
21345     { reserved_block      , 0                   , 0   , 32,
21346        0xfc007f07, 0xa4007107, 0                      , 0,
21347        0x0                 },        /* P.LLD~*(7) */
21348 };
21349
21350
21351 NMD::Pool NMD::P_SCD[8] = {
21352     { instruction         , 0                   , 0   , 32,
21353        0xfc007f07, 0xa4007900, &NMD::SCD              , 0,
21354        MIPS64_             },        /* SCD */
21355     { instruction         , 0                   , 0   , 32,
21356        0xfc007f07, 0xa4007901, &NMD::SCDP             , 0,
21357        MIPS64_             },        /* SCDP */
21358     { reserved_block      , 0                   , 0   , 32,
21359        0xfc007f07, 0xa4007902, 0                      , 0,
21360        0x0                 },        /* P.SCD~*(2) */
21361     { reserved_block      , 0                   , 0   , 32,
21362        0xfc007f07, 0xa4007903, 0                      , 0,
21363        0x0                 },        /* P.SCD~*(3) */
21364     { reserved_block      , 0                   , 0   , 32,
21365        0xfc007f07, 0xa4007904, 0                      , 0,
21366        0x0                 },        /* P.SCD~*(4) */
21367     { reserved_block      , 0                   , 0   , 32,
21368        0xfc007f07, 0xa4007905, 0                      , 0,
21369        0x0                 },        /* P.SCD~*(5) */
21370     { reserved_block      , 0                   , 0   , 32,
21371        0xfc007f07, 0xa4007906, 0                      , 0,
21372        0x0                 },        /* P.SCD~*(6) */
21373     { reserved_block      , 0                   , 0   , 32,
21374        0xfc007f07, 0xa4007907, 0                      , 0,
21375        0x0                 },        /* P.SCD~*(7) */
21376 };
21377
21378
21379 NMD::Pool NMD::P_LS_S1[16] = {
21380     { reserved_block      , 0                   , 0   , 32,
21381        0xfc007f00, 0xa4000100, 0                      , 0,
21382        0x0                 },        /* P.LS.S1~*(0) */
21383     { reserved_block      , 0                   , 0   , 32,
21384        0xfc007f00, 0xa4000900, 0                      , 0,
21385        0x0                 },        /* P.LS.S1~*(1) */
21386     { pool                , ASET_ACLR           , 2   , 32,
21387        0xfc007f00, 0xa4001100, 0                      , 0,
21388        0x0                 },        /* ASET_ACLR */
21389     { reserved_block      , 0                   , 0   , 32,
21390        0xfc007f00, 0xa4001900, 0                      , 0,
21391        0x0                 },        /* P.LS.S1~*(3) */
21392     { instruction         , 0                   , 0   , 32,
21393        0xfc007f00, 0xa4002100, &NMD::UALH             , 0,
21394        XMMS_               },        /* UALH */
21395     { instruction         , 0                   , 0   , 32,
21396        0xfc007f00, 0xa4002900, &NMD::UASH             , 0,
21397        XMMS_               },        /* UASH */
21398     { reserved_block      , 0                   , 0   , 32,
21399        0xfc007f00, 0xa4003100, 0                      , 0,
21400        0x0                 },        /* P.LS.S1~*(6) */
21401     { instruction         , 0                   , 0   , 32,
21402        0xfc007f00, 0xa4003900, &NMD::CACHE            , 0,
21403        CP0_                },        /* CACHE */
21404     { instruction         , 0                   , 0   , 32,
21405        0xfc007f00, 0xa4004100, &NMD::LWC2             , 0,
21406        CP2_                },        /* LWC2 */
21407     { instruction         , 0                   , 0   , 32,
21408        0xfc007f00, 0xa4004900, &NMD::SWC2             , 0,
21409        CP2_                },        /* SWC2 */
21410     { pool                , P_LL                , 4   , 32,
21411        0xfc007f00, 0xa4005100, 0                      , 0,
21412        0x0                 },        /* P.LL */
21413     { pool                , P_SC                , 4   , 32,
21414        0xfc007f00, 0xa4005900, 0                      , 0,
21415        0x0                 },        /* P.SC */
21416     { instruction         , 0                   , 0   , 32,
21417        0xfc007f00, 0xa4006100, &NMD::LDC2             , 0,
21418        CP2_                },        /* LDC2 */
21419     { instruction         , 0                   , 0   , 32,
21420        0xfc007f00, 0xa4006900, &NMD::SDC2             , 0,
21421        CP2_                },        /* SDC2 */
21422     { pool                , P_LLD               , 8   , 32,
21423        0xfc007f00, 0xa4007100, 0                      , 0,
21424        0x0                 },        /* P.LLD */
21425     { pool                , P_SCD               , 8   , 32,
21426        0xfc007f00, 0xa4007900, 0                      , 0,
21427        0x0                 },        /* P.SCD */
21428 };
21429
21430
21431 NMD::Pool NMD::P_PREFE[2] = {
21432     { instruction         , 0                   , 0   , 32,
21433        0xffe07f00, 0xa7e01a00, &NMD::SYNCIE           , 0,
21434        CP0_ | EVA_         },        /* SYNCIE */
21435     { instruction         , 0                   , 0   , 32,
21436        0xfc007f00, 0xa4001a00, &NMD::PREFE            , &NMD::PREFE_cond       ,
21437        CP0_ | EVA_         },        /* PREFE */
21438 };
21439
21440
21441 NMD::Pool NMD::P_LLE[4] = {
21442     { instruction         , 0                   , 0   , 32,
21443        0xfc007f03, 0xa4005200, &NMD::LLE              , 0,
21444        CP0_ | EVA_         },        /* LLE */
21445     { instruction         , 0                   , 0   , 32,
21446        0xfc007f03, 0xa4005201, &NMD::LLWPE            , 0,
21447        CP0_ | EVA_         },        /* LLWPE */
21448     { reserved_block      , 0                   , 0   , 32,
21449        0xfc007f03, 0xa4005202, 0                      , 0,
21450        0x0                 },        /* P.LLE~*(2) */
21451     { reserved_block      , 0                   , 0   , 32,
21452        0xfc007f03, 0xa4005203, 0                      , 0,
21453        0x0                 },        /* P.LLE~*(3) */
21454 };
21455
21456
21457 NMD::Pool NMD::P_SCE[4] = {
21458     { instruction         , 0                   , 0   , 32,
21459        0xfc007f03, 0xa4005a00, &NMD::SCE              , 0,
21460        CP0_ | EVA_         },        /* SCE */
21461     { instruction         , 0                   , 0   , 32,
21462        0xfc007f03, 0xa4005a01, &NMD::SCWPE            , 0,
21463        CP0_ | EVA_         },        /* SCWPE */
21464     { reserved_block      , 0                   , 0   , 32,
21465        0xfc007f03, 0xa4005a02, 0                      , 0,
21466        0x0                 },        /* P.SCE~*(2) */
21467     { reserved_block      , 0                   , 0   , 32,
21468        0xfc007f03, 0xa4005a03, 0                      , 0,
21469        0x0                 },        /* P.SCE~*(3) */
21470 };
21471
21472
21473 NMD::Pool NMD::P_LS_E0[16] = {
21474     { instruction         , 0                   , 0   , 32,
21475        0xfc007f00, 0xa4000200, &NMD::LBE              , 0,
21476        CP0_ | EVA_         },        /* LBE */
21477     { instruction         , 0                   , 0   , 32,
21478        0xfc007f00, 0xa4000a00, &NMD::SBE              , 0,
21479        CP0_ | EVA_         },        /* SBE */
21480     { instruction         , 0                   , 0   , 32,
21481        0xfc007f00, 0xa4001200, &NMD::LBUE             , 0,
21482        CP0_ | EVA_         },        /* LBUE */
21483     { pool                , P_PREFE             , 2   , 32,
21484        0xfc007f00, 0xa4001a00, 0                      , 0,
21485        0x0                 },        /* P.PREFE */
21486     { instruction         , 0                   , 0   , 32,
21487        0xfc007f00, 0xa4002200, &NMD::LHE              , 0,
21488        CP0_ | EVA_         },        /* LHE */
21489     { instruction         , 0                   , 0   , 32,
21490        0xfc007f00, 0xa4002a00, &NMD::SHE              , 0,
21491        CP0_ | EVA_         },        /* SHE */
21492     { instruction         , 0                   , 0   , 32,
21493        0xfc007f00, 0xa4003200, &NMD::LHUE             , 0,
21494        CP0_ | EVA_         },        /* LHUE */
21495     { instruction         , 0                   , 0   , 32,
21496        0xfc007f00, 0xa4003a00, &NMD::CACHEE           , 0,
21497        CP0_ | EVA_         },        /* CACHEE */
21498     { instruction         , 0                   , 0   , 32,
21499        0xfc007f00, 0xa4004200, &NMD::LWE              , 0,
21500        CP0_ | EVA_         },        /* LWE */
21501     { instruction         , 0                   , 0   , 32,
21502        0xfc007f00, 0xa4004a00, &NMD::SWE              , 0,
21503        CP0_ | EVA_         },        /* SWE */
21504     { pool                , P_LLE               , 4   , 32,
21505        0xfc007f00, 0xa4005200, 0                      , 0,
21506        0x0                 },        /* P.LLE */
21507     { pool                , P_SCE               , 4   , 32,
21508        0xfc007f00, 0xa4005a00, 0                      , 0,
21509        0x0                 },        /* P.SCE */
21510     { reserved_block      , 0                   , 0   , 32,
21511        0xfc007f00, 0xa4006200, 0                      , 0,
21512        0x0                 },        /* P.LS.E0~*(12) */
21513     { reserved_block      , 0                   , 0   , 32,
21514        0xfc007f00, 0xa4006a00, 0                      , 0,
21515        0x0                 },        /* P.LS.E0~*(13) */
21516     { reserved_block      , 0                   , 0   , 32,
21517        0xfc007f00, 0xa4007200, 0                      , 0,
21518        0x0                 },        /* P.LS.E0~*(14) */
21519     { reserved_block      , 0                   , 0   , 32,
21520        0xfc007f00, 0xa4007a00, 0                      , 0,
21521        0x0                 },        /* P.LS.E0~*(15) */
21522 };
21523
21524
21525 NMD::Pool NMD::P_LS_WM[2] = {
21526     { instruction         , 0                   , 0   , 32,
21527        0xfc000f00, 0xa4000400, &NMD::LWM              , 0,
21528        XMMS_               },        /* LWM */
21529     { instruction         , 0                   , 0   , 32,
21530        0xfc000f00, 0xa4000c00, &NMD::SWM              , 0,
21531        XMMS_               },        /* SWM */
21532 };
21533
21534
21535 NMD::Pool NMD::P_LS_UAWM[2] = {
21536     { instruction         , 0                   , 0   , 32,
21537        0xfc000f00, 0xa4000500, &NMD::UALWM            , 0,
21538        XMMS_               },        /* UALWM */
21539     { instruction         , 0                   , 0   , 32,
21540        0xfc000f00, 0xa4000d00, &NMD::UASWM            , 0,
21541        XMMS_               },        /* UASWM */
21542 };
21543
21544
21545 NMD::Pool NMD::P_LS_DM[2] = {
21546     { instruction         , 0                   , 0   , 32,
21547        0xfc000f00, 0xa4000600, &NMD::LDM              , 0,
21548        MIPS64_             },        /* LDM */
21549     { instruction         , 0                   , 0   , 32,
21550        0xfc000f00, 0xa4000e00, &NMD::SDM              , 0,
21551        MIPS64_             },        /* SDM */
21552 };
21553
21554
21555 NMD::Pool NMD::P_LS_UADM[2] = {
21556     { instruction         , 0                   , 0   , 32,
21557        0xfc000f00, 0xa4000700, &NMD::UALDM            , 0,
21558        MIPS64_             },        /* UALDM */
21559     { instruction         , 0                   , 0   , 32,
21560        0xfc000f00, 0xa4000f00, &NMD::UASDM            , 0,
21561        MIPS64_             },        /* UASDM */
21562 };
21563
21564
21565 NMD::Pool NMD::P_LS_S9[8] = {
21566     { pool                , P_LS_S0             , 16  , 32,
21567        0xfc000700, 0xa4000000, 0                      , 0,
21568        0x0                 },        /* P.LS.S0 */
21569     { pool                , P_LS_S1             , 16  , 32,
21570        0xfc000700, 0xa4000100, 0                      , 0,
21571        0x0                 },        /* P.LS.S1 */
21572     { pool                , P_LS_E0             , 16  , 32,
21573        0xfc000700, 0xa4000200, 0                      , 0,
21574        0x0                 },        /* P.LS.E0 */
21575     { reserved_block      , 0                   , 0   , 32,
21576        0xfc000700, 0xa4000300, 0                      , 0,
21577        0x0                 },        /* P.LS.S9~*(3) */
21578     { pool                , P_LS_WM             , 2   , 32,
21579        0xfc000700, 0xa4000400, 0                      , 0,
21580        0x0                 },        /* P.LS.WM */
21581     { pool                , P_LS_UAWM           , 2   , 32,
21582        0xfc000700, 0xa4000500, 0                      , 0,
21583        0x0                 },        /* P.LS.UAWM */
21584     { pool                , P_LS_DM             , 2   , 32,
21585        0xfc000700, 0xa4000600, 0                      , 0,
21586        0x0                 },        /* P.LS.DM */
21587     { pool                , P_LS_UADM           , 2   , 32,
21588        0xfc000700, 0xa4000700, 0                      , 0,
21589        0x0                 },        /* P.LS.UADM */
21590 };
21591
21592
21593 NMD::Pool NMD::P_BAL[2] = {
21594     { branch_instruction  , 0                   , 0   , 32,
21595        0xfe000000, 0x28000000, &NMD::BC_32_           , 0,
21596        0x0                 },        /* BC[32] */
21597     { call_instruction    , 0                   , 0   , 32,
21598        0xfe000000, 0x2a000000, &NMD::BALC_32_         , 0,
21599        0x0                 },        /* BALC[32] */
21600 };
21601
21602
21603 NMD::Pool NMD::P_BALRSC[2] = {
21604     { branch_instruction  , 0                   , 0   , 32,
21605        0xffe0f000, 0x48008000, &NMD::BRSC             , 0,
21606        0x0                 },        /* BRSC */
21607     { call_instruction    , 0                   , 0   , 32,
21608        0xfc00f000, 0x48008000, &NMD::BALRSC           , &NMD::BALRSC_cond      ,
21609        0x0                 },        /* BALRSC */
21610 };
21611
21612
21613 NMD::Pool NMD::P_J[16] = {
21614     { call_instruction    , 0                   , 0   , 32,
21615        0xfc00f000, 0x48000000, &NMD::JALRC_32_        , 0,
21616        0x0                 },        /* JALRC[32] */
21617     { call_instruction    , 0                   , 0   , 32,
21618        0xfc00f000, 0x48001000, &NMD::JALRC_HB         , 0,
21619        0x0                 },        /* JALRC.HB */
21620     { reserved_block      , 0                   , 0   , 32,
21621        0xfc00f000, 0x48002000, 0                      , 0,
21622        0x0                 },        /* P.J~*(2) */
21623     { reserved_block      , 0                   , 0   , 32,
21624        0xfc00f000, 0x48003000, 0                      , 0,
21625        0x0                 },        /* P.J~*(3) */
21626     { reserved_block      , 0                   , 0   , 32,
21627        0xfc00f000, 0x48004000, 0                      , 0,
21628        0x0                 },        /* P.J~*(4) */
21629     { reserved_block      , 0                   , 0   , 32,
21630        0xfc00f000, 0x48005000, 0                      , 0,
21631        0x0                 },        /* P.J~*(5) */
21632     { reserved_block      , 0                   , 0   , 32,
21633        0xfc00f000, 0x48006000, 0                      , 0,
21634        0x0                 },        /* P.J~*(6) */
21635     { reserved_block      , 0                   , 0   , 32,
21636        0xfc00f000, 0x48007000, 0                      , 0,
21637        0x0                 },        /* P.J~*(7) */
21638     { pool                , P_BALRSC            , 2   , 32,
21639        0xfc00f000, 0x48008000, 0                      , 0,
21640        0x0                 },        /* P.BALRSC */
21641     { reserved_block      , 0                   , 0   , 32,
21642        0xfc00f000, 0x48009000, 0                      , 0,
21643        0x0                 },        /* P.J~*(9) */
21644     { reserved_block      , 0                   , 0   , 32,
21645        0xfc00f000, 0x4800a000, 0                      , 0,
21646        0x0                 },        /* P.J~*(10) */
21647     { reserved_block      , 0                   , 0   , 32,
21648        0xfc00f000, 0x4800b000, 0                      , 0,
21649        0x0                 },        /* P.J~*(11) */
21650     { reserved_block      , 0                   , 0   , 32,
21651        0xfc00f000, 0x4800c000, 0                      , 0,
21652        0x0                 },        /* P.J~*(12) */
21653     { reserved_block      , 0                   , 0   , 32,
21654        0xfc00f000, 0x4800d000, 0                      , 0,
21655        0x0                 },        /* P.J~*(13) */
21656     { reserved_block      , 0                   , 0   , 32,
21657        0xfc00f000, 0x4800e000, 0                      , 0,
21658        0x0                 },        /* P.J~*(14) */
21659     { reserved_block      , 0                   , 0   , 32,
21660        0xfc00f000, 0x4800f000, 0                      , 0,
21661        0x0                 },        /* P.J~*(15) */
21662 };
21663
21664
21665 NMD::Pool NMD::P_BR3A[32] = {
21666     { branch_instruction  , 0                   , 0   , 32,
21667        0xfc1fc000, 0x88004000, &NMD::BC1EQZC          , 0,
21668        CP1_                },        /* BC1EQZC */
21669     { branch_instruction  , 0                   , 0   , 32,
21670        0xfc1fc000, 0x88014000, &NMD::BC1NEZC          , 0,
21671        CP1_                },        /* BC1NEZC */
21672     { branch_instruction  , 0                   , 0   , 32,
21673        0xfc1fc000, 0x88024000, &NMD::BC2EQZC          , 0,
21674        CP2_                },        /* BC2EQZC */
21675     { branch_instruction  , 0                   , 0   , 32,
21676        0xfc1fc000, 0x88034000, &NMD::BC2NEZC          , 0,
21677        CP2_                },        /* BC2NEZC */
21678     { branch_instruction  , 0                   , 0   , 32,
21679        0xfc1fc000, 0x88044000, &NMD::BPOSGE32C        , 0,
21680        DSP_                },        /* BPOSGE32C */
21681     { reserved_block      , 0                   , 0   , 32,
21682        0xfc1fc000, 0x88054000, 0                      , 0,
21683        0x0                 },        /* P.BR3A~*(5) */
21684     { reserved_block      , 0                   , 0   , 32,
21685        0xfc1fc000, 0x88064000, 0                      , 0,
21686        0x0                 },        /* P.BR3A~*(6) */
21687     { reserved_block      , 0                   , 0   , 32,
21688        0xfc1fc000, 0x88074000, 0                      , 0,
21689        0x0                 },        /* P.BR3A~*(7) */
21690     { reserved_block      , 0                   , 0   , 32,
21691        0xfc1fc000, 0x88084000, 0                      , 0,
21692        0x0                 },        /* P.BR3A~*(8) */
21693     { reserved_block      , 0                   , 0   , 32,
21694        0xfc1fc000, 0x88094000, 0                      , 0,
21695        0x0                 },        /* P.BR3A~*(9) */
21696     { reserved_block      , 0                   , 0   , 32,
21697        0xfc1fc000, 0x880a4000, 0                      , 0,
21698        0x0                 },        /* P.BR3A~*(10) */
21699     { reserved_block      , 0                   , 0   , 32,
21700        0xfc1fc000, 0x880b4000, 0                      , 0,
21701        0x0                 },        /* P.BR3A~*(11) */
21702     { reserved_block      , 0                   , 0   , 32,
21703        0xfc1fc000, 0x880c4000, 0                      , 0,
21704        0x0                 },        /* P.BR3A~*(12) */
21705     { reserved_block      , 0                   , 0   , 32,
21706        0xfc1fc000, 0x880d4000, 0                      , 0,
21707        0x0                 },        /* P.BR3A~*(13) */
21708     { reserved_block      , 0                   , 0   , 32,
21709        0xfc1fc000, 0x880e4000, 0                      , 0,
21710        0x0                 },        /* P.BR3A~*(14) */
21711     { reserved_block      , 0                   , 0   , 32,
21712        0xfc1fc000, 0x880f4000, 0                      , 0,
21713        0x0                 },        /* P.BR3A~*(15) */
21714     { reserved_block      , 0                   , 0   , 32,
21715        0xfc1fc000, 0x88104000, 0                      , 0,
21716        0x0                 },        /* P.BR3A~*(16) */
21717     { reserved_block      , 0                   , 0   , 32,
21718        0xfc1fc000, 0x88114000, 0                      , 0,
21719        0x0                 },        /* P.BR3A~*(17) */
21720     { reserved_block      , 0                   , 0   , 32,
21721        0xfc1fc000, 0x88124000, 0                      , 0,
21722        0x0                 },        /* P.BR3A~*(18) */
21723     { reserved_block      , 0                   , 0   , 32,
21724        0xfc1fc000, 0x88134000, 0                      , 0,
21725        0x0                 },        /* P.BR3A~*(19) */
21726     { reserved_block      , 0                   , 0   , 32,
21727        0xfc1fc000, 0x88144000, 0                      , 0,
21728        0x0                 },        /* P.BR3A~*(20) */
21729     { reserved_block      , 0                   , 0   , 32,
21730        0xfc1fc000, 0x88154000, 0                      , 0,
21731        0x0                 },        /* P.BR3A~*(21) */
21732     { reserved_block      , 0                   , 0   , 32,
21733        0xfc1fc000, 0x88164000, 0                      , 0,
21734        0x0                 },        /* P.BR3A~*(22) */
21735     { reserved_block      , 0                   , 0   , 32,
21736        0xfc1fc000, 0x88174000, 0                      , 0,
21737        0x0                 },        /* P.BR3A~*(23) */
21738     { reserved_block      , 0                   , 0   , 32,
21739        0xfc1fc000, 0x88184000, 0                      , 0,
21740        0x0                 },        /* P.BR3A~*(24) */
21741     { reserved_block      , 0                   , 0   , 32,
21742        0xfc1fc000, 0x88194000, 0                      , 0,
21743        0x0                 },        /* P.BR3A~*(25) */
21744     { reserved_block      , 0                   , 0   , 32,
21745        0xfc1fc000, 0x881a4000, 0                      , 0,
21746        0x0                 },        /* P.BR3A~*(26) */
21747     { reserved_block      , 0                   , 0   , 32,
21748        0xfc1fc000, 0x881b4000, 0                      , 0,
21749        0x0                 },        /* P.BR3A~*(27) */
21750     { reserved_block      , 0                   , 0   , 32,
21751        0xfc1fc000, 0x881c4000, 0                      , 0,
21752        0x0                 },        /* P.BR3A~*(28) */
21753     { reserved_block      , 0                   , 0   , 32,
21754        0xfc1fc000, 0x881d4000, 0                      , 0,
21755        0x0                 },        /* P.BR3A~*(29) */
21756     { reserved_block      , 0                   , 0   , 32,
21757        0xfc1fc000, 0x881e4000, 0                      , 0,
21758        0x0                 },        /* P.BR3A~*(30) */
21759     { reserved_block      , 0                   , 0   , 32,
21760        0xfc1fc000, 0x881f4000, 0                      , 0,
21761        0x0                 },        /* P.BR3A~*(31) */
21762 };
21763
21764
21765 NMD::Pool NMD::P_BR1[4] = {
21766     { branch_instruction  , 0                   , 0   , 32,
21767        0xfc00c000, 0x88000000, &NMD::BEQC_32_         , 0,
21768        0x0                 },        /* BEQC[32] */
21769     { pool                , P_BR3A              , 32  , 32,
21770        0xfc00c000, 0x88004000, 0                      , 0,
21771        0x0                 },        /* P.BR3A */
21772     { branch_instruction  , 0                   , 0   , 32,
21773        0xfc00c000, 0x88008000, &NMD::BGEC             , 0,
21774        0x0                 },        /* BGEC */
21775     { branch_instruction  , 0                   , 0   , 32,
21776        0xfc00c000, 0x8800c000, &NMD::BGEUC            , 0,
21777        0x0                 },        /* BGEUC */
21778 };
21779
21780
21781 NMD::Pool NMD::P_BR2[4] = {
21782     { branch_instruction  , 0                   , 0   , 32,
21783        0xfc00c000, 0xa8000000, &NMD::BNEC_32_         , 0,
21784        0x0                 },        /* BNEC[32] */
21785     { reserved_block      , 0                   , 0   , 32,
21786        0xfc00c000, 0xa8004000, 0                      , 0,
21787        0x0                 },        /* P.BR2~*(1) */
21788     { branch_instruction  , 0                   , 0   , 32,
21789        0xfc00c000, 0xa8008000, &NMD::BLTC             , 0,
21790        0x0                 },        /* BLTC */
21791     { branch_instruction  , 0                   , 0   , 32,
21792        0xfc00c000, 0xa800c000, &NMD::BLTUC            , 0,
21793        0x0                 },        /* BLTUC */
21794 };
21795
21796
21797 NMD::Pool NMD::P_BRI[8] = {
21798     { branch_instruction  , 0                   , 0   , 32,
21799        0xfc1c0000, 0xc8000000, &NMD::BEQIC            , 0,
21800        0x0                 },        /* BEQIC */
21801     { branch_instruction  , 0                   , 0   , 32,
21802        0xfc1c0000, 0xc8040000, &NMD::BBEQZC           , 0,
21803        XMMS_               },        /* BBEQZC */
21804     { branch_instruction  , 0                   , 0   , 32,
21805        0xfc1c0000, 0xc8080000, &NMD::BGEIC            , 0,
21806        0x0                 },        /* BGEIC */
21807     { branch_instruction  , 0                   , 0   , 32,
21808        0xfc1c0000, 0xc80c0000, &NMD::BGEIUC           , 0,
21809        0x0                 },        /* BGEIUC */
21810     { branch_instruction  , 0                   , 0   , 32,
21811        0xfc1c0000, 0xc8100000, &NMD::BNEIC            , 0,
21812        0x0                 },        /* BNEIC */
21813     { branch_instruction  , 0                   , 0   , 32,
21814        0xfc1c0000, 0xc8140000, &NMD::BBNEZC           , 0,
21815        XMMS_               },        /* BBNEZC */
21816     { branch_instruction  , 0                   , 0   , 32,
21817        0xfc1c0000, 0xc8180000, &NMD::BLTIC            , 0,
21818        0x0                 },        /* BLTIC */
21819     { branch_instruction  , 0                   , 0   , 32,
21820        0xfc1c0000, 0xc81c0000, &NMD::BLTIUC           , 0,
21821        0x0                 },        /* BLTIUC */
21822 };
21823
21824
21825 NMD::Pool NMD::P32[32] = {
21826     { pool                , P_ADDIU             , 2   , 32,
21827        0xfc000000, 0x00000000, 0                      , 0,
21828        0x0                 },        /* P.ADDIU */
21829     { pool                , P32A                , 8   , 32,
21830        0xfc000000, 0x20000000, 0                      , 0,
21831        0x0                 },        /* P32A */
21832     { pool                , P_GP_W              , 4   , 32,
21833        0xfc000000, 0x40000000, 0                      , 0,
21834        0x0                 },        /* P.GP.W */
21835     { pool                , POOL48I             , 32  , 48,
21836        0xfc0000000000ull, 0x600000000000ull, 0                      , 0,
21837        0x0                 },        /* POOL48I */
21838     { pool                , P_U12               , 16  , 32,
21839        0xfc000000, 0x80000000, 0                      , 0,
21840        0x0                 },        /* P.U12 */
21841     { pool                , POOL32F             , 8   , 32,
21842        0xfc000000, 0xa0000000, 0                      , 0,
21843        CP1_                },        /* POOL32F */
21844     { pool                , POOL32S             , 8   , 32,
21845        0xfc000000, 0xc0000000, 0                      , 0,
21846        0x0                 },        /* POOL32S */
21847     { pool                , P_LUI               , 2   , 32,
21848        0xfc000000, 0xe0000000, 0                      , 0,
21849        0x0                 },        /* P.LUI */
21850     { instruction         , 0                   , 0   , 32,
21851        0xfc000000, 0x04000000, &NMD::ADDIUPC_32_      , 0,
21852        0x0                 },        /* ADDIUPC[32] */
21853     { reserved_block      , 0                   , 0   , 32,
21854        0xfc000000, 0x24000000, 0                      , 0,
21855        0x0                 },        /* P32~*(5) */
21856     { pool                , P_GP_BH             , 8   , 32,
21857        0xfc000000, 0x44000000, 0                      , 0,
21858        0x0                 },        /* P.GP.BH */
21859     { reserved_block      , 0                   , 0   , 32,
21860        0xfc000000, 0x64000000, 0                      , 0,
21861        0x0                 },        /* P32~*(13) */
21862     { pool                , P_LS_U12            , 16  , 32,
21863        0xfc000000, 0x84000000, 0                      , 0,
21864        0x0                 },        /* P.LS.U12 */
21865     { pool                , P_LS_S9             , 8   , 32,
21866        0xfc000000, 0xa4000000, 0                      , 0,
21867        0x0                 },        /* P.LS.S9 */
21868     { reserved_block      , 0                   , 0   , 32,
21869        0xfc000000, 0xc4000000, 0                      , 0,
21870        0x0                 },        /* P32~*(25) */
21871     { reserved_block      , 0                   , 0   , 32,
21872        0xfc000000, 0xe4000000, 0                      , 0,
21873        0x0                 },        /* P32~*(29) */
21874     { call_instruction    , 0                   , 0   , 32,
21875        0xfc000000, 0x08000000, &NMD::MOVE_BALC        , 0,
21876        XMMS_               },        /* MOVE.BALC */
21877     { pool                , P_BAL               , 2   , 32,
21878        0xfc000000, 0x28000000, 0                      , 0,
21879        0x0                 },        /* P.BAL */
21880     { pool                , P_J                 , 16  , 32,
21881        0xfc000000, 0x48000000, 0                      , 0,
21882        0x0                 },        /* P.J */
21883     { reserved_block      , 0                   , 0   , 32,
21884        0xfc000000, 0x68000000, 0                      , 0,
21885        0x0                 },        /* P32~*(14) */
21886     { pool                , P_BR1               , 4   , 32,
21887        0xfc000000, 0x88000000, 0                      , 0,
21888        0x0                 },        /* P.BR1 */
21889     { pool                , P_BR2               , 4   , 32,
21890        0xfc000000, 0xa8000000, 0                      , 0,
21891        0x0                 },        /* P.BR2 */
21892     { pool                , P_BRI               , 8   , 32,
21893        0xfc000000, 0xc8000000, 0                      , 0,
21894        0x0                 },        /* P.BRI */
21895     { reserved_block      , 0                   , 0   , 32,
21896        0xfc000000, 0xe8000000, 0                      , 0,
21897        0x0                 },        /* P32~*(30) */
21898     { reserved_block      , 0                   , 0   , 32,
21899        0xfc000000, 0x0c000000, 0                      , 0,
21900        0x0                 },        /* P32~*(3) */
21901     { reserved_block      , 0                   , 0   , 32,
21902        0xfc000000, 0x2c000000, 0                      , 0,
21903        0x0                 },        /* P32~*(7) */
21904     { reserved_block      , 0                   , 0   , 32,
21905        0xfc000000, 0x4c000000, 0                      , 0,
21906        0x0                 },        /* P32~*(11) */
21907     { reserved_block      , 0                   , 0   , 32,
21908        0xfc000000, 0x6c000000, 0                      , 0,
21909        0x0                 },        /* P32~*(15) */
21910     { reserved_block      , 0                   , 0   , 32,
21911        0xfc000000, 0x8c000000, 0                      , 0,
21912        0x0                 },        /* P32~*(19) */
21913     { reserved_block      , 0                   , 0   , 32,
21914        0xfc000000, 0xac000000, 0                      , 0,
21915        0x0                 },        /* P32~*(23) */
21916     { reserved_block      , 0                   , 0   , 32,
21917        0xfc000000, 0xcc000000, 0                      , 0,
21918        0x0                 },        /* P32~*(27) */
21919     { reserved_block      , 0                   , 0   , 32,
21920        0xfc000000, 0xec000000, 0                      , 0,
21921        0x0                 },        /* P32~*(31) */
21922 };
21923
21924
21925 NMD::Pool NMD::P16_SYSCALL[2] = {
21926     { instruction         , 0                   , 0   , 16,
21927        0xfffc    , 0x1008    , &NMD::SYSCALL_16_      , 0,
21928        0x0                 },        /* SYSCALL[16] */
21929     { instruction         , 0                   , 0   , 16,
21930        0xfffc    , 0x100c    , &NMD::HYPCALL_16_      , 0,
21931        CP0_ | VZ_          },        /* HYPCALL[16] */
21932 };
21933
21934
21935 NMD::Pool NMD::P16_RI[4] = {
21936     { reserved_block      , 0                   , 0   , 16,
21937        0xfff8    , 0x1000    , 0                      , 0,
21938        0x0                 },        /* P16.RI~*(0) */
21939     { pool                , P16_SYSCALL         , 2   , 16,
21940        0xfff8    , 0x1008    , 0                      , 0,
21941        0x0                 },        /* P16.SYSCALL */
21942     { instruction         , 0                   , 0   , 16,
21943        0xfff8    , 0x1010    , &NMD::BREAK_16_        , 0,
21944        0x0                 },        /* BREAK[16] */
21945     { instruction         , 0                   , 0   , 16,
21946        0xfff8    , 0x1018    , &NMD::SDBBP_16_        , 0,
21947        EJTAG_              },        /* SDBBP[16] */
21948 };
21949
21950
21951 NMD::Pool NMD::P16_MV[2] = {
21952     { pool                , P16_RI              , 4   , 16,
21953        0xffe0    , 0x1000    , 0                      , 0,
21954        0x0                 },        /* P16.RI */
21955     { instruction         , 0                   , 0   , 16,
21956        0xfc00    , 0x1000    , &NMD::MOVE             , &NMD::MOVE_cond        ,
21957        0x0                 },        /* MOVE */
21958 };
21959
21960
21961 NMD::Pool NMD::P16_SHIFT[2] = {
21962     { instruction         , 0                   , 0   , 16,
21963        0xfc08    , 0x3000    , &NMD::SLL_16_          , 0,
21964        0x0                 },        /* SLL[16] */
21965     { instruction         , 0                   , 0   , 16,
21966        0xfc08    , 0x3008    , &NMD::SRL_16_          , 0,
21967        0x0                 },        /* SRL[16] */
21968 };
21969
21970
21971 NMD::Pool NMD::POOL16C_00[4] = {
21972     { instruction         , 0                   , 0   , 16,
21973        0xfc0f    , 0x5000    , &NMD::NOT_16_          , 0,
21974        0x0                 },        /* NOT[16] */
21975     { instruction         , 0                   , 0   , 16,
21976        0xfc0f    , 0x5004    , &NMD::XOR_16_          , 0,
21977        0x0                 },        /* XOR[16] */
21978     { instruction         , 0                   , 0   , 16,
21979        0xfc0f    , 0x5008    , &NMD::AND_16_          , 0,
21980        0x0                 },        /* AND[16] */
21981     { instruction         , 0                   , 0   , 16,
21982        0xfc0f    , 0x500c    , &NMD::OR_16_           , 0,
21983        0x0                 },        /* OR[16] */
21984 };
21985
21986
21987 NMD::Pool NMD::POOL16C_0[2] = {
21988     { pool                , POOL16C_00          , 4   , 16,
21989        0xfc03    , 0x5000    , 0                      , 0,
21990        0x0                 },        /* POOL16C_00 */
21991     { reserved_block      , 0                   , 0   , 16,
21992        0xfc03    , 0x5002    , 0                      , 0,
21993        0x0                 },        /* POOL16C_0~*(1) */
21994 };
21995
21996
21997 NMD::Pool NMD::P16C[2] = {
21998     { pool                , POOL16C_0           , 2   , 16,
21999        0xfc01    , 0x5000    , 0                      , 0,
22000        0x0                 },        /* POOL16C_0 */
22001     { instruction         , 0                   , 0   , 16,
22002        0xfc01    , 0x5001    , &NMD::LWXS_16_         , 0,
22003        0x0                 },        /* LWXS[16] */
22004 };
22005
22006
22007 NMD::Pool NMD::P16_A1[2] = {
22008     { reserved_block      , 0                   , 0   , 16,
22009        0xfc40    , 0x7000    , 0                      , 0,
22010        0x0                 },        /* P16.A1~*(0) */
22011     { instruction         , 0                   , 0   , 16,
22012        0xfc40    , 0x7040    , &NMD::ADDIU_R1_SP_     , 0,
22013        0x0                 },        /* ADDIU[R1.SP] */
22014 };
22015
22016
22017 NMD::Pool NMD::P_ADDIU_RS5_[2] = {
22018     { instruction         , 0                   , 0   , 16,
22019        0xffe8    , 0x9008    , &NMD::NOP_16_          , 0,
22020        0x0                 },        /* NOP[16] */
22021     { instruction         , 0                   , 0   , 16,
22022        0xfc08    , 0x9008    , &NMD::ADDIU_RS5_       , &NMD::ADDIU_RS5__cond  ,
22023        0x0                 },        /* ADDIU[RS5] */
22024 };
22025
22026
22027 NMD::Pool NMD::P16_A2[2] = {
22028     { instruction         , 0                   , 0   , 16,
22029        0xfc08    , 0x9000    , &NMD::ADDIU_R2_        , 0,
22030        0x0                 },        /* ADDIU[R2] */
22031     { pool                , P_ADDIU_RS5_        , 2   , 16,
22032        0xfc08    , 0x9008    , 0                      , 0,
22033        0x0                 },        /* P.ADDIU[RS5] */
22034 };
22035
22036
22037 NMD::Pool NMD::P16_ADDU[2] = {
22038     { instruction         , 0                   , 0   , 16,
22039        0xfc01    , 0xb000    , &NMD::ADDU_16_         , 0,
22040        0x0                 },        /* ADDU[16] */
22041     { instruction         , 0                   , 0   , 16,
22042        0xfc01    , 0xb001    , &NMD::SUBU_16_         , 0,
22043        0x0                 },        /* SUBU[16] */
22044 };
22045
22046
22047 NMD::Pool NMD::P16_JRC[2] = {
22048     { branch_instruction  , 0                   , 0   , 16,
22049        0xfc1f    , 0xd800    , &NMD::JRC              , 0,
22050        0x0                 },        /* JRC */
22051     { call_instruction    , 0                   , 0   , 16,
22052        0xfc1f    , 0xd810    , &NMD::JALRC_16_        , 0,
22053        0x0                 },        /* JALRC[16] */
22054 };
22055
22056
22057 NMD::Pool NMD::P16_BR1[2] = {
22058     { branch_instruction  , 0                   , 0   , 16,
22059        0xfc00    , 0xd800    , &NMD::BEQC_16_         , &NMD::BEQC_16__cond    ,
22060        XMMS_               },        /* BEQC[16] */
22061     { branch_instruction  , 0                   , 0   , 16,
22062        0xfc00    , 0xd800    , &NMD::BNEC_16_         , &NMD::BNEC_16__cond    ,
22063        XMMS_               },        /* BNEC[16] */
22064 };
22065
22066
22067 NMD::Pool NMD::P16_BR[2] = {
22068     { pool                , P16_JRC             , 2   , 16,
22069        0xfc0f    , 0xd800    , 0                      , 0,
22070        0x0                 },        /* P16.JRC */
22071     { pool                , P16_BR1             , 2   , 16,
22072        0xfc00    , 0xd800    , 0                      , &NMD::P16_BR1_cond     ,
22073        0x0                 },        /* P16.BR1 */
22074 };
22075
22076
22077 NMD::Pool NMD::P16_SR[2] = {
22078     { instruction         , 0                   , 0   , 16,
22079        0xfd00    , 0x1c00    , &NMD::SAVE_16_         , 0,
22080        0x0                 },        /* SAVE[16] */
22081     { return_instruction  , 0                   , 0   , 16,
22082        0xfd00    , 0x1d00    , &NMD::RESTORE_JRC_16_  , 0,
22083        0x0                 },        /* RESTORE.JRC[16] */
22084 };
22085
22086
22087 NMD::Pool NMD::P16_4X4[4] = {
22088     { instruction         , 0                   , 0   , 16,
22089        0xfd08    , 0x3c00    , &NMD::ADDU_4X4_        , 0,
22090        XMMS_               },        /* ADDU[4X4] */
22091     { instruction         , 0                   , 0   , 16,
22092        0xfd08    , 0x3c08    , &NMD::MUL_4X4_         , 0,
22093        XMMS_               },        /* MUL[4X4] */
22094     { reserved_block      , 0                   , 0   , 16,
22095        0xfd08    , 0x3d00    , 0                      , 0,
22096        0x0                 },        /* P16.4X4~*(2) */
22097     { reserved_block      , 0                   , 0   , 16,
22098        0xfd08    , 0x3d08    , 0                      , 0,
22099        0x0                 },        /* P16.4X4~*(3) */
22100 };
22101
22102
22103 NMD::Pool NMD::P16_LB[4] = {
22104     { instruction         , 0                   , 0   , 16,
22105        0xfc0c    , 0x5c00    , &NMD::LB_16_           , 0,
22106        0x0                 },        /* LB[16] */
22107     { instruction         , 0                   , 0   , 16,
22108        0xfc0c    , 0x5c04    , &NMD::SB_16_           , 0,
22109        0x0                 },        /* SB[16] */
22110     { instruction         , 0                   , 0   , 16,
22111        0xfc0c    , 0x5c08    , &NMD::LBU_16_          , 0,
22112        0x0                 },        /* LBU[16] */
22113     { reserved_block      , 0                   , 0   , 16,
22114        0xfc0c    , 0x5c0c    , 0                      , 0,
22115        0x0                 },        /* P16.LB~*(3) */
22116 };
22117
22118
22119 NMD::Pool NMD::P16_LH[4] = {
22120     { instruction         , 0                   , 0   , 16,
22121        0xfc09    , 0x7c00    , &NMD::LH_16_           , 0,
22122        0x0                 },        /* LH[16] */
22123     { instruction         , 0                   , 0   , 16,
22124        0xfc09    , 0x7c01    , &NMD::SH_16_           , 0,
22125        0x0                 },        /* SH[16] */
22126     { instruction         , 0                   , 0   , 16,
22127        0xfc09    , 0x7c08    , &NMD::LHU_16_          , 0,
22128        0x0                 },        /* LHU[16] */
22129     { reserved_block      , 0                   , 0   , 16,
22130        0xfc09    , 0x7c09    , 0                      , 0,
22131        0x0                 },        /* P16.LH~*(3) */
22132 };
22133
22134
22135 NMD::Pool NMD::P16[32] = {
22136     { pool                , P16_MV              , 2   , 16,
22137        0xfc00    , 0x1000    , 0                      , 0,
22138        0x0                 },        /* P16.MV */
22139     { pool                , P16_SHIFT           , 2   , 16,
22140        0xfc00    , 0x3000    , 0                      , 0,
22141        0x0                 },        /* P16.SHIFT */
22142     { pool                , P16C                , 2   , 16,
22143        0xfc00    , 0x5000    , 0                      , 0,
22144        0x0                 },        /* P16C */
22145     { pool                , P16_A1              , 2   , 16,
22146        0xfc00    , 0x7000    , 0                      , 0,
22147        0x0                 },        /* P16.A1 */
22148     { pool                , P16_A2              , 2   , 16,
22149        0xfc00    , 0x9000    , 0                      , 0,
22150        0x0                 },        /* P16.A2 */
22151     { pool                , P16_ADDU            , 2   , 16,
22152        0xfc00    , 0xb000    , 0                      , 0,
22153        0x0                 },        /* P16.ADDU */
22154     { instruction         , 0                   , 0   , 16,
22155        0xfc00    , 0xd000    , &NMD::LI_16_           , 0,
22156        0x0                 },        /* LI[16] */
22157     { instruction         , 0                   , 0   , 16,
22158        0xfc00    , 0xf000    , &NMD::ANDI_16_         , 0,
22159        0x0                 },        /* ANDI[16] */
22160     { instruction         , 0                   , 0   , 16,
22161        0xfc00    , 0x1400    , &NMD::LW_16_           , 0,
22162        0x0                 },        /* LW[16] */
22163     { instruction         , 0                   , 0   , 16,
22164        0xfc00    , 0x3400    , &NMD::LW_SP_           , 0,
22165        0x0                 },        /* LW[SP] */
22166     { instruction         , 0                   , 0   , 16,
22167        0xfc00    , 0x5400    , &NMD::LW_GP16_         , 0,
22168        0x0                 },        /* LW[GP16] */
22169     { instruction         , 0                   , 0   , 16,
22170        0xfc00    , 0x7400    , &NMD::LW_4X4_          , 0,
22171        XMMS_               },        /* LW[4X4] */
22172     { instruction         , 0                   , 0   , 16,
22173        0xfc00    , 0x9400    , &NMD::SW_16_           , 0,
22174        0x0                 },        /* SW[16] */
22175     { instruction         , 0                   , 0   , 16,
22176        0xfc00    , 0xb400    , &NMD::SW_SP_           , 0,
22177        0x0                 },        /* SW[SP] */
22178     { instruction         , 0                   , 0   , 16,
22179        0xfc00    , 0xd400    , &NMD::SW_GP16_         , 0,
22180        0x0                 },        /* SW[GP16] */
22181     { instruction         , 0                   , 0   , 16,
22182        0xfc00    , 0xf400    , &NMD::SW_4X4_          , 0,
22183        XMMS_               },        /* SW[4X4] */
22184     { branch_instruction  , 0                   , 0   , 16,
22185        0xfc00    , 0x1800    , &NMD::BC_16_           , 0,
22186        0x0                 },        /* BC[16] */
22187     { call_instruction    , 0                   , 0   , 16,
22188        0xfc00    , 0x3800    , &NMD::BALC_16_         , 0,
22189        0x0                 },        /* BALC[16] */
22190     { reserved_block      , 0                   , 0   , 16,
22191        0xfc00    , 0x5800    , 0                      , 0,
22192        0x0                 },        /* P16~*(10) */
22193     { reserved_block      , 0                   , 0   , 16,
22194        0xfc00    , 0x7800    , 0                      , 0,
22195        0x0                 },        /* P16~*(14) */
22196     { branch_instruction  , 0                   , 0   , 16,
22197        0xfc00    , 0x9800    , &NMD::BEQZC_16_        , 0,
22198        0x0                 },        /* BEQZC[16] */
22199     { branch_instruction  , 0                   , 0   , 16,
22200        0xfc00    , 0xb800    , &NMD::BNEZC_16_        , 0,
22201        0x0                 },        /* BNEZC[16] */
22202     { pool                , P16_BR              , 2   , 16,
22203        0xfc00    , 0xd800    , 0                      , 0,
22204        0x0                 },        /* P16.BR */
22205     { reserved_block      , 0                   , 0   , 16,
22206        0xfc00    , 0xf800    , 0                      , 0,
22207        0x0                 },        /* P16~*(30) */
22208     { pool                , P16_SR              , 2   , 16,
22209        0xfc00    , 0x1c00    , 0                      , 0,
22210        0x0                 },        /* P16.SR */
22211     { pool                , P16_4X4             , 4   , 16,
22212        0xfc00    , 0x3c00    , 0                      , 0,
22213        0x0                 },        /* P16.4X4 */
22214     { pool                , P16_LB              , 4   , 16,
22215        0xfc00    , 0x5c00    , 0                      , 0,
22216        0x0                 },        /* P16.LB */
22217     { pool                , P16_LH              , 4   , 16,
22218        0xfc00    , 0x7c00    , 0                      , 0,
22219        0x0                 },        /* P16.LH */
22220     { reserved_block      , 0                   , 0   , 16,
22221        0xfc00    , 0x9c00    , 0                      , 0,
22222        0x0                 },        /* P16~*(19) */
22223     { instruction         , 0                   , 0   , 16,
22224        0xfc00    , 0xbc00    , &NMD::MOVEP            , 0,
22225        XMMS_               },        /* MOVEP */
22226     { reserved_block      , 0                   , 0   , 16,
22227        0xfc00    , 0xdc00    , 0                      , 0,
22228        0x0                 },        /* P16~*(27) */
22229     { instruction         , 0                   , 0   , 16,
22230        0xfc00    , 0xfc00    , &NMD::MOVEP_REV_       , 0,
22231        XMMS_               },        /* MOVEP[REV] */
22232 };
22233
22234
22235 NMD::Pool NMD::MAJOR[2] = {
22236     { pool                , P32                 , 32  , 32,
22237        0x10000000, 0x00000000, 0                      , 0,
22238        0x0                 },        /* P32 */
22239     { pool                , P16                 , 32  , 16,
22240        0x1000    , 0x1000    , 0                      , 0,
22241        0x0                 },        /* P16 */
22242 };