target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         env->pstate = PSTATE_MODE_EL1h;
 117         env->pc = cpu->rvbar;
 118 #endif
 119     } else {
 120 #if defined(CONFIG_USER_ONLY)
 121         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 122         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 123 #endif
 124     }
 125
 126 #if defined(CONFIG_USER_ONLY)
 127     env->uncached_cpsr = ARM_CPU_MODE_USR;
 128     /* For user mode we must enable access to coprocessors */
 129     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 130     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 131         env->cp15.c15_cpar = 3;
 132     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 133         env->cp15.c15_cpar = 1;
 134     }
 135 #else
 136     /* SVC mode with interrupts disabled.  */
 137     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 138     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 139     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 140      * clear at reset. Initial SP and PC are loaded from ROM.
 141      */
 142     if (IS_M(env)) {
 143         uint32_t initial_msp; /* Loaded from 0x0 */
 144         uint32_t initial_pc; /* Loaded from 0x4 */
 145         uint8_t *rom;
 146
 147         env->daif &= ~PSTATE_I;
 148         rom = rom_ptr(0);
 149         if (rom) {
 150             /* Address zero is covered by ROM which hasn't yet been
 151              * copied into physical memory.
 152              */
 153             initial_msp = ldl_p(rom);
 154             initial_pc = ldl_p(rom + 4);
 155         } else {
 156             /* Address zero not covered by a ROM blob, or the ROM blob
 157              * is in non-modifiable memory and this is a second reset after
 158              * it got copied into memory. In the latter case, rom_ptr
 159              * will return a NULL pointer and we should use ldl_phys instead.
 160              */
 161             initial_msp = ldl_phys(s->as, 0);
 162             initial_pc = ldl_phys(s->as, 4);
 163         }
 164
 165         env->regs[13] = initial_msp & 0xFFFFFFFC;
 166         env->regs[15] = initial_pc & ~1;
 167         env->thumb = initial_pc & 1;
 168     }
 169
 170     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 171      * executing as AArch32 then check if highvecs are enabled and
 172      * adjust the PC accordingly.
 173      */
 174     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 175         env->regs[15] = 0xFFFF0000;
 176     }
 177
 178     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 179 #endif
 180     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 181     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 182     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 183     set_float_detect_tininess(float_tininess_before_rounding,
 184                               &env->vfp.fp_status);
 185     set_float_detect_tininess(float_tininess_before_rounding,
 186                               &env->vfp.standard_fp_status);
 187     tlb_flush(s, 1);
 188
 189 #ifndef CONFIG_USER_ONLY
 190     if (kvm_enabled()) {
 191         kvm_arm_reset_vcpu(cpu);
 192     }
 193 #endif
 194
 195     hw_breakpoint_update_all(cpu);
 196     hw_watchpoint_update_all(cpu);
 197 }
 198
 199 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 200 {
 201     CPUClass *cc = CPU_GET_CLASS(cs);
 202     bool ret = false;
 203
 204     if (interrupt_request & CPU_INTERRUPT_FIQ
 205         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 206         cs->exception_index = EXCP_FIQ;
 207         cc->do_interrupt(cs);
 208         ret = true;
 209     }
 210     if (interrupt_request & CPU_INTERRUPT_HARD
 211         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 212         cs->exception_index = EXCP_IRQ;
 213         cc->do_interrupt(cs);
 214         ret = true;
 215     }
 216     if (interrupt_request & CPU_INTERRUPT_VIRQ
 217         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 218         cs->exception_index = EXCP_VIRQ;
 219         cc->do_interrupt(cs);
 220         ret = true;
 221     }
 222     if (interrupt_request & CPU_INTERRUPT_VFIQ
 223         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 224         cs->exception_index = EXCP_VFIQ;
 225         cc->do_interrupt(cs);
 226         ret = true;
 227     }
 228
 229     return ret;
 230 }
 231
 232 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 233 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 234 {
 235     CPUClass *cc = CPU_GET_CLASS(cs);
 236     ARMCPU *cpu = ARM_CPU(cs);
 237     CPUARMState *env = &cpu->env;
 238     bool ret = false;
 239
 240
 241     if (interrupt_request & CPU_INTERRUPT_FIQ
 242         && !(env->daif & PSTATE_F)) {
 243         cs->exception_index = EXCP_FIQ;
 244         cc->do_interrupt(cs);
 245         ret = true;
 246     }
 247     /* ARMv7-M interrupt return works by loading a magic value
 248      * into the PC.  On real hardware the load causes the
 249      * return to occur.  The qemu implementation performs the
 250      * jump normally, then does the exception return when the
 251      * CPU tries to execute code at the magic address.
 252      * This will cause the magic PC value to be pushed to
 253      * the stack if an interrupt occurred at the wrong time.
 254      * We avoid this by disabling interrupts when
 255      * pc contains a magic address.
 256      */
 257     if (interrupt_request & CPU_INTERRUPT_HARD
 258         && !(env->daif & PSTATE_I)
 259         && (env->regs[15] < 0xfffffff0)) {
 260         cs->exception_index = EXCP_IRQ;
 261         cc->do_interrupt(cs);
 262         ret = true;
 263     }
 264     return ret;
 265 }
 266 #endif
 267
 268 #ifndef CONFIG_USER_ONLY
 269 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 270 {
 271     ARMCPU *cpu = opaque;
 272     CPUARMState *env = &cpu->env;
 273     CPUState *cs = CPU(cpu);
 274     static const int mask[] = {
 275         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 276         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 277         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 278         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 279     };
 280
 281     switch (irq) {
 282     case ARM_CPU_VIRQ:
 283     case ARM_CPU_VFIQ:
 284         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 285             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 286                      __func__, irq);
 287         }
 288         /* fall through */
 289     case ARM_CPU_IRQ:
 290     case ARM_CPU_FIQ:
 291         if (level) {
 292             cpu_interrupt(cs, mask[irq]);
 293         } else {
 294             cpu_reset_interrupt(cs, mask[irq]);
 295         }
 296         break;
 297     default:
 298         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 299     }
 300 }
 301
 302 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 303 {
 304 #ifdef CONFIG_KVM
 305     ARMCPU *cpu = opaque;
 306     CPUState *cs = CPU(cpu);
 307     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 308
 309     switch (irq) {
 310     case ARM_CPU_IRQ:
 311         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 312         break;
 313     case ARM_CPU_FIQ:
 314         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 315         break;
 316     default:
 317         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 318     }
 319     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 320     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 321 #endif
 322 }
 323 #endif
 324
 325 static inline void set_feature(CPUARMState *env, int feature)
 326 {
 327     env->features |= 1ULL << feature;
 328 }
 329
 330 static inline void unset_feature(CPUARMState *env, int feature)
 331 {
 332     env->features &= ~(1ULL << feature);
 333 }
 334
 335 static void arm_cpu_initfn(Object *obj)
 336 {
 337     CPUState *cs = CPU(obj);
 338     ARMCPU *cpu = ARM_CPU(obj);
 339     static bool inited;
 340
 341     cs->env_ptr = &cpu->env;
 342     cpu_exec_init(&cpu->env);
 343     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 344                                          g_free, g_free);
 345
 346 #ifndef CONFIG_USER_ONLY
 347     /* Our inbound IRQ and FIQ lines */
 348     if (kvm_enabled()) {
 349         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 350          * the same interface as non-KVM CPUs.
 351          */
 352         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 353     } else {
 354         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 355     }
 356
 357     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 358                                                 arm_gt_ptimer_cb, cpu);
 359     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 360                                                 arm_gt_vtimer_cb, cpu);
 361     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 362                        ARRAY_SIZE(cpu->gt_timer_outputs));
 363 #endif
 364
 365     /* DTB consumers generally don't in fact care what the 'compatible'
 366      * string is, so always provide some string and trust that a hypothetical
 367      * picky DTB consumer will also provide a helpful error message.
 368      */
 369     cpu->dtb_compatible = "qemu,unknown";
 370     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 371     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 372
 373     if (tcg_enabled()) {
 374         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 375         if (!inited) {
 376             inited = true;
 377             arm_translate_init();
 378         }
 379     }
 380 }
 381
 382 static Property arm_cpu_reset_cbar_property =
 383             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 384
 385 static Property arm_cpu_reset_hivecs_property =
 386             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 387
 388 static Property arm_cpu_rvbar_property =
 389             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 390
 391 static void arm_cpu_post_init(Object *obj)
 392 {
 393     ARMCPU *cpu = ARM_CPU(obj);
 394
 395     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 396         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 397         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 398                                  &error_abort);
 399     }
 400
 401     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 402         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 403                                  &error_abort);
 404     }
 405
 406     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 407         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 408                                  &error_abort);
 409     }
 410 }
 411
 412 static void arm_cpu_finalizefn(Object *obj)
 413 {
 414     ARMCPU *cpu = ARM_CPU(obj);
 415     g_hash_table_destroy(cpu->cp_regs);
 416 }
 417
 418 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 419 {
 420     CPUState *cs = CPU(dev);
 421     ARMCPU *cpu = ARM_CPU(dev);
 422     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 423     CPUARMState *env = &cpu->env;
 424
 425     /* Some features automatically imply others: */
 426     if (arm_feature(env, ARM_FEATURE_V8)) {
 427         set_feature(env, ARM_FEATURE_V7);
 428         set_feature(env, ARM_FEATURE_ARM_DIV);
 429         set_feature(env, ARM_FEATURE_LPAE);
 430     }
 431     if (arm_feature(env, ARM_FEATURE_V7)) {
 432         set_feature(env, ARM_FEATURE_VAPA);
 433         set_feature(env, ARM_FEATURE_THUMB2);
 434         set_feature(env, ARM_FEATURE_MPIDR);
 435         if (!arm_feature(env, ARM_FEATURE_M)) {
 436             set_feature(env, ARM_FEATURE_V6K);
 437         } else {
 438             set_feature(env, ARM_FEATURE_V6);
 439         }
 440     }
 441     if (arm_feature(env, ARM_FEATURE_V6K)) {
 442         set_feature(env, ARM_FEATURE_V6);
 443         set_feature(env, ARM_FEATURE_MVFR);
 444     }
 445     if (arm_feature(env, ARM_FEATURE_V6)) {
 446         set_feature(env, ARM_FEATURE_V5);
 447         if (!arm_feature(env, ARM_FEATURE_M)) {
 448             set_feature(env, ARM_FEATURE_AUXCR);
 449         }
 450     }
 451     if (arm_feature(env, ARM_FEATURE_V5)) {
 452         set_feature(env, ARM_FEATURE_V4T);
 453     }
 454     if (arm_feature(env, ARM_FEATURE_M)) {
 455         set_feature(env, ARM_FEATURE_THUMB_DIV);
 456     }
 457     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 458         set_feature(env, ARM_FEATURE_THUMB_DIV);
 459     }
 460     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 461         set_feature(env, ARM_FEATURE_VFP3);
 462         set_feature(env, ARM_FEATURE_VFP_FP16);
 463     }
 464     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 465         set_feature(env, ARM_FEATURE_VFP);
 466     }
 467     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 468         set_feature(env, ARM_FEATURE_V7MP);
 469         set_feature(env, ARM_FEATURE_PXN);
 470     }
 471     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 472         set_feature(env, ARM_FEATURE_CBAR);
 473     }
 474
 475     if (cpu->reset_hivecs) {
 476             cpu->reset_sctlr |= (1 << 13);
 477     }
 478
 479     register_cp_regs_for_features(cpu);
 480     arm_cpu_register_gdb_regs_for_features(cpu);
 481
 482     init_cpreg_list(cpu);
 483
 484     qemu_init_vcpu(cs);
 485     cpu_reset(cs);
 486
 487     acc->parent_realize(dev, errp);
 488 }
 489
 490 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 491 {
 492     ObjectClass *oc;
 493     char *typename;
 494
 495     if (!cpu_model) {
 496         return NULL;
 497     }
 498
 499     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 500     oc = object_class_by_name(typename);
 501     g_free(typename);
 502     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 503         object_class_is_abstract(oc)) {
 504         return NULL;
 505     }
 506     return oc;
 507 }
 508
 509 /* CPU models. These are not needed for the AArch64 linux-user build. */
 510 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 511
 512 static void arm926_initfn(Object *obj)
 513 {
 514     ARMCPU *cpu = ARM_CPU(obj);
 515
 516     cpu->dtb_compatible = "arm,arm926";
 517     set_feature(&cpu->env, ARM_FEATURE_V5);
 518     set_feature(&cpu->env, ARM_FEATURE_VFP);
 519     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 520     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 521     cpu->midr = 0x41069265;
 522     cpu->reset_fpsid = 0x41011090;
 523     cpu->ctr = 0x1dd20d2;
 524     cpu->reset_sctlr = 0x00090078;
 525 }
 526
 527 static void arm946_initfn(Object *obj)
 528 {
 529     ARMCPU *cpu = ARM_CPU(obj);
 530
 531     cpu->dtb_compatible = "arm,arm946";
 532     set_feature(&cpu->env, ARM_FEATURE_V5);
 533     set_feature(&cpu->env, ARM_FEATURE_MPU);
 534     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 535     cpu->midr = 0x41059461;
 536     cpu->ctr = 0x0f004006;
 537     cpu->reset_sctlr = 0x00000078;
 538 }
 539
 540 static void arm1026_initfn(Object *obj)
 541 {
 542     ARMCPU *cpu = ARM_CPU(obj);
 543
 544     cpu->dtb_compatible = "arm,arm1026";
 545     set_feature(&cpu->env, ARM_FEATURE_V5);
 546     set_feature(&cpu->env, ARM_FEATURE_VFP);
 547     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 548     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 549     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 550     cpu->midr = 0x4106a262;
 551     cpu->reset_fpsid = 0x410110a0;
 552     cpu->ctr = 0x1dd20d2;
 553     cpu->reset_sctlr = 0x00090078;
 554     cpu->reset_auxcr = 1;
 555     {
 556         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 557         ARMCPRegInfo ifar = {
 558             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 559             .access = PL1_RW,
 560             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 561             .resetvalue = 0
 562         };
 563         define_one_arm_cp_reg(cpu, &ifar);
 564     }
 565 }
 566
 567 static void arm1136_r2_initfn(Object *obj)
 568 {
 569     ARMCPU *cpu = ARM_CPU(obj);
 570     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 571      * older core than plain "arm1136". In particular this does not
 572      * have the v6K features.
 573      * These ID register values are correct for 1136 but may be wrong
 574      * for 1136_r2 (in particular r0p2 does not actually implement most
 575      * of the ID registers).
 576      */
 577
 578     cpu->dtb_compatible = "arm,arm1136";
 579     set_feature(&cpu->env, ARM_FEATURE_V6);
 580     set_feature(&cpu->env, ARM_FEATURE_VFP);
 581     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 582     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 583     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 584     cpu->midr = 0x4107b362;
 585     cpu->reset_fpsid = 0x410120b4;
 586     cpu->mvfr0 = 0x11111111;
 587     cpu->mvfr1 = 0x00000000;
 588     cpu->ctr = 0x1dd20d2;
 589     cpu->reset_sctlr = 0x00050078;
 590     cpu->id_pfr0 = 0x111;
 591     cpu->id_pfr1 = 0x1;
 592     cpu->id_dfr0 = 0x2;
 593     cpu->id_afr0 = 0x3;
 594     cpu->id_mmfr0 = 0x01130003;
 595     cpu->id_mmfr1 = 0x10030302;
 596     cpu->id_mmfr2 = 0x01222110;
 597     cpu->id_isar0 = 0x00140011;
 598     cpu->id_isar1 = 0x12002111;
 599     cpu->id_isar2 = 0x11231111;
 600     cpu->id_isar3 = 0x01102131;
 601     cpu->id_isar4 = 0x141;
 602     cpu->reset_auxcr = 7;
 603 }
 604
 605 static void arm1136_initfn(Object *obj)
 606 {
 607     ARMCPU *cpu = ARM_CPU(obj);
 608
 609     cpu->dtb_compatible = "arm,arm1136";
 610     set_feature(&cpu->env, ARM_FEATURE_V6K);
 611     set_feature(&cpu->env, ARM_FEATURE_V6);
 612     set_feature(&cpu->env, ARM_FEATURE_VFP);
 613     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 614     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 615     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 616     cpu->midr = 0x4117b363;
 617     cpu->reset_fpsid = 0x410120b4;
 618     cpu->mvfr0 = 0x11111111;
 619     cpu->mvfr1 = 0x00000000;
 620     cpu->ctr = 0x1dd20d2;
 621     cpu->reset_sctlr = 0x00050078;
 622     cpu->id_pfr0 = 0x111;
 623     cpu->id_pfr1 = 0x1;
 624     cpu->id_dfr0 = 0x2;
 625     cpu->id_afr0 = 0x3;
 626     cpu->id_mmfr0 = 0x01130003;
 627     cpu->id_mmfr1 = 0x10030302;
 628     cpu->id_mmfr2 = 0x01222110;
 629     cpu->id_isar0 = 0x00140011;
 630     cpu->id_isar1 = 0x12002111;
 631     cpu->id_isar2 = 0x11231111;
 632     cpu->id_isar3 = 0x01102131;
 633     cpu->id_isar4 = 0x141;
 634     cpu->reset_auxcr = 7;
 635 }
 636
 637 static void arm1176_initfn(Object *obj)
 638 {
 639     ARMCPU *cpu = ARM_CPU(obj);
 640
 641     cpu->dtb_compatible = "arm,arm1176";
 642     set_feature(&cpu->env, ARM_FEATURE_V6K);
 643     set_feature(&cpu->env, ARM_FEATURE_VFP);
 644     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 645     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 646     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 647     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 648     cpu->midr = 0x410fb767;
 649     cpu->reset_fpsid = 0x410120b5;
 650     cpu->mvfr0 = 0x11111111;
 651     cpu->mvfr1 = 0x00000000;
 652     cpu->ctr = 0x1dd20d2;
 653     cpu->reset_sctlr = 0x00050078;
 654     cpu->id_pfr0 = 0x111;
 655     cpu->id_pfr1 = 0x11;
 656     cpu->id_dfr0 = 0x33;
 657     cpu->id_afr0 = 0;
 658     cpu->id_mmfr0 = 0x01130003;
 659     cpu->id_mmfr1 = 0x10030302;
 660     cpu->id_mmfr2 = 0x01222100;
 661     cpu->id_isar0 = 0x0140011;
 662     cpu->id_isar1 = 0x12002111;
 663     cpu->id_isar2 = 0x11231121;
 664     cpu->id_isar3 = 0x01102131;
 665     cpu->id_isar4 = 0x01141;
 666     cpu->reset_auxcr = 7;
 667 }
 668
 669 static void arm11mpcore_initfn(Object *obj)
 670 {
 671     ARMCPU *cpu = ARM_CPU(obj);
 672
 673     cpu->dtb_compatible = "arm,arm11mpcore";
 674     set_feature(&cpu->env, ARM_FEATURE_V6K);
 675     set_feature(&cpu->env, ARM_FEATURE_VFP);
 676     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 677     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 678     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 679     cpu->midr = 0x410fb022;
 680     cpu->reset_fpsid = 0x410120b4;
 681     cpu->mvfr0 = 0x11111111;
 682     cpu->mvfr1 = 0x00000000;
 683     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 684     cpu->id_pfr0 = 0x111;
 685     cpu->id_pfr1 = 0x1;
 686     cpu->id_dfr0 = 0;
 687     cpu->id_afr0 = 0x2;
 688     cpu->id_mmfr0 = 0x01100103;
 689     cpu->id_mmfr1 = 0x10020302;
 690     cpu->id_mmfr2 = 0x01222000;
 691     cpu->id_isar0 = 0x00100011;
 692     cpu->id_isar1 = 0x12002111;
 693     cpu->id_isar2 = 0x11221011;
 694     cpu->id_isar3 = 0x01102131;
 695     cpu->id_isar4 = 0x141;
 696     cpu->reset_auxcr = 1;
 697 }
 698
 699 static void cortex_m3_initfn(Object *obj)
 700 {
 701     ARMCPU *cpu = ARM_CPU(obj);
 702     set_feature(&cpu->env, ARM_FEATURE_V7);
 703     set_feature(&cpu->env, ARM_FEATURE_M);
 704     cpu->midr = 0x410fc231;
 705 }
 706
 707 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 708 {
 709     CPUClass *cc = CPU_CLASS(oc);
 710
 711 #ifndef CONFIG_USER_ONLY
 712     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 713 #endif
 714
 715     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 716 }
 717
 718 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 719     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 720       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 721     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 722       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 723     REGINFO_SENTINEL
 724 };
 725
 726 static void cortex_a8_initfn(Object *obj)
 727 {
 728     ARMCPU *cpu = ARM_CPU(obj);
 729
 730     cpu->dtb_compatible = "arm,cortex-a8";
 731     set_feature(&cpu->env, ARM_FEATURE_V7);
 732     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 733     set_feature(&cpu->env, ARM_FEATURE_NEON);
 734     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 735     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 736     cpu->midr = 0x410fc080;
 737     cpu->reset_fpsid = 0x410330c0;
 738     cpu->mvfr0 = 0x11110222;
 739     cpu->mvfr1 = 0x00011100;
 740     cpu->ctr = 0x82048004;
 741     cpu->reset_sctlr = 0x00c50078;
 742     cpu->id_pfr0 = 0x1031;
 743     cpu->id_pfr1 = 0x11;
 744     cpu->id_dfr0 = 0x400;
 745     cpu->id_afr0 = 0;
 746     cpu->id_mmfr0 = 0x31100003;
 747     cpu->id_mmfr1 = 0x20000000;
 748     cpu->id_mmfr2 = 0x01202000;
 749     cpu->id_mmfr3 = 0x11;
 750     cpu->id_isar0 = 0x00101111;
 751     cpu->id_isar1 = 0x12112111;
 752     cpu->id_isar2 = 0x21232031;
 753     cpu->id_isar3 = 0x11112131;
 754     cpu->id_isar4 = 0x00111142;
 755     cpu->dbgdidr = 0x15141000;
 756     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 757     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 758     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 759     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 760     cpu->reset_auxcr = 2;
 761     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 762 }
 763
 764 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 765     /* power_control should be set to maximum latency. Again,
 766      * default to 0 and set by private hook
 767      */
 768     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 769       .access = PL1_RW, .resetvalue = 0,
 770       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 771     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 772       .access = PL1_RW, .resetvalue = 0,
 773       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 774     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 775       .access = PL1_RW, .resetvalue = 0,
 776       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 777     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 778       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 779     /* TLB lockdown control */
 780     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 781       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 782     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 783       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 784     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 785       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 786     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 787       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 788     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 789       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 790     REGINFO_SENTINEL
 791 };
 792
 793 static void cortex_a9_initfn(Object *obj)
 794 {
 795     ARMCPU *cpu = ARM_CPU(obj);
 796
 797     cpu->dtb_compatible = "arm,cortex-a9";
 798     set_feature(&cpu->env, ARM_FEATURE_V7);
 799     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 800     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 801     set_feature(&cpu->env, ARM_FEATURE_NEON);
 802     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 803     /* Note that A9 supports the MP extensions even for
 804      * A9UP and single-core A9MP (which are both different
 805      * and valid configurations; we don't model A9UP).
 806      */
 807     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 808     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 809     cpu->midr = 0x410fc090;
 810     cpu->reset_fpsid = 0x41033090;
 811     cpu->mvfr0 = 0x11110222;
 812     cpu->mvfr1 = 0x01111111;
 813     cpu->ctr = 0x80038003;
 814     cpu->reset_sctlr = 0x00c50078;
 815     cpu->id_pfr0 = 0x1031;
 816     cpu->id_pfr1 = 0x11;
 817     cpu->id_dfr0 = 0x000;
 818     cpu->id_afr0 = 0;
 819     cpu->id_mmfr0 = 0x00100103;
 820     cpu->id_mmfr1 = 0x20000000;
 821     cpu->id_mmfr2 = 0x01230000;
 822     cpu->id_mmfr3 = 0x00002111;
 823     cpu->id_isar0 = 0x00101111;
 824     cpu->id_isar1 = 0x13112111;
 825     cpu->id_isar2 = 0x21232041;
 826     cpu->id_isar3 = 0x11112131;
 827     cpu->id_isar4 = 0x00111142;
 828     cpu->dbgdidr = 0x35141000;
 829     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 830     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 831     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 832     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 833 }
 834
 835 #ifndef CONFIG_USER_ONLY
 836 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 837 {
 838     /* Linux wants the number of processors from here.
 839      * Might as well set the interrupt-controller bit too.
 840      */
 841     return ((smp_cpus - 1) << 24) | (1 << 23);
 842 }
 843 #endif
 844
 845 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 846 #ifndef CONFIG_USER_ONLY
 847     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 848       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 849       .writefn = arm_cp_write_ignore, },
 850 #endif
 851     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 852       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 853     REGINFO_SENTINEL
 854 };
 855
 856 static void cortex_a15_initfn(Object *obj)
 857 {
 858     ARMCPU *cpu = ARM_CPU(obj);
 859
 860     cpu->dtb_compatible = "arm,cortex-a15";
 861     set_feature(&cpu->env, ARM_FEATURE_V7);
 862     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 863     set_feature(&cpu->env, ARM_FEATURE_NEON);
 864     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 865     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 866     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 867     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 868     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 869     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 870     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 871     cpu->midr = 0x412fc0f1;
 872     cpu->reset_fpsid = 0x410430f0;
 873     cpu->mvfr0 = 0x10110222;
 874     cpu->mvfr1 = 0x11111111;
 875     cpu->ctr = 0x8444c004;
 876     cpu->reset_sctlr = 0x00c50078;
 877     cpu->id_pfr0 = 0x00001131;
 878     cpu->id_pfr1 = 0x00011011;
 879     cpu->id_dfr0 = 0x02010555;
 880     cpu->id_afr0 = 0x00000000;
 881     cpu->id_mmfr0 = 0x10201105;
 882     cpu->id_mmfr1 = 0x20000000;
 883     cpu->id_mmfr2 = 0x01240000;
 884     cpu->id_mmfr3 = 0x02102211;
 885     cpu->id_isar0 = 0x02101110;
 886     cpu->id_isar1 = 0x13112111;
 887     cpu->id_isar2 = 0x21232041;
 888     cpu->id_isar3 = 0x11112131;
 889     cpu->id_isar4 = 0x10011142;
 890     cpu->dbgdidr = 0x3515f021;
 891     cpu->clidr = 0x0a200023;
 892     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 893     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 894     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 895     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 896 }
 897
 898 static void ti925t_initfn(Object *obj)
 899 {
 900     ARMCPU *cpu = ARM_CPU(obj);
 901     set_feature(&cpu->env, ARM_FEATURE_V4T);
 902     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 903     cpu->midr = ARM_CPUID_TI925T;
 904     cpu->ctr = 0x5109149;
 905     cpu->reset_sctlr = 0x00000070;
 906 }
 907
 908 static void sa1100_initfn(Object *obj)
 909 {
 910     ARMCPU *cpu = ARM_CPU(obj);
 911
 912     cpu->dtb_compatible = "intel,sa1100";
 913     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 914     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 915     cpu->midr = 0x4401A11B;
 916     cpu->reset_sctlr = 0x00000070;
 917 }
 918
 919 static void sa1110_initfn(Object *obj)
 920 {
 921     ARMCPU *cpu = ARM_CPU(obj);
 922     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 923     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 924     cpu->midr = 0x6901B119;
 925     cpu->reset_sctlr = 0x00000070;
 926 }
 927
 928 static void pxa250_initfn(Object *obj)
 929 {
 930     ARMCPU *cpu = ARM_CPU(obj);
 931
 932     cpu->dtb_compatible = "marvell,xscale";
 933     set_feature(&cpu->env, ARM_FEATURE_V5);
 934     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 935     cpu->midr = 0x69052100;
 936     cpu->ctr = 0xd172172;
 937     cpu->reset_sctlr = 0x00000078;
 938 }
 939
 940 static void pxa255_initfn(Object *obj)
 941 {
 942     ARMCPU *cpu = ARM_CPU(obj);
 943
 944     cpu->dtb_compatible = "marvell,xscale";
 945     set_feature(&cpu->env, ARM_FEATURE_V5);
 946     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 947     cpu->midr = 0x69052d00;
 948     cpu->ctr = 0xd172172;
 949     cpu->reset_sctlr = 0x00000078;
 950 }
 951
 952 static void pxa260_initfn(Object *obj)
 953 {
 954     ARMCPU *cpu = ARM_CPU(obj);
 955
 956     cpu->dtb_compatible = "marvell,xscale";
 957     set_feature(&cpu->env, ARM_FEATURE_V5);
 958     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 959     cpu->midr = 0x69052903;
 960     cpu->ctr = 0xd172172;
 961     cpu->reset_sctlr = 0x00000078;
 962 }
 963
 964 static void pxa261_initfn(Object *obj)
 965 {
 966     ARMCPU *cpu = ARM_CPU(obj);
 967
 968     cpu->dtb_compatible = "marvell,xscale";
 969     set_feature(&cpu->env, ARM_FEATURE_V5);
 970     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 971     cpu->midr = 0x69052d05;
 972     cpu->ctr = 0xd172172;
 973     cpu->reset_sctlr = 0x00000078;
 974 }
 975
 976 static void pxa262_initfn(Object *obj)
 977 {
 978     ARMCPU *cpu = ARM_CPU(obj);
 979
 980     cpu->dtb_compatible = "marvell,xscale";
 981     set_feature(&cpu->env, ARM_FEATURE_V5);
 982     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 983     cpu->midr = 0x69052d06;
 984     cpu->ctr = 0xd172172;
 985     cpu->reset_sctlr = 0x00000078;
 986 }
 987
 988 static void pxa270a0_initfn(Object *obj)
 989 {
 990     ARMCPU *cpu = ARM_CPU(obj);
 991
 992     cpu->dtb_compatible = "marvell,xscale";
 993     set_feature(&cpu->env, ARM_FEATURE_V5);
 994     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 995     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 996     cpu->midr = 0x69054110;
 997     cpu->ctr = 0xd172172;
 998     cpu->reset_sctlr = 0x00000078;
 999 }
1000
1001 static void pxa270a1_initfn(Object *obj)
1002 {
1003     ARMCPU *cpu = ARM_CPU(obj);
1004
1005     cpu->dtb_compatible = "marvell,xscale";
1006     set_feature(&cpu->env, ARM_FEATURE_V5);
1007     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1008     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1009     cpu->midr = 0x69054111;
1010     cpu->ctr = 0xd172172;
1011     cpu->reset_sctlr = 0x00000078;
1012 }
1013
1014 static void pxa270b0_initfn(Object *obj)
1015 {
1016     ARMCPU *cpu = ARM_CPU(obj);
1017
1018     cpu->dtb_compatible = "marvell,xscale";
1019     set_feature(&cpu->env, ARM_FEATURE_V5);
1020     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1021     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1022     cpu->midr = 0x69054112;
1023     cpu->ctr = 0xd172172;
1024     cpu->reset_sctlr = 0x00000078;
1025 }
1026
1027 static void pxa270b1_initfn(Object *obj)
1028 {
1029     ARMCPU *cpu = ARM_CPU(obj);
1030
1031     cpu->dtb_compatible = "marvell,xscale";
1032     set_feature(&cpu->env, ARM_FEATURE_V5);
1033     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1034     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1035     cpu->midr = 0x69054113;
1036     cpu->ctr = 0xd172172;
1037     cpu->reset_sctlr = 0x00000078;
1038 }
1039
1040 static void pxa270c0_initfn(Object *obj)
1041 {
1042     ARMCPU *cpu = ARM_CPU(obj);
1043
1044     cpu->dtb_compatible = "marvell,xscale";
1045     set_feature(&cpu->env, ARM_FEATURE_V5);
1046     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1047     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1048     cpu->midr = 0x69054114;
1049     cpu->ctr = 0xd172172;
1050     cpu->reset_sctlr = 0x00000078;
1051 }
1052
1053 static void pxa270c5_initfn(Object *obj)
1054 {
1055     ARMCPU *cpu = ARM_CPU(obj);
1056
1057     cpu->dtb_compatible = "marvell,xscale";
1058     set_feature(&cpu->env, ARM_FEATURE_V5);
1059     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1060     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1061     cpu->midr = 0x69054117;
1062     cpu->ctr = 0xd172172;
1063     cpu->reset_sctlr = 0x00000078;
1064 }
1065
1066 #ifdef CONFIG_USER_ONLY
1067 static void arm_any_initfn(Object *obj)
1068 {
1069     ARMCPU *cpu = ARM_CPU(obj);
1070     set_feature(&cpu->env, ARM_FEATURE_V8);
1071     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1072     set_feature(&cpu->env, ARM_FEATURE_NEON);
1073     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1074     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1075     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1076     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1077     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1078     set_feature(&cpu->env, ARM_FEATURE_CRC);
1079     cpu->midr = 0xffffffff;
1080 }
1081 #endif
1082
1083 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1084
1085 typedef struct ARMCPUInfo {
1086     const char *name;
1087     void (*initfn)(Object *obj);
1088     void (*class_init)(ObjectClass *oc, void *data);
1089 } ARMCPUInfo;
1090
1091 static const ARMCPUInfo arm_cpus[] = {
1092 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1093     { .name = "arm926",      .initfn = arm926_initfn },
1094     { .name = "arm946",      .initfn = arm946_initfn },
1095     { .name = "arm1026",     .initfn = arm1026_initfn },
1096     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1097      * older core than plain "arm1136". In particular this does not
1098      * have the v6K features.
1099      */
1100     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1101     { .name = "arm1136",     .initfn = arm1136_initfn },
1102     { .name = "arm1176",     .initfn = arm1176_initfn },
1103     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1104     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1105                              .class_init = arm_v7m_class_init },
1106     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1107     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1108     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1109     { .name = "ti925t",      .initfn = ti925t_initfn },
1110     { .name = "sa1100",      .initfn = sa1100_initfn },
1111     { .name = "sa1110",      .initfn = sa1110_initfn },
1112     { .name = "pxa250",      .initfn = pxa250_initfn },
1113     { .name = "pxa255",      .initfn = pxa255_initfn },
1114     { .name = "pxa260",      .initfn = pxa260_initfn },
1115     { .name = "pxa261",      .initfn = pxa261_initfn },
1116     { .name = "pxa262",      .initfn = pxa262_initfn },
1117     /* "pxa270" is an alias for "pxa270-a0" */
1118     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1119     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1120     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1121     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1122     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1123     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1124     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1125 #ifdef CONFIG_USER_ONLY
1126     { .name = "any",         .initfn = arm_any_initfn },
1127 #endif
1128 #endif
1129     { .name = NULL }
1130 };
1131
1132 static Property arm_cpu_properties[] = {
1133     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1134     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1135     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1136     DEFINE_PROP_END_OF_LIST()
1137 };
1138
1139 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1140 {
1141     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1142     CPUClass *cc = CPU_CLASS(acc);
1143     DeviceClass *dc = DEVICE_CLASS(oc);
1144
1145     acc->parent_realize = dc->realize;
1146     dc->realize = arm_cpu_realizefn;
1147     dc->props = arm_cpu_properties;
1148
1149     acc->parent_reset = cc->reset;
1150     cc->reset = arm_cpu_reset;
1151
1152     cc->class_by_name = arm_cpu_class_by_name;
1153     cc->has_work = arm_cpu_has_work;
1154     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1155     cc->dump_state = arm_cpu_dump_state;
1156     cc->set_pc = arm_cpu_set_pc;
1157     cc->gdb_read_register = arm_cpu_gdb_read_register;
1158     cc->gdb_write_register = arm_cpu_gdb_write_register;
1159 #ifdef CONFIG_USER_ONLY
1160     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1161 #else
1162     cc->do_interrupt = arm_cpu_do_interrupt;
1163     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1164     cc->vmsd = &vmstate_arm_cpu;
1165 #endif
1166     cc->gdb_num_core_regs = 26;
1167     cc->gdb_core_xml_file = "arm-core.xml";
1168     cc->gdb_stop_before_watchpoint = true;
1169     cc->debug_excp_handler = arm_debug_excp_handler;
1170 }
1171
1172 static void cpu_register(const ARMCPUInfo *info)
1173 {
1174     TypeInfo type_info = {
1175         .parent = TYPE_ARM_CPU,
1176         .instance_size = sizeof(ARMCPU),
1177         .instance_init = info->initfn,
1178         .class_size = sizeof(ARMCPUClass),
1179         .class_init = info->class_init,
1180     };
1181
1182     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1183     type_register(&type_info);
1184     g_free((void *)type_info.name);
1185 }
1186
1187 static const TypeInfo arm_cpu_type_info = {
1188     .name = TYPE_ARM_CPU,
1189     .parent = TYPE_CPU,
1190     .instance_size = sizeof(ARMCPU),
1191     .instance_init = arm_cpu_initfn,
1192     .instance_post_init = arm_cpu_post_init,
1193     .instance_finalize = arm_cpu_finalizefn,
1194     .abstract = true,
1195     .class_size = sizeof(ARMCPUClass),
1196     .class_init = arm_cpu_class_init,
1197 };
1198
1199 static void arm_cpu_register_types(void)
1200 {
1201     const ARMCPUInfo *info = arm_cpus;
1202
1203     type_register_static(&arm_cpu_type_info);
1204
1205     while (info->name) {
1206         cpu_register(info);
1207         info++;
1208     }
1209 }
1210
1211 type_init(arm_cpu_register_types)