target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "qapi/qmp/qerror.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31
  32 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     ARMCPU *cpu = ARM_CPU(cs);
  35
  36     cpu->env.regs[15] = value;
  37 }
  38
  39 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  40 {
  41     /* Reset a single ARMCPRegInfo register */
  42     ARMCPRegInfo *ri = value;
  43     ARMCPU *cpu = opaque;
  44
  45     if (ri->type & ARM_CP_SPECIAL) {
  46         return;
  47     }
  48
  49     if (ri->resetfn) {
  50         ri->resetfn(&cpu->env, ri);
  51         return;
  52     }
  53
  54     /* A zero offset is never possible as it would be regs[0]
  55      * so we use it to indicate that reset is being handled elsewhere.
  56      * This is basically only used for fields in non-core coprocessors
  57      * (like the pxa2xx ones).
  58      */
  59     if (!ri->fieldoffset) {
  60         return;
  61     }
  62
  63     if (ri->type & ARM_CP_64BIT) {
  64         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  65     } else {
  66         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  67     }
  68 }
  69
  70 /* CPUClass::reset() */
  71 static void arm_cpu_reset(CPUState *s)
  72 {
  73     ARMCPU *cpu = ARM_CPU(s);
  74     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  75     CPUARMState *env = &cpu->env;
  76
  77     acc->parent_reset(s);
  78
  79     memset(env, 0, offsetof(CPUARMState, breakpoints));
  80     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  81     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  82     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  83     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  84
  85     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  86         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  87     }
  88
  89     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  90         /* 64 bit CPUs always start in 64 bit mode */
  91         env->aarch64 = 1;
  92     }
  93
  94 #if defined(CONFIG_USER_ONLY)
  95     env->uncached_cpsr = ARM_CPU_MODE_USR;
  96     /* For user mode we must enable access to coprocessors */
  97     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  98     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  99         env->cp15.c15_cpar = 3;
 100     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 101         env->cp15.c15_cpar = 1;
 102     }
 103 #else
 104     /* SVC mode with interrupts disabled.  */
 105     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 106     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 107        clear at reset.  Initial SP and PC are loaded from ROM.  */
 108     if (IS_M(env)) {
 109         uint32_t pc;
 110         uint8_t *rom;
 111         env->uncached_cpsr &= ~CPSR_I;
 112         rom = rom_ptr(0);
 113         if (rom) {
 114             /* We should really use ldl_phys here, in case the guest
 115                modified flash and reset itself.  However images
 116                loaded via -kernel have not been copied yet, so load the
 117                values directly from there.  */
 118             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 119             pc = ldl_p(rom + 4);
 120             env->thumb = pc & 1;
 121             env->regs[15] = pc & ~1;
 122         }
 123     }
 124     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 125 #endif
 126     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 127     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 128     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 129     set_float_detect_tininess(float_tininess_before_rounding,
 130                               &env->vfp.fp_status);
 131     set_float_detect_tininess(float_tininess_before_rounding,
 132                               &env->vfp.standard_fp_status);
 133     tlb_flush(env, 1);
 134     /* Reset is a state change for some CPUARMState fields which we
 135      * bake assumptions about into translated code, so we need to
 136      * tb_flush().
 137      */
 138     tb_flush(env);
 139 }
 140
 141 #ifndef CONFIG_USER_ONLY
 142 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 143 {
 144     ARMCPU *cpu = opaque;
 145     CPUState *cs = CPU(cpu);
 146
 147     switch (irq) {
 148     case ARM_CPU_IRQ:
 149         if (level) {
 150             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 151         } else {
 152             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 153         }
 154         break;
 155     case ARM_CPU_FIQ:
 156         if (level) {
 157             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 158         } else {
 159             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 160         }
 161         break;
 162     default:
 163         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 164     }
 165 }
 166
 167 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 168 {
 169 #ifdef CONFIG_KVM
 170     ARMCPU *cpu = opaque;
 171     CPUState *cs = CPU(cpu);
 172     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 173
 174     switch (irq) {
 175     case ARM_CPU_IRQ:
 176         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 177         break;
 178     case ARM_CPU_FIQ:
 179         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 180         break;
 181     default:
 182         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 183     }
 184     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 185     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 186 #endif
 187 }
 188 #endif
 189
 190 static inline void set_feature(CPUARMState *env, int feature)
 191 {
 192     env->features |= 1ULL << feature;
 193 }
 194
 195 static void arm_cpu_initfn(Object *obj)
 196 {
 197     CPUState *cs = CPU(obj);
 198     ARMCPU *cpu = ARM_CPU(obj);
 199     static bool inited;
 200
 201     cs->env_ptr = &cpu->env;
 202     cpu_exec_init(&cpu->env);
 203     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 204                                          g_free, g_free);
 205
 206 #ifndef CONFIG_USER_ONLY
 207     /* Our inbound IRQ and FIQ lines */
 208     if (kvm_enabled()) {
 209         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 210     } else {
 211         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 212     }
 213
 214     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 215                                                 arm_gt_ptimer_cb, cpu);
 216     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 217                                                 arm_gt_vtimer_cb, cpu);
 218     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 219                        ARRAY_SIZE(cpu->gt_timer_outputs));
 220 #endif
 221
 222     /* DTB consumers generally don't in fact care what the 'compatible'
 223      * string is, so always provide some string and trust that a hypothetical
 224      * picky DTB consumer will also provide a helpful error message.
 225      */
 226     cpu->dtb_compatible = "qemu,unknown";
 227     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 228
 229     if (tcg_enabled() && !inited) {
 230         inited = true;
 231         arm_translate_init();
 232     }
 233 }
 234
 235 static Property arm_cpu_reset_cbar_property =
 236             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 237
 238 static void arm_cpu_post_init(Object *obj)
 239 {
 240     ARMCPU *cpu = ARM_CPU(obj);
 241     Error *err = NULL;
 242
 243     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 244         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 245                                  &err);
 246         assert_no_error(err);
 247     }
 248 }
 249
 250 static void arm_cpu_finalizefn(Object *obj)
 251 {
 252     ARMCPU *cpu = ARM_CPU(obj);
 253     g_hash_table_destroy(cpu->cp_regs);
 254 }
 255
 256 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 257 {
 258     CPUState *cs = CPU(dev);
 259     ARMCPU *cpu = ARM_CPU(dev);
 260     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 261     CPUARMState *env = &cpu->env;
 262
 263     /* Some features automatically imply others: */
 264     if (arm_feature(env, ARM_FEATURE_V8)) {
 265         set_feature(env, ARM_FEATURE_V7);
 266         set_feature(env, ARM_FEATURE_ARM_DIV);
 267         set_feature(env, ARM_FEATURE_LPAE);
 268         set_feature(env, ARM_FEATURE_V8_AES);
 269     }
 270     if (arm_feature(env, ARM_FEATURE_V7)) {
 271         set_feature(env, ARM_FEATURE_VAPA);
 272         set_feature(env, ARM_FEATURE_THUMB2);
 273         set_feature(env, ARM_FEATURE_MPIDR);
 274         if (!arm_feature(env, ARM_FEATURE_M)) {
 275             set_feature(env, ARM_FEATURE_V6K);
 276         } else {
 277             set_feature(env, ARM_FEATURE_V6);
 278         }
 279     }
 280     if (arm_feature(env, ARM_FEATURE_V6K)) {
 281         set_feature(env, ARM_FEATURE_V6);
 282         set_feature(env, ARM_FEATURE_MVFR);
 283     }
 284     if (arm_feature(env, ARM_FEATURE_V6)) {
 285         set_feature(env, ARM_FEATURE_V5);
 286         if (!arm_feature(env, ARM_FEATURE_M)) {
 287             set_feature(env, ARM_FEATURE_AUXCR);
 288         }
 289     }
 290     if (arm_feature(env, ARM_FEATURE_V5)) {
 291         set_feature(env, ARM_FEATURE_V4T);
 292     }
 293     if (arm_feature(env, ARM_FEATURE_M)) {
 294         set_feature(env, ARM_FEATURE_THUMB_DIV);
 295     }
 296     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 297         set_feature(env, ARM_FEATURE_THUMB_DIV);
 298     }
 299     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 300         set_feature(env, ARM_FEATURE_VFP3);
 301     }
 302     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 303         set_feature(env, ARM_FEATURE_VFP);
 304     }
 305     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 306         set_feature(env, ARM_FEATURE_V7MP);
 307         set_feature(env, ARM_FEATURE_PXN);
 308     }
 309
 310     register_cp_regs_for_features(cpu);
 311     arm_cpu_register_gdb_regs_for_features(cpu);
 312
 313     init_cpreg_list(cpu);
 314
 315     cpu_reset(cs);
 316     qemu_init_vcpu(cs);
 317
 318     acc->parent_realize(dev, errp);
 319 }
 320
 321 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 322 {
 323     ObjectClass *oc;
 324     char *typename;
 325
 326     if (!cpu_model) {
 327         return NULL;
 328     }
 329
 330     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 331     oc = object_class_by_name(typename);
 332     g_free(typename);
 333     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 334         object_class_is_abstract(oc)) {
 335         return NULL;
 336     }
 337     return oc;
 338 }
 339
 340 /* CPU models. These are not needed for the AArch64 linux-user build. */
 341 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 342
 343 static void arm926_initfn(Object *obj)
 344 {
 345     ARMCPU *cpu = ARM_CPU(obj);
 346
 347     cpu->dtb_compatible = "arm,arm926";
 348     set_feature(&cpu->env, ARM_FEATURE_V5);
 349     set_feature(&cpu->env, ARM_FEATURE_VFP);
 350     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 351     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 352     cpu->midr = 0x41069265;
 353     cpu->reset_fpsid = 0x41011090;
 354     cpu->ctr = 0x1dd20d2;
 355     cpu->reset_sctlr = 0x00090078;
 356 }
 357
 358 static void arm946_initfn(Object *obj)
 359 {
 360     ARMCPU *cpu = ARM_CPU(obj);
 361
 362     cpu->dtb_compatible = "arm,arm946";
 363     set_feature(&cpu->env, ARM_FEATURE_V5);
 364     set_feature(&cpu->env, ARM_FEATURE_MPU);
 365     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 366     cpu->midr = 0x41059461;
 367     cpu->ctr = 0x0f004006;
 368     cpu->reset_sctlr = 0x00000078;
 369 }
 370
 371 static void arm1026_initfn(Object *obj)
 372 {
 373     ARMCPU *cpu = ARM_CPU(obj);
 374
 375     cpu->dtb_compatible = "arm,arm1026";
 376     set_feature(&cpu->env, ARM_FEATURE_V5);
 377     set_feature(&cpu->env, ARM_FEATURE_VFP);
 378     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 379     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 380     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 381     cpu->midr = 0x4106a262;
 382     cpu->reset_fpsid = 0x410110a0;
 383     cpu->ctr = 0x1dd20d2;
 384     cpu->reset_sctlr = 0x00090078;
 385     cpu->reset_auxcr = 1;
 386     {
 387         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 388         ARMCPRegInfo ifar = {
 389             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 390             .access = PL1_RW,
 391             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 392             .resetvalue = 0
 393         };
 394         define_one_arm_cp_reg(cpu, &ifar);
 395     }
 396 }
 397
 398 static void arm1136_r2_initfn(Object *obj)
 399 {
 400     ARMCPU *cpu = ARM_CPU(obj);
 401     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 402      * older core than plain "arm1136". In particular this does not
 403      * have the v6K features.
 404      * These ID register values are correct for 1136 but may be wrong
 405      * for 1136_r2 (in particular r0p2 does not actually implement most
 406      * of the ID registers).
 407      */
 408
 409     cpu->dtb_compatible = "arm,arm1136";
 410     set_feature(&cpu->env, ARM_FEATURE_V6);
 411     set_feature(&cpu->env, ARM_FEATURE_VFP);
 412     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 413     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 414     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 415     cpu->midr = 0x4107b362;
 416     cpu->reset_fpsid = 0x410120b4;
 417     cpu->mvfr0 = 0x11111111;
 418     cpu->mvfr1 = 0x00000000;
 419     cpu->ctr = 0x1dd20d2;
 420     cpu->reset_sctlr = 0x00050078;
 421     cpu->id_pfr0 = 0x111;
 422     cpu->id_pfr1 = 0x1;
 423     cpu->id_dfr0 = 0x2;
 424     cpu->id_afr0 = 0x3;
 425     cpu->id_mmfr0 = 0x01130003;
 426     cpu->id_mmfr1 = 0x10030302;
 427     cpu->id_mmfr2 = 0x01222110;
 428     cpu->id_isar0 = 0x00140011;
 429     cpu->id_isar1 = 0x12002111;
 430     cpu->id_isar2 = 0x11231111;
 431     cpu->id_isar3 = 0x01102131;
 432     cpu->id_isar4 = 0x141;
 433     cpu->reset_auxcr = 7;
 434 }
 435
 436 static void arm1136_initfn(Object *obj)
 437 {
 438     ARMCPU *cpu = ARM_CPU(obj);
 439
 440     cpu->dtb_compatible = "arm,arm1136";
 441     set_feature(&cpu->env, ARM_FEATURE_V6K);
 442     set_feature(&cpu->env, ARM_FEATURE_V6);
 443     set_feature(&cpu->env, ARM_FEATURE_VFP);
 444     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 445     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 446     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 447     cpu->midr = 0x4117b363;
 448     cpu->reset_fpsid = 0x410120b4;
 449     cpu->mvfr0 = 0x11111111;
 450     cpu->mvfr1 = 0x00000000;
 451     cpu->ctr = 0x1dd20d2;
 452     cpu->reset_sctlr = 0x00050078;
 453     cpu->id_pfr0 = 0x111;
 454     cpu->id_pfr1 = 0x1;
 455     cpu->id_dfr0 = 0x2;
 456     cpu->id_afr0 = 0x3;
 457     cpu->id_mmfr0 = 0x01130003;
 458     cpu->id_mmfr1 = 0x10030302;
 459     cpu->id_mmfr2 = 0x01222110;
 460     cpu->id_isar0 = 0x00140011;
 461     cpu->id_isar1 = 0x12002111;
 462     cpu->id_isar2 = 0x11231111;
 463     cpu->id_isar3 = 0x01102131;
 464     cpu->id_isar4 = 0x141;
 465     cpu->reset_auxcr = 7;
 466 }
 467
 468 static void arm1176_initfn(Object *obj)
 469 {
 470     ARMCPU *cpu = ARM_CPU(obj);
 471
 472     cpu->dtb_compatible = "arm,arm1176";
 473     set_feature(&cpu->env, ARM_FEATURE_V6K);
 474     set_feature(&cpu->env, ARM_FEATURE_VFP);
 475     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 476     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 477     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 478     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 479     cpu->midr = 0x410fb767;
 480     cpu->reset_fpsid = 0x410120b5;
 481     cpu->mvfr0 = 0x11111111;
 482     cpu->mvfr1 = 0x00000000;
 483     cpu->ctr = 0x1dd20d2;
 484     cpu->reset_sctlr = 0x00050078;
 485     cpu->id_pfr0 = 0x111;
 486     cpu->id_pfr1 = 0x11;
 487     cpu->id_dfr0 = 0x33;
 488     cpu->id_afr0 = 0;
 489     cpu->id_mmfr0 = 0x01130003;
 490     cpu->id_mmfr1 = 0x10030302;
 491     cpu->id_mmfr2 = 0x01222100;
 492     cpu->id_isar0 = 0x0140011;
 493     cpu->id_isar1 = 0x12002111;
 494     cpu->id_isar2 = 0x11231121;
 495     cpu->id_isar3 = 0x01102131;
 496     cpu->id_isar4 = 0x01141;
 497     cpu->reset_auxcr = 7;
 498 }
 499
 500 static void arm11mpcore_initfn(Object *obj)
 501 {
 502     ARMCPU *cpu = ARM_CPU(obj);
 503
 504     cpu->dtb_compatible = "arm,arm11mpcore";
 505     set_feature(&cpu->env, ARM_FEATURE_V6K);
 506     set_feature(&cpu->env, ARM_FEATURE_VFP);
 507     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 508     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 509     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 510     cpu->midr = 0x410fb022;
 511     cpu->reset_fpsid = 0x410120b4;
 512     cpu->mvfr0 = 0x11111111;
 513     cpu->mvfr1 = 0x00000000;
 514     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 515     cpu->id_pfr0 = 0x111;
 516     cpu->id_pfr1 = 0x1;
 517     cpu->id_dfr0 = 0;
 518     cpu->id_afr0 = 0x2;
 519     cpu->id_mmfr0 = 0x01100103;
 520     cpu->id_mmfr1 = 0x10020302;
 521     cpu->id_mmfr2 = 0x01222000;
 522     cpu->id_isar0 = 0x00100011;
 523     cpu->id_isar1 = 0x12002111;
 524     cpu->id_isar2 = 0x11221011;
 525     cpu->id_isar3 = 0x01102131;
 526     cpu->id_isar4 = 0x141;
 527     cpu->reset_auxcr = 1;
 528 }
 529
 530 static void cortex_m3_initfn(Object *obj)
 531 {
 532     ARMCPU *cpu = ARM_CPU(obj);
 533     set_feature(&cpu->env, ARM_FEATURE_V7);
 534     set_feature(&cpu->env, ARM_FEATURE_M);
 535     cpu->midr = 0x410fc231;
 536 }
 537
 538 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 539 {
 540 #ifndef CONFIG_USER_ONLY
 541     CPUClass *cc = CPU_CLASS(oc);
 542
 543     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 544 #endif
 545 }
 546
 547 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 548     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 549       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 550     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 551       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 552     REGINFO_SENTINEL
 553 };
 554
 555 static void cortex_a8_initfn(Object *obj)
 556 {
 557     ARMCPU *cpu = ARM_CPU(obj);
 558
 559     cpu->dtb_compatible = "arm,cortex-a8";
 560     set_feature(&cpu->env, ARM_FEATURE_V7);
 561     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 562     set_feature(&cpu->env, ARM_FEATURE_NEON);
 563     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 564     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 565     cpu->midr = 0x410fc080;
 566     cpu->reset_fpsid = 0x410330c0;
 567     cpu->mvfr0 = 0x11110222;
 568     cpu->mvfr1 = 0x00011100;
 569     cpu->ctr = 0x82048004;
 570     cpu->reset_sctlr = 0x00c50078;
 571     cpu->id_pfr0 = 0x1031;
 572     cpu->id_pfr1 = 0x11;
 573     cpu->id_dfr0 = 0x400;
 574     cpu->id_afr0 = 0;
 575     cpu->id_mmfr0 = 0x31100003;
 576     cpu->id_mmfr1 = 0x20000000;
 577     cpu->id_mmfr2 = 0x01202000;
 578     cpu->id_mmfr3 = 0x11;
 579     cpu->id_isar0 = 0x00101111;
 580     cpu->id_isar1 = 0x12112111;
 581     cpu->id_isar2 = 0x21232031;
 582     cpu->id_isar3 = 0x11112131;
 583     cpu->id_isar4 = 0x00111142;
 584     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 585     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 586     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 587     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 588     cpu->reset_auxcr = 2;
 589     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 590 }
 591
 592 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 593     /* power_control should be set to maximum latency. Again,
 594      * default to 0 and set by private hook
 595      */
 596     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 597       .access = PL1_RW, .resetvalue = 0,
 598       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 599     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 600       .access = PL1_RW, .resetvalue = 0,
 601       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 602     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 603       .access = PL1_RW, .resetvalue = 0,
 604       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 605     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 606       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 607     /* TLB lockdown control */
 608     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 609       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 610     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 611       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 612     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 613       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 614     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 615       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 616     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 617       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 618     REGINFO_SENTINEL
 619 };
 620
 621 static void cortex_a9_initfn(Object *obj)
 622 {
 623     ARMCPU *cpu = ARM_CPU(obj);
 624
 625     cpu->dtb_compatible = "arm,cortex-a9";
 626     set_feature(&cpu->env, ARM_FEATURE_V7);
 627     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 628     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 629     set_feature(&cpu->env, ARM_FEATURE_NEON);
 630     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 631     /* Note that A9 supports the MP extensions even for
 632      * A9UP and single-core A9MP (which are both different
 633      * and valid configurations; we don't model A9UP).
 634      */
 635     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 636     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 637     cpu->midr = 0x410fc090;
 638     cpu->reset_fpsid = 0x41033090;
 639     cpu->mvfr0 = 0x11110222;
 640     cpu->mvfr1 = 0x01111111;
 641     cpu->ctr = 0x80038003;
 642     cpu->reset_sctlr = 0x00c50078;
 643     cpu->id_pfr0 = 0x1031;
 644     cpu->id_pfr1 = 0x11;
 645     cpu->id_dfr0 = 0x000;
 646     cpu->id_afr0 = 0;
 647     cpu->id_mmfr0 = 0x00100103;
 648     cpu->id_mmfr1 = 0x20000000;
 649     cpu->id_mmfr2 = 0x01230000;
 650     cpu->id_mmfr3 = 0x00002111;
 651     cpu->id_isar0 = 0x00101111;
 652     cpu->id_isar1 = 0x13112111;
 653     cpu->id_isar2 = 0x21232041;
 654     cpu->id_isar3 = 0x11112131;
 655     cpu->id_isar4 = 0x00111142;
 656     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 657     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 658     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 659     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 660 }
 661
 662 #ifndef CONFIG_USER_ONLY
 663 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 664                            uint64_t *value)
 665 {
 666     /* Linux wants the number of processors from here.
 667      * Might as well set the interrupt-controller bit too.
 668      */
 669     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 670     return 0;
 671 }
 672 #endif
 673
 674 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 675 #ifndef CONFIG_USER_ONLY
 676     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 677       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 678       .writefn = arm_cp_write_ignore, },
 679 #endif
 680     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 681       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 682     REGINFO_SENTINEL
 683 };
 684
 685 static void cortex_a15_initfn(Object *obj)
 686 {
 687     ARMCPU *cpu = ARM_CPU(obj);
 688
 689     cpu->dtb_compatible = "arm,cortex-a15";
 690     set_feature(&cpu->env, ARM_FEATURE_V7);
 691     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 692     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 693     set_feature(&cpu->env, ARM_FEATURE_NEON);
 694     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 695     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 696     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 697     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 698     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 699     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 700     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 701     cpu->midr = 0x412fc0f1;
 702     cpu->reset_fpsid = 0x410430f0;
 703     cpu->mvfr0 = 0x10110222;
 704     cpu->mvfr1 = 0x11111111;
 705     cpu->ctr = 0x8444c004;
 706     cpu->reset_sctlr = 0x00c50078;
 707     cpu->id_pfr0 = 0x00001131;
 708     cpu->id_pfr1 = 0x00011011;
 709     cpu->id_dfr0 = 0x02010555;
 710     cpu->id_afr0 = 0x00000000;
 711     cpu->id_mmfr0 = 0x10201105;
 712     cpu->id_mmfr1 = 0x20000000;
 713     cpu->id_mmfr2 = 0x01240000;
 714     cpu->id_mmfr3 = 0x02102211;
 715     cpu->id_isar0 = 0x02101110;
 716     cpu->id_isar1 = 0x13112111;
 717     cpu->id_isar2 = 0x21232041;
 718     cpu->id_isar3 = 0x11112131;
 719     cpu->id_isar4 = 0x10011142;
 720     cpu->clidr = 0x0a200023;
 721     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 722     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 723     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 724     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 725 }
 726
 727 static void ti925t_initfn(Object *obj)
 728 {
 729     ARMCPU *cpu = ARM_CPU(obj);
 730     set_feature(&cpu->env, ARM_FEATURE_V4T);
 731     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 732     cpu->midr = ARM_CPUID_TI925T;
 733     cpu->ctr = 0x5109149;
 734     cpu->reset_sctlr = 0x00000070;
 735 }
 736
 737 static void sa1100_initfn(Object *obj)
 738 {
 739     ARMCPU *cpu = ARM_CPU(obj);
 740
 741     cpu->dtb_compatible = "intel,sa1100";
 742     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 743     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 744     cpu->midr = 0x4401A11B;
 745     cpu->reset_sctlr = 0x00000070;
 746 }
 747
 748 static void sa1110_initfn(Object *obj)
 749 {
 750     ARMCPU *cpu = ARM_CPU(obj);
 751     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 752     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 753     cpu->midr = 0x6901B119;
 754     cpu->reset_sctlr = 0x00000070;
 755 }
 756
 757 static void pxa250_initfn(Object *obj)
 758 {
 759     ARMCPU *cpu = ARM_CPU(obj);
 760
 761     cpu->dtb_compatible = "marvell,xscale";
 762     set_feature(&cpu->env, ARM_FEATURE_V5);
 763     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 764     cpu->midr = 0x69052100;
 765     cpu->ctr = 0xd172172;
 766     cpu->reset_sctlr = 0x00000078;
 767 }
 768
 769 static void pxa255_initfn(Object *obj)
 770 {
 771     ARMCPU *cpu = ARM_CPU(obj);
 772
 773     cpu->dtb_compatible = "marvell,xscale";
 774     set_feature(&cpu->env, ARM_FEATURE_V5);
 775     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 776     cpu->midr = 0x69052d00;
 777     cpu->ctr = 0xd172172;
 778     cpu->reset_sctlr = 0x00000078;
 779 }
 780
 781 static void pxa260_initfn(Object *obj)
 782 {
 783     ARMCPU *cpu = ARM_CPU(obj);
 784
 785     cpu->dtb_compatible = "marvell,xscale";
 786     set_feature(&cpu->env, ARM_FEATURE_V5);
 787     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 788     cpu->midr = 0x69052903;
 789     cpu->ctr = 0xd172172;
 790     cpu->reset_sctlr = 0x00000078;
 791 }
 792
 793 static void pxa261_initfn(Object *obj)
 794 {
 795     ARMCPU *cpu = ARM_CPU(obj);
 796
 797     cpu->dtb_compatible = "marvell,xscale";
 798     set_feature(&cpu->env, ARM_FEATURE_V5);
 799     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 800     cpu->midr = 0x69052d05;
 801     cpu->ctr = 0xd172172;
 802     cpu->reset_sctlr = 0x00000078;
 803 }
 804
 805 static void pxa262_initfn(Object *obj)
 806 {
 807     ARMCPU *cpu = ARM_CPU(obj);
 808
 809     cpu->dtb_compatible = "marvell,xscale";
 810     set_feature(&cpu->env, ARM_FEATURE_V5);
 811     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 812     cpu->midr = 0x69052d06;
 813     cpu->ctr = 0xd172172;
 814     cpu->reset_sctlr = 0x00000078;
 815 }
 816
 817 static void pxa270a0_initfn(Object *obj)
 818 {
 819     ARMCPU *cpu = ARM_CPU(obj);
 820
 821     cpu->dtb_compatible = "marvell,xscale";
 822     set_feature(&cpu->env, ARM_FEATURE_V5);
 823     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 824     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 825     cpu->midr = 0x69054110;
 826     cpu->ctr = 0xd172172;
 827     cpu->reset_sctlr = 0x00000078;
 828 }
 829
 830 static void pxa270a1_initfn(Object *obj)
 831 {
 832     ARMCPU *cpu = ARM_CPU(obj);
 833
 834     cpu->dtb_compatible = "marvell,xscale";
 835     set_feature(&cpu->env, ARM_FEATURE_V5);
 836     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 837     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 838     cpu->midr = 0x69054111;
 839     cpu->ctr = 0xd172172;
 840     cpu->reset_sctlr = 0x00000078;
 841 }
 842
 843 static void pxa270b0_initfn(Object *obj)
 844 {
 845     ARMCPU *cpu = ARM_CPU(obj);
 846
 847     cpu->dtb_compatible = "marvell,xscale";
 848     set_feature(&cpu->env, ARM_FEATURE_V5);
 849     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 850     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 851     cpu->midr = 0x69054112;
 852     cpu->ctr = 0xd172172;
 853     cpu->reset_sctlr = 0x00000078;
 854 }
 855
 856 static void pxa270b1_initfn(Object *obj)
 857 {
 858     ARMCPU *cpu = ARM_CPU(obj);
 859
 860     cpu->dtb_compatible = "marvell,xscale";
 861     set_feature(&cpu->env, ARM_FEATURE_V5);
 862     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 863     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 864     cpu->midr = 0x69054113;
 865     cpu->ctr = 0xd172172;
 866     cpu->reset_sctlr = 0x00000078;
 867 }
 868
 869 static void pxa270c0_initfn(Object *obj)
 870 {
 871     ARMCPU *cpu = ARM_CPU(obj);
 872
 873     cpu->dtb_compatible = "marvell,xscale";
 874     set_feature(&cpu->env, ARM_FEATURE_V5);
 875     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 876     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 877     cpu->midr = 0x69054114;
 878     cpu->ctr = 0xd172172;
 879     cpu->reset_sctlr = 0x00000078;
 880 }
 881
 882 static void pxa270c5_initfn(Object *obj)
 883 {
 884     ARMCPU *cpu = ARM_CPU(obj);
 885
 886     cpu->dtb_compatible = "marvell,xscale";
 887     set_feature(&cpu->env, ARM_FEATURE_V5);
 888     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 889     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 890     cpu->midr = 0x69054117;
 891     cpu->ctr = 0xd172172;
 892     cpu->reset_sctlr = 0x00000078;
 893 }
 894
 895 #ifdef CONFIG_USER_ONLY
 896 static void arm_any_initfn(Object *obj)
 897 {
 898     ARMCPU *cpu = ARM_CPU(obj);
 899     set_feature(&cpu->env, ARM_FEATURE_V8);
 900     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 901     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 902     set_feature(&cpu->env, ARM_FEATURE_NEON);
 903     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 904     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 905     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 906 #ifdef TARGET_AARCH64
 907     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 908 #endif
 909     cpu->midr = 0xffffffff;
 910 }
 911 #endif
 912
 913 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 914
 915 typedef struct ARMCPUInfo {
 916     const char *name;
 917     void (*initfn)(Object *obj);
 918     void (*class_init)(ObjectClass *oc, void *data);
 919 } ARMCPUInfo;
 920
 921 static const ARMCPUInfo arm_cpus[] = {
 922 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 923     { .name = "arm926",      .initfn = arm926_initfn },
 924     { .name = "arm946",      .initfn = arm946_initfn },
 925     { .name = "arm1026",     .initfn = arm1026_initfn },
 926     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 927      * older core than plain "arm1136". In particular this does not
 928      * have the v6K features.
 929      */
 930     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 931     { .name = "arm1136",     .initfn = arm1136_initfn },
 932     { .name = "arm1176",     .initfn = arm1176_initfn },
 933     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 934     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 935                              .class_init = arm_v7m_class_init },
 936     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 937     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 938     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 939     { .name = "ti925t",      .initfn = ti925t_initfn },
 940     { .name = "sa1100",      .initfn = sa1100_initfn },
 941     { .name = "sa1110",      .initfn = sa1110_initfn },
 942     { .name = "pxa250",      .initfn = pxa250_initfn },
 943     { .name = "pxa255",      .initfn = pxa255_initfn },
 944     { .name = "pxa260",      .initfn = pxa260_initfn },
 945     { .name = "pxa261",      .initfn = pxa261_initfn },
 946     { .name = "pxa262",      .initfn = pxa262_initfn },
 947     /* "pxa270" is an alias for "pxa270-a0" */
 948     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 949     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 950     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 951     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 952     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 953     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 954     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 955 #ifdef CONFIG_USER_ONLY
 956     { .name = "any",         .initfn = arm_any_initfn },
 957 #endif
 958 #endif
 959 };
 960
 961 static Property arm_cpu_properties[] = {
 962     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 963     DEFINE_PROP_END_OF_LIST()
 964 };
 965
 966 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 967 {
 968     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 969     CPUClass *cc = CPU_CLASS(acc);
 970     DeviceClass *dc = DEVICE_CLASS(oc);
 971
 972     acc->parent_realize = dc->realize;
 973     dc->realize = arm_cpu_realizefn;
 974     dc->props = arm_cpu_properties;
 975
 976     acc->parent_reset = cc->reset;
 977     cc->reset = arm_cpu_reset;
 978
 979     cc->class_by_name = arm_cpu_class_by_name;
 980     cc->do_interrupt = arm_cpu_do_interrupt;
 981     cc->dump_state = arm_cpu_dump_state;
 982     cc->set_pc = arm_cpu_set_pc;
 983     cc->gdb_read_register = arm_cpu_gdb_read_register;
 984     cc->gdb_write_register = arm_cpu_gdb_write_register;
 985 #ifndef CONFIG_USER_ONLY
 986     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
 987     cc->vmsd = &vmstate_arm_cpu;
 988 #endif
 989     cc->gdb_num_core_regs = 26;
 990     cc->gdb_core_xml_file = "arm-core.xml";
 991 }
 992
 993 static void cpu_register(const ARMCPUInfo *info)
 994 {
 995     TypeInfo type_info = {
 996         .parent = TYPE_ARM_CPU,
 997         .instance_size = sizeof(ARMCPU),
 998         .instance_init = info->initfn,
 999         .class_size = sizeof(ARMCPUClass),
1000         .class_init = info->class_init,
1001     };
1002
1003     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1004     type_register(&type_info);
1005     g_free((void *)type_info.name);
1006 }
1007
1008 static const TypeInfo arm_cpu_type_info = {
1009     .name = TYPE_ARM_CPU,
1010     .parent = TYPE_CPU,
1011     .instance_size = sizeof(ARMCPU),
1012     .instance_init = arm_cpu_initfn,
1013     .instance_post_init = arm_cpu_post_init,
1014     .instance_finalize = arm_cpu_finalizefn,
1015     .abstract = true,
1016     .class_size = sizeof(ARMCPUClass),
1017     .class_init = arm_cpu_class_init,
1018 };
1019
1020 static void arm_cpu_register_types(void)
1021 {
1022     int i;
1023
1024     type_register_static(&arm_cpu_type_info);
1025     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
1026         cpu_register(&arm_cpus[i]);
1027     }
1028 }
1029
1030 type_init(arm_cpu_register_types)