target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "topology.h"
  28
  29 #include "qemu/option.h"
  30 #include "qemu/config-file.h"
  31 #include "qapi/qmp/qerror.h"
  32
  33 #include "qapi/visitor.h"
  34 #include "sysemu/arch_init.h"
  35
  36 #include "hyperv.h"
  37
  38 #include "hw/hw.h"
  39 #if defined(CONFIG_KVM)
  40 #include <linux/kvm_para.h>
  41 #endif
  42
  43 #include "sysemu/sysemu.h"
  44 #include "hw/qdev-properties.h"
  45 #include "hw/cpu/icc_bus.h"
  46 #ifndef CONFIG_USER_ONLY
  47 #include "hw/xen/xen.h"
  48 #include "hw/i386/apic_internal.h"
  49 #endif
  50
  51 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
  52                                      uint32_t vendor2, uint32_t vendor3)
  53 {
  54     int i;
  55     for (i = 0; i < 4; i++) {
  56         dst[i] = vendor1 >> (8 * i);
  57         dst[i + 4] = vendor2 >> (8 * i);
  58         dst[i + 8] = vendor3 >> (8 * i);
  59     }
  60     dst[CPUID_VENDOR_SZ] = '\0';
  61 }
  62
  63 /* feature flags taken from "Intel Processor Identification and the CPUID
  64  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
  65  * between feature naming conventions, aliases may be added.
  66  */
  67 static const char *feature_name[] = {
  68     "fpu", "vme", "de", "pse",
  69     "tsc", "msr", "pae", "mce",
  70     "cx8", "apic", NULL, "sep",
  71     "mtrr", "pge", "mca", "cmov",
  72     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
  73     NULL, "ds" /* Intel dts */, "acpi", "mmx",
  74     "fxsr", "sse", "sse2", "ss",
  75     "ht" /* Intel htt */, "tm", "ia64", "pbe",
  76 };
  77 static const char *ext_feature_name[] = {
  78     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
  79     "ds_cpl", "vmx", "smx", "est",
  80     "tm2", "ssse3", "cid", NULL,
  81     "fma", "cx16", "xtpr", "pdcm",
  82     NULL, "pcid", "dca", "sse4.1|sse4_1",
  83     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
  84     "tsc-deadline", "aes", "xsave", "osxsave",
  85     "avx", "f16c", "rdrand", "hypervisor",
  86 };
  87 /* Feature names that are already defined on feature_name[] but are set on
  88  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
  89  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
  90  * if and only if CPU vendor is AMD.
  91  */
  92 static const char *ext2_feature_name[] = {
  93     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
  94     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
  95     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
  96     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
  97     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
  98     "nx|xd", NULL, "mmxext", NULL /* mmx */,
  99     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 100     NULL, "lm|i64", "3dnowext", "3dnow",
 101 };
 102 static const char *ext3_feature_name[] = {
 103     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 104     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 105     "3dnowprefetch", "osvw", "ibs", "xop",
 106     "skinit", "wdt", NULL, "lwp",
 107     "fma4", "tce", NULL, "nodeid_msr",
 108     NULL, "tbm", "topoext", "perfctr_core",
 109     "perfctr_nb", NULL, NULL, NULL,
 110     NULL, NULL, NULL, NULL,
 111 };
 112
 113 static const char *ext4_feature_name[] = {
 114     NULL, NULL, "xstore", "xstore-en",
 115     NULL, NULL, "xcrypt", "xcrypt-en",
 116     "ace2", "ace2-en", "phe", "phe-en",
 117     "pmm", "pmm-en", NULL, NULL,
 118     NULL, NULL, NULL, NULL,
 119     NULL, NULL, NULL, NULL,
 120     NULL, NULL, NULL, NULL,
 121     NULL, NULL, NULL, NULL,
 122 };
 123
 124 static const char *kvm_feature_name[] = {
 125     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 126     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
 127     NULL, NULL, NULL, NULL,
 128     NULL, NULL, NULL, NULL,
 129     NULL, NULL, NULL, NULL,
 130     NULL, NULL, NULL, NULL,
 131     NULL, NULL, NULL, NULL,
 132     NULL, NULL, NULL, NULL,
 133 };
 134
 135 static const char *svm_feature_name[] = {
 136     "npt", "lbrv", "svm_lock", "nrip_save",
 137     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 138     NULL, NULL, "pause_filter", NULL,
 139     "pfthreshold", NULL, NULL, NULL,
 140     NULL, NULL, NULL, NULL,
 141     NULL, NULL, NULL, NULL,
 142     NULL, NULL, NULL, NULL,
 143     NULL, NULL, NULL, NULL,
 144 };
 145
 146 static const char *cpuid_7_0_ebx_feature_name[] = {
 147     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 148     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 149     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 150     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 151 };
 152
 153 typedef struct FeatureWordInfo {
 154     const char **feat_names;
 155     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 156     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 157     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 158     int cpuid_reg;        /* output register (R_* constant) */
 159 } FeatureWordInfo;
 160
 161 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 162     [FEAT_1_EDX] = {
 163         .feat_names = feature_name,
 164         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 165     },
 166     [FEAT_1_ECX] = {
 167         .feat_names = ext_feature_name,
 168         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 169     },
 170     [FEAT_8000_0001_EDX] = {
 171         .feat_names = ext2_feature_name,
 172         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 173     },
 174     [FEAT_8000_0001_ECX] = {
 175         .feat_names = ext3_feature_name,
 176         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 177     },
 178     [FEAT_C000_0001_EDX] = {
 179         .feat_names = ext4_feature_name,
 180         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 181     },
 182     [FEAT_KVM] = {
 183         .feat_names = kvm_feature_name,
 184         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 185     },
 186     [FEAT_SVM] = {
 187         .feat_names = svm_feature_name,
 188         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 189     },
 190     [FEAT_7_0_EBX] = {
 191         .feat_names = cpuid_7_0_ebx_feature_name,
 192         .cpuid_eax = 7,
 193         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 194         .cpuid_reg = R_EBX,
 195     },
 196 };
 197
 198 const char *get_register_name_32(unsigned int reg)
 199 {
 200     static const char *reg_names[CPU_NB_REGS32] = {
 201         [R_EAX] = "EAX",
 202         [R_ECX] = "ECX",
 203         [R_EDX] = "EDX",
 204         [R_EBX] = "EBX",
 205         [R_ESP] = "ESP",
 206         [R_EBP] = "EBP",
 207         [R_ESI] = "ESI",
 208         [R_EDI] = "EDI",
 209     };
 210
 211     if (reg > CPU_NB_REGS32) {
 212         return NULL;
 213     }
 214     return reg_names[reg];
 215 }
 216
 217 /* collects per-function cpuid data
 218  */
 219 typedef struct model_features_t {
 220     uint32_t *guest_feat;
 221     uint32_t *host_feat;
 222     FeatureWord feat_word;
 223 } model_features_t;
 224
 225 int check_cpuid = 0;
 226 int enforce_cpuid = 0;
 227
 228 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
 229         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 230         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 231         (1 << KVM_FEATURE_ASYNC_PF) |
 232         (1 << KVM_FEATURE_STEAL_TIME) |
 233         (1 << KVM_FEATURE_PV_EOI) |
 234         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 235
 236 void disable_kvm_pv_eoi(void)
 237 {
 238     kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
 239 }
 240
 241 void host_cpuid(uint32_t function, uint32_t count,
 242                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 243 {
 244 #if defined(CONFIG_KVM)
 245     uint32_t vec[4];
 246
 247 #ifdef __x86_64__
 248     asm volatile("cpuid"
 249                  : "=a"(vec[0]), "=b"(vec[1]),
 250                    "=c"(vec[2]), "=d"(vec[3])
 251                  : "0"(function), "c"(count) : "cc");
 252 #else
 253     asm volatile("pusha \n\t"
 254                  "cpuid \n\t"
 255                  "mov %%eax, 0(%2) \n\t"
 256                  "mov %%ebx, 4(%2) \n\t"
 257                  "mov %%ecx, 8(%2) \n\t"
 258                  "mov %%edx, 12(%2) \n\t"
 259                  "popa"
 260                  : : "a"(function), "c"(count), "S"(vec)
 261                  : "memory", "cc");
 262 #endif
 263
 264     if (eax)
 265         *eax = vec[0];
 266     if (ebx)
 267         *ebx = vec[1];
 268     if (ecx)
 269         *ecx = vec[2];
 270     if (edx)
 271         *edx = vec[3];
 272 #endif
 273 }
 274
 275 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 276
 277 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 278  * a substring.  ex if !NULL points to the first char after a substring,
 279  * otherwise the string is assumed to sized by a terminating nul.
 280  * Return lexical ordering of *s1:*s2.
 281  */
 282 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 283     const char *e2)
 284 {
 285     for (;;) {
 286         if (!*s1 || !*s2 || *s1 != *s2)
 287             return (*s1 - *s2);
 288         ++s1, ++s2;
 289         if (s1 == e1 && s2 == e2)
 290             return (0);
 291         else if (s1 == e1)
 292             return (*s2);
 293         else if (s2 == e2)
 294             return (*s1);
 295     }
 296 }
 297
 298 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 299  * '|' delimited (possibly empty) strings in which case search for a match
 300  * within the alternatives proceeds left to right.  Return 0 for success,
 301  * non-zero otherwise.
 302  */
 303 static int altcmp(const char *s, const char *e, const char *altstr)
 304 {
 305     const char *p, *q;
 306
 307     for (q = p = altstr; ; ) {
 308         while (*p && *p != '|')
 309             ++p;
 310         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 311             return (0);
 312         if (!*p)
 313             return (1);
 314         else
 315             q = ++p;
 316     }
 317 }
 318
 319 /* search featureset for flag *[s..e), if found set corresponding bit in
 320  * *pval and return true, otherwise return false
 321  */
 322 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 323                            const char **featureset)
 324 {
 325     uint32_t mask;
 326     const char **ppc;
 327     bool found = false;
 328
 329     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 330         if (*ppc && !altcmp(s, e, *ppc)) {
 331             *pval |= mask;
 332             found = true;
 333         }
 334     }
 335     return found;
 336 }
 337
 338 static void add_flagname_to_bitmaps(const char *flagname,
 339                                     FeatureWordArray words)
 340 {
 341     FeatureWord w;
 342     for (w = 0; w < FEATURE_WORDS; w++) {
 343         FeatureWordInfo *wi = &feature_word_info[w];
 344         if (wi->feat_names &&
 345             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 346             break;
 347         }
 348     }
 349     if (w == FEATURE_WORDS) {
 350         fprintf(stderr, "CPU feature %s not found\n", flagname);
 351     }
 352 }
 353
 354 typedef struct x86_def_t {
 355     const char *name;
 356     uint32_t level;
 357     uint32_t xlevel;
 358     uint32_t xlevel2;
 359     /* vendor is zero-terminated, 12 character ASCII string */
 360     char vendor[CPUID_VENDOR_SZ + 1];
 361     int family;
 362     int model;
 363     int stepping;
 364     FeatureWordArray features;
 365     char model_id[48];
 366 } x86_def_t;
 367
 368 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 369 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 370           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 371 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 372           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 373           CPUID_PSE36 | CPUID_FXSR)
 374 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 375 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 376           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 377           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 378           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 379
 380 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 381           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 382           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 383           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 384           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 385           /* partly implemented:
 386           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 387           CPUID_PSE36 (needed for Solaris) */
 388           /* missing:
 389           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 390 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 391           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 392           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 393           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 394           /* missing:
 395           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 396           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 397           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 398           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 399           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 400           CPUID_EXT_RDRAND */
 401 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 402           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 403           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 404           /* missing:
 405           CPUID_EXT2_PDPE1GB */
 406 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 407           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 408 #define TCG_SVM_FEATURES 0
 409 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
 410           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 411           /* missing:
 412           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 413           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 414           CPUID_7_0_EBX_RDSEED */
 415
 416 /* built-in CPU model definitions
 417  */
 418 static x86_def_t builtin_x86_defs[] = {
 419     {
 420         .name = "qemu64",
 421         .level = 4,
 422         .vendor = CPUID_VENDOR_AMD,
 423         .family = 6,
 424         .model = 2,
 425         .stepping = 3,
 426         .features[FEAT_1_EDX] =
 427             PPRO_FEATURES |
 428             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 429             CPUID_PSE36,
 430         .features[FEAT_1_ECX] =
 431             CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 432         .features[FEAT_8000_0001_EDX] =
 433             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 434             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 435         .features[FEAT_8000_0001_ECX] =
 436             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 437             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 438         .xlevel = 0x8000000A,
 439     },
 440     {
 441         .name = "phenom",
 442         .level = 5,
 443         .vendor = CPUID_VENDOR_AMD,
 444         .family = 16,
 445         .model = 2,
 446         .stepping = 3,
 447         .features[FEAT_1_EDX] =
 448             PPRO_FEATURES |
 449             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 450             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 451         .features[FEAT_1_ECX] =
 452             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 453             CPUID_EXT_POPCNT,
 454         .features[FEAT_8000_0001_EDX] =
 455             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 456             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 457             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 458             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 459         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 460                     CPUID_EXT3_CR8LEG,
 461                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 462                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 463         .features[FEAT_8000_0001_ECX] =
 464             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 465             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 466         .features[FEAT_SVM] =
 467             CPUID_SVM_NPT | CPUID_SVM_LBRV,
 468         .xlevel = 0x8000001A,
 469         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 470     },
 471     {
 472         .name = "core2duo",
 473         .level = 10,
 474         .vendor = CPUID_VENDOR_INTEL,
 475         .family = 6,
 476         .model = 15,
 477         .stepping = 11,
 478         .features[FEAT_1_EDX] =
 479             PPRO_FEATURES |
 480             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 481             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 482             CPUID_HT | CPUID_TM | CPUID_PBE,
 483         .features[FEAT_1_ECX] =
 484             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 485             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 486             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 487         .features[FEAT_8000_0001_EDX] =
 488             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 489         .features[FEAT_8000_0001_ECX] =
 490             CPUID_EXT3_LAHF_LM,
 491         .xlevel = 0x80000008,
 492         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 493     },
 494     {
 495         .name = "kvm64",
 496         .level = 5,
 497         .vendor = CPUID_VENDOR_INTEL,
 498         .family = 15,
 499         .model = 6,
 500         .stepping = 1,
 501         /* Missing: CPUID_VME, CPUID_HT */
 502         .features[FEAT_1_EDX] =
 503             PPRO_FEATURES |
 504             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 505             CPUID_PSE36,
 506         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 507         .features[FEAT_1_ECX] =
 508             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 509         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 510         .features[FEAT_8000_0001_EDX] =
 511             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 512             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 513         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 514                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 515                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 516                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 517         .features[FEAT_8000_0001_ECX] =
 518             0,
 519         .xlevel = 0x80000008,
 520         .model_id = "Common KVM processor"
 521     },
 522     {
 523         .name = "qemu32",
 524         .level = 4,
 525         .vendor = CPUID_VENDOR_INTEL,
 526         .family = 6,
 527         .model = 3,
 528         .stepping = 3,
 529         .features[FEAT_1_EDX] =
 530             PPRO_FEATURES,
 531         .features[FEAT_1_ECX] =
 532             CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 533         .xlevel = 0x80000004,
 534     },
 535     {
 536         .name = "kvm32",
 537         .level = 5,
 538         .vendor = CPUID_VENDOR_INTEL,
 539         .family = 15,
 540         .model = 6,
 541         .stepping = 1,
 542         .features[FEAT_1_EDX] =
 543             PPRO_FEATURES |
 544             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 545         .features[FEAT_1_ECX] =
 546             CPUID_EXT_SSE3,
 547         .features[FEAT_8000_0001_EDX] =
 548             PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 549         .features[FEAT_8000_0001_ECX] =
 550             0,
 551         .xlevel = 0x80000008,
 552         .model_id = "Common 32-bit KVM processor"
 553     },
 554     {
 555         .name = "coreduo",
 556         .level = 10,
 557         .vendor = CPUID_VENDOR_INTEL,
 558         .family = 6,
 559         .model = 14,
 560         .stepping = 8,
 561         .features[FEAT_1_EDX] =
 562             PPRO_FEATURES | CPUID_VME |
 563             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 564             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 565         .features[FEAT_1_ECX] =
 566             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 567             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 568         .features[FEAT_8000_0001_EDX] =
 569             CPUID_EXT2_NX,
 570         .xlevel = 0x80000008,
 571         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 572     },
 573     {
 574         .name = "486",
 575         .level = 1,
 576         .vendor = CPUID_VENDOR_INTEL,
 577         .family = 4,
 578         .model = 0,
 579         .stepping = 0,
 580         .features[FEAT_1_EDX] =
 581             I486_FEATURES,
 582         .xlevel = 0,
 583     },
 584     {
 585         .name = "pentium",
 586         .level = 1,
 587         .vendor = CPUID_VENDOR_INTEL,
 588         .family = 5,
 589         .model = 4,
 590         .stepping = 3,
 591         .features[FEAT_1_EDX] =
 592             PENTIUM_FEATURES,
 593         .xlevel = 0,
 594     },
 595     {
 596         .name = "pentium2",
 597         .level = 2,
 598         .vendor = CPUID_VENDOR_INTEL,
 599         .family = 6,
 600         .model = 5,
 601         .stepping = 2,
 602         .features[FEAT_1_EDX] =
 603             PENTIUM2_FEATURES,
 604         .xlevel = 0,
 605     },
 606     {
 607         .name = "pentium3",
 608         .level = 2,
 609         .vendor = CPUID_VENDOR_INTEL,
 610         .family = 6,
 611         .model = 7,
 612         .stepping = 3,
 613         .features[FEAT_1_EDX] =
 614             PENTIUM3_FEATURES,
 615         .xlevel = 0,
 616     },
 617     {
 618         .name = "athlon",
 619         .level = 2,
 620         .vendor = CPUID_VENDOR_AMD,
 621         .family = 6,
 622         .model = 2,
 623         .stepping = 3,
 624         .features[FEAT_1_EDX] =
 625             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 626             CPUID_MCA,
 627         .features[FEAT_8000_0001_EDX] =
 628             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 629             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 630         .xlevel = 0x80000008,
 631     },
 632     {
 633         .name = "n270",
 634         /* original is on level 10 */
 635         .level = 5,
 636         .vendor = CPUID_VENDOR_INTEL,
 637         .family = 6,
 638         .model = 28,
 639         .stepping = 2,
 640         .features[FEAT_1_EDX] =
 641             PPRO_FEATURES |
 642             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 643             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 644             /* Some CPUs got no CPUID_SEP */
 645         .features[FEAT_1_ECX] =
 646             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 647             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
 648         .features[FEAT_8000_0001_EDX] =
 649             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 650             CPUID_EXT2_NX,
 651         .features[FEAT_8000_0001_ECX] =
 652             CPUID_EXT3_LAHF_LM,
 653         .xlevel = 0x8000000A,
 654         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 655     },
 656     {
 657         .name = "Conroe",
 658         .level = 2,
 659         .vendor = CPUID_VENDOR_INTEL,
 660         .family = 6,
 661         .model = 2,
 662         .stepping = 3,
 663         .features[FEAT_1_EDX] =
 664             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 665              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 666              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 667              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 668              CPUID_DE | CPUID_FP87,
 669         .features[FEAT_1_ECX] =
 670             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 671         .features[FEAT_8000_0001_EDX] =
 672             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 673         .features[FEAT_8000_0001_ECX] =
 674             CPUID_EXT3_LAHF_LM,
 675         .xlevel = 0x8000000A,
 676         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 677     },
 678     {
 679         .name = "Penryn",
 680         .level = 2,
 681         .vendor = CPUID_VENDOR_INTEL,
 682         .family = 6,
 683         .model = 2,
 684         .stepping = 3,
 685         .features[FEAT_1_EDX] =
 686             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 687              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 688              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 689              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 690              CPUID_DE | CPUID_FP87,
 691         .features[FEAT_1_ECX] =
 692             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 693              CPUID_EXT_SSE3,
 694         .features[FEAT_8000_0001_EDX] =
 695             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 696         .features[FEAT_8000_0001_ECX] =
 697             CPUID_EXT3_LAHF_LM,
 698         .xlevel = 0x8000000A,
 699         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 700     },
 701     {
 702         .name = "Nehalem",
 703         .level = 2,
 704         .vendor = CPUID_VENDOR_INTEL,
 705         .family = 6,
 706         .model = 2,
 707         .stepping = 3,
 708         .features[FEAT_1_EDX] =
 709             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 710              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 711              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 712              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 713              CPUID_DE | CPUID_FP87,
 714         .features[FEAT_1_ECX] =
 715             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 716              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 717         .features[FEAT_8000_0001_EDX] =
 718             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 719         .features[FEAT_8000_0001_ECX] =
 720             CPUID_EXT3_LAHF_LM,
 721         .xlevel = 0x8000000A,
 722         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 723     },
 724     {
 725         .name = "Westmere",
 726         .level = 11,
 727         .vendor = CPUID_VENDOR_INTEL,
 728         .family = 6,
 729         .model = 44,
 730         .stepping = 1,
 731         .features[FEAT_1_EDX] =
 732             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 733              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 734              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 735              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 736              CPUID_DE | CPUID_FP87,
 737         .features[FEAT_1_ECX] =
 738             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 739              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 740              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 741         .features[FEAT_8000_0001_EDX] =
 742             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 743         .features[FEAT_8000_0001_ECX] =
 744             CPUID_EXT3_LAHF_LM,
 745         .xlevel = 0x8000000A,
 746         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 747     },
 748     {
 749         .name = "SandyBridge",
 750         .level = 0xd,
 751         .vendor = CPUID_VENDOR_INTEL,
 752         .family = 6,
 753         .model = 42,
 754         .stepping = 1,
 755         .features[FEAT_1_EDX] =
 756             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 757              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 758              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 759              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 760              CPUID_DE | CPUID_FP87,
 761         .features[FEAT_1_ECX] =
 762             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 763              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 764              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 765              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 766              CPUID_EXT_SSE3,
 767         .features[FEAT_8000_0001_EDX] =
 768             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 769              CPUID_EXT2_SYSCALL,
 770         .features[FEAT_8000_0001_ECX] =
 771             CPUID_EXT3_LAHF_LM,
 772         .xlevel = 0x8000000A,
 773         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 774     },
 775     {
 776         .name = "Haswell",
 777         .level = 0xd,
 778         .vendor = CPUID_VENDOR_INTEL,
 779         .family = 6,
 780         .model = 60,
 781         .stepping = 1,
 782         .features[FEAT_1_EDX] =
 783             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 784              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 785              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 786              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 787              CPUID_DE | CPUID_FP87,
 788         .features[FEAT_1_ECX] =
 789             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 790              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 791              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 792              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 793              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 794              CPUID_EXT_PCID,
 795         .features[FEAT_8000_0001_EDX] =
 796             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 797              CPUID_EXT2_SYSCALL,
 798         .features[FEAT_8000_0001_ECX] =
 799             CPUID_EXT3_LAHF_LM,
 800         .features[FEAT_7_0_EBX] =
 801             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 802             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 803             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 804             CPUID_7_0_EBX_RTM,
 805         .xlevel = 0x8000000A,
 806         .model_id = "Intel Core Processor (Haswell)",
 807     },
 808     {
 809         .name = "Opteron_G1",
 810         .level = 5,
 811         .vendor = CPUID_VENDOR_AMD,
 812         .family = 15,
 813         .model = 6,
 814         .stepping = 1,
 815         .features[FEAT_1_EDX] =
 816             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 817              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 818              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 819              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 820              CPUID_DE | CPUID_FP87,
 821         .features[FEAT_1_ECX] =
 822             CPUID_EXT_SSE3,
 823         .features[FEAT_8000_0001_EDX] =
 824             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 825              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 826              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 827              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 828              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 829              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 830         .xlevel = 0x80000008,
 831         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 832     },
 833     {
 834         .name = "Opteron_G2",
 835         .level = 5,
 836         .vendor = CPUID_VENDOR_AMD,
 837         .family = 15,
 838         .model = 6,
 839         .stepping = 1,
 840         .features[FEAT_1_EDX] =
 841             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 842              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 843              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 844              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 845              CPUID_DE | CPUID_FP87,
 846         .features[FEAT_1_ECX] =
 847             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
 848         .features[FEAT_8000_0001_EDX] =
 849             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 850              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 851              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 852              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 853              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 854              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 855              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 856         .features[FEAT_8000_0001_ECX] =
 857             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 858         .xlevel = 0x80000008,
 859         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
 860     },
 861     {
 862         .name = "Opteron_G3",
 863         .level = 5,
 864         .vendor = CPUID_VENDOR_AMD,
 865         .family = 15,
 866         .model = 6,
 867         .stepping = 1,
 868         .features[FEAT_1_EDX] =
 869             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 870              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 871              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 872              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 873              CPUID_DE | CPUID_FP87,
 874         .features[FEAT_1_ECX] =
 875             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
 876              CPUID_EXT_SSE3,
 877         .features[FEAT_8000_0001_EDX] =
 878             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 879              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 880              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 881              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 882              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 883              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 884              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 885         .features[FEAT_8000_0001_ECX] =
 886             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
 887              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 888         .xlevel = 0x80000008,
 889         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
 890     },
 891     {
 892         .name = "Opteron_G4",
 893         .level = 0xd,
 894         .vendor = CPUID_VENDOR_AMD,
 895         .family = 21,
 896         .model = 1,
 897         .stepping = 2,
 898         .features[FEAT_1_EDX] =
 899             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 900              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 901              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 902              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 903              CPUID_DE | CPUID_FP87,
 904         .features[FEAT_1_ECX] =
 905             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 906              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 907              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 908              CPUID_EXT_SSE3,
 909         .features[FEAT_8000_0001_EDX] =
 910             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 911              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 912              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 913              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 914              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 915              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 916              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 917         .features[FEAT_8000_0001_ECX] =
 918             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 919              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 920              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 921              CPUID_EXT3_LAHF_LM,
 922         .xlevel = 0x8000001A,
 923         .model_id = "AMD Opteron 62xx class CPU",
 924     },
 925     {
 926         .name = "Opteron_G5",
 927         .level = 0xd,
 928         .vendor = CPUID_VENDOR_AMD,
 929         .family = 21,
 930         .model = 2,
 931         .stepping = 0,
 932         .features[FEAT_1_EDX] =
 933             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 934              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 935              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 936              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 937              CPUID_DE | CPUID_FP87,
 938         .features[FEAT_1_ECX] =
 939             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
 940              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 941              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
 942              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 943         .features[FEAT_8000_0001_EDX] =
 944             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 945              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 946              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 947              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 948              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 949              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 950              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 951         .features[FEAT_8000_0001_ECX] =
 952             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 953              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 954              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 955              CPUID_EXT3_LAHF_LM,
 956         .xlevel = 0x8000001A,
 957         .model_id = "AMD Opteron 63xx class CPU",
 958     },
 959 };
 960
 961 #ifdef CONFIG_KVM
 962 static int cpu_x86_fill_model_id(char *str)
 963 {
 964     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 965     int i;
 966
 967     for (i = 0; i < 3; i++) {
 968         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
 969         memcpy(str + i * 16 +  0, &eax, 4);
 970         memcpy(str + i * 16 +  4, &ebx, 4);
 971         memcpy(str + i * 16 +  8, &ecx, 4);
 972         memcpy(str + i * 16 + 12, &edx, 4);
 973     }
 974     return 0;
 975 }
 976 #endif
 977
 978 /* Fill a x86_def_t struct with information about the host CPU, and
 979  * the CPU features supported by the host hardware + host kernel
 980  *
 981  * This function may be called only if KVM is enabled.
 982  */
 983 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
 984 {
 985 #ifdef CONFIG_KVM
 986     KVMState *s = kvm_state;
 987     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 988
 989     assert(kvm_enabled());
 990
 991     x86_cpu_def->name = "host";
 992     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
 993     x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
 994
 995     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
 996     x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
 997     x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
 998     x86_cpu_def->stepping = eax & 0x0F;
 999
1000     x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1001     x86_cpu_def->features[FEAT_1_EDX] =
1002         kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1003     x86_cpu_def->features[FEAT_1_ECX] =
1004         kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1005
1006     if (x86_cpu_def->level >= 7) {
1007         x86_cpu_def->features[FEAT_7_0_EBX] =
1008                     kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1009     } else {
1010         x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1011     }
1012
1013     x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1014     x86_cpu_def->features[FEAT_8000_0001_EDX] =
1015                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1016     x86_cpu_def->features[FEAT_8000_0001_ECX] =
1017                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1018
1019     cpu_x86_fill_model_id(x86_cpu_def->model_id);
1020
1021     /* Call Centaur's CPUID instruction. */
1022     if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1023         host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1024         eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1025         if (eax >= 0xC0000001) {
1026             /* Support VIA max extended level */
1027             x86_cpu_def->xlevel2 = eax;
1028             host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1029             x86_cpu_def->features[FEAT_C000_0001_EDX] =
1030                     kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1031         }
1032     }
1033
1034     /* Other KVM-specific feature fields: */
1035     x86_cpu_def->features[FEAT_SVM] =
1036         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1037     x86_cpu_def->features[FEAT_KVM] =
1038         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1039
1040 #endif /* CONFIG_KVM */
1041 }
1042
1043 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1044 {
1045     int i;
1046
1047     for (i = 0; i < 32; ++i)
1048         if (1 << i & mask) {
1049             const char *reg = get_register_name_32(f->cpuid_reg);
1050             assert(reg);
1051             fprintf(stderr, "warning: host doesn't support requested feature: "
1052                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1053                 f->cpuid_eax, reg,
1054                 f->feat_names[i] ? "." : "",
1055                 f->feat_names[i] ? f->feat_names[i] : "", i);
1056             break;
1057         }
1058     return 0;
1059 }
1060
1061 /* Check if all requested cpu flags are making their way to the guest
1062  *
1063  * Returns 0 if all flags are supported by the host, non-zero otherwise.
1064  *
1065  * This function may be called only if KVM is enabled.
1066  */
1067 static int kvm_check_features_against_host(X86CPU *cpu)
1068 {
1069     CPUX86State *env = &cpu->env;
1070     x86_def_t host_def;
1071     uint32_t mask;
1072     int rv, i;
1073     struct model_features_t ft[] = {
1074         {&env->features[FEAT_1_EDX],
1075             &host_def.features[FEAT_1_EDX],
1076             FEAT_1_EDX },
1077         {&env->features[FEAT_1_ECX],
1078             &host_def.features[FEAT_1_ECX],
1079             FEAT_1_ECX },
1080         {&env->features[FEAT_8000_0001_EDX],
1081             &host_def.features[FEAT_8000_0001_EDX],
1082             FEAT_8000_0001_EDX },
1083         {&env->features[FEAT_8000_0001_ECX],
1084             &host_def.features[FEAT_8000_0001_ECX],
1085             FEAT_8000_0001_ECX },
1086         {&env->features[FEAT_C000_0001_EDX],
1087             &host_def.features[FEAT_C000_0001_EDX],
1088             FEAT_C000_0001_EDX },
1089         {&env->features[FEAT_7_0_EBX],
1090             &host_def.features[FEAT_7_0_EBX],
1091             FEAT_7_0_EBX },
1092         {&env->features[FEAT_SVM],
1093             &host_def.features[FEAT_SVM],
1094             FEAT_SVM },
1095         {&env->features[FEAT_KVM],
1096             &host_def.features[FEAT_KVM],
1097             FEAT_KVM },
1098     };
1099
1100     assert(kvm_enabled());
1101
1102     kvm_cpu_fill_host(&host_def);
1103     for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1104         FeatureWord w = ft[i].feat_word;
1105         FeatureWordInfo *wi = &feature_word_info[w];
1106         for (mask = 1; mask; mask <<= 1) {
1107             if (*ft[i].guest_feat & mask &&
1108                 !(*ft[i].host_feat & mask)) {
1109                 unavailable_host_feature(wi, mask);
1110                 rv = 1;
1111             }
1112         }
1113     }
1114     return rv;
1115 }
1116
1117 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1118                                          const char *name, Error **errp)
1119 {
1120     X86CPU *cpu = X86_CPU(obj);
1121     CPUX86State *env = &cpu->env;
1122     int64_t value;
1123
1124     value = (env->cpuid_version >> 8) & 0xf;
1125     if (value == 0xf) {
1126         value += (env->cpuid_version >> 20) & 0xff;
1127     }
1128     visit_type_int(v, &value, name, errp);
1129 }
1130
1131 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1132                                          const char *name, Error **errp)
1133 {
1134     X86CPU *cpu = X86_CPU(obj);
1135     CPUX86State *env = &cpu->env;
1136     const int64_t min = 0;
1137     const int64_t max = 0xff + 0xf;
1138     int64_t value;
1139
1140     visit_type_int(v, &value, name, errp);
1141     if (error_is_set(errp)) {
1142         return;
1143     }
1144     if (value < min || value > max) {
1145         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1146                   name ? name : "null", value, min, max);
1147         return;
1148     }
1149
1150     env->cpuid_version &= ~0xff00f00;
1151     if (value > 0x0f) {
1152         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1153     } else {
1154         env->cpuid_version |= value << 8;
1155     }
1156 }
1157
1158 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1159                                         const char *name, Error **errp)
1160 {
1161     X86CPU *cpu = X86_CPU(obj);
1162     CPUX86State *env = &cpu->env;
1163     int64_t value;
1164
1165     value = (env->cpuid_version >> 4) & 0xf;
1166     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1167     visit_type_int(v, &value, name, errp);
1168 }
1169
1170 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1171                                         const char *name, Error **errp)
1172 {
1173     X86CPU *cpu = X86_CPU(obj);
1174     CPUX86State *env = &cpu->env;
1175     const int64_t min = 0;
1176     const int64_t max = 0xff;
1177     int64_t value;
1178
1179     visit_type_int(v, &value, name, errp);
1180     if (error_is_set(errp)) {
1181         return;
1182     }
1183     if (value < min || value > max) {
1184         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1185                   name ? name : "null", value, min, max);
1186         return;
1187     }
1188
1189     env->cpuid_version &= ~0xf00f0;
1190     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1191 }
1192
1193 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1194                                            void *opaque, const char *name,
1195                                            Error **errp)
1196 {
1197     X86CPU *cpu = X86_CPU(obj);
1198     CPUX86State *env = &cpu->env;
1199     int64_t value;
1200
1201     value = env->cpuid_version & 0xf;
1202     visit_type_int(v, &value, name, errp);
1203 }
1204
1205 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1206                                            void *opaque, const char *name,
1207                                            Error **errp)
1208 {
1209     X86CPU *cpu = X86_CPU(obj);
1210     CPUX86State *env = &cpu->env;
1211     const int64_t min = 0;
1212     const int64_t max = 0xf;
1213     int64_t value;
1214
1215     visit_type_int(v, &value, name, errp);
1216     if (error_is_set(errp)) {
1217         return;
1218     }
1219     if (value < min || value > max) {
1220         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1221                   name ? name : "null", value, min, max);
1222         return;
1223     }
1224
1225     env->cpuid_version &= ~0xf;
1226     env->cpuid_version |= value & 0xf;
1227 }
1228
1229 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1230                                 const char *name, Error **errp)
1231 {
1232     X86CPU *cpu = X86_CPU(obj);
1233
1234     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1235 }
1236
1237 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1238                                 const char *name, Error **errp)
1239 {
1240     X86CPU *cpu = X86_CPU(obj);
1241
1242     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1243 }
1244
1245 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1246                                  const char *name, Error **errp)
1247 {
1248     X86CPU *cpu = X86_CPU(obj);
1249
1250     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1251 }
1252
1253 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1254                                  const char *name, Error **errp)
1255 {
1256     X86CPU *cpu = X86_CPU(obj);
1257
1258     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1259 }
1260
1261 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1262 {
1263     X86CPU *cpu = X86_CPU(obj);
1264     CPUX86State *env = &cpu->env;
1265     char *value;
1266
1267     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1268     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1269                              env->cpuid_vendor3);
1270     return value;
1271 }
1272
1273 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1274                                  Error **errp)
1275 {
1276     X86CPU *cpu = X86_CPU(obj);
1277     CPUX86State *env = &cpu->env;
1278     int i;
1279
1280     if (strlen(value) != CPUID_VENDOR_SZ) {
1281         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1282                   "vendor", value);
1283         return;
1284     }
1285
1286     env->cpuid_vendor1 = 0;
1287     env->cpuid_vendor2 = 0;
1288     env->cpuid_vendor3 = 0;
1289     for (i = 0; i < 4; i++) {
1290         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1291         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1292         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1293     }
1294 }
1295
1296 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1297 {
1298     X86CPU *cpu = X86_CPU(obj);
1299     CPUX86State *env = &cpu->env;
1300     char *value;
1301     int i;
1302
1303     value = g_malloc(48 + 1);
1304     for (i = 0; i < 48; i++) {
1305         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1306     }
1307     value[48] = '\0';
1308     return value;
1309 }
1310
1311 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1312                                    Error **errp)
1313 {
1314     X86CPU *cpu = X86_CPU(obj);
1315     CPUX86State *env = &cpu->env;
1316     int c, len, i;
1317
1318     if (model_id == NULL) {
1319         model_id = "";
1320     }
1321     len = strlen(model_id);
1322     memset(env->cpuid_model, 0, 48);
1323     for (i = 0; i < 48; i++) {
1324         if (i >= len) {
1325             c = '\0';
1326         } else {
1327             c = (uint8_t)model_id[i];
1328         }
1329         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1330     }
1331 }
1332
1333 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1334                                    const char *name, Error **errp)
1335 {
1336     X86CPU *cpu = X86_CPU(obj);
1337     int64_t value;
1338
1339     value = cpu->env.tsc_khz * 1000;
1340     visit_type_int(v, &value, name, errp);
1341 }
1342
1343 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1344                                    const char *name, Error **errp)
1345 {
1346     X86CPU *cpu = X86_CPU(obj);
1347     const int64_t min = 0;
1348     const int64_t max = INT64_MAX;
1349     int64_t value;
1350
1351     visit_type_int(v, &value, name, errp);
1352     if (error_is_set(errp)) {
1353         return;
1354     }
1355     if (value < min || value > max) {
1356         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1357                   name ? name : "null", value, min, max);
1358         return;
1359     }
1360
1361     cpu->env.tsc_khz = value / 1000;
1362 }
1363
1364 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1365                                   const char *name, Error **errp)
1366 {
1367     X86CPU *cpu = X86_CPU(obj);
1368     int64_t value = cpu->env.cpuid_apic_id;
1369
1370     visit_type_int(v, &value, name, errp);
1371 }
1372
1373 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1374                                   const char *name, Error **errp)
1375 {
1376     X86CPU *cpu = X86_CPU(obj);
1377     DeviceState *dev = DEVICE(obj);
1378     const int64_t min = 0;
1379     const int64_t max = UINT32_MAX;
1380     Error *error = NULL;
1381     int64_t value;
1382
1383     if (dev->realized) {
1384         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1385                    "it was realized", name, object_get_typename(obj));
1386         return;
1387     }
1388
1389     visit_type_int(v, &value, name, &error);
1390     if (error) {
1391         error_propagate(errp, error);
1392         return;
1393     }
1394     if (value < min || value > max) {
1395         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1396                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1397                    object_get_typename(obj), name, value, min, max);
1398         return;
1399     }
1400
1401     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1402         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1403         return;
1404     }
1405     cpu->env.cpuid_apic_id = value;
1406 }
1407
1408 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1409 {
1410     x86_def_t *def;
1411     int i;
1412
1413     if (name == NULL) {
1414         return -1;
1415     }
1416     if (kvm_enabled() && strcmp(name, "host") == 0) {
1417         kvm_cpu_fill_host(x86_cpu_def);
1418         return 0;
1419     }
1420
1421     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1422         def = &builtin_x86_defs[i];
1423         if (strcmp(name, def->name) == 0) {
1424             memcpy(x86_cpu_def, def, sizeof(*def));
1425             /* sysenter isn't supported in compatibility mode on AMD,
1426              * syscall isn't supported in compatibility mode on Intel.
1427              * Normally we advertise the actual CPU vendor, but you can
1428              * override this using the 'vendor' property if you want to use
1429              * KVM's sysenter/syscall emulation in compatibility mode and
1430              * when doing cross vendor migration
1431              */
1432             if (kvm_enabled()) {
1433                 uint32_t  ebx = 0, ecx = 0, edx = 0;
1434                 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1435                 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1436             }
1437             return 0;
1438         }
1439     }
1440
1441     return -1;
1442 }
1443
1444 /* Convert all '_' in a feature string option name to '-', to make feature
1445  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1446  */
1447 static inline void feat2prop(char *s)
1448 {
1449     while ((s = strchr(s, '_'))) {
1450         *s = '-';
1451     }
1452 }
1453
1454 /* Parse "+feature,-feature,feature=foo" CPU feature string
1455  */
1456 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1457 {
1458     char *featurestr; /* Single 'key=value" string being parsed */
1459     /* Features to be added */
1460     FeatureWordArray plus_features = { 0 };
1461     /* Features to be removed */
1462     FeatureWordArray minus_features = { 0 };
1463     uint32_t numvalue;
1464     CPUX86State *env = &cpu->env;
1465
1466     featurestr = features ? strtok(features, ",") : NULL;
1467
1468     while (featurestr) {
1469         char *val;
1470         if (featurestr[0] == '+') {
1471             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1472         } else if (featurestr[0] == '-') {
1473             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1474         } else if ((val = strchr(featurestr, '='))) {
1475             *val = 0; val++;
1476             feat2prop(featurestr);
1477             if (!strcmp(featurestr, "family")) {
1478                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1479             } else if (!strcmp(featurestr, "model")) {
1480                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1481             } else if (!strcmp(featurestr, "stepping")) {
1482                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1483             } else if (!strcmp(featurestr, "level")) {
1484                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1485             } else if (!strcmp(featurestr, "xlevel")) {
1486                 char *err;
1487                 char num[32];
1488
1489                 numvalue = strtoul(val, &err, 0);
1490                 if (!*val || *err) {
1491                     error_setg(errp, "bad numerical value %s", val);
1492                     goto out;
1493                 }
1494                 if (numvalue < 0x80000000) {
1495                     fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1496                             ", fixup will be removed in future versions\n");
1497                     numvalue += 0x80000000;
1498                 }
1499                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1500                 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1501             } else if (!strcmp(featurestr, "vendor")) {
1502                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1503             } else if (!strcmp(featurestr, "model-id")) {
1504                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1505             } else if (!strcmp(featurestr, "tsc-freq")) {
1506                 int64_t tsc_freq;
1507                 char *err;
1508                 char num[32];
1509
1510                 tsc_freq = strtosz_suffix_unit(val, &err,
1511                                                STRTOSZ_DEFSUFFIX_B, 1000);
1512                 if (tsc_freq < 0 || *err) {
1513                     error_setg(errp, "bad numerical value %s", val);
1514                     goto out;
1515                 }
1516                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1517                 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1518             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1519                 char *err;
1520                 numvalue = strtoul(val, &err, 0);
1521                 if (!*val || *err) {
1522                     error_setg(errp, "bad numerical value %s", val);
1523                     goto out;
1524                 }
1525                 hyperv_set_spinlock_retries(numvalue);
1526             } else {
1527                 error_setg(errp, "unrecognized feature %s", featurestr);
1528                 goto out;
1529             }
1530         } else if (!strcmp(featurestr, "check")) {
1531             check_cpuid = 1;
1532         } else if (!strcmp(featurestr, "enforce")) {
1533             check_cpuid = enforce_cpuid = 1;
1534         } else if (!strcmp(featurestr, "hv_relaxed")) {
1535             hyperv_enable_relaxed_timing(true);
1536         } else if (!strcmp(featurestr, "hv_vapic")) {
1537             hyperv_enable_vapic_recommended(true);
1538         } else {
1539             error_setg(errp, "feature string `%s' not in format (+feature|"
1540                        "-feature|feature=xyz)", featurestr);
1541             goto out;
1542         }
1543         if (error_is_set(errp)) {
1544             goto out;
1545         }
1546         featurestr = strtok(NULL, ",");
1547     }
1548     env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1549     env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1550     env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1551     env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1552     env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1553     env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1554     env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1555     env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1556     env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1557     env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1558     env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1559     env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1560     env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1561     env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1562     env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1563     env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1564
1565 out:
1566     return;
1567 }
1568
1569 /* generate a composite string into buf of all cpuid names in featureset
1570  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1571  * if flags, suppress names undefined in featureset.
1572  */
1573 static void listflags(char *buf, int bufsize, uint32_t fbits,
1574     const char **featureset, uint32_t flags)
1575 {
1576     const char **p = &featureset[31];
1577     char *q, *b, bit;
1578     int nc;
1579
1580     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1581     *buf = '\0';
1582     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1583         if (fbits & 1 << bit && (*p || !flags)) {
1584             if (*p)
1585                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1586             else
1587                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1588             if (bufsize <= nc) {
1589                 if (b) {
1590                     memcpy(b, "...", sizeof("..."));
1591                 }
1592                 return;
1593             }
1594             q += nc;
1595             bufsize -= nc;
1596         }
1597 }
1598
1599 /* generate CPU information. */
1600 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1601 {
1602     x86_def_t *def;
1603     char buf[256];
1604     int i;
1605
1606     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1607         def = &builtin_x86_defs[i];
1608         snprintf(buf, sizeof(buf), "%s", def->name);
1609         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1610     }
1611 #ifdef CONFIG_KVM
1612     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1613                    "KVM processor with all supported host features "
1614                    "(only available in KVM mode)");
1615 #endif
1616
1617     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1618     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1619         FeatureWordInfo *fw = &feature_word_info[i];
1620
1621         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1622         (*cpu_fprintf)(f, "  %s\n", buf);
1623     }
1624 }
1625
1626 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1627 {
1628     CpuDefinitionInfoList *cpu_list = NULL;
1629     x86_def_t *def;
1630     int i;
1631
1632     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1633         CpuDefinitionInfoList *entry;
1634         CpuDefinitionInfo *info;
1635
1636         def = &builtin_x86_defs[i];
1637         info = g_malloc0(sizeof(*info));
1638         info->name = g_strdup(def->name);
1639
1640         entry = g_malloc0(sizeof(*entry));
1641         entry->value = info;
1642         entry->next = cpu_list;
1643         cpu_list = entry;
1644     }
1645
1646     return cpu_list;
1647 }
1648
1649 #ifdef CONFIG_KVM
1650 static void filter_features_for_kvm(X86CPU *cpu)
1651 {
1652     CPUX86State *env = &cpu->env;
1653     KVMState *s = kvm_state;
1654
1655     env->features[FEAT_1_EDX] &=
1656         kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1657     env->features[FEAT_1_ECX] &=
1658         kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1659     env->features[FEAT_8000_0001_EDX] &=
1660         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1661     env->features[FEAT_8000_0001_ECX] &=
1662         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1663     env->features[FEAT_SVM]  &=
1664         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1665     env->features[FEAT_7_0_EBX] &=
1666         kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1667     env->features[FEAT_KVM] &=
1668         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1669     env->features[FEAT_C000_0001_EDX] &=
1670         kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1671
1672 }
1673 #endif
1674
1675 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1676 {
1677     CPUX86State *env = &cpu->env;
1678     x86_def_t def1, *def = &def1;
1679
1680     memset(def, 0, sizeof(*def));
1681
1682     if (cpu_x86_find_by_name(def, name) < 0) {
1683         error_setg(errp, "Unable to find CPU definition: %s", name);
1684         return;
1685     }
1686
1687     if (kvm_enabled()) {
1688         def->features[FEAT_KVM] |= kvm_default_features;
1689     }
1690     def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1691
1692     object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1693     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1694     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1695     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1696     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1697     env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1698     env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1699     env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1700     env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1701     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1702     env->features[FEAT_KVM] = def->features[FEAT_KVM];
1703     env->features[FEAT_SVM] = def->features[FEAT_SVM];
1704     env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1705     env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1706     env->cpuid_xlevel2 = def->xlevel2;
1707
1708     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1709 }
1710
1711 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1712                        Error **errp)
1713 {
1714     X86CPU *cpu = NULL;
1715     CPUX86State *env;
1716     gchar **model_pieces;
1717     char *name, *features;
1718     Error *error = NULL;
1719
1720     model_pieces = g_strsplit(cpu_model, ",", 2);
1721     if (!model_pieces[0]) {
1722         error_setg(&error, "Invalid/empty CPU model name");
1723         goto out;
1724     }
1725     name = model_pieces[0];
1726     features = model_pieces[1];
1727
1728     cpu = X86_CPU(object_new(TYPE_X86_CPU));
1729 #ifndef CONFIG_USER_ONLY
1730     if (icc_bridge == NULL) {
1731         error_setg(&error, "Invalid icc-bridge value");
1732         goto out;
1733     }
1734     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1735     object_unref(OBJECT(cpu));
1736 #endif
1737     env = &cpu->env;
1738     env->cpu_model_str = cpu_model;
1739
1740     cpu_x86_register(cpu, name, &error);
1741     if (error) {
1742         goto out;
1743     }
1744
1745     cpu_x86_parse_featurestr(cpu, features, &error);
1746     if (error) {
1747         goto out;
1748     }
1749
1750 out:
1751     error_propagate(errp, error);
1752     g_strfreev(model_pieces);
1753     return cpu;
1754 }
1755
1756 X86CPU *cpu_x86_init(const char *cpu_model)
1757 {
1758     Error *error = NULL;
1759     X86CPU *cpu;
1760
1761     cpu = cpu_x86_create(cpu_model, NULL, &error);
1762     if (error) {
1763         goto out;
1764     }
1765
1766     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1767
1768 out:
1769     if (error) {
1770         fprintf(stderr, "%s\n", error_get_pretty(error));
1771         error_free(error);
1772         if (cpu != NULL) {
1773             object_unref(OBJECT(cpu));
1774             cpu = NULL;
1775         }
1776     }
1777     return cpu;
1778 }
1779
1780 #if !defined(CONFIG_USER_ONLY)
1781
1782 void cpu_clear_apic_feature(CPUX86State *env)
1783 {
1784     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1785 }
1786
1787 #endif /* !CONFIG_USER_ONLY */
1788
1789 /* Initialize list of CPU models, filling some non-static fields if necessary
1790  */
1791 void x86_cpudef_setup(void)
1792 {
1793     int i, j;
1794     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1795
1796     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1797         x86_def_t *def = &builtin_x86_defs[i];
1798
1799         /* Look for specific "cpudef" models that */
1800         /* have the QEMU version in .model_id */
1801         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1802             if (strcmp(model_with_versions[j], def->name) == 0) {
1803                 pstrcpy(def->model_id, sizeof(def->model_id),
1804                         "QEMU Virtual CPU version ");
1805                 pstrcat(def->model_id, sizeof(def->model_id),
1806                         qemu_get_version());
1807                 break;
1808             }
1809         }
1810     }
1811 }
1812
1813 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1814                              uint32_t *ecx, uint32_t *edx)
1815 {
1816     *ebx = env->cpuid_vendor1;
1817     *edx = env->cpuid_vendor2;
1818     *ecx = env->cpuid_vendor3;
1819 }
1820
1821 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1822                    uint32_t *eax, uint32_t *ebx,
1823                    uint32_t *ecx, uint32_t *edx)
1824 {
1825     X86CPU *cpu = x86_env_get_cpu(env);
1826     CPUState *cs = CPU(cpu);
1827
1828     /* test if maximum index reached */
1829     if (index & 0x80000000) {
1830         if (index > env->cpuid_xlevel) {
1831             if (env->cpuid_xlevel2 > 0) {
1832                 /* Handle the Centaur's CPUID instruction. */
1833                 if (index > env->cpuid_xlevel2) {
1834                     index = env->cpuid_xlevel2;
1835                 } else if (index < 0xC0000000) {
1836                     index = env->cpuid_xlevel;
1837                 }
1838             } else {
1839                 /* Intel documentation states that invalid EAX input will
1840                  * return the same information as EAX=cpuid_level
1841                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1842                  */
1843                 index =  env->cpuid_level;
1844             }
1845         }
1846     } else {
1847         if (index > env->cpuid_level)
1848             index = env->cpuid_level;
1849     }
1850
1851     switch(index) {
1852     case 0:
1853         *eax = env->cpuid_level;
1854         get_cpuid_vendor(env, ebx, ecx, edx);
1855         break;
1856     case 1:
1857         *eax = env->cpuid_version;
1858         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1859         *ecx = env->features[FEAT_1_ECX];
1860         *edx = env->features[FEAT_1_EDX];
1861         if (cs->nr_cores * cs->nr_threads > 1) {
1862             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1863             *edx |= 1 << 28;    /* HTT bit */
1864         }
1865         break;
1866     case 2:
1867         /* cache info: needed for Pentium Pro compatibility */
1868         *eax = 1;
1869         *ebx = 0;
1870         *ecx = 0;
1871         *edx = 0x2c307d;
1872         break;
1873     case 4:
1874         /* cache info: needed for Core compatibility */
1875         if (cs->nr_cores > 1) {
1876             *eax = (cs->nr_cores - 1) << 26;
1877         } else {
1878             *eax = 0;
1879         }
1880         switch (count) {
1881             case 0: /* L1 dcache info */
1882                 *eax |= 0x0000121;
1883                 *ebx = 0x1c0003f;
1884                 *ecx = 0x000003f;
1885                 *edx = 0x0000001;
1886                 break;
1887             case 1: /* L1 icache info */
1888                 *eax |= 0x0000122;
1889                 *ebx = 0x1c0003f;
1890                 *ecx = 0x000003f;
1891                 *edx = 0x0000001;
1892                 break;
1893             case 2: /* L2 cache info */
1894                 *eax |= 0x0000143;
1895                 if (cs->nr_threads > 1) {
1896                     *eax |= (cs->nr_threads - 1) << 14;
1897                 }
1898                 *ebx = 0x3c0003f;
1899                 *ecx = 0x0000fff;
1900                 *edx = 0x0000001;
1901                 break;
1902             default: /* end of info */
1903                 *eax = 0;
1904                 *ebx = 0;
1905                 *ecx = 0;
1906                 *edx = 0;
1907                 break;
1908         }
1909         break;
1910     case 5:
1911         /* mwait info: needed for Core compatibility */
1912         *eax = 0; /* Smallest monitor-line size in bytes */
1913         *ebx = 0; /* Largest monitor-line size in bytes */
1914         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1915         *edx = 0;
1916         break;
1917     case 6:
1918         /* Thermal and Power Leaf */
1919         *eax = 0;
1920         *ebx = 0;
1921         *ecx = 0;
1922         *edx = 0;
1923         break;
1924     case 7:
1925         /* Structured Extended Feature Flags Enumeration Leaf */
1926         if (count == 0) {
1927             *eax = 0; /* Maximum ECX value for sub-leaves */
1928             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
1929             *ecx = 0; /* Reserved */
1930             *edx = 0; /* Reserved */
1931         } else {
1932             *eax = 0;
1933             *ebx = 0;
1934             *ecx = 0;
1935             *edx = 0;
1936         }
1937         break;
1938     case 9:
1939         /* Direct Cache Access Information Leaf */
1940         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1941         *ebx = 0;
1942         *ecx = 0;
1943         *edx = 0;
1944         break;
1945     case 0xA:
1946         /* Architectural Performance Monitoring Leaf */
1947         if (kvm_enabled()) {
1948             KVMState *s = cs->kvm_state;
1949
1950             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1951             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1952             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1953             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1954         } else {
1955             *eax = 0;
1956             *ebx = 0;
1957             *ecx = 0;
1958             *edx = 0;
1959         }
1960         break;
1961     case 0xD:
1962         /* Processor Extended State */
1963         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
1964             *eax = 0;
1965             *ebx = 0;
1966             *ecx = 0;
1967             *edx = 0;
1968             break;
1969         }
1970         if (kvm_enabled()) {
1971             KVMState *s = cs->kvm_state;
1972
1973             *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1974             *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1975             *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1976             *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1977         } else {
1978             *eax = 0;
1979             *ebx = 0;
1980             *ecx = 0;
1981             *edx = 0;
1982         }
1983         break;
1984     case 0x80000000:
1985         *eax = env->cpuid_xlevel;
1986         *ebx = env->cpuid_vendor1;
1987         *edx = env->cpuid_vendor2;
1988         *ecx = env->cpuid_vendor3;
1989         break;
1990     case 0x80000001:
1991         *eax = env->cpuid_version;
1992         *ebx = 0;
1993         *ecx = env->features[FEAT_8000_0001_ECX];
1994         *edx = env->features[FEAT_8000_0001_EDX];
1995
1996         /* The Linux kernel checks for the CMPLegacy bit and
1997          * discards multiple thread information if it is set.
1998          * So dont set it here for Intel to make Linux guests happy.
1999          */
2000         if (cs->nr_cores * cs->nr_threads > 1) {
2001             uint32_t tebx, tecx, tedx;
2002             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2003             if (tebx != CPUID_VENDOR_INTEL_1 ||
2004                 tedx != CPUID_VENDOR_INTEL_2 ||
2005                 tecx != CPUID_VENDOR_INTEL_3) {
2006                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2007             }
2008         }
2009         break;
2010     case 0x80000002:
2011     case 0x80000003:
2012     case 0x80000004:
2013         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2014         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2015         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2016         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2017         break;
2018     case 0x80000005:
2019         /* cache info (L1 cache) */
2020         *eax = 0x01ff01ff;
2021         *ebx = 0x01ff01ff;
2022         *ecx = 0x40020140;
2023         *edx = 0x40020140;
2024         break;
2025     case 0x80000006:
2026         /* cache info (L2 cache) */
2027         *eax = 0;
2028         *ebx = 0x42004200;
2029         *ecx = 0x02008140;
2030         *edx = 0;
2031         break;
2032     case 0x80000008:
2033         /* virtual & phys address size in low 2 bytes. */
2034 /* XXX: This value must match the one used in the MMU code. */
2035         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2036             /* 64 bit processor */
2037 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2038             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2039         } else {
2040             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2041                 *eax = 0x00000024; /* 36 bits physical */
2042             } else {
2043                 *eax = 0x00000020; /* 32 bits physical */
2044             }
2045         }
2046         *ebx = 0;
2047         *ecx = 0;
2048         *edx = 0;
2049         if (cs->nr_cores * cs->nr_threads > 1) {
2050             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2051         }
2052         break;
2053     case 0x8000000A:
2054         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2055             *eax = 0x00000001; /* SVM Revision */
2056             *ebx = 0x00000010; /* nr of ASIDs */
2057             *ecx = 0;
2058             *edx = env->features[FEAT_SVM]; /* optional features */
2059         } else {
2060             *eax = 0;
2061             *ebx = 0;
2062             *ecx = 0;
2063             *edx = 0;
2064         }
2065         break;
2066     case 0xC0000000:
2067         *eax = env->cpuid_xlevel2;
2068         *ebx = 0;
2069         *ecx = 0;
2070         *edx = 0;
2071         break;
2072     case 0xC0000001:
2073         /* Support for VIA CPU's CPUID instruction */
2074         *eax = env->cpuid_version;
2075         *ebx = 0;
2076         *ecx = 0;
2077         *edx = env->features[FEAT_C000_0001_EDX];
2078         break;
2079     case 0xC0000002:
2080     case 0xC0000003:
2081     case 0xC0000004:
2082         /* Reserved for the future, and now filled with zero */
2083         *eax = 0;
2084         *ebx = 0;
2085         *ecx = 0;
2086         *edx = 0;
2087         break;
2088     default:
2089         /* reserved values: zero */
2090         *eax = 0;
2091         *ebx = 0;
2092         *ecx = 0;
2093         *edx = 0;
2094         break;
2095     }
2096 }
2097
2098 /* CPUClass::reset() */
2099 static void x86_cpu_reset(CPUState *s)
2100 {
2101     X86CPU *cpu = X86_CPU(s);
2102     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2103     CPUX86State *env = &cpu->env;
2104     int i;
2105
2106     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2107         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
2108         log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
2109     }
2110
2111     xcc->parent_reset(s);
2112
2113
2114     memset(env, 0, offsetof(CPUX86State, breakpoints));
2115
2116     tlb_flush(env, 1);
2117
2118     env->old_exception = -1;
2119
2120     /* init to reset state */
2121
2122 #ifdef CONFIG_SOFTMMU
2123     env->hflags |= HF_SOFTMMU_MASK;
2124 #endif
2125     env->hflags2 |= HF2_GIF_MASK;
2126
2127     cpu_x86_update_cr0(env, 0x60000010);
2128     env->a20_mask = ~0x0;
2129     env->smbase = 0x30000;
2130
2131     env->idt.limit = 0xffff;
2132     env->gdt.limit = 0xffff;
2133     env->ldt.limit = 0xffff;
2134     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2135     env->tr.limit = 0xffff;
2136     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2137
2138     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2139                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2140                            DESC_R_MASK | DESC_A_MASK);
2141     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2142                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2143                            DESC_A_MASK);
2144     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2145                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2146                            DESC_A_MASK);
2147     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2148                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2149                            DESC_A_MASK);
2150     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2151                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2152                            DESC_A_MASK);
2153     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2154                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2155                            DESC_A_MASK);
2156
2157     env->eip = 0xfff0;
2158     env->regs[R_EDX] = env->cpuid_version;
2159
2160     env->eflags = 0x2;
2161
2162     /* FPU init */
2163     for (i = 0; i < 8; i++) {
2164         env->fptags[i] = 1;
2165     }
2166     env->fpuc = 0x37f;
2167
2168     env->mxcsr = 0x1f80;
2169
2170     env->pat = 0x0007040600070406ULL;
2171     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2172
2173     memset(env->dr, 0, sizeof(env->dr));
2174     env->dr[6] = DR6_FIXED_1;
2175     env->dr[7] = DR7_FIXED_1;
2176     cpu_breakpoint_remove_all(env, BP_CPU);
2177     cpu_watchpoint_remove_all(env, BP_CPU);
2178
2179 #if !defined(CONFIG_USER_ONLY)
2180     /* We hard-wire the BSP to the first CPU. */
2181     if (s->cpu_index == 0) {
2182         apic_designate_bsp(env->apic_state);
2183     }
2184
2185     s->halted = !cpu_is_bsp(cpu);
2186 #endif
2187 }
2188
2189 #ifndef CONFIG_USER_ONLY
2190 bool cpu_is_bsp(X86CPU *cpu)
2191 {
2192     return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2193 }
2194
2195 /* TODO: remove me, when reset over QOM tree is implemented */
2196 static void x86_cpu_machine_reset_cb(void *opaque)
2197 {
2198     X86CPU *cpu = opaque;
2199     cpu_reset(CPU(cpu));
2200 }
2201 #endif
2202
2203 static void mce_init(X86CPU *cpu)
2204 {
2205     CPUX86State *cenv = &cpu->env;
2206     unsigned int bank;
2207
2208     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2209         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2210             (CPUID_MCE | CPUID_MCA)) {
2211         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2212         cenv->mcg_ctl = ~(uint64_t)0;
2213         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2214             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2215         }
2216     }
2217 }
2218
2219 #ifndef CONFIG_USER_ONLY
2220 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2221 {
2222     CPUX86State *env = &cpu->env;
2223     DeviceState *dev = DEVICE(cpu);
2224     APICCommonState *apic;
2225     const char *apic_type = "apic";
2226
2227     if (kvm_irqchip_in_kernel()) {
2228         apic_type = "kvm-apic";
2229     } else if (xen_enabled()) {
2230         apic_type = "xen-apic";
2231     }
2232
2233     env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2234     if (env->apic_state == NULL) {
2235         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2236         return;
2237     }
2238
2239     object_property_add_child(OBJECT(cpu), "apic",
2240                               OBJECT(env->apic_state), NULL);
2241     qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2242     /* TODO: convert to link<> */
2243     apic = APIC_COMMON(env->apic_state);
2244     apic->cpu = cpu;
2245 }
2246
2247 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2248 {
2249     CPUX86State *env = &cpu->env;
2250
2251     if (env->apic_state == NULL) {
2252         return;
2253     }
2254
2255     if (qdev_init(env->apic_state)) {
2256         error_setg(errp, "APIC device '%s' could not be initialized",
2257                    object_get_typename(OBJECT(env->apic_state)));
2258         return;
2259     }
2260 }
2261 #else
2262 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2263 {
2264 }
2265 #endif
2266
2267 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2268 {
2269     X86CPU *cpu = X86_CPU(dev);
2270     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2271     CPUX86State *env = &cpu->env;
2272     Error *local_err = NULL;
2273
2274     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2275         env->cpuid_level = 7;
2276     }
2277
2278     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2279      * CPUID[1].EDX.
2280      */
2281     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2282         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2283         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2284         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2285         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2286            & CPUID_EXT2_AMD_ALIASES);
2287     }
2288
2289     if (!kvm_enabled()) {
2290         env->features[FEAT_1_EDX] &= TCG_FEATURES;
2291         env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2292         env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2293 #ifdef TARGET_X86_64
2294             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2295 #endif
2296             );
2297         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2298         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2299     } else {
2300         if (check_cpuid && kvm_check_features_against_host(cpu)
2301             && enforce_cpuid) {
2302             error_setg(&local_err,
2303                        "Host's CPU doesn't support requested features");
2304             goto out;
2305         }
2306 #ifdef CONFIG_KVM
2307         filter_features_for_kvm(cpu);
2308 #endif
2309     }
2310
2311 #ifndef CONFIG_USER_ONLY
2312     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2313
2314     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2315         x86_cpu_apic_create(cpu, &local_err);
2316         if (local_err != NULL) {
2317             goto out;
2318         }
2319     }
2320 #endif
2321
2322     mce_init(cpu);
2323     qemu_init_vcpu(&cpu->env);
2324
2325     x86_cpu_apic_realize(cpu, &local_err);
2326     if (local_err != NULL) {
2327         goto out;
2328     }
2329     cpu_reset(CPU(cpu));
2330
2331     xcc->parent_realize(dev, &local_err);
2332 out:
2333     if (local_err != NULL) {
2334         error_propagate(errp, local_err);
2335         return;
2336     }
2337 }
2338
2339 /* Enables contiguous-apic-ID mode, for compatibility */
2340 static bool compat_apic_id_mode;
2341
2342 void enable_compat_apic_id_mode(void)
2343 {
2344     compat_apic_id_mode = true;
2345 }
2346
2347 /* Calculates initial APIC ID for a specific CPU index
2348  *
2349  * Currently we need to be able to calculate the APIC ID from the CPU index
2350  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2351  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2352  * all CPUs up to max_cpus.
2353  */
2354 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2355 {
2356     uint32_t correct_id;
2357     static bool warned;
2358
2359     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2360     if (compat_apic_id_mode) {
2361         if (cpu_index != correct_id && !warned) {
2362             error_report("APIC IDs set in compatibility mode, "
2363                          "CPU topology won't match the configuration");
2364             warned = true;
2365         }
2366         return cpu_index;
2367     } else {
2368         return correct_id;
2369     }
2370 }
2371
2372 static void x86_cpu_initfn(Object *obj)
2373 {
2374     CPUState *cs = CPU(obj);
2375     X86CPU *cpu = X86_CPU(obj);
2376     CPUX86State *env = &cpu->env;
2377     static int inited;
2378
2379     cs->env_ptr = env;
2380     cpu_exec_init(env);
2381
2382     object_property_add(obj, "family", "int",
2383                         x86_cpuid_version_get_family,
2384                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2385     object_property_add(obj, "model", "int",
2386                         x86_cpuid_version_get_model,
2387                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2388     object_property_add(obj, "stepping", "int",
2389                         x86_cpuid_version_get_stepping,
2390                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2391     object_property_add(obj, "level", "int",
2392                         x86_cpuid_get_level,
2393                         x86_cpuid_set_level, NULL, NULL, NULL);
2394     object_property_add(obj, "xlevel", "int",
2395                         x86_cpuid_get_xlevel,
2396                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2397     object_property_add_str(obj, "vendor",
2398                             x86_cpuid_get_vendor,
2399                             x86_cpuid_set_vendor, NULL);
2400     object_property_add_str(obj, "model-id",
2401                             x86_cpuid_get_model_id,
2402                             x86_cpuid_set_model_id, NULL);
2403     object_property_add(obj, "tsc-frequency", "int",
2404                         x86_cpuid_get_tsc_freq,
2405                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2406     object_property_add(obj, "apic-id", "int",
2407                         x86_cpuid_get_apic_id,
2408                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2409
2410     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2411
2412     /* init various static tables used in TCG mode */
2413     if (tcg_enabled() && !inited) {
2414         inited = 1;
2415         optimize_flags_init();
2416 #ifndef CONFIG_USER_ONLY
2417         cpu_set_debug_excp_handler(breakpoint_handler);
2418 #endif
2419     }
2420 }
2421
2422 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2423 {
2424     X86CPU *cpu = X86_CPU(cs);
2425     CPUX86State *env = &cpu->env;
2426
2427     return env->cpuid_apic_id;
2428 }
2429
2430 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2431 {
2432     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2433     CPUClass *cc = CPU_CLASS(oc);
2434     DeviceClass *dc = DEVICE_CLASS(oc);
2435
2436     xcc->parent_realize = dc->realize;
2437     dc->realize = x86_cpu_realizefn;
2438     dc->bus_type = TYPE_ICC_BUS;
2439
2440     xcc->parent_reset = cc->reset;
2441     cc->reset = x86_cpu_reset;
2442
2443     cc->do_interrupt = x86_cpu_do_interrupt;
2444 #ifndef CONFIG_USER_ONLY
2445     cc->write_elf64_note = x86_cpu_write_elf64_note;
2446     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2447     cc->write_elf32_note = x86_cpu_write_elf32_note;
2448     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2449 #endif
2450     cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2451
2452     cc->get_arch_id = x86_cpu_get_arch_id;
2453 }
2454
2455 static const TypeInfo x86_cpu_type_info = {
2456     .name = TYPE_X86_CPU,
2457     .parent = TYPE_CPU,
2458     .instance_size = sizeof(X86CPU),
2459     .instance_init = x86_cpu_initfn,
2460     .abstract = false,
2461     .class_size = sizeof(X86CPUClass),
2462     .class_init = x86_cpu_common_class_init,
2463 };
2464
2465 static void x86_cpu_register_types(void)
2466 {
2467     type_register_static(&x86_cpu_type_info);
2468 }
2469
2470 type_init(x86_cpu_register_types)