hw/intc/lm32_pic.c

   1 /*
   2  *  LatticeMico32 CPU interrupt controller logic.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <assert.h>
  21
  22 #include "hw/hw.h"
  23 #include "hw/i386/pc.h"
  24 #include "monitor/monitor.h"
  25 #include "hw/sysbus.h"
  26 #include "trace.h"
  27 #include "hw/lm32/lm32_pic.h"
  28
  29 #define TYPE_LM32_PIC "lm32-pic"
  30 #define LM32_PIC(obj) OBJECT_CHECK(LM32PicState, (obj), TYPE_LM32_PIC)
  31
  32 struct LM32PicState {
  33     SysBusDevice parent_obj;
  34
  35     qemu_irq parent_irq;
  36     uint32_t im;        /* interrupt mask */
  37     uint32_t ip;        /* interrupt pending */
  38     uint32_t irq_state;
  39
  40     /* statistics */
  41     uint32_t stats_irq_count[32];
  42 };
  43 typedef struct LM32PicState LM32PicState;
  44
  45 static LM32PicState *pic;
  46 void lm32_hmp_info_pic(Monitor *mon, const QDict *qdict)
  47 {
  48     if (pic == NULL) {
  49         return;
  50     }
  51
  52     monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n",
  53             pic->im, pic->ip, pic->irq_state);
  54 }
  55
  56 void lm32_hmp_info_irq(Monitor *mon, const QDict *qdict)
  57 {
  58     int i;
  59     uint32_t count;
  60
  61     if (pic == NULL) {
  62         return;
  63     }
  64
  65     monitor_printf(mon, "IRQ statistics:\n");
  66     for (i = 0; i < 32; i++) {
  67         count = pic->stats_irq_count[i];
  68         if (count > 0) {
  69             monitor_printf(mon, "%2d: %u\n", i, count);
  70         }
  71     }
  72 }
  73
  74 static void update_irq(LM32PicState *s)
  75 {
  76     s->ip |= s->irq_state;
  77
  78     if (s->ip & s->im) {
  79         trace_lm32_pic_raise_irq();
  80         qemu_irq_raise(s->parent_irq);
  81     } else {
  82         trace_lm32_pic_lower_irq();
  83         qemu_irq_lower(s->parent_irq);
  84     }
  85 }
  86
  87 static void irq_handler(void *opaque, int irq, int level)
  88 {
  89     LM32PicState *s = opaque;
  90
  91     assert(irq < 32);
  92     trace_lm32_pic_interrupt(irq, level);
  93
  94     if (level) {
  95         s->irq_state |= (1 << irq);
  96         s->stats_irq_count[irq]++;
  97     } else {
  98         s->irq_state &= ~(1 << irq);
  99     }
 100
 101     update_irq(s);
 102 }
 103
 104 void lm32_pic_set_im(DeviceState *d, uint32_t im)
 105 {
 106     LM32PicState *s = LM32_PIC(d);
 107
 108     trace_lm32_pic_set_im(im);
 109     s->im = im;
 110
 111     update_irq(s);
 112 }
 113
 114 void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
 115 {
 116     LM32PicState *s = LM32_PIC(d);
 117
 118     trace_lm32_pic_set_ip(ip);
 119
 120     /* ack interrupt */
 121     s->ip &= ~ip;
 122
 123     update_irq(s);
 124 }
 125
 126 uint32_t lm32_pic_get_im(DeviceState *d)
 127 {
 128     LM32PicState *s = LM32_PIC(d);
 129
 130     trace_lm32_pic_get_im(s->im);
 131     return s->im;
 132 }
 133
 134 uint32_t lm32_pic_get_ip(DeviceState *d)
 135 {
 136     LM32PicState *s = LM32_PIC(d);
 137
 138     trace_lm32_pic_get_ip(s->ip);
 139     return s->ip;
 140 }
 141
 142 static void pic_reset(DeviceState *d)
 143 {
 144     LM32PicState *s = LM32_PIC(d);
 145     int i;
 146
 147     s->im = 0;
 148     s->ip = 0;
 149     s->irq_state = 0;
 150     for (i = 0; i < 32; i++) {
 151         s->stats_irq_count[i] = 0;
 152     }
 153 }
 154
 155 static int lm32_pic_init(SysBusDevice *sbd)
 156 {
 157     DeviceState *dev = DEVICE(sbd);
 158     LM32PicState *s = LM32_PIC(dev);
 159
 160     qdev_init_gpio_in(dev, irq_handler, 32);
 161     sysbus_init_irq(sbd, &s->parent_irq);
 162
 163     pic = s;
 164
 165     return 0;
 166 }
 167
 168 static const VMStateDescription vmstate_lm32_pic = {
 169     .name = "lm32-pic",
 170     .version_id = 1,
 171     .minimum_version_id = 1,
 172     .fields = (VMStateField[]) {
 173         VMSTATE_UINT32(im, LM32PicState),
 174         VMSTATE_UINT32(ip, LM32PicState),
 175         VMSTATE_UINT32(irq_state, LM32PicState),
 176         VMSTATE_UINT32_ARRAY(stats_irq_count, LM32PicState, 32),
 177         VMSTATE_END_OF_LIST()
 178     }
 179 };
 180
 181 static void lm32_pic_class_init(ObjectClass *klass, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(klass);
 184     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 185
 186     k->init = lm32_pic_init;
 187     dc->reset = pic_reset;
 188     dc->vmsd = &vmstate_lm32_pic;
 189 }
 190
 191 static const TypeInfo lm32_pic_info = {
 192     .name          = TYPE_LM32_PIC,
 193     .parent        = TYPE_SYS_BUS_DEVICE,
 194     .instance_size = sizeof(LM32PicState),
 195     .class_init    = lm32_pic_class_init,
 196 };
 197
 198 static void lm32_pic_register_types(void)
 199 {
 200     type_register_static(&lm32_pic_info);
 201 }
 202
 203 type_init(lm32_pic_register_types)