4 #include "qemu-common.h"
6 /* PC-style peripherals (also used by other machines). */
10 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
11 CharDriverState *chr);
12 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
13 qemu_irq irq, int baudbase,
14 CharDriverState *chr, int ioregister);
18 typedef struct ParallelState ParallelState;
19 ParallelState *parallel_init(int index, CharDriverState *chr);
20 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
24 typedef struct PicState2 PicState2;
25 extern PicState2 *isa_pic;
26 void pic_set_irq(int irq, int level);
27 void pic_set_irq_new(void *opaque, int irq, int level);
28 qemu_irq *i8259_init(qemu_irq parent_irq);
29 int pic_read_irq(PicState2 *s);
30 void pic_update_irq(PicState2 *s);
31 uint32_t pic_intack_read(PicState2 *s);
32 void pic_info(Monitor *mon);
33 void irq_info(Monitor *mon);
36 typedef struct IOAPICState IOAPICState;
37 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
38 uint8_t delivery_mode,
39 uint8_t vector_num, uint8_t polarity,
40 uint8_t trigger_mode);
41 int apic_init(CPUState *env);
42 int apic_accept_pic_intr(CPUState *env);
43 void apic_deliver_pic_intr(CPUState *env, int level);
44 int apic_get_interrupt(CPUState *env);
45 qemu_irq *ioapic_init(void);
46 void ioapic_set_irq(void *opaque, int vector, int level);
47 void apic_reset_irq_delivered(void);
48 int apic_get_irq_delivered(void);
52 #define PIT_FREQ 1193182
54 typedef struct PITState PITState;
56 PITState *pit_init(int base, qemu_irq irq);
57 void pit_set_gate(PITState *pit, int channel, int val);
58 int pit_get_gate(PITState *pit, int channel);
59 int pit_get_initial_count(PITState *pit, int channel);
60 int pit_get_mode(PITState *pit, int channel);
61 int pit_get_out(PITState *pit, int channel, int64_t current_time);
63 void hpet_pit_disable(void);
64 void hpet_pit_enable(void);
67 void vmport_init(void);
68 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
71 void *vmmouse_init(void *m);
75 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
76 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
77 target_phys_addr_t base, ram_addr_t size,
78 target_phys_addr_t mask);
82 typedef struct RTCState RTCState;
84 RTCState *rtc_init(int base_year);
85 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
87 void rtc_set_memory(RTCState *s, int addr, int val);
88 void rtc_set_date(RTCState *s, const struct tm *tm);
89 void cmos_set_s3_resume(void);
92 extern int fd_bootchk;
94 void ioport_set_a20(int enable);
95 int ioport_get_a20(void);
98 extern int acpi_enabled;
99 extern char *acpi_tables;
100 extern size_t acpi_tables_len;
102 void acpi_bios_init(void);
103 int acpi_table_add(const char *table_desc);
106 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
108 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
109 void piix4_acpi_system_hot_add_init(void);
115 void pcspk_init(PITState *);
116 int pcspk_audio_init(qemu_irq *pic);
119 struct PCII440FXState;
120 typedef struct PCII440FXState PCII440FXState;
122 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic);
123 void i440fx_set_smm(PCII440FXState *d, int val);
124 void i440fx_init_memory_mappings(PCII440FXState *d);
127 extern PCIDevice *piix4_dev;
128 int piix4_init(PCIBus *bus, int devfn);
131 enum vga_retrace_method {
136 extern enum vga_retrace_method vga_retrace_method;
138 int isa_vga_init(void);
139 int pci_vga_init(PCIBus *bus,
140 unsigned long vga_bios_offset, int vga_bios_size);
141 int isa_vga_mm_init(target_phys_addr_t vram_base,
142 target_phys_addr_t ctrl_base, int it_shift);
145 void pci_cirrus_vga_init(PCIBus *bus);
146 void isa_cirrus_vga_init(void);
150 void isa_ne2000_init(int base, int irq, NICInfo *nd);
152 int cpu_is_bsp(CPUState *env);