hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define XEN_PIIX_NUM_PIRQS      128ULL
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 typedef struct PAMMemoryRegion {
  70     MemoryRegion mem;
  71     bool initialized;
  72 } PAMMemoryRegion;
  73
  74 struct PCII440FXState {
  75     PCIDevice dev;
  76     MemoryRegion *system_memory;
  77     MemoryRegion *pci_address_space;
  78     MemoryRegion *ram_memory;
  79     MemoryRegion pci_hole;
  80     MemoryRegion pci_hole_64bit;
  81     PAMMemoryRegion pam_regions[13];
  82     MemoryRegion smram_region;
  83     uint8_t smm_enabled;
  84     bool smram_enabled;
  85     PIIX3State *piix3;
  86 };
  87
  88
  89 #define I440FX_PAM      0x59
  90 #define I440FX_PAM_SIZE 7
  91 #define I440FX_SMRAM    0x72
  92
  93 static void piix3_set_irq(void *opaque, int pirq, int level);
  94 static void piix3_write_config_xen(PCIDevice *dev,
  95                                uint32_t address, uint32_t val, int len);
  96
  97 /* return the global irq number corresponding to a given device irq
  98    pin. We could also use the bus number to have a more precise
  99    mapping. */
 100 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 101 {
 102     int slot_addend;
 103     slot_addend = (pci_dev->devfn >> 3) - 1;
 104     return (pci_intx + slot_addend) & 3;
 105 }
 106
 107 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
 108                        PAMMemoryRegion *mem)
 109 {
 110     if (mem->initialized) {
 111         memory_region_del_subregion(d->system_memory, &mem->mem);
 112         memory_region_destroy(&mem->mem);
 113     }
 114
 115     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
 116     switch(r) {
 117     case 3:
 118         /* RAM */
 119         memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
 120                                  start, end - start);
 121         break;
 122     case 1:
 123         /* ROM (XXX: not quite correct) */
 124         memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
 125                                  start, end - start);
 126         memory_region_set_readonly(&mem->mem, true);
 127         break;
 128     case 2:
 129     case 0:
 130         /* XXX: should distinguish read/write cases */
 131         memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
 132                                  start, end - start);
 133         break;
 134     }
 135     memory_region_add_subregion_overlap(d->system_memory,
 136                                         start, &mem->mem, 1);
 137     mem->initialized = true;
 138 }
 139
 140 static void i440fx_update_memory_mappings(PCII440FXState *d)
 141 {
 142     int i, r;
 143     uint32_t smram;
 144
 145     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
 146                &d->pam_regions[0]);
 147     for(i = 0; i < 12; i++) {
 148         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 149         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
 150                    &d->pam_regions[i+1]);
 151     }
 152     smram = d->dev.config[I440FX_SMRAM];
 153     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 154         if (!d->smram_enabled) {
 155             memory_region_del_subregion(d->system_memory, &d->smram_region);
 156             d->smram_enabled = true;
 157         }
 158     } else {
 159         if (d->smram_enabled) {
 160             memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
 161                                                 &d->smram_region, 1);
 162             d->smram_enabled = false;
 163         }
 164     }
 165 }
 166
 167 static void i440fx_set_smm(int val, void *arg)
 168 {
 169     PCII440FXState *d = arg;
 170
 171     val = (val != 0);
 172     if (d->smm_enabled != val) {
 173         d->smm_enabled = val;
 174         i440fx_update_memory_mappings(d);
 175     }
 176 }
 177
 178
 179 static void i440fx_write_config(PCIDevice *dev,
 180                                 uint32_t address, uint32_t val, int len)
 181 {
 182     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 183
 184     /* XXX: implement SMRAM.D_LOCK */
 185     pci_default_write_config(dev, address, val, len);
 186     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 187         range_covers_byte(address, len, I440FX_SMRAM)) {
 188         i440fx_update_memory_mappings(d);
 189     }
 190 }
 191
 192 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 193 {
 194     PCII440FXState *d = opaque;
 195     int ret, i;
 196
 197     ret = pci_device_load(&d->dev, f);
 198     if (ret < 0)
 199         return ret;
 200     i440fx_update_memory_mappings(d);
 201     qemu_get_8s(f, &d->smm_enabled);
 202
 203     if (version_id == 2) {
 204         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 205             qemu_get_be32(f); /* dummy load for compatibility */
 206         }
 207     }
 208
 209     return 0;
 210 }
 211
 212 static int i440fx_post_load(void *opaque, int version_id)
 213 {
 214     PCII440FXState *d = opaque;
 215
 216     i440fx_update_memory_mappings(d);
 217     return 0;
 218 }
 219
 220 static const VMStateDescription vmstate_i440fx = {
 221     .name = "I440FX",
 222     .version_id = 3,
 223     .minimum_version_id = 3,
 224     .minimum_version_id_old = 1,
 225     .load_state_old = i440fx_load_old,
 226     .post_load = i440fx_post_load,
 227     .fields      = (VMStateField []) {
 228         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 229         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 230         VMSTATE_END_OF_LIST()
 231     }
 232 };
 233
 234 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 235 {
 236     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 237
 238     pci_host_conf_register_ioport(0xcf8, s);
 239
 240     pci_host_data_register_ioport(0xcfc, s);
 241     return 0;
 242 }
 243
 244 static int i440fx_initfn(PCIDevice *dev)
 245 {
 246     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 247
 248     d->dev.config[I440FX_SMRAM] = 0x02;
 249
 250     cpu_smm_register(&i440fx_set_smm, d);
 251     return 0;
 252 }
 253
 254 static PCIBus *i440fx_common_init(const char *device_name,
 255                                   PCII440FXState **pi440fx_state,
 256                                   int *piix3_devfn,
 257                                   qemu_irq *pic,
 258                                   MemoryRegion *address_space_mem,
 259                                   MemoryRegion *address_space_io,
 260                                   ram_addr_t ram_size,
 261                                   target_phys_addr_t pci_hole_start,
 262                                   target_phys_addr_t pci_hole_size,
 263                                   target_phys_addr_t pci_hole64_start,
 264                                   target_phys_addr_t pci_hole64_size,
 265                                   MemoryRegion *pci_address_space,
 266                                   MemoryRegion *ram_memory)
 267 {
 268     DeviceState *dev;
 269     PCIBus *b;
 270     PCIDevice *d;
 271     I440FXState *s;
 272     PIIX3State *piix3;
 273     PCII440FXState *f;
 274
 275     dev = qdev_create(NULL, "i440FX-pcihost");
 276     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 277     s->address_space = address_space_mem;
 278     b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
 279                     address_space_io, 0);
 280     s->bus = b;
 281     qdev_init_nofail(dev);
 282
 283     d = pci_create_simple(b, 0, device_name);
 284     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 285     f = *pi440fx_state;
 286     f->system_memory = address_space_mem;
 287     f->pci_address_space = pci_address_space;
 288     f->ram_memory = ram_memory;
 289     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 290                              pci_hole_start, pci_hole_size);
 291     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 292     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 293                              f->pci_address_space,
 294                              pci_hole64_start, pci_hole64_size);
 295     if (pci_hole64_size) {
 296         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 297                                     &f->pci_hole_64bit);
 298     }
 299     memory_region_init_alias(&f->smram_region, "smram-region",
 300                              f->pci_address_space, 0xa0000, 0x20000);
 301     f->smram_enabled = true;
 302
 303     /* Xen supports additional interrupt routes from the PCI devices to
 304      * the IOAPIC: the four pins of each PCI device on the bus are also
 305      * connected to the IOAPIC directly.
 306      * These additional routes can be discovered through ACPI. */
 307     if (xen_enabled()) {
 308         piix3 = DO_UPCAST(PIIX3State, dev,
 309                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 310         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 311                 piix3, XEN_PIIX_NUM_PIRQS);
 312     } else {
 313         piix3 = DO_UPCAST(PIIX3State, dev,
 314                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 315         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 316                 PIIX_NUM_PIRQS);
 317     }
 318     piix3->pic = pic;
 319
 320     (*pi440fx_state)->piix3 = piix3;
 321
 322     *piix3_devfn = piix3->dev.devfn;
 323
 324     ram_size = ram_size / 8 / 1024 / 1024;
 325     if (ram_size > 255)
 326         ram_size = 255;
 327     (*pi440fx_state)->dev.config[0x57]=ram_size;
 328
 329     i440fx_update_memory_mappings(f);
 330
 331     return b;
 332 }
 333
 334 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 335                     qemu_irq *pic,
 336                     MemoryRegion *address_space_mem,
 337                     MemoryRegion *address_space_io,
 338                     ram_addr_t ram_size,
 339                     target_phys_addr_t pci_hole_start,
 340                     target_phys_addr_t pci_hole_size,
 341                     target_phys_addr_t pci_hole64_start,
 342                     target_phys_addr_t pci_hole64_size,
 343                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 344
 345 {
 346     PCIBus *b;
 347
 348     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
 349                            address_space_mem, address_space_io, ram_size,
 350                            pci_hole_start, pci_hole_size,
 351                            pci_hole64_size, pci_hole64_size,
 352                            pci_memory, ram_memory);
 353     return b;
 354 }
 355
 356 /* PIIX3 PCI to ISA bridge */
 357 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 358 {
 359     qemu_set_irq(piix3->pic[pic_irq],
 360                  !!(piix3->pic_levels &
 361                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 362                      (pic_irq * PIIX_NUM_PIRQS))));
 363 }
 364
 365 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 366 {
 367     int pic_irq;
 368     uint64_t mask;
 369
 370     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 371     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 372         return;
 373     }
 374
 375     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 376     piix3->pic_levels &= ~mask;
 377     piix3->pic_levels |= mask * !!level;
 378
 379     piix3_set_irq_pic(piix3, pic_irq);
 380 }
 381
 382 static void piix3_set_irq(void *opaque, int pirq, int level)
 383 {
 384     PIIX3State *piix3 = opaque;
 385     piix3_set_irq_level(piix3, pirq, level);
 386 }
 387
 388 /* irq routing is changed. so rebuild bitmap */
 389 static void piix3_update_irq_levels(PIIX3State *piix3)
 390 {
 391     int pirq;
 392
 393     piix3->pic_levels = 0;
 394     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 395         piix3_set_irq_level(piix3, pirq,
 396                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 397     }
 398 }
 399
 400 static void piix3_write_config(PCIDevice *dev,
 401                                uint32_t address, uint32_t val, int len)
 402 {
 403     pci_default_write_config(dev, address, val, len);
 404     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 405         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 406         int pic_irq;
 407         piix3_update_irq_levels(piix3);
 408         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 409             piix3_set_irq_pic(piix3, pic_irq);
 410         }
 411     }
 412 }
 413
 414 static void piix3_write_config_xen(PCIDevice *dev,
 415                                uint32_t address, uint32_t val, int len)
 416 {
 417     xen_piix_pci_write_config_client(address, val, len);
 418     piix3_write_config(dev, address, val, len);
 419 }
 420
 421 static void piix3_reset(void *opaque)
 422 {
 423     PIIX3State *d = opaque;
 424     uint8_t *pci_conf = d->dev.config;
 425
 426     pci_conf[0x04] = 0x07; // master, memory and I/O
 427     pci_conf[0x05] = 0x00;
 428     pci_conf[0x06] = 0x00;
 429     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 430     pci_conf[0x4c] = 0x4d;
 431     pci_conf[0x4e] = 0x03;
 432     pci_conf[0x4f] = 0x00;
 433     pci_conf[0x60] = 0x80;
 434     pci_conf[0x61] = 0x80;
 435     pci_conf[0x62] = 0x80;
 436     pci_conf[0x63] = 0x80;
 437     pci_conf[0x69] = 0x02;
 438     pci_conf[0x70] = 0x80;
 439     pci_conf[0x76] = 0x0c;
 440     pci_conf[0x77] = 0x0c;
 441     pci_conf[0x78] = 0x02;
 442     pci_conf[0x79] = 0x00;
 443     pci_conf[0x80] = 0x00;
 444     pci_conf[0x82] = 0x00;
 445     pci_conf[0xa0] = 0x08;
 446     pci_conf[0xa2] = 0x00;
 447     pci_conf[0xa3] = 0x00;
 448     pci_conf[0xa4] = 0x00;
 449     pci_conf[0xa5] = 0x00;
 450     pci_conf[0xa6] = 0x00;
 451     pci_conf[0xa7] = 0x00;
 452     pci_conf[0xa8] = 0x0f;
 453     pci_conf[0xaa] = 0x00;
 454     pci_conf[0xab] = 0x00;
 455     pci_conf[0xac] = 0x00;
 456     pci_conf[0xae] = 0x00;
 457
 458     d->pic_levels = 0;
 459 }
 460
 461 static int piix3_post_load(void *opaque, int version_id)
 462 {
 463     PIIX3State *piix3 = opaque;
 464     piix3_update_irq_levels(piix3);
 465     return 0;
 466 }
 467
 468 static void piix3_pre_save(void *opaque)
 469 {
 470     int i;
 471     PIIX3State *piix3 = opaque;
 472
 473     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 474         piix3->pci_irq_levels_vmstate[i] =
 475             pci_bus_get_irq_level(piix3->dev.bus, i);
 476     }
 477 }
 478
 479 static const VMStateDescription vmstate_piix3 = {
 480     .name = "PIIX3",
 481     .version_id = 3,
 482     .minimum_version_id = 2,
 483     .minimum_version_id_old = 2,
 484     .post_load = piix3_post_load,
 485     .pre_save = piix3_pre_save,
 486     .fields      = (VMStateField []) {
 487         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 488         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 489                               PIIX_NUM_PIRQS, 3),
 490         VMSTATE_END_OF_LIST()
 491     }
 492 };
 493
 494 static int piix3_initfn(PCIDevice *dev)
 495 {
 496     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 497
 498     isa_bus_new(&d->dev.qdev);
 499     qemu_register_reset(piix3_reset, d);
 500     return 0;
 501 }
 502
 503 static PCIDeviceInfo i440fx_info[] = {
 504     {
 505         .qdev.name    = "i440FX",
 506         .qdev.desc    = "Host bridge",
 507         .qdev.size    = sizeof(PCII440FXState),
 508         .qdev.vmsd    = &vmstate_i440fx,
 509         .qdev.no_user = 1,
 510         .no_hotplug   = 1,
 511         .init         = i440fx_initfn,
 512         .config_write = i440fx_write_config,
 513         .vendor_id    = PCI_VENDOR_ID_INTEL,
 514         .device_id    = PCI_DEVICE_ID_INTEL_82441,
 515         .revision     = 0x02,
 516         .class_id     = PCI_CLASS_BRIDGE_HOST,
 517     },{
 518         .qdev.name    = "PIIX3",
 519         .qdev.desc    = "ISA bridge",
 520         .qdev.size    = sizeof(PIIX3State),
 521         .qdev.vmsd    = &vmstate_piix3,
 522         .qdev.no_user = 1,
 523         .no_hotplug   = 1,
 524         .init         = piix3_initfn,
 525         .config_write = piix3_write_config,
 526         .vendor_id    = PCI_VENDOR_ID_INTEL,
 527         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 528         .class_id     = PCI_CLASS_BRIDGE_ISA,
 529     },{
 530         .qdev.name    = "PIIX3-xen",
 531         .qdev.desc    = "ISA bridge",
 532         .qdev.size    = sizeof(PIIX3State),
 533         .qdev.vmsd    = &vmstate_piix3,
 534         .qdev.no_user = 1,
 535         .no_hotplug   = 1,
 536         .init         = piix3_initfn,
 537         .config_write = piix3_write_config_xen,
 538         .vendor_id    = PCI_VENDOR_ID_INTEL,
 539         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 540         .class_id     = PCI_CLASS_BRIDGE_ISA,
 541     },{
 542         /* end of list */
 543     }
 544 };
 545
 546 static SysBusDeviceInfo i440fx_pcihost_info = {
 547     .init         = i440fx_pcihost_initfn,
 548     .qdev.name    = "i440FX-pcihost",
 549     .qdev.fw_name = "pci",
 550     .qdev.size    = sizeof(I440FXState),
 551     .qdev.no_user = 1,
 552 };
 553
 554 static void i440fx_register(void)
 555 {
 556     sysbus_register_withprop(&i440fx_pcihost_info);
 557     pci_qdev_register_many(i440fx_info);
 558 }
 559 device_init(i440fx_register);