[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci/pci.h"
#include "pci/pci_host.h"
#include "pci/pci_bridge.h"
#include "pci/pci_bus.h"
#include "apb_pci.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

#define MAX_IVEC 0x30

typedef struct APBState {
    SysBusDevice busdev;
    PCIBus      *bus;
    MemoryRegion apb_config;
    MemoryRegion pci_config;
    MemoryRegion pci_mmio;
    MemoryRegion pci_ioport;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq *pbm_irqs;
    qemu_irq *ivec_irqs;
    uint32_t reset_control;
    unsigned int nr_resets;
} APBState;

static void pci_apb_set_irq(void *opaque, int irq_num, int level);

static void apb_config_writel (void *opaque, hwaddr addr,
                               uint64_t val, unsigned size)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x1000 ... 0x1080: /* OBIO interrupt control */
        if (addr & 4) {
            s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
            s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x1400 ... 0x143f: /* PCI interrupt clear */
        if (addr & 4) {
            pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
        }
        break;
    case 0x1800 ... 0x1860: /* OBIO interrupt clear */
        if (addr & 4) {
            pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                s->nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint64_t apb_config_readl (void *opaque,
                                  hwaddr addr, unsigned size)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x1000 ... 0x1080: /* OBIO interrupt control */
        if (addr & 4) {
            val = s->obio_irq_map[(addr & 0xff) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static const MemoryRegionOps apb_config_ops = {
    .read = apb_config_readl,
    .write = apb_config_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void apb_pci_config_write(void *opaque, hwaddr addr,
                                 uint64_t val, unsigned size)
{
    APBState *s = opaque;

    val = qemu_bswap_len(val, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
    pci_data_write(s->bus, addr, val, size);
}

static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
                                    unsigned size)
{
    uint32_t ret;
    APBState *s = opaque;

    ret = pci_data_read(s->bus, addr, size);
    ret = qemu_bswap_len(ret, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void pci_apb_iowriteb (void *opaque, hwaddr addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, hwaddr addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, hwaddr addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static const MemoryRegionOps pci_ioport_ops = {
    .old_mmio = {
        .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
        .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->ivec_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->ivec_irqs[irq_num]);
        }
    } else {
        /* OBIO IRQ map onto the next 16 INO.  */
        if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->ivec_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->ivec_irqs[irq_num]);
        }
    }
}

static int apb_pci_bridge_initfn(PCIDevice *dev)
{
    int rc;

    rc = pci_bridge_initfn(dev);
    if (rc < 0) {
        return rc;
    }

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY);
    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

PCIBus *pci_apb_init(hwaddr special_base,
                     hwaddr mem_base,
                     qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
                     qemu_irq **pbm_irqs)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    PCIDevice *pci_dev;
    PCIBridge *br;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* PCI configuration space */
    sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
    d = FROM_SYSBUS(APBState, s);

    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);

    d->bus = pci_register_bus(&d->busdev.qdev, "pci",
                              pci_apb_set_irq, pci_pbm_map_irq, d,
                              &d->pci_mmio,
                              get_system_io(),
                              0, 32);

    *pbm_irqs = d->pbm_irqs;
    d->ivec_irqs = ivec_irqs;

    pci_create_simple(d->bus, 0, "pbm-pci");

    /* APB secondary busses */
    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus2 = pci_bridge_get_sec_bus(br);

    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus3 = pci_bridge_get_sec_bus(br);

    return d->bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }
    for (i = 0; i < 32; i++) {
        s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (s->nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static const MemoryRegionOps pci_config_ops = {
    .read = apb_pci_config_read,
    .write = apb_pci_config_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
    }
    s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);

    /* apb_config */
    memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
                          0x10000);
    /* at region 0 */
    sysbus_init_mmio(dev, &s->apb_config);

    memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
                          0x1000000);
    /* at region 1 */
    sysbus_init_mmio(dev, &s->pci_config);

    /* pci_ioport */
    memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
                          "apb-pci-ioport", 0x10000);
    /* at region 2 */
    sysbus_init_mmio(dev, &s->pci_ioport);

    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_set_word(d->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(d->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pbm_pci_host_init;
    k->vendor_id = PCI_VENDOR_ID_SUN;
    k->device_id = PCI_DEVICE_ID_SUN_SABRE;
    k->class_id = PCI_CLASS_BRIDGE_HOST;
}

static const TypeInfo pbm_pci_host_info = {
    .name          = "pbm-pci",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = pbm_pci_host_class_init,
};

static void pbm_host_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pci_pbm_init_device;
    dc->reset = pci_pbm_reset;
}

static const TypeInfo pbm_host_info = {
    .name          = "pbm",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(APBState),
    .class_init    = pbm_host_class_init,
};

static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = apb_pci_bridge_initfn;
    k->exit = pci_bridge_exitfn;
    k->vendor_id = PCI_VENDOR_ID_SUN;
    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
    k->revision = 0x11;
    k->config_write = pci_bridge_write_config;
    k->is_bridge = 1;
    dc->reset = pci_bridge_reset;
    dc->vmsd = &vmstate_pci_device;
}

static const TypeInfo pbm_pci_bridge_info = {
    .name          = "pbm-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIBridge),
    .class_init    = pbm_pci_bridge_class_init,
};

static void pbm_register_types(void)
{
    type_register_static(&pbm_host_info);
    type_register_static(&pbm_pci_host_info);
    type_register_static(&pbm_pci_bridge_info);
}

type_init(pbm_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
a2cb15b0 MT	30	#include "pci/pci.h"
	31	#include "pci/pci_host.h"
	32	#include "pci/pci_bridge.h"
06aac7bd	33	#include "pci/pci_bus.h"
18e08a55	34	#include "apb_pci.h"
9c17d615	35	#include "sysemu/sysemu.h"
022c62cb	36	#include "exec/address-spaces.h"
a94fd955 BS	37
	38	/* debug APB */
	39	//#define DEBUG_APB
	40
	41	#ifdef DEBUG_APB
001faf32 BS	42	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	43	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	44	#else
001faf32	45	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	46	#endif
a94fd955 BS	47
930f3fe1 BS	48	/*
	49	* Chipset docs:
	50	* PBM: "UltraSPARC IIi User's Manual",
	51	* http://www.sun.com/processors/manuals/805-0087.pdf
	52	*
	53	* APB: "Advanced PCI Bridge (APB) User's Manual",
	54	* http://www.sun.com/processors/manuals/805-1251.pdf
	55	*/
	56
95819af0 BS	57	#define PBM_PCI_IMR_MASK 0x7fffffff
	58	#define PBM_PCI_IMR_ENABLED 0x80000000
	59
	60	#define POR (1 << 31)
	61	#define SOFT_POR (1 << 30)
	62	#define SOFT_XIR (1 << 29)
	63	#define BTN_POR (1 << 28)
	64	#define BTN_XIR (1 << 27)
	65	#define RESET_MASK 0xf8000000
	66	#define RESET_WCMASK 0x98000000
	67	#define RESET_WMASK 0x60000000
	68
361dea40 BS	69	#define MAX_IVEC 0x30
361dea40 BS	70
72f44c8c BS	71	typedef struct APBState {
72f44c8c BS	72	SysBusDevice busdev;
d63baf92	73	PCIBus *bus;
3812ed0b AK	74	MemoryRegion apb_config;
3812ed0b AK	75	MemoryRegion pci_config;
f69539b1	76	MemoryRegion pci_mmio;
3812ed0b	77	MemoryRegion pci_ioport;
95819af0 BS	78	uint32_t iommu[4];
	79	uint32_t pci_control[16];
	80	uint32_t pci_irq_map[8];
	81	uint32_t obio_irq_map[32];
361dea40 BS	82	qemu_irq *pbm_irqs;
361dea40 BS	83	qemu_irq *ivec_irqs;
95819af0	84	uint32_t reset_control;
9c0afd0e	85	unsigned int nr_resets;
72f44c8c	86	} APBState;
502a5395	87
94d19914 AT	88	static void pci_apb_set_irq(void *opaque, int irq_num, int level);
94d19914 AT	89
a8170e5e	90	static void apb_config_writel (void *opaque, hwaddr addr,
3812ed0b	91	uint64_t val, unsigned size)
502a5395	92	{
95819af0 BS	93	APBState *s = opaque;
95819af0 BS	94
361dea40	95	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
95819af0 BS	96
	97	switch (addr & 0xffff) {
	98	case 0x30 ... 0x4f: /* DMA error registers */
	99	/* XXX: not implemented yet */
	100	break;
	101	case 0x200 ... 0x20b: /* IOMMU */
	102	s->iommu[(addr & 0xf) >> 2] = val;
	103	break;
	104	case 0x20c ... 0x3ff: /* IOMMU flush */
	105	break;
	106	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	107	if (addr & 4) {
	108	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	109	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	110	}
	111	break;
361dea40 BS	112	case 0x1000 ... 0x1080: /* OBIO interrupt control */
	113	if (addr & 4) {
	114	s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
	115	s->obio_irq_map[(addr & 0xff) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	116	}
	117	break;
94d19914 AT	118	case 0x1400 ... 0x143f: /* PCI interrupt clear */
	119	if (addr & 4) {
	120	pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
	121	}
	122	break;
	123	case 0x1800 ... 0x1860: /* OBIO interrupt clear */
	124	if (addr & 4) {
	125	pci_apb_set_irq(s, 0x20 \| ((addr & 0xff) >> 3), 0);
	126	}
	127	break;
95819af0 BS	128	case 0x2000 ... 0x202f: /* PCI control */
	129	s->pci_control[(addr & 0x3f) >> 2] = val;
	130	break;
	131	case 0xf020 ... 0xf027: /* Reset control */
	132	if (addr & 4) {
	133	val &= RESET_MASK;
	134	s->reset_control &= ~(val & RESET_WCMASK);
	135	s->reset_control \|= val & RESET_WMASK;
	136	if (val & SOFT_POR) {
9c0afd0e	137	s->nr_resets = 0;
95819af0 BS	138	qemu_system_reset_request();
	139	} else if (val & SOFT_XIR) {
	140	qemu_system_reset_request();
	141	}
	142	}
	143	break;
	144	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	145	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	146	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	147	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	148	/* we don't care */
502a5395	149	default:
f930d07e	150	break;
502a5395 PB	151	}
	152	}
	153
3812ed0b	154	static uint64_t apb_config_readl (void *opaque,
a8170e5e	155	hwaddr addr, unsigned size)
502a5395	156	{
95819af0	157	APBState *s = opaque;
502a5395 PB	158	uint32_t val;
502a5395 PB	159
95819af0 BS	160	switch (addr & 0xffff) {
	161	case 0x30 ... 0x4f: /* DMA error registers */
	162	val = 0;
	163	/* XXX: not implemented yet */
	164	break;
	165	case 0x200 ... 0x20b: /* IOMMU */
	166	val = s->iommu[(addr & 0xf) >> 2];
	167	break;
	168	case 0x20c ... 0x3ff: /* IOMMU flush */
	169	val = 0;
	170	break;
	171	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	172	if (addr & 4) {
	173	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	174	} else {
	175	val = 0;
	176	}
	177	break;
361dea40 BS	178	case 0x1000 ... 0x1080: /* OBIO interrupt control */
	179	if (addr & 4) {
	180	val = s->obio_irq_map[(addr & 0xff) >> 3];
	181	} else {
	182	val = 0;
	183	}
	184	break;
95819af0 BS	185	case 0x2000 ... 0x202f: /* PCI control */
	186	val = s->pci_control[(addr & 0x3f) >> 2];
	187	break;
	188	case 0xf020 ... 0xf027: /* Reset control */
	189	if (addr & 4) {
	190	val = s->reset_control;
	191	} else {
	192	val = 0;
	193	}
	194	break;
	195	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	196	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	197	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	198	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	199	/* we don't care */
502a5395	200	default:
f930d07e BS	201	val = 0;
f930d07e BS	202	break;
502a5395	203	}
95819af0 BS	204	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	205
502a5395 PB	206	return val;
	207	}
	208
3812ed0b AK	209	static const MemoryRegionOps apb_config_ops = {
	210	.read = apb_config_readl,
	211	.write = apb_config_writel,
	212	.endianness = DEVICE_NATIVE_ENDIAN,
502a5395 PB	213	};
502a5395 PB	214
a8170e5e	215	static void apb_pci_config_write(void *opaque, hwaddr addr,
3812ed0b	216	uint64_t val, unsigned size)
5a5d4a76	217	{
3812ed0b	218	APBState *s = opaque;
63e6f31d MT	219
63e6f31d MT	220	val = qemu_bswap_len(val, size);
361dea40	221	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
d63baf92	222	pci_data_write(s->bus, addr, val, size);
5a5d4a76 BS	223	}
5a5d4a76 BS	224
a8170e5e	225	static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
3812ed0b	226	unsigned size)
5a5d4a76 BS	227	{
5a5d4a76 BS	228	uint32_t ret;
3812ed0b	229	APBState *s = opaque;
5a5d4a76	230
d63baf92	231	ret = pci_data_read(s->bus, addr, size);
63e6f31d	232	ret = qemu_bswap_len(ret, size);
5a5d4a76 BS	233	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	234	return ret;
	235	}
	236
a8170e5e	237	static void pci_apb_iowriteb (void *opaque, hwaddr addr,
502a5395 PB	238	uint32_t val)
502a5395 PB	239	{
afcea8cb	240	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	241	}
502a5395 PB	242
a8170e5e	243	static void pci_apb_iowritew (void *opaque, hwaddr addr,
502a5395 PB	244	uint32_t val)
502a5395 PB	245	{
a4d5f62c	246	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	247	}
502a5395 PB	248
a8170e5e	249	static void pci_apb_iowritel (void *opaque, hwaddr addr,
502a5395 PB	250	uint32_t val)
502a5395 PB	251	{
a4d5f62c	252	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	253	}
502a5395 PB	254
a8170e5e	255	static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
502a5395 PB	256	{
	257	uint32_t val;
	258
afcea8cb	259	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	260	return val;
	261	}
	262
a8170e5e	263	static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
502a5395 PB	264	{
	265	uint32_t val;
	266
a4d5f62c	267	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	268	return val;
	269	}
	270
a8170e5e	271	static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
502a5395 PB	272	{
	273	uint32_t val;
	274
a4d5f62c	275	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	276	return val;
	277	}
	278
3812ed0b AK	279	static const MemoryRegionOps pci_ioport_ops = {
	280	.old_mmio = {
	281	.read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
	282	.write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
	283	},
	284	.endianness = DEVICE_NATIVE_ENDIAN,
502a5395 PB	285	};
502a5395 PB	286
80b3ada7	287	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	288	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	289	{
80b3ada7 PB	290	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	291	}
	292
	293	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	294	{
	295	int bus_offset;
	296	if (pci_dev->devfn & 1)
	297	bus_offset = 16;
	298	else
	299	bus_offset = 0;
	300	return bus_offset + irq_num;
d2b59317 PB	301	}
d2b59317 PB	302
5d4e84c8	303	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	304	{
95819af0	305	APBState *s = opaque;
5d4e84c8	306
80b3ada7	307	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	308	if (irq_num < 32) {
	309	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	310	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
361dea40 BS	311	qemu_set_irq(s->ivec_irqs[irq_num], level);
	312	} else {
	313	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	314	qemu_irq_lower(s->ivec_irqs[irq_num]);
	315	}
	316	} else {
	317	/* OBIO IRQ map onto the next 16 INO. */
	318	if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
	319	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	320	qemu_set_irq(s->ivec_irqs[irq_num], level);
95819af0 BS	321	} else {
95819af0 BS	322	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
361dea40	323	qemu_irq_lower(s->ivec_irqs[irq_num]);
95819af0 BS	324	}
95819af0 BS	325	}
502a5395 PB	326	}
502a5395 PB	327
68f79994	328	static int apb_pci_bridge_initfn(PCIDevice *dev)
d6318738	329	{
68f79994 IY	330	int rc;
	331
	332	rc = pci_bridge_initfn(dev);
	333	if (rc < 0) {
	334	return rc;
	335	}
	336
d6318738 MT	337	/*
	338	* command register:
	339	* According to PCI bridge spec, after reset
	340	* bus master bit is off
	341	* memory space enable bit is off
	342	* According to manual (805-1251.pdf).
	343	* the reset value should be zero unless the boot pin is tied high
	344	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	345	*/
	346	pci_set_word(dev->config + PCI_COMMAND,
9fe52c7f BS	347	PCI_COMMAND_MEMORY);
	348	pci_set_word(dev->config + PCI_STATUS,
	349	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	350	PCI_STATUS_DEVSEL_MEDIUM);
68f79994	351	return 0;
d6318738 MT	352	}
d6318738 MT	353
a8170e5e AK	354	PCIBus *pci_apb_init(hwaddr special_base,
a8170e5e AK	355	hwaddr mem_base,
361dea40 BS	356	qemu_irq ivec_irqs, PCIBus bus2, PCIBus *bus3,
361dea40 BS	357	qemu_irq **pbm_irqs)
502a5395	358	{
72f44c8c BS	359	DeviceState *dev;
	360	SysBusDevice *s;
	361	APBState *d;
68f79994 IY	362	PCIDevice *pci_dev;
68f79994 IY	363	PCIBridge *br;
502a5395	364
80b3ada7	365	/* Ultrasparc PBM main bus */
72f44c8c	366	dev = qdev_create(NULL, "pbm");
e23a1b33	367	qdev_init_nofail(dev);
72f44c8c BS	368	s = sysbus_from_qdev(dev);
72f44c8c BS	369	/* apb_config */
bae7b517	370	sysbus_mmio_map(s, 0, special_base);
d63baf92 IK	371	/* PCI configuration space */
d63baf92 IK	372	sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
72f44c8c	373	/* pci_ioport */
d63baf92	374	sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
72f44c8c	375	d = FROM_SYSBUS(APBState, s);
d63baf92	376
f69539b1 BS	377	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	378	memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
	379
d63baf92	380	d->bus = pci_register_bus(&d->busdev.qdev, "pci",
f69539b1 BS	381	pci_apb_set_irq, pci_pbm_map_irq, d,
	382	&d->pci_mmio,
	383	get_system_io(),
	384	0, 32);
f6b6f1bc	385
361dea40 BS	386	*pbm_irqs = d->pbm_irqs;
361dea40 BS	387	d->ivec_irqs = ivec_irqs;
95819af0	388
73093354	389	pci_create_simple(d->bus, 0, "pbm-pci");
d63baf92	390
72f44c8c	391	/* APB secondary busses */
68f79994 IY	392	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
	393	"pbm-bridge");
	394	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	395	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
	396	pci_apb_map_irq);
	397	qdev_init_nofail(&pci_dev->qdev);
	398	*bus2 = pci_bridge_get_sec_bus(br);
	399
	400	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
	401	"pbm-bridge");
	402	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	403	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
	404	pci_apb_map_irq);
	405	qdev_init_nofail(&pci_dev->qdev);
	406	*bus3 = pci_bridge_get_sec_bus(br);
502a5395	407
d63baf92	408	return d->bus;
72f44c8c BS	409	}
72f44c8c BS	410
95819af0	411	static void pci_pbm_reset(DeviceState *d)
72f44c8c	412	{
95819af0 BS	413	unsigned int i;
95819af0 BS	414	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	415
95819af0 BS	416	for (i = 0; i < 8; i++) {
	417	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	418	}
d1d80055 AT	419	for (i = 0; i < 32; i++) {
	420	s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
	421	}
95819af0	422
9c0afd0e	423	if (s->nr_resets++ == 0) {
95819af0 BS	424	/* Power on reset */
	425	s->reset_control = POR;
	426	}
	427	}
	428
3812ed0b AK	429	static const MemoryRegionOps pci_config_ops = {
	430	.read = apb_pci_config_read,
	431	.write = apb_pci_config_write,
	432	.endianness = DEVICE_NATIVE_ENDIAN,
	433	};
	434
95819af0 BS	435	static int pci_pbm_init_device(SysBusDevice *dev)
95819af0 BS	436	{
72f44c8c	437	APBState *s;
95819af0	438	unsigned int i;
72f44c8c BS	439
72f44c8c BS	440	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	441	for (i = 0; i < 8; i++) {
	442	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	443	}
d1d80055 AT	444	for (i = 0; i < 32; i++) {
	445	s->obio_irq_map[i] = ((0x1f << 6) \| 0x20) + i;
	446	}
361dea40	447	s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
95819af0	448
72f44c8c	449	/* apb_config */
3812ed0b AK	450	memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
3812ed0b AK	451	0x10000);
d63baf92	452	/* at region 0 */
750ecd44	453	sysbus_init_mmio(dev, &s->apb_config);
d63baf92	454
3812ed0b AK	455	memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
3812ed0b AK	456	0x1000000);
d63baf92	457	/* at region 1 */
750ecd44	458	sysbus_init_mmio(dev, &s->pci_config);
d63baf92 IK	459
d63baf92 IK	460	/* pci_ioport */
3812ed0b AK	461	memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
3812ed0b AK	462	"apb-pci-ioport", 0x10000);
d63baf92	463	/* at region 2 */
750ecd44	464	sysbus_init_mmio(dev, &s->pci_ioport);
d63baf92	465
81a322d4	466	return 0;
72f44c8c	467	}
502a5395	468
81a322d4	469	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	470	{
9fe52c7f BS	471	pci_set_word(d->config + PCI_COMMAND,
	472	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	473	pci_set_word(d->config + PCI_STATUS,
	474	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	475	PCI_STATUS_DEVSEL_MEDIUM);
81a322d4	476	return 0;
72f44c8c	477	}
80b3ada7	478
40021f08 AL	479	static void pbm_pci_host_class_init(ObjectClass klass, void data)
	480	{
	481	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	482
	483	k->init = pbm_pci_host_init;
	484	k->vendor_id = PCI_VENDOR_ID_SUN;
	485	k->device_id = PCI_DEVICE_ID_SUN_SABRE;
	486	k->class_id = PCI_CLASS_BRIDGE_HOST;
40021f08 AL	487	}
40021f08 AL	488
8c43a6f0	489	static const TypeInfo pbm_pci_host_info = {
39bffca2 AL	490	.name = "pbm-pci",
	491	.parent = TYPE_PCI_DEVICE,
	492	.instance_size = sizeof(PCIDevice),
	493	.class_init = pbm_pci_host_class_init,
72f44c8c BS	494	};
72f44c8c BS	495
999e12bb AL	496	static void pbm_host_class_init(ObjectClass klass, void data)
999e12bb AL	497	{
39bffca2	498	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	499	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	500
	501	k->init = pci_pbm_init_device;
39bffca2	502	dc->reset = pci_pbm_reset;
999e12bb AL	503	}
999e12bb AL	504
8c43a6f0	505	static const TypeInfo pbm_host_info = {
39bffca2 AL	506	.name = "pbm",
	507	.parent = TYPE_SYS_BUS_DEVICE,
	508	.instance_size = sizeof(APBState),
	509	.class_init = pbm_host_class_init,
95819af0	510	};
68f79994	511
40021f08 AL	512	static void pbm_pci_bridge_class_init(ObjectClass klass, void data)
40021f08 AL	513	{
39bffca2	514	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	515	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	516
	517	k->init = apb_pci_bridge_initfn;
	518	k->exit = pci_bridge_exitfn;
	519	k->vendor_id = PCI_VENDOR_ID_SUN;
	520	k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
	521	k->revision = 0x11;
	522	k->config_write = pci_bridge_write_config;
	523	k->is_bridge = 1;
39bffca2 AL	524	dc->reset = pci_bridge_reset;
39bffca2 AL	525	dc->vmsd = &vmstate_pci_device;
40021f08 AL	526	}
40021f08 AL	527
8c43a6f0	528	static const TypeInfo pbm_pci_bridge_info = {
39bffca2 AL	529	.name = "pbm-bridge",
	530	.parent = TYPE_PCI_DEVICE,
	531	.instance_size = sizeof(PCIBridge),
	532	.class_init = pbm_pci_bridge_class_init,
68f79994 IY	533	};
68f79994 IY	534
83f7d43a	535	static void pbm_register_types(void)
72f44c8c	536	{
39bffca2 AL	537	type_register_static(&pbm_host_info);
	538	type_register_static(&pbm_pci_host_info);
	539	type_register_static(&pbm_pci_bridge_info);
502a5395	540	}
72f44c8c	541
83f7d43a	542	type_init(pbm_register_types)