[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
#include "apb_pci.h"
#include "sysemu.h"
#include "exec-memory.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

typedef struct APBState {
    SysBusDevice busdev;
    PCIBus      *bus;
    MemoryRegion apb_config;
    MemoryRegion pci_config;
    MemoryRegion pci_mmio;
    MemoryRegion pci_ioport;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq pci_irqs[32];
    uint32_t reset_control;
    unsigned int nr_resets;
} APBState;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint64_t val, unsigned size)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                s->nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint64_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr, unsigned size)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static const MemoryRegionOps apb_config_ops = {
    .read = apb_config_readl,
    .write = apb_config_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
                                 uint64_t val, unsigned size)
{
    APBState *s = opaque;

    val = qemu_bswap_len(val, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->bus, addr, val, size);
}

static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
                                    unsigned size)
{
    uint32_t ret;
    APBState *s = opaque;

    ret = pci_data_read(s->bus, addr, size);
    ret = qemu_bswap_len(ret, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static const MemoryRegionOps pci_ioport_ops = {
    .old_mmio = {
        .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
        .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->pci_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->pci_irqs[irq_num]);
        }
    }
}

static int apb_pci_bridge_initfn(PCIDevice *dev)
{
    int rc;

    rc = pci_bridge_initfn(dev);
    if (rc < 0) {
        return rc;
    }

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY);
    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    unsigned int i;
    PCIDevice *pci_dev;
    PCIBridge *br;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* PCI configuration space */
    sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
    d = FROM_SYSBUS(APBState, s);

    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);

    d->bus = pci_register_bus(&d->busdev.qdev, "pci",
                              pci_apb_set_irq, pci_pbm_map_irq, d,
                              &d->pci_mmio,
                              get_system_io(),
                              0, 32);

    for (i = 0; i < 32; i++) {
        sysbus_connect_irq(s, i, pic[i]);
    }

    pci_create_simple(d->bus, 0, "pbm");

    /* APB secondary busses */
    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus2 = pci_bridge_get_sec_bus(br);

    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus3 = pci_bridge_get_sec_bus(br);

    return d->bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (s->nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static const MemoryRegionOps pci_config_ops = {
    .read = apb_pci_config_read,
    .write = apb_pci_config_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->pci_irqs[i]);
    }

    /* apb_config */
    memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
                          0x10000);
    /* at region 0 */
    sysbus_init_mmio(dev, &s->apb_config);

    memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
                          0x1000000);
    /* at region 1 */
    sysbus_init_mmio(dev, &s->pci_config);

    /* pci_ioport */
    memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
                          "apb-pci-ioport", 0x10000);
    /* at region 2 */
    sysbus_init_mmio(dev, &s->pci_ioport);

    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_set_word(d->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(d->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SABRE,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
    .is_bridge = 1,
};

static SysBusDeviceInfo pbm_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(APBState),
    .qdev.reset = pci_pbm_reset,
    .init = pci_pbm_init_device,
};

static PCIDeviceInfo pbm_pci_bridge_info = {
    .qdev.name = "pbm-bridge",
    .qdev.size = sizeof(PCIBridge),
    .qdev.vmsd = &vmstate_pci_device,
    .qdev.reset = pci_bridge_reset,
    .init = apb_pci_bridge_initfn,
    .exit = pci_bridge_exitfn,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SIMBA,
    .revision = 0x11,
    .config_write = pci_bridge_write_config,
    .is_bridge = 1,
};

static void pbm_register_devices(void)
{
    sysbus_register_withprop(&pbm_host_info);
    pci_qdev_register(&pbm_pci_host_info);
    pci_qdev_register(&pbm_pci_bridge_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
783753fd	32	#include "pci_bridge.h"
68f79994	33	#include "pci_internals.h"
18e08a55	34	#include "apb_pci.h"
666daa68	35	#include "sysemu.h"
1e39101c	36	#include "exec-memory.h"
a94fd955 BS	37
	38	/* debug APB */
	39	//#define DEBUG_APB
	40
	41	#ifdef DEBUG_APB
001faf32 BS	42	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	43	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	44	#else
001faf32	45	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	46	#endif
a94fd955 BS	47
930f3fe1 BS	48	/*
	49	* Chipset docs:
	50	* PBM: "UltraSPARC IIi User's Manual",
	51	* http://www.sun.com/processors/manuals/805-0087.pdf
	52	*
	53	* APB: "Advanced PCI Bridge (APB) User's Manual",
	54	* http://www.sun.com/processors/manuals/805-1251.pdf
	55	*/
	56
95819af0 BS	57	#define PBM_PCI_IMR_MASK 0x7fffffff
	58	#define PBM_PCI_IMR_ENABLED 0x80000000
	59
	60	#define POR (1 << 31)
	61	#define SOFT_POR (1 << 30)
	62	#define SOFT_XIR (1 << 29)
	63	#define BTN_POR (1 << 28)
	64	#define BTN_XIR (1 << 27)
	65	#define RESET_MASK 0xf8000000
	66	#define RESET_WCMASK 0x98000000
	67	#define RESET_WMASK 0x60000000
	68
72f44c8c BS	69	typedef struct APBState {
72f44c8c BS	70	SysBusDevice busdev;
d63baf92	71	PCIBus *bus;
3812ed0b AK	72	MemoryRegion apb_config;
3812ed0b AK	73	MemoryRegion pci_config;
f69539b1	74	MemoryRegion pci_mmio;
3812ed0b	75	MemoryRegion pci_ioport;
95819af0 BS	76	uint32_t iommu[4];
	77	uint32_t pci_control[16];
	78	uint32_t pci_irq_map[8];
	79	uint32_t obio_irq_map[32];
	80	qemu_irq pci_irqs[32];
	81	uint32_t reset_control;
9c0afd0e	82	unsigned int nr_resets;
72f44c8c	83	} APBState;
502a5395	84
c227f099	85	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
3812ed0b	86	uint64_t val, unsigned size)
502a5395	87	{
95819af0 BS	88	APBState *s = opaque;
	89
	90	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	91
	92	switch (addr & 0xffff) {
	93	case 0x30 ... 0x4f: /* DMA error registers */
	94	/* XXX: not implemented yet */
	95	break;
	96	case 0x200 ... 0x20b: /* IOMMU */
	97	s->iommu[(addr & 0xf) >> 2] = val;
	98	break;
	99	case 0x20c ... 0x3ff: /* IOMMU flush */
	100	break;
	101	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	102	if (addr & 4) {
	103	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	104	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	105	}
	106	break;
	107	case 0x2000 ... 0x202f: /* PCI control */
	108	s->pci_control[(addr & 0x3f) >> 2] = val;
	109	break;
	110	case 0xf020 ... 0xf027: /* Reset control */
	111	if (addr & 4) {
	112	val &= RESET_MASK;
	113	s->reset_control &= ~(val & RESET_WCMASK);
	114	s->reset_control \|= val & RESET_WMASK;
	115	if (val & SOFT_POR) {
9c0afd0e	116	s->nr_resets = 0;
95819af0 BS	117	qemu_system_reset_request();
	118	} else if (val & SOFT_XIR) {
	119	qemu_system_reset_request();
	120	}
	121	}
	122	break;
	123	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	124	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	125	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	126	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	127	/* we don't care */
502a5395	128	default:
f930d07e	129	break;
502a5395 PB	130	}
	131	}
	132
3812ed0b AK	133	static uint64_t apb_config_readl (void *opaque,
3812ed0b AK	134	target_phys_addr_t addr, unsigned size)
502a5395	135	{
95819af0	136	APBState *s = opaque;
502a5395 PB	137	uint32_t val;
502a5395 PB	138
95819af0 BS	139	switch (addr & 0xffff) {
	140	case 0x30 ... 0x4f: /* DMA error registers */
	141	val = 0;
	142	/* XXX: not implemented yet */
	143	break;
	144	case 0x200 ... 0x20b: /* IOMMU */
	145	val = s->iommu[(addr & 0xf) >> 2];
	146	break;
	147	case 0x20c ... 0x3ff: /* IOMMU flush */
	148	val = 0;
	149	break;
	150	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	151	if (addr & 4) {
	152	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	153	} else {
	154	val = 0;
	155	}
	156	break;
	157	case 0x2000 ... 0x202f: /* PCI control */
	158	val = s->pci_control[(addr & 0x3f) >> 2];
	159	break;
	160	case 0xf020 ... 0xf027: /* Reset control */
	161	if (addr & 4) {
	162	val = s->reset_control;
	163	} else {
	164	val = 0;
	165	}
	166	break;
	167	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	168	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	169	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	170	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	171	/* we don't care */
502a5395	172	default:
f930d07e BS	173	val = 0;
f930d07e BS	174	break;
502a5395	175	}
95819af0 BS	176	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	177
502a5395 PB	178	return val;
	179	}
	180
3812ed0b AK	181	static const MemoryRegionOps apb_config_ops = {
	182	.read = apb_config_readl,
	183	.write = apb_config_writel,
	184	.endianness = DEVICE_NATIVE_ENDIAN,
502a5395 PB	185	};
502a5395 PB	186
3812ed0b AK	187	static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
3812ed0b AK	188	uint64_t val, unsigned size)
5a5d4a76	189	{
3812ed0b	190	APBState *s = opaque;
63e6f31d MT	191
63e6f31d MT	192	val = qemu_bswap_len(val, size);
5a5d4a76	193	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
d63baf92	194	pci_data_write(s->bus, addr, val, size);
5a5d4a76 BS	195	}
5a5d4a76 BS	196
3812ed0b AK	197	static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
3812ed0b AK	198	unsigned size)
5a5d4a76 BS	199	{
5a5d4a76 BS	200	uint32_t ret;
3812ed0b	201	APBState *s = opaque;
5a5d4a76	202
d63baf92	203	ret = pci_data_read(s->bus, addr, size);
63e6f31d	204	ret = qemu_bswap_len(ret, size);
5a5d4a76 BS	205	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	206	return ret;
	207	}
	208
c227f099	209	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	210	uint32_t val)
502a5395 PB	211	{
afcea8cb	212	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	213	}
502a5395 PB	214
c227f099	215	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	216	uint32_t val)
502a5395 PB	217	{
a4d5f62c	218	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	219	}
502a5395 PB	220
c227f099	221	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	222	uint32_t val)
502a5395 PB	223	{
a4d5f62c	224	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	225	}
502a5395 PB	226
c227f099	227	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	228	{
	229	uint32_t val;
	230
afcea8cb	231	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	232	return val;
	233	}
	234
c227f099	235	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	236	{
	237	uint32_t val;
	238
a4d5f62c	239	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	240	return val;
	241	}
	242
c227f099	243	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	244	{
	245	uint32_t val;
	246
a4d5f62c	247	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	248	return val;
	249	}
	250
3812ed0b AK	251	static const MemoryRegionOps pci_ioport_ops = {
	252	.old_mmio = {
	253	.read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
	254	.write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
	255	},
	256	.endianness = DEVICE_NATIVE_ENDIAN,
502a5395 PB	257	};
502a5395 PB	258
80b3ada7	259	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	260	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	261	{
80b3ada7 PB	262	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	263	}
	264
	265	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	266	{
	267	int bus_offset;
	268	if (pci_dev->devfn & 1)
	269	bus_offset = 16;
	270	else
	271	bus_offset = 0;
	272	return bus_offset + irq_num;
d2b59317 PB	273	}
d2b59317 PB	274
5d4e84c8	275	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	276	{
95819af0	277	APBState *s = opaque;
5d4e84c8	278
80b3ada7	279	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	280	if (irq_num < 32) {
	281	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	282	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	283	qemu_set_irq(s->pci_irqs[irq_num], level);
	284	} else {
	285	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	286	qemu_irq_lower(s->pci_irqs[irq_num]);
	287	}
	288	}
502a5395 PB	289	}
502a5395 PB	290
68f79994	291	static int apb_pci_bridge_initfn(PCIDevice *dev)
d6318738	292	{
68f79994 IY	293	int rc;
	294
	295	rc = pci_bridge_initfn(dev);
	296	if (rc < 0) {
	297	return rc;
	298	}
	299
d6318738 MT	300	/*
	301	* command register:
	302	* According to PCI bridge spec, after reset
	303	* bus master bit is off
	304	* memory space enable bit is off
	305	* According to manual (805-1251.pdf).
	306	* the reset value should be zero unless the boot pin is tied high
	307	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	308	*/
	309	pci_set_word(dev->config + PCI_COMMAND,
9fe52c7f BS	310	PCI_COMMAND_MEMORY);
	311	pci_set_word(dev->config + PCI_STATUS,
	312	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	313	PCI_STATUS_DEVSEL_MEDIUM);
68f79994	314	return 0;
d6318738 MT	315	}
d6318738 MT	316
c227f099 AL	317	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	318	target_phys_addr_t mem_base,
c190ea07	319	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	320	{
72f44c8c BS	321	DeviceState *dev;
	322	SysBusDevice *s;
	323	APBState *d;
95819af0	324	unsigned int i;
68f79994 IY	325	PCIDevice *pci_dev;
68f79994 IY	326	PCIBridge *br;
502a5395	327
80b3ada7	328	/* Ultrasparc PBM main bus */
72f44c8c	329	dev = qdev_create(NULL, "pbm");
e23a1b33	330	qdev_init_nofail(dev);
72f44c8c BS	331	s = sysbus_from_qdev(dev);
72f44c8c BS	332	/* apb_config */
bae7b517	333	sysbus_mmio_map(s, 0, special_base);
d63baf92 IK	334	/* PCI configuration space */
d63baf92 IK	335	sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
72f44c8c	336	/* pci_ioport */
d63baf92	337	sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
72f44c8c	338	d = FROM_SYSBUS(APBState, s);
d63baf92	339
f69539b1 BS	340	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	341	memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
	342
d63baf92	343	d->bus = pci_register_bus(&d->busdev.qdev, "pci",
f69539b1 BS	344	pci_apb_set_irq, pci_pbm_map_irq, d,
	345	&d->pci_mmio,
	346	get_system_io(),
	347	0, 32);
f6b6f1bc	348
95819af0 BS	349	for (i = 0; i < 32; i++) {
	350	sysbus_connect_irq(s, i, pic[i]);
	351	}
	352
d63baf92 IK	353	pci_create_simple(d->bus, 0, "pbm");
d63baf92 IK	354
72f44c8c	355	/* APB secondary busses */
68f79994 IY	356	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
	357	"pbm-bridge");
	358	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	359	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
	360	pci_apb_map_irq);
	361	qdev_init_nofail(&pci_dev->qdev);
	362	*bus2 = pci_bridge_get_sec_bus(br);
	363
	364	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
	365	"pbm-bridge");
	366	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	367	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
	368	pci_apb_map_irq);
	369	qdev_init_nofail(&pci_dev->qdev);
	370	*bus3 = pci_bridge_get_sec_bus(br);
502a5395	371
d63baf92	372	return d->bus;
72f44c8c BS	373	}
72f44c8c BS	374
95819af0	375	static void pci_pbm_reset(DeviceState *d)
72f44c8c	376	{
95819af0 BS	377	unsigned int i;
95819af0 BS	378	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	379
95819af0 BS	380	for (i = 0; i < 8; i++) {
	381	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	382	}
	383
9c0afd0e	384	if (s->nr_resets++ == 0) {
95819af0 BS	385	/* Power on reset */
	386	s->reset_control = POR;
	387	}
	388	}
	389
3812ed0b AK	390	static const MemoryRegionOps pci_config_ops = {
	391	.read = apb_pci_config_read,
	392	.write = apb_pci_config_write,
	393	.endianness = DEVICE_NATIVE_ENDIAN,
	394	};
	395
95819af0 BS	396	static int pci_pbm_init_device(SysBusDevice *dev)
95819af0 BS	397	{
72f44c8c	398	APBState *s;
95819af0	399	unsigned int i;
72f44c8c BS	400
72f44c8c BS	401	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	402	for (i = 0; i < 8; i++) {
	403	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	404	}
	405	for (i = 0; i < 32; i++) {
	406	sysbus_init_irq(dev, &s->pci_irqs[i]);
	407	}
	408
72f44c8c	409	/* apb_config */
3812ed0b AK	410	memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
3812ed0b AK	411	0x10000);
d63baf92	412	/* at region 0 */
750ecd44	413	sysbus_init_mmio(dev, &s->apb_config);
d63baf92	414
3812ed0b AK	415	memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
3812ed0b AK	416	0x1000000);
d63baf92	417	/* at region 1 */
750ecd44	418	sysbus_init_mmio(dev, &s->pci_config);
d63baf92 IK	419
d63baf92 IK	420	/* pci_ioport */
3812ed0b AK	421	memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
3812ed0b AK	422	"apb-pci-ioport", 0x10000);
d63baf92	423	/* at region 2 */
750ecd44	424	sysbus_init_mmio(dev, &s->pci_ioport);
d63baf92	425
81a322d4	426	return 0;
72f44c8c	427	}
502a5395	428
81a322d4	429	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	430	{
9fe52c7f BS	431	pci_set_word(d->config + PCI_COMMAND,
	432	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	433	pci_set_word(d->config + PCI_STATUS,
	434	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	435	PCI_STATUS_DEVSEL_MEDIUM);
81a322d4	436	return 0;
72f44c8c	437	}
80b3ada7	438
72f44c8c BS	439	static PCIDeviceInfo pbm_pci_host_info = {
	440	.qdev.name = "pbm",
	441	.qdev.size = sizeof(PCIDevice),
	442	.init = pbm_pci_host_init,
92f9a4f1 IY	443	.vendor_id = PCI_VENDOR_ID_SUN,
	444	.device_id = PCI_DEVICE_ID_SUN_SABRE,
	445	.class_id = PCI_CLASS_BRIDGE_HOST,
e327e323	446	.is_bridge = 1,
72f44c8c BS	447	};
72f44c8c BS	448
95819af0 BS	449	static SysBusDeviceInfo pbm_host_info = {
	450	.qdev.name = "pbm",
	451	.qdev.size = sizeof(APBState),
	452	.qdev.reset = pci_pbm_reset,
	453	.init = pci_pbm_init_device,
	454	};
68f79994 IY	455
	456	static PCIDeviceInfo pbm_pci_bridge_info = {
	457	.qdev.name = "pbm-bridge",
	458	.qdev.size = sizeof(PCIBridge),
	459	.qdev.vmsd = &vmstate_pci_device,
	460	.qdev.reset = pci_bridge_reset,
	461	.init = apb_pci_bridge_initfn,
	462	.exit = pci_bridge_exitfn,
92f9a4f1 IY	463	.vendor_id = PCI_VENDOR_ID_SUN,
	464	.device_id = PCI_DEVICE_ID_SUN_SIMBA,
	465	.revision = 0x11,
68f79994 IY	466	.config_write = pci_bridge_write_config,
	467	.is_bridge = 1,
	468	};
	469
72f44c8c BS	470	static void pbm_register_devices(void)
72f44c8c BS	471	{
95819af0	472	sysbus_register_withprop(&pbm_host_info);
72f44c8c	473	pci_qdev_register(&pbm_pci_host_info);
68f79994	474	pci_qdev_register(&pbm_pci_bridge_info);
502a5395	475	}
72f44c8c BS	476
72f44c8c BS	477	device_init(pbm_register_devices)