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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
9a78eead 23#include "qemu-common.h"
3fc6c082 24
a4f30719
JM		 25//#define PPC_EMULATE_32BITS_HYPV
26
76a66253 27#if defined (TARGET_PPC64)
3cd7d1dd 28/* PowerPC 64 definitions */
d9d7210c 29#define TARGET_LONG_BITS 64
35cdaad6 30#define TARGET_PAGE_BITS 12
3cd7d1dd 31
52705890
RH		 32/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
ad3e67d0 46#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 47#define TARGET_PAGE_BITS_16M 24
48
3cd7d1dd
JM		 49#else /* defined (TARGET_PPC64) */
50/* PowerPC 32 definitions */
d9d7210c 51#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 52
53#if defined(TARGET_PPCEMB)
54/* Specific definitions for PowerPC embedded */
55/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 56#if defined(CONFIG_USER_ONLY)
57/* It looks like a lot of Linux programs assume page size
58 * is 4kB long. This is evil, but we have to deal with it...
59 */
35cdaad6 60#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 61#else /* defined(CONFIG_USER_ONLY) */
62/* Pages can be 1 kB small */
63#define TARGET_PAGE_BITS 10
64#endif /* defined(CONFIG_USER_ONLY) */
65#else /* defined(TARGET_PPCEMB) */
66/* "standard" PowerPC 32 definitions */
67#define TARGET_PAGE_BITS 12
68#endif /* defined(TARGET_PPCEMB) */
69
8b242eba 70#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 71#define TARGET_VIRT_ADDR_SPACE_BITS 32
72
3cd7d1dd 73#endif /* defined (TARGET_PPC64) */
3cf1e035 74
9349b4f9 75#define CPUArchState struct CPUPPCState
c2764719 76
022c62cb 77#include "exec/cpu-defs.h"
2d34fe39 78#include "cpu-qom.h"
6b4c305c 79#include "fpu/softfloat.h"
4ecc3190 80
7f70c937 81#if defined (TARGET_PPC64)
4ecd4d16 82#define PPC_ELF_MACHINE EM_PPC64
76a66253 83#else
4ecd4d16 84#define PPC_ELF_MACHINE EM_PPC
76a66253 85#endif
9042c0e2 86
e1833e1f
JM		 87/*****************************************************************************/
88/* Exception vectors definitions */
89enum {
90 POWERPC_EXCP_NONE = -1,
91 /* The 64 first entries are used by the PowerPC embedded specification */
92 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
93 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
94 POWERPC_EXCP_DSI = 2, /* Data storage exception */
95 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
96 POWERPC_EXCP_EXTERNAL = 4, /* External input */
97 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
98 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
99 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
100 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
101 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
102 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
103 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
104 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 105 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
106 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 107 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
108 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 109 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
110 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
111 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
112 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
113 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
114 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 115 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
116 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
117 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
118 /* Vectors 42 to 63 are reserved */
e1833e1f 119 /* Exceptions defined in the PowerPC server specification */
f03a1af5
BH		 120 /* Server doorbell variants */
121#define POWERPC_EXCP_SDOOR POWERPC_EXCP_GDOORI
122#define POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_DOORI
e1833e1f 123 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 124 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
125 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 126 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 127 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 128 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
129 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
130 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
131 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 132 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
133 /* 40x specific exceptions */
134 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
135 /* 601 specific exceptions */
136 POWERPC_EXCP_IO = 75, /* IO error exception */
137 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
138 /* 602 specific exceptions */
139 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
140 /* 602/603 specific exceptions */
b4095fed 141 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 142 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
143 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
144 /* Exceptions available on most PowerPC */
145 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 146 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
147 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
148 POWERPC_EXCP_SMI = 84, /* System management interrupt */
149 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 150 /* 7xx/74xx specific exceptions */
b4095fed 151 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 152 /* 74xx specific exceptions */
b4095fed 153 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 154 /* 970FX specific exceptions */
b4095fed
JM		 155 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
156 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 157 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 158 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
159 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
160 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
161 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 162 /* VSX Unavailable (Power ISA 2.06 and later) */
163 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 164 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 165 /* Additional ISA 2.06 and later server exceptions */
166 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
167 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
168 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
e1833e1f 169 /* EOL */
f03a1af5 170 POWERPC_EXCP_NB = 99,
5cbdb3a3 171 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 172 POWERPC_EXCP_STOP = 0x200, /* stop translation */
173 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 174 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 175 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
176 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 177 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 178};
179
e1833e1f
JM		 180/* Exceptions error codes */
181enum {
182 /* Exception subtypes for POWERPC_EXCP_ALIGN */
183 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
184 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
185 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
186 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
187 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
188 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
189 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
190 /* FP exceptions */
191 POWERPC_EXCP_FP = 0x10,
192 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
193 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
194 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
195 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 196 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 197 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
198 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
199 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
200 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
201 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
202 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
203 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
204 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
205 /* Invalid instruction */
206 POWERPC_EXCP_INVAL = 0x20,
207 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
208 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
209 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
210 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
211 /* Privileged instruction */
212 POWERPC_EXCP_PRIV = 0x30,
213 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
214 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
215 /* Trap */
216 POWERPC_EXCP_TRAP = 0x40,
217};
218
a750fc0b 219#define PPC_INPUT(env) (env->bus_model)
3fc6c082 220
be147d08 221/*****************************************************************************/
c227f099 222typedef struct opc_handler_t opc_handler_t;
79aceca5 223
3fc6c082
FB		 224/*****************************************************************************/
225/* Types used to describe some PowerPC registers */
69b058c8 226typedef struct DisasContext DisasContext;
c227f099 227typedef struct ppc_spr_t ppc_spr_t;
c227f099
AL		 228typedef union ppc_avr_t ppc_avr_t;
229typedef union ppc_tlb_t ppc_tlb_t;
76a66253 230
3fc6c082 231/* SPR access micro-ops generations callbacks */
c227f099 232struct ppc_spr_t {
69b058c8
PB		 233 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
234 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 235#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 236 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
237 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
238 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
239 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 240#endif
b55266b5 241 const char *name;
d197fdbc 242 target_ulong default_value;
d67d40ea
DG		 243#ifdef CONFIG_KVM
244 /* We (ab)use the fact that all the SPRs will have ids for the
245 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
246 * don't sync this */
247 uint64_t one_reg_id;
248#endif
3fc6c082
FB		 249};
250
251/* Altivec registers (128 bits) */
c227f099 252union ppc_avr_t {
0f6fbcbc 253 float32 f[4];
a9d9eb8f
JM		 254 uint8_t u8[16];
255 uint16_t u16[8];
256 uint32_t u32[4];
ab5f265d
AJ		 257 int8_t s8[16];
258 int16_t s16[8];
259 int32_t s32[4];
a9d9eb8f 260 uint64_t u64[2];
bb527533
TM		 261 int64_t s64[2];
262#ifdef CONFIG_INT128
263 __uint128_t u128;
264#endif
3fc6c082 265};
9fddaa0c 266
3c7b48b7 267#if !defined(CONFIG_USER_ONLY)
3fc6c082 268/* Software TLB cache */
c227f099
AL		 269typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
270struct ppc6xx_tlb_t {
76a66253
JM		 271 target_ulong pte0;
272 target_ulong pte1;
273 target_ulong EPN;
1d0a48fb
JM		 274};
275
c227f099
AL		 276typedef struct ppcemb_tlb_t ppcemb_tlb_t;
277struct ppcemb_tlb_t {
b162d02e 278 uint64_t RPN;
1d0a48fb 279 target_ulong EPN;
76a66253 280 target_ulong PID;
c55e9aef
JM		 281 target_ulong size;
282 uint32_t prot;
283 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 284};
285
d1e256fe
AG		 286typedef struct ppcmas_tlb_t {
287 uint32_t mas8;
288 uint32_t mas1;
289 uint64_t mas2;
290 uint64_t mas7_3;
291} ppcmas_tlb_t;
292
c227f099 293union ppc_tlb_t {
1c53accc
AG		 294 ppc6xx_tlb_t *tlb6;
295 ppcemb_tlb_t *tlbe;
296 ppcmas_tlb_t *tlbm;
3fc6c082 297};
1c53accc
AG		 298
299/* possible TLB variants */
300#define TLB_NONE 0
301#define TLB_6XX 1
302#define TLB_EMB 2
303#define TLB_MAS 3
3c7b48b7 304#endif
3fc6c082 305
bb593904
DG		 306#define SDR_32_HTABORG 0xFFFF0000UL
307#define SDR_32_HTABMASK 0x000001FFUL
308
309#if defined(TARGET_PPC64)
310#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
311#define SDR_64_HTABSIZE 0x000000000000001FULL
312#endif /* defined(TARGET_PPC64 */
313
c227f099
AL		 314typedef struct ppc_slb_t ppc_slb_t;
315struct ppc_slb_t {
81762d6d
DG		 316 uint64_t esid;
317 uint64_t vsid;
cd6a9bb6 318 const struct ppc_one_seg_page_size *sps;
8eee0af9
BS		 319};
320
d83af167 321#define MAX_SLB_ENTRIES 64
81762d6d
DG		 322#define SEGMENT_SHIFT_256M 28
323#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
324
cdaee006
DG		 325#define SEGMENT_SHIFT_1T 40
326#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
327
328
3fc6c082
FB		 329/*****************************************************************************/
330/* Machine state register bits definition */
76a66253 331#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 332#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 333#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 334#define MSR_SHV 60 /* hypervisor state hflags */
cdcdda27
AK		 335#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
336#define MSR_TS1 33
337#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 338#define MSR_CM 31 /* Computation mode for BookE hflags */
339#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 340#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 341#define MSR_GS 28 /* guest state for BookE */
363be49c 342#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 343#define MSR_VR 25 /* altivec available x hflags */
344#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 345#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 346#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 347#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 348#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 349#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 350#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
351#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 352#define MSR_ILE 16 /* Interrupt little-endian mode */
353#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 354#define MSR_PR 14 /* Problem state hflags */
355#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 356#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 357#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 358#define MSR_SE 10 /* Single-step trace enable x hflags */
359#define MSR_DWE 10 /* Debug wait enable on 405 x */
360#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
361#define MSR_BE 9 /* Branch trace enable x hflags */
362#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 363#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 364#define MSR_AL 7 /* AL bit on POWER */
0411a972 365#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 366#define MSR_IR 5 /* Instruction relocate */
3fc6c082 367#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 368#define MSR_IS 5 /* Instruction address space (BookE) */
369#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 370#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 371#define MSR_PX 2 /* Protection exclusive on 403 x */
372#define MSR_PMM 2 /* Performance monitor mark on POWER x */
373#define MSR_RI 1 /* Recoverable interrupt 1 */
374#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 375
1488270e
BH		 376/* LPCR bits */
377#define LPCR_VPM0 (1ull << (63 - 0))
378#define LPCR_VPM1 (1ull << (63 - 1))
379#define LPCR_ISL (1ull << (63 - 2))
380#define LPCR_KBV (1ull << (63 - 3))
88536935
BH		 381#define LPCR_DPFD_SHIFT (63 - 11)
382#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
383#define LPCR_VRMASD_SHIFT (63 - 16)
384#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
385#define LPCR_RMLS_SHIFT (63 - 37)
386#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
1488270e 387#define LPCR_ILE (1ull << (63 - 38))
1488270e
BH		 388#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
389#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
88536935 390#define LPCR_ONL (1ull << (63 - 45))
7778a575
BH		 391#define LPCR_P7_PECE0 (1ull << (63 - 49))
392#define LPCR_P7_PECE1 (1ull << (63 - 50))
393#define LPCR_P7_PECE2 (1ull << (63 - 51))
394#define LPCR_P8_PECE0 (1ull << (63 - 47))
395#define LPCR_P8_PECE1 (1ull << (63 - 48))
396#define LPCR_P8_PECE2 (1ull << (63 - 49))
397#define LPCR_P8_PECE3 (1ull << (63 - 50))
398#define LPCR_P8_PECE4 (1ull << (63 - 51))
88536935
BH		 399#define LPCR_MER (1ull << (63 - 52))
400#define LPCR_TC (1ull << (63 - 54))
401#define LPCR_LPES0 (1ull << (63 - 60))
402#define LPCR_LPES1 (1ull << (63 - 61))
403#define LPCR_RMI (1ull << (63 - 62))
404#define LPCR_HDICE (1ull << (63 - 63))
1e0c7e55 405
0411a972
JM		 406#define msr_sf ((env->msr >> MSR_SF) & 1)
407#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 408#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 409#define msr_cm ((env->msr >> MSR_CM) & 1)
410#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 411#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 412#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 413#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
414#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 415#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 416#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 417#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 418#define msr_sa ((env->msr >> MSR_SA) & 1)
419#define msr_key ((env->msr >> MSR_KEY) & 1)
420#define msr_pow ((env->msr >> MSR_POW) & 1)
421#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
422#define msr_ce ((env->msr >> MSR_CE) & 1)
423#define msr_ile ((env->msr >> MSR_ILE) & 1)
424#define msr_ee ((env->msr >> MSR_EE) & 1)
425#define msr_pr ((env->msr >> MSR_PR) & 1)
426#define msr_fp ((env->msr >> MSR_FP) & 1)
427#define msr_me ((env->msr >> MSR_ME) & 1)
428#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
429#define msr_se ((env->msr >> MSR_SE) & 1)
430#define msr_dwe ((env->msr >> MSR_DWE) & 1)
431#define msr_uble ((env->msr >> MSR_UBLE) & 1)
432#define msr_be ((env->msr >> MSR_BE) & 1)
433#define msr_de ((env->msr >> MSR_DE) & 1)
434#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
435#define msr_al ((env->msr >> MSR_AL) & 1)
436#define msr_ep ((env->msr >> MSR_EP) & 1)
437#define msr_ir ((env->msr >> MSR_IR) & 1)
438#define msr_dr ((env->msr >> MSR_DR) & 1)
9fb04491
BH		 439#define msr_is ((env->msr >> MSR_IS) & 1)
440#define msr_ds ((env->msr >> MSR_DS) & 1)
0411a972
JM		 441#define msr_pe ((env->msr >> MSR_PE) & 1)
442#define msr_px ((env->msr >> MSR_PX) & 1)
443#define msr_pmm ((env->msr >> MSR_PMM) & 1)
444#define msr_ri ((env->msr >> MSR_RI) & 1)
445#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 446#define msr_ts ((env->msr >> MSR_TS1) & 3)
447#define msr_tm ((env->msr >> MSR_TM) & 1)
448
a4f30719
JM		 449/* Hypervisor bit is more specific */
450#if defined(TARGET_PPC64)
451#define MSR_HVB (1ULL << MSR_SHV)
452#define msr_hv msr_shv
453#else
454#if defined(PPC_EMULATE_32BITS_HYPV)
455#define MSR_HVB (1ULL << MSR_THV)
456#define msr_hv msr_thv
a4f30719
JM		 457#else
458#define MSR_HVB (0ULL)
459#define msr_hv (0)
460#endif
461#endif
79aceca5 462
7019cb3d
AK		 463/* Facility Status and Control (FSCR) bits */
464#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
465#define FSCR_TAR (63 - 55) /* Target Address Register */
466/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
467#define FSCR_IC_MASK (0xFFULL)
468#define FSCR_IC_POS (63 - 7)
469#define FSCR_IC_DSCR_SPR3 2
470#define FSCR_IC_PMU 3
471#define FSCR_IC_BHRB 4
472#define FSCR_IC_TM 5
473#define FSCR_IC_EBB 7
474#define FSCR_IC_TAR 8
475
a586e548 476/* Exception state register bits definition */
542df9bf
AG		 477#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
478#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
479#define ESR_PTR (1 << (63 - 38)) /* Trap */
480#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
481#define ESR_ST (1 << (63 - 40)) /* Store Operation */
482#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
483#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
484#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
485#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
486#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
487#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
488#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
489#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
490#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
491#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
492#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
a586e548 493
aac86237
TM		 494/* Transaction EXception And Summary Register bits */
495#define TEXASR_FAILURE_PERSISTENT (63 - 7)
496#define TEXASR_DISALLOWED (63 - 8)
497#define TEXASR_NESTING_OVERFLOW (63 - 9)
498#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
499#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
500#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
501#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
502#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
503#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
504#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
505#define TEXASR_ABORT (63 - 31)
506#define TEXASR_SUSPENDED (63 - 32)
507#define TEXASR_PRIVILEGE_HV (63 - 34)
508#define TEXASR_PRIVILEGE_PR (63 - 35)
509#define TEXASR_FAILURE_SUMMARY (63 - 36)
510#define TEXASR_TFIAR_EXACT (63 - 37)
511#define TEXASR_ROT (63 - 38)
512#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
513
d26bfc9a 514enum {
4018bae9 515 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 516 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 517 POWERPC_FLAG_SPE = 0x00000001,
518 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 519 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 520 POWERPC_FLAG_TGPR = 0x00000004,
521 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 522 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 523 POWERPC_FLAG_SE = 0x00000010,
524 POWERPC_FLAG_DWE = 0x00000020,
525 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 526 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 527 POWERPC_FLAG_BE = 0x00000080,
528 POWERPC_FLAG_DE = 0x00000100,
a4f30719 529 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 530 POWERPC_FLAG_PX = 0x00000200,
531 POWERPC_FLAG_PMM = 0x00000400,
532 /* Flag for special features */
533 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
534 POWERPC_FLAG_RTC_CLK = 0x00010000,
535 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 536 /* Has CFAR */
537 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 538 /* Has VSX */
539 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 540 /* Has Transaction Memory (ISA 2.07) */
541 POWERPC_FLAG_TM = 0x00100000,
d26bfc9a
JM		 542};
543
7c58044c
JM		 544/*****************************************************************************/
545/* Floating point status and control register */
546#define FPSCR_FX 31 /* Floating-point exception summary */
547#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
548#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
549#define FPSCR_OX 28 /* Floating-point overflow exception */
550#define FPSCR_UX 27 /* Floating-point underflow exception */
551#define FPSCR_ZX 26 /* Floating-point zero divide exception */
552#define FPSCR_XX 25 /* Floating-point inexact exception */
553#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
554#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
555#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
556#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
557#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
558#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
559#define FPSCR_FR 18 /* Floating-point fraction rounded */
560#define FPSCR_FI 17 /* Floating-point fraction inexact */
561#define FPSCR_C 16 /* Floating-point result class descriptor */
562#define FPSCR_FL 15 /* Floating-point less than or negative */
563#define FPSCR_FG 14 /* Floating-point greater than or negative */
564#define FPSCR_FE 13 /* Floating-point equal or zero */
565#define FPSCR_FU 12 /* Floating-point unordered or NaN */
566#define FPSCR_FPCC 12 /* Floating-point condition code */
567#define FPSCR_FPRF 12 /* Floating-point result flags */
568#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
569#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
570#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
571#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
572#define FPSCR_OE 6 /* Floating-point overflow exception enable */
573#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
574#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
575#define FPSCR_XE 3 /* Floating-point inexact exception enable */
576#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
577#define FPSCR_RN1 1
578#define FPSCR_RN 0 /* Floating-point rounding control */
579#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
580#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
581#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
582#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
583#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
584#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
585#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
586#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
587#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
588#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
589#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
590#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
591#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
592#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
593#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
594#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
595#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
596#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
597#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
598#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
599#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
600#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
601#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
602/* Invalid operation exception summary */
603#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
604 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
605 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
606 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
607 (1 << FPSCR_VXCVI)))
608/* exception summary */
609#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
610/* enabled exception summary */
611#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
612 0x1F)
613
dbdc13a1
MS		 614#define FP_FX (1ull << FPSCR_FX)
615#define FP_FEX (1ull << FPSCR_FEX)
fc03cfef 616#define FP_VX (1ull << FPSCR_VX)
dbdc13a1 617#define FP_OX (1ull << FPSCR_OX)
dbdc13a1 618#define FP_UX (1ull << FPSCR_UX)
dbdc13a1 619#define FP_ZX (1ull << FPSCR_ZX)
fc03cfef 620#define FP_XX (1ull << FPSCR_XX)
dbdc13a1
MS		 621#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
622#define FP_VXISI (1ull << FPSCR_VXISI)
dbdc13a1 623#define FP_VXIDI (1ull << FPSCR_VXIDI)
fc03cfef
JC		 624#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
625#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
dbdc13a1 626#define FP_VXVC (1ull << FPSCR_VXVC)
fc03cfef
JC		 627#define FP_FR (1ull << FSPCR_FR)
628#define FP_FI (1ull << FPSCR_FI)
629#define FP_C (1ull << FPSCR_C)
630#define FP_FL (1ull << FPSCR_FL)
631#define FP_FG (1ull << FPSCR_FG)
632#define FP_FE (1ull << FPSCR_FE)
633#define FP_FU (1ull << FPSCR_FU)
634#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
635#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
636#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
637#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
dbdc13a1
MS		 638#define FP_VXCVI (1ull << FPSCR_VXCVI)
639#define FP_VE (1ull << FPSCR_VE)
fc03cfef
JC		 640#define FP_OE (1ull << FPSCR_OE)
641#define FP_UE (1ull << FPSCR_UE)
642#define FP_ZE (1ull << FPSCR_ZE)
643#define FP_XE (1ull << FPSCR_XE)
644#define FP_NI (1ull << FPSCR_NI)
645#define FP_RN1 (1ull << FPSCR_RN1)
646#define FP_RN (1ull << FPSCR_RN)
dbdc13a1 647
d1277156
JC		 648/* the exception bits which can be cleared by mcrfs - includes FX */
649#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
650 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
651 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
652 FP_VXSQRT | FP_VXCVI)
653
7c58044c 654/*****************************************************************************/
6fa724a3
AJ		 655/* Vector status and control register */
656#define VSCR_NJ 16 /* Vector non-java */
657#define VSCR_SAT 0 /* Vector saturation */
658#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
659#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
660
01662f3e
AG		 661/*****************************************************************************/
662/* BookE e500 MMU registers */
663
664#define MAS0_NV_SHIFT 0
665#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
666
667#define MAS0_WQ_SHIFT 12
668#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
669/* Write TLB entry regardless of reservation */
670#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
671/* Write TLB entry only already in use */
672#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
673/* Clear TLB entry */
674#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
675
676#define MAS0_HES_SHIFT 14
677#define MAS0_HES (1 << MAS0_HES_SHIFT)
678
679#define MAS0_ESEL_SHIFT 16
680#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
681
682#define MAS0_TLBSEL_SHIFT 28
683#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
684#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
685#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
686#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
687#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
688
689#define MAS0_ATSEL_SHIFT 31
690#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
691#define MAS0_ATSEL_TLB 0
692#define MAS0_ATSEL_LRAT MAS0_ATSEL
693
2bd9543c
SW		 694#define MAS1_TSIZE_SHIFT 7
695#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 696
697#define MAS1_TS_SHIFT 12
698#define MAS1_TS (1 << MAS1_TS_SHIFT)
699
700#define MAS1_IND_SHIFT 13
701#define MAS1_IND (1 << MAS1_IND_SHIFT)
702
703#define MAS1_TID_SHIFT 16
704#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
705
706#define MAS1_IPROT_SHIFT 30
707#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
708
709#define MAS1_VALID_SHIFT 31
710#define MAS1_VALID 0x80000000
711
712#define MAS2_EPN_SHIFT 12
96091698 713#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 714
715#define MAS2_ACM_SHIFT 6
716#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
717
718#define MAS2_VLE_SHIFT 5
719#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
720
721#define MAS2_W_SHIFT 4
722#define MAS2_W (1 << MAS2_W_SHIFT)
723
724#define MAS2_I_SHIFT 3
725#define MAS2_I (1 << MAS2_I_SHIFT)
726
727#define MAS2_M_SHIFT 2
728#define MAS2_M (1 << MAS2_M_SHIFT)
729
730#define MAS2_G_SHIFT 1
731#define MAS2_G (1 << MAS2_G_SHIFT)
732
733#define MAS2_E_SHIFT 0
734#define MAS2_E (1 << MAS2_E_SHIFT)
735
736#define MAS3_RPN_SHIFT 12
737#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
738
739#define MAS3_U0 0x00000200
740#define MAS3_U1 0x00000100
741#define MAS3_U2 0x00000080
742#define MAS3_U3 0x00000040
743#define MAS3_UX 0x00000020
744#define MAS3_SX 0x00000010
745#define MAS3_UW 0x00000008
746#define MAS3_SW 0x00000004
747#define MAS3_UR 0x00000002
748#define MAS3_SR 0x00000001
749#define MAS3_SPSIZE_SHIFT 1
750#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
751
752#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
753#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
754#define MAS4_TIDSELD_MASK 0x00030000
755#define MAS4_TIDSELD_PID0 0x00000000
756#define MAS4_TIDSELD_PID1 0x00010000
757#define MAS4_TIDSELD_PID2 0x00020000
758#define MAS4_TIDSELD_PIDZ 0x00030000
759#define MAS4_INDD 0x00008000 /* Default IND */
760#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
761#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
762#define MAS4_ACMD 0x00000040
763#define MAS4_VLED 0x00000020
764#define MAS4_WD 0x00000010
765#define MAS4_ID 0x00000008
766#define MAS4_MD 0x00000004
767#define MAS4_GD 0x00000002
768#define MAS4_ED 0x00000001
769#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
770#define MAS4_WIMGED_SHIFT 0
771
772#define MAS5_SGS 0x80000000
773#define MAS5_SLPID_MASK 0x00000fff
774
775#define MAS6_SPID0 0x3fff0000
776#define MAS6_SPID1 0x00007ffe
777#define MAS6_ISIZE(x) MAS1_TSIZE(x)
778#define MAS6_SAS 0x00000001
779#define MAS6_SPID MAS6_SPID0
780#define MAS6_SIND 0x00000002 /* Indirect page */
781#define MAS6_SIND_SHIFT 1
782#define MAS6_SPID_MASK 0x3fff0000
783#define MAS6_SPID_SHIFT 16
784#define MAS6_ISIZE_MASK 0x00000f80
785#define MAS6_ISIZE_SHIFT 7
786
787#define MAS7_RPN 0xffffffff
788
789#define MAS8_TGS 0x80000000
790#define MAS8_VF 0x40000000
791#define MAS8_TLBPID 0x00000fff
792
793/* Bit definitions for MMUCFG */
794#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
795#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
796#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
797#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
798#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
799#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
800#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
801#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
802#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
803
804/* Bit definitions for MMUCSR0 */
805#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
806#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
807#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
808#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
809#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
810 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
811#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
812#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
813#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
814#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
815
816/* TLBnCFG encoding */
817#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
818#define TLBnCFG_HES 0x00002000 /* HW select supported */
819#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
820#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
821#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
822#define TLBnCFG_IND 0x00020000 /* IND entries supported */
823#define TLBnCFG_PT 0x00040000 /* Can load from page table */
824#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
825#define TLBnCFG_MINSIZE_SHIFT 20
826#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
827#define TLBnCFG_MAXSIZE_SHIFT 16
828#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
829#define TLBnCFG_ASSOC_SHIFT 24
830
831/* TLBnPS encoding */
832#define TLBnPS_4K 0x00000004
833#define TLBnPS_8K 0x00000008
834#define TLBnPS_16K 0x00000010
835#define TLBnPS_32K 0x00000020
836#define TLBnPS_64K 0x00000040
837#define TLBnPS_128K 0x00000080
838#define TLBnPS_256K 0x00000100
839#define TLBnPS_512K 0x00000200
840#define TLBnPS_1M 0x00000400
841#define TLBnPS_2M 0x00000800
842#define TLBnPS_4M 0x00001000
843#define TLBnPS_8M 0x00002000
844#define TLBnPS_16M 0x00004000
845#define TLBnPS_32M 0x00008000
846#define TLBnPS_64M 0x00010000
847#define TLBnPS_128M 0x00020000
848#define TLBnPS_256M 0x00040000
849#define TLBnPS_512M 0x00080000
850#define TLBnPS_1G 0x00100000
851#define TLBnPS_2G 0x00200000
852#define TLBnPS_4G 0x00400000
853#define TLBnPS_8G 0x00800000
854#define TLBnPS_16G 0x01000000
855#define TLBnPS_32G 0x02000000
856#define TLBnPS_64G 0x04000000
857#define TLBnPS_128G 0x08000000
858#define TLBnPS_256G 0x10000000
859
860/* tlbilx action encoding */
861#define TLBILX_T_ALL 0
862#define TLBILX_T_TID 1
863#define TLBILX_T_FULLMATCH 3
864#define TLBILX_T_CLASS0 4
865#define TLBILX_T_CLASS1 5
866#define TLBILX_T_CLASS2 6
867#define TLBILX_T_CLASS3 7
868
869/* BookE 2.06 helper defines */
870
871#define BOOKE206_FLUSH_TLB0 (1 << 0)
872#define BOOKE206_FLUSH_TLB1 (1 << 1)
873#define BOOKE206_FLUSH_TLB2 (1 << 2)
874#define BOOKE206_FLUSH_TLB3 (1 << 3)
875
876/* number of possible TLBs */
877#define BOOKE206_MAX_TLBN 4
878
58e00a24
AG		 879/*****************************************************************************/
880/* Embedded.Processor Control */
881
882#define DBELL_TYPE_SHIFT 27
883#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
884#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
885#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
886#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
887#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
888#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
889
890#define DBELL_BRDCAST (1 << 26)
891#define DBELL_LPIDTAG_SHIFT 14
892#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
893#define DBELL_PIRTAG_MASK 0x3fff
894
4656e1f0
BH		 895/*****************************************************************************/
896/* Segment page size information, used by recent hash MMUs
897 * The format of this structure mirrors kvm_ppc_smmu_info
898 */
899
900#define PPC_PAGE_SIZES_MAX_SZ 8
901
902struct ppc_one_page_size {
903 uint32_t page_shift; /* Page shift (or 0) */
904 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
905};
906
907struct ppc_one_seg_page_size {
908 uint32_t page_shift; /* Base page shift of segment (or 0) */
909 uint32_t slb_enc; /* SLB encoding for BookS */
910 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
911};
912
913struct ppc_segment_page_sizes {
914 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
915};
916
917
6fa724a3 918/*****************************************************************************/
7c58044c 919/* The whole PowerPC CPU context */
9fb04491 920#define NB_MMU_MODES 8
6ebbf390 921
54ff58bb
BR		 922#define PPC_CPU_OPCODES_LEN 0x40
923#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 924
3fc6c082
FB		 925struct CPUPPCState {
926 /* First are the most commonly used resources
927 * during translated code execution
928 */
79aceca5 929 /* general purpose registers */
bd7d9a6d 930 target_ulong gpr[32];
3cd7d1dd 931 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 932 target_ulong gprh[32];
3fc6c082
FB		 933 /* LR */
934 target_ulong lr;
935 /* CTR */
936 target_ulong ctr;
937 /* condition register */
47e4661c 938 uint32_t crf[8];
697ab892
DG		 939#if defined(TARGET_PPC64)
940 /* CFAR */
941 target_ulong cfar;
942#endif
da91a00f 943 /* XER (with SO, OV, CA split out) */
3d7b417e 944 target_ulong xer;
da91a00f
RH		 945 target_ulong so;
946 target_ulong ov;
947 target_ulong ca;
79aceca5 948 /* Reservation address */
18b21a2f
NF		 949 target_ulong reserve_addr;
950 /* Reservation value */
951 target_ulong reserve_val;
9c294d5a 952 target_ulong reserve_val2;
4425265b
NF		 953 /* Reservation store address */
954 target_ulong reserve_ea;
955 /* Reserved store source register and size */
956 target_ulong reserve_info;
3fc6c082
FB		 957
958 /* Those ones are used in supervisor mode only */
79aceca5 959 /* machine state register */
0411a972 960 target_ulong msr;
3fc6c082 961 /* temporary general purpose registers */
bd7d9a6d 962 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 963
964 /* Floating point execution context */
4ecc3190 965 float_status fp_status;
3fc6c082
FB		 966 /* floating point registers */
967 float64 fpr[32];
968 /* floating point status and control register */
30304420 969 target_ulong fpscr;
4ecc3190 970
cb2dbfc3
AJ		 971 /* Next instruction pointer */
972 target_ulong nip;
a316d335 973
ac9eb073
FB		 974 int access_type; /* when a memory exception occurs, the access
975 type is stored here */
a541f297 976
cb2dbfc3
AJ		 977 CPU_COMMON
978
f2e63a42
JM		 979 /* MMU context - only relevant for full system emulation */
980#if !defined(CONFIG_USER_ONLY)
981#if defined(TARGET_PPC64)
f2e63a42 982 /* PowerPC 64 SLB area */
d83af167 983 ppc_slb_t slb[MAX_SLB_ENTRIES];
a90db158 984 int32_t slb_nr;
cd0c6f47 985 /* tcg TLB needs flush (deferred slb inval instruction typically) */
f2e63a42 986#endif
3fc6c082 987 /* segment registers */
a8170e5e 988 hwaddr htab_base;
f3c75d42 989 /* mask used to normalize hash value to PTEG index */
a8170e5e 990 hwaddr htab_mask;
74d37793 991 target_ulong sr[32];
f43e3525
DG		 992 /* externally stored hash table */
993 uint8_t *external_htab;
3fc6c082 994 /* BATs */
a90db158 995 uint32_t nb_BATs;
3fc6c082
FB		 996 target_ulong DBAT[2][8];
997 target_ulong IBAT[2][8];
01662f3e 998 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
a90db158 999 int32_t nb_tlb; /* Total number of TLB */
f2e63a42
JM		 1000 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1001 int nb_ways; /* Number of ways in the TLB set */
1002 int last_way; /* Last used way used to allocate TLB in a LRU way */
1003 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1004 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 1005 int tlb_type; /* Type of TLB we're dealing with */
1006 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 1007 /* 403 dedicated access protection registers */
1008 target_ulong pb[4];
93dd5e85
SW		 1009 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1010 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1011 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1012#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1013#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1014#endif
9fddaa0c 1015
3fc6c082
FB		 1016 /* Other registers */
1017 /* Special purpose registers */
1018 target_ulong spr[1024];
c227f099 1019 ppc_spr_t spr_cb[1024];
3fc6c082 1020 /* Altivec registers */
c227f099 1021 ppc_avr_t avr[32];
3fc6c082 1022 uint32_t vscr;
30304420
DG		 1023 /* VSX registers */
1024 uint64_t vsr[32];
d9bce9d9 1025 /* SPE registers */
2231ef10 1026 uint64_t spe_acc;
d9bce9d9 1027 uint32_t spe_fscr;
fbd265b6
AJ		 1028 /* SPE and Altivec can share a status since they will never be used
1029 * simultaneously */
1030 float_status vec_status;
3fc6c082
FB		 1031
1032 /* Internal devices resources */
9fddaa0c 1033 /* Time base and decrementer */
c227f099 1034 ppc_tb_t *tb_env;
3fc6c082 1035 /* Device control registers */
c227f099 1036 ppc_dcr_t *dcr_env;
3fc6c082 1037
d63001d1
JM		 1038 int dcache_line_size;
1039 int icache_line_size;
1040
3fc6c082
FB		 1041 /* Those resources are used during exception processing */
1042 /* CPU model definition */
a750fc0b 1043 target_ulong msr_mask;
c227f099
AL		 1044 powerpc_mmu_t mmu_model;
1045 powerpc_excp_t excp_model;
1046 powerpc_input_t bus_model;
237c0af0 1047 int bfd_mach;
3fc6c082 1048 uint32_t flags;
c29b735c 1049 uint64_t insns_flags;
a5858d7a 1050 uint64_t insns_flags2;
4656e1f0
BH		 1051#if defined(TARGET_PPC64)
1052 struct ppc_segment_page_sizes sps;
912acdf4
BH		 1053 ppc_slb_t vrma_slb;
1054 target_ulong rmls;
90da0d5a 1055 bool ci_large_pages;
4656e1f0 1056#endif
3fc6c082 1057
ed120055 1058#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
ac7d12ba
DG		 1059 uint64_t vpa_addr;
1060 uint64_t slb_shadow_addr, slb_shadow_size;
1061 uint64_t dtl_addr, dtl_size;
ed120055
DG		 1062#endif /* TARGET_PPC64 */
1063
3fc6c082 1064 int error_code;
47103572 1065 uint32_t pending_interrupts;
e9df014c 1066#if !defined(CONFIG_USER_ONLY)
4abf79a4 1067 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1068 * and only relevant when emulating a complete machine.
1069 */
1070 uint32_t irq_input_state;
1071 void **irq_inputs;
e1833e1f
JM		 1072 /* Exception vectors */
1073 target_ulong excp_vectors[POWERPC_EXCP_NB];
1074 target_ulong excp_prefix;
1075 target_ulong ivor_mask;
1076 target_ulong ivpr_mask;
d63001d1 1077 target_ulong hreset_vector;
68c2dd70
AG		 1078 hwaddr mpic_iack;
1079 /* true when the external proxy facility mode is enabled */
1080 bool mpic_proxy;
932ccbdd
BH		 1081 /* set when the processor has an HV mode, thus HV priv
1082 * instructions and SPRs are diallowed if MSR:HV is 0
1083 */
1084 bool has_hv_mode;
7778a575
BH		 1085 /* On P7/P8, set when in PM state, we need to handle resume
1086 * in a special way (such as routing some resume causes to
1087 * 0x100), so flag this here.
1088 */
1089 bool in_pm_state;
e9df014c 1090#endif
3fc6c082
FB		 1091
1092 /* Those resources are used only during code translation */
3fc6c082 1093 /* opcode handlers */
b048960f 1094 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
3fc6c082 1095
5cbdb3a3 1096 /* Those resources are used only in QEMU core */
056401ea 1097 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1098 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
9fb04491
BH		 1099 int immu_idx; /* precomputed MMU index to speed up insn access */
1100 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
3fc6c082 1101
9fddaa0c 1102 /* Power management */
cd346349 1103 int (*check_pow)(CPUPPCState *env);
a541f297 1104
2c50e26e
EI		 1105#if !defined(CONFIG_USER_ONLY)
1106 void *load_info; /* Holds boot loading state. */
1107#endif
ddd1055b
FC		 1108
1109 /* booke timers */
1110
1111 /* Specifies bit locations of the Time Base used to signal a fixed timer
1112 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1113 *
1114 * 0 selects the least significant bit.
1115 * 63 selects the most significant bit.
1116 */
1117 uint8_t fit_period[4];
1118 uint8_t wdt_period[4];
80b3f79b
AK		 1119
1120 /* Transactional memory state */
1121 target_ulong tm_gpr[32];
1122 ppc_avr_t tm_vsr[64];
1123 uint64_t tm_cr;
1124 uint64_t tm_lr;
1125 uint64_t tm_ctr;
1126 uint64_t tm_fpscr;
1127 uint64_t tm_amr;
1128 uint64_t tm_ppr;
1129 uint64_t tm_vrsave;
1130 uint32_t tm_vscr;
1131 uint64_t tm_dscr;
1132 uint64_t tm_tar;
3fc6c082 1133};
79aceca5 1134
ddd1055b
FC		 1135#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1136do { \
1137 env->fit_period[0] = (a_); \
1138 env->fit_period[1] = (b_); \
1139 env->fit_period[2] = (c_); \
1140 env->fit_period[3] = (d_); \
1141 } while (0)
1142
1143#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1144do { \
1145 env->wdt_period[0] = (a_); \
1146 env->wdt_period[1] = (b_); \
1147 env->wdt_period[2] = (c_); \
1148 env->wdt_period[3] = (d_); \
1149 } while (0)
1150
2d34fe39
PB		 1151/**
1152 * PowerPCCPU:
1153 * @env: #CPUPPCState
1154 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1155 * @max_compat: Maximal supported logical PVR from the command line
1156 * @cpu_version: Current logical PVR, zero if in "raw" mode
1157 *
1158 * A PowerPC CPU.
1159 */
1160struct PowerPCCPU {
1161 /*< private >*/
1162 CPUState parent_obj;
1163 /*< public >*/
1164
1165 CPUPPCState env;
1166 int cpu_dt_id;
1167 uint32_t max_compat;
1168 uint32_t cpu_version;
16a2497b 1169
146c11f1
DG		 1170 /* Fields related to migration compatibility hacks */
1171 bool pre_2_8_migration;
16a2497b
DG		 1172 target_ulong mig_msr_mask;
1173 uint64_t mig_insns_flags;
1174 uint64_t mig_insns_flags2;
1175 uint32_t mig_nb_BATs;
2d34fe39
PB		 1176};
1177
1178static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1179{
1180 return container_of(env, PowerPCCPU, env);
1181}
1182
1183#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1184
1185#define ENV_OFFSET offsetof(PowerPCCPU, env)
1186
1187PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1188PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1189
1190void ppc_cpu_do_interrupt(CPUState *cpu);
1191bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1192void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1193 int flags);
1194void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1195 fprintf_function cpu_fprintf, int flags);
2d34fe39
PB		 1196hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1197int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1198int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1199int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1200int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1201int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1202 int cpuid, void *opaque);
1203#ifndef CONFIG_USER_ONLY
1204void ppc_cpu_do_system_reset(CPUState *cs);
1205extern const struct VMStateDescription vmstate_ppc_cpu;
1206#endif
1d0cb67d 1207
3fc6c082 1208/*****************************************************************************/
397b457d 1209PowerPCCPU *cpu_ppc_init(const char *cpu_model);
2e70f6ef 1210void ppc_translate_init(void);
caf6316d 1211const char *ppc_cpu_lookup_alias(const char *alias);
79aceca5
FB		 1212/* you can call this signal handler from your SIGBUS and SIGSEGV
1213 signal handlers to inform the virtual CPU of exceptions. non zero
1214 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1215int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1216 void *puc);
cc8eae8a 1217#if defined(CONFIG_USER_ONLY)
7510454e
AF		 1218int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1219 int mmu_idx);
cc8eae8a 1220#endif
a541f297 1221
76a66253 1222#if !defined(CONFIG_USER_ONLY)
45d827d2 1223void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
12de9a39 1224#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1225void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1226
9a78eead 1227void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
2a48d993 1228int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
eac4fba9 1229#if defined(TARGET_PPC64)
f9ab1e87 1230void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
eac4fba9 1231#endif
aaed909a 1232
9fddaa0c
FB		 1233/* Time-base and decrementer management */
1234#ifndef NO_CPU_IO_DEFS
e3ea6529 1235uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1236uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1237void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1238void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1239uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1240uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1241void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1242void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
e81a982a 1243bool ppc_decr_clear_on_delivery(CPUPPCState *env);
9fddaa0c
FB		 1244uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1245void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1246uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1247void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1248uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1249uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1250uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1251#if !defined(CONFIG_USER_ONLY)
1252void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1253void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1254target_ulong load_40x_pit (CPUPPCState *env);
1255void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1256void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1257void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1258void store_booke_tcr (CPUPPCState *env, target_ulong val);
1259void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1260void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1261void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
26a7f129 1262void cpu_ppc_set_papr(PowerPCCPU *cpu);
d9bce9d9 1263#endif
9fddaa0c 1264#endif
79aceca5 1265
d6478bc7
FC		 1266void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1267
636aa200 1268static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1269{
1270 uint64_t gprv;
1271
1272 gprv = env->gpr[gprn];
6b542af7
JM		 1273 if (env->flags & POWERPC_FLAG_SPE) {
1274 /* If the CPU implements the SPE extension, we have to get the
1275 * high bits of the GPR from the gprh storage area
1276 */
1277 gprv &= 0xFFFFFFFFULL;
1278 gprv |= (uint64_t)env->gprh[gprn] << 32;
1279 }
6b542af7
JM		 1280
1281 return gprv;
1282}
1283
2e719ba3 1284/* Device control registers */
73b01960
AG		 1285int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1286int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1287
2994fd96 1288#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
397b457d 1289
9467d44c 1290#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1291#define cpu_list ppc_cpu_list
9467d44c 1292
6ebbf390 1293/* MMU modes definitions */
6ebbf390 1294#define MMU_USER_IDX 0
97ed5ccd 1295static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
6ebbf390 1296{
9fb04491 1297 return ifetch ? env->immu_idx : env->dmmu_idx;
6ebbf390
JM		 1298}
1299
022c62cb 1300#include "exec/cpu-all.h"
79aceca5 1301
3fc6c082 1302/*****************************************************************************/
e1571908 1303/* CRF definitions */
57951c27
AJ		 1304#define CRF_LT 3
1305#define CRF_GT 2
1306#define CRF_EQ 1
1307#define CRF_SO 0
e6bba2ef
NF		 1308#define CRF_CH (1 << CRF_LT)
1309#define CRF_CL (1 << CRF_GT)
1310#define CRF_CH_OR_CL (1 << CRF_EQ)
1311#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ		 1312
1313/* XER definitions */
3d7b417e
AJ		 1314#define XER_SO 31
1315#define XER_OV 30
1316#define XER_CA 29
1317#define XER_CMP 8
1318#define XER_BC 0
da91a00f
RH		 1319#define xer_so (env->so)
1320#define xer_ov (env->ov)
1321#define xer_ca (env->ca)
3d7b417e
AJ		 1322#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1323#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1324
3fc6c082 1325/* SPR definitions */
80d11f44
JM		 1326#define SPR_MQ (0x000)
1327#define SPR_XER (0x001)
1328#define SPR_601_VRTCU (0x004)
1329#define SPR_601_VRTCL (0x005)
1330#define SPR_601_UDECR (0x006)
1331#define SPR_LR (0x008)
1332#define SPR_CTR (0x009)
f80872e2 1333#define SPR_UAMR (0x00C)
697ab892 1334#define SPR_DSCR (0x011)
80d11f44
JM		 1335#define SPR_DSISR (0x012)
1336#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1337#define SPR_601_RTCU (0x014)
1338#define SPR_601_RTCL (0x015)
1339#define SPR_DECR (0x016)
1340#define SPR_SDR1 (0x019)
1341#define SPR_SRR0 (0x01A)
1342#define SPR_SRR1 (0x01B)
697ab892 1343#define SPR_CFAR (0x01C)
80d11f44 1344#define SPR_AMR (0x01D)
9c1cf38d 1345#define SPR_ACOP (0x01F)
80d11f44 1346#define SPR_BOOKE_PID (0x030)
9c1cf38d 1347#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1348#define SPR_BOOKE_DECAR (0x036)
1349#define SPR_BOOKE_CSRR0 (0x03A)
1350#define SPR_BOOKE_CSRR1 (0x03B)
1351#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1352#define SPR_IAMR (0x03D)
80d11f44
JM		 1353#define SPR_BOOKE_ESR (0x03E)
1354#define SPR_BOOKE_IVPR (0x03F)
1355#define SPR_MPC_EIE (0x050)
1356#define SPR_MPC_EID (0x051)
1357#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1358#define SPR_TFHAR (0x080)
1359#define SPR_TFIAR (0x081)
1360#define SPR_TEXASR (0x082)
1361#define SPR_TEXASRU (0x083)
0bfe9299 1362#define SPR_UCTRL (0x088)
80d11f44
JM		 1363#define SPR_MPC_CMPA (0x090)
1364#define SPR_MPC_CMPB (0x091)
1365#define SPR_MPC_CMPC (0x092)
1366#define SPR_MPC_CMPD (0x093)
1367#define SPR_MPC_ECR (0x094)
1368#define SPR_MPC_DER (0x095)
1369#define SPR_MPC_COUNTA (0x096)
1370#define SPR_MPC_COUNTB (0x097)
0bfe9299 1371#define SPR_CTRL (0x098)
80d11f44
JM		 1372#define SPR_MPC_CMPE (0x098)
1373#define SPR_MPC_CMPF (0x099)
7019cb3d 1374#define SPR_FSCR (0x099)
80d11f44
JM		 1375#define SPR_MPC_CMPG (0x09A)
1376#define SPR_MPC_CMPH (0x09B)
1377#define SPR_MPC_LCTRL1 (0x09C)
1378#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1379#define SPR_UAMOR (0x09D)
80d11f44
JM		 1380#define SPR_MPC_ICTRL (0x09E)
1381#define SPR_MPC_BAR (0x09F)
d6f1445f 1382#define SPR_PSPB (0x09F)
1488270e
BH		 1383#define SPR_DAWR (0x0B4)
1384#define SPR_RPR (0x0BA)
eb5ceb4d 1385#define SPR_CIABR (0x0BB)
1488270e
BH		 1386#define SPR_DAWRX (0x0BC)
1387#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1388#define SPR_VRSAVE (0x100)
1389#define SPR_USPRG0 (0x100)
1390#define SPR_USPRG1 (0x101)
1391#define SPR_USPRG2 (0x102)
1392#define SPR_USPRG3 (0x103)
1393#define SPR_USPRG4 (0x104)
1394#define SPR_USPRG5 (0x105)
1395#define SPR_USPRG6 (0x106)
1396#define SPR_USPRG7 (0x107)
1397#define SPR_VTBL (0x10C)
1398#define SPR_VTBU (0x10D)
1399#define SPR_SPRG0 (0x110)
1400#define SPR_SPRG1 (0x111)
1401#define SPR_SPRG2 (0x112)
1402#define SPR_SPRG3 (0x113)
1403#define SPR_SPRG4 (0x114)
1404#define SPR_SCOMC (0x114)
1405#define SPR_SPRG5 (0x115)
1406#define SPR_SCOMD (0x115)
1407#define SPR_SPRG6 (0x116)
1408#define SPR_SPRG7 (0x117)
1409#define SPR_ASR (0x118)
1410#define SPR_EAR (0x11A)
1411#define SPR_TBL (0x11C)
1412#define SPR_TBU (0x11D)
1413#define SPR_TBU40 (0x11E)
1414#define SPR_SVR (0x11E)
1415#define SPR_BOOKE_PIR (0x11E)
1416#define SPR_PVR (0x11F)
1417#define SPR_HSPRG0 (0x130)
1418#define SPR_BOOKE_DBSR (0x130)
1419#define SPR_HSPRG1 (0x131)
1420#define SPR_HDSISR (0x132)
1421#define SPR_HDAR (0x133)
90dc8812 1422#define SPR_BOOKE_EPCR (0x133)
9d52e907 1423#define SPR_SPURR (0x134)
80d11f44
JM		 1424#define SPR_BOOKE_DBCR0 (0x134)
1425#define SPR_IBCR (0x135)
1426#define SPR_PURR (0x135)
1427#define SPR_BOOKE_DBCR1 (0x135)
1428#define SPR_DBCR (0x136)
1429#define SPR_HDEC (0x136)
1430#define SPR_BOOKE_DBCR2 (0x136)
1431#define SPR_HIOR (0x137)
1432#define SPR_MBAR (0x137)
1433#define SPR_RMOR (0x138)
1434#define SPR_BOOKE_IAC1 (0x138)
1435#define SPR_HRMOR (0x139)
1436#define SPR_BOOKE_IAC2 (0x139)
1437#define SPR_HSRR0 (0x13A)
1438#define SPR_BOOKE_IAC3 (0x13A)
1439#define SPR_HSRR1 (0x13B)
1440#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1441#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1442#define SPR_MMCRH (0x13C)
80d11f44
JM		 1443#define SPR_DABR2 (0x13D)
1444#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1445#define SPR_TFMR (0x13D)
80d11f44 1446#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1447#define SPR_LPCR (0x13E)
80d11f44 1448#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1449#define SPR_LPIDR (0x13F)
80d11f44 1450#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1451#define SPR_HMER (0x150)
1452#define SPR_HMEER (0x151)
6d9412ea 1453#define SPR_PCR (0x152)
1488270e 1454#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1455#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1456#define SPR_BOOKE_TLB0PS (0x158)
1457#define SPR_BOOKE_TLB1PS (0x159)
1458#define SPR_BOOKE_TLB2PS (0x15A)
1459#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1460#define SPR_AMOR (0x15D)
84755ed5 1461#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1462#define SPR_BOOKE_IVOR0 (0x190)
1463#define SPR_BOOKE_IVOR1 (0x191)
1464#define SPR_BOOKE_IVOR2 (0x192)
1465#define SPR_BOOKE_IVOR3 (0x193)
1466#define SPR_BOOKE_IVOR4 (0x194)
1467#define SPR_BOOKE_IVOR5 (0x195)
1468#define SPR_BOOKE_IVOR6 (0x196)
1469#define SPR_BOOKE_IVOR7 (0x197)
1470#define SPR_BOOKE_IVOR8 (0x198)
1471#define SPR_BOOKE_IVOR9 (0x199)
1472#define SPR_BOOKE_IVOR10 (0x19A)
1473#define SPR_BOOKE_IVOR11 (0x19B)
1474#define SPR_BOOKE_IVOR12 (0x19C)
1475#define SPR_BOOKE_IVOR13 (0x19D)
1476#define SPR_BOOKE_IVOR14 (0x19E)
1477#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1478#define SPR_BOOKE_IVOR38 (0x1B0)
1479#define SPR_BOOKE_IVOR39 (0x1B1)
1480#define SPR_BOOKE_IVOR40 (0x1B2)
1481#define SPR_BOOKE_IVOR41 (0x1B3)
1482#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1483#define SPR_BOOKE_GIVOR2 (0x1B8)
1484#define SPR_BOOKE_GIVOR3 (0x1B9)
1485#define SPR_BOOKE_GIVOR4 (0x1BA)
1486#define SPR_BOOKE_GIVOR8 (0x1BB)
1487#define SPR_BOOKE_GIVOR13 (0x1BC)
1488#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1489#define SPR_TIR (0x1BE)
80d11f44
JM		 1490#define SPR_BOOKE_SPEFSCR (0x200)
1491#define SPR_Exxx_BBEAR (0x201)
1492#define SPR_Exxx_BBTAR (0x202)
1493#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1494#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1495#define SPR_Exxx_NPIDR (0x205)
1496#define SPR_ATBL (0x20E)
1497#define SPR_ATBU (0x20F)
1498#define SPR_IBAT0U (0x210)
1499#define SPR_BOOKE_IVOR32 (0x210)
1500#define SPR_RCPU_MI_GRA (0x210)
1501#define SPR_IBAT0L (0x211)
1502#define SPR_BOOKE_IVOR33 (0x211)
1503#define SPR_IBAT1U (0x212)
1504#define SPR_BOOKE_IVOR34 (0x212)
1505#define SPR_IBAT1L (0x213)
1506#define SPR_BOOKE_IVOR35 (0x213)
1507#define SPR_IBAT2U (0x214)
1508#define SPR_BOOKE_IVOR36 (0x214)
1509#define SPR_IBAT2L (0x215)
1510#define SPR_BOOKE_IVOR37 (0x215)
1511#define SPR_IBAT3U (0x216)
1512#define SPR_IBAT3L (0x217)
1513#define SPR_DBAT0U (0x218)
1514#define SPR_RCPU_L2U_GRA (0x218)
1515#define SPR_DBAT0L (0x219)
1516#define SPR_DBAT1U (0x21A)
1517#define SPR_DBAT1L (0x21B)
1518#define SPR_DBAT2U (0x21C)
1519#define SPR_DBAT2L (0x21D)
1520#define SPR_DBAT3U (0x21E)
1521#define SPR_DBAT3L (0x21F)
1522#define SPR_IBAT4U (0x230)
1523#define SPR_RPCU_BBCMCR (0x230)
1524#define SPR_MPC_IC_CST (0x230)
1525#define SPR_Exxx_CTXCR (0x230)
1526#define SPR_IBAT4L (0x231)
1527#define SPR_MPC_IC_ADR (0x231)
1528#define SPR_Exxx_DBCR3 (0x231)
1529#define SPR_IBAT5U (0x232)
1530#define SPR_MPC_IC_DAT (0x232)
1531#define SPR_Exxx_DBCNT (0x232)
1532#define SPR_IBAT5L (0x233)
1533#define SPR_IBAT6U (0x234)
1534#define SPR_IBAT6L (0x235)
1535#define SPR_IBAT7U (0x236)
1536#define SPR_IBAT7L (0x237)
1537#define SPR_DBAT4U (0x238)
1538#define SPR_RCPU_L2U_MCR (0x238)
1539#define SPR_MPC_DC_CST (0x238)
1540#define SPR_Exxx_ALTCTXCR (0x238)
1541#define SPR_DBAT4L (0x239)
1542#define SPR_MPC_DC_ADR (0x239)
1543#define SPR_DBAT5U (0x23A)
1544#define SPR_BOOKE_MCSRR0 (0x23A)
1545#define SPR_MPC_DC_DAT (0x23A)
1546#define SPR_DBAT5L (0x23B)
1547#define SPR_BOOKE_MCSRR1 (0x23B)
1548#define SPR_DBAT6U (0x23C)
1549#define SPR_BOOKE_MCSR (0x23C)
1550#define SPR_DBAT6L (0x23D)
1551#define SPR_Exxx_MCAR (0x23D)
1552#define SPR_DBAT7U (0x23E)
1553#define SPR_BOOKE_DSRR0 (0x23E)
1554#define SPR_DBAT7L (0x23F)
1555#define SPR_BOOKE_DSRR1 (0x23F)
1556#define SPR_BOOKE_SPRG8 (0x25C)
1557#define SPR_BOOKE_SPRG9 (0x25D)
1558#define SPR_BOOKE_MAS0 (0x270)
1559#define SPR_BOOKE_MAS1 (0x271)
1560#define SPR_BOOKE_MAS2 (0x272)
1561#define SPR_BOOKE_MAS3 (0x273)
1562#define SPR_BOOKE_MAS4 (0x274)
1563#define SPR_BOOKE_MAS5 (0x275)
1564#define SPR_BOOKE_MAS6 (0x276)
1565#define SPR_BOOKE_PID1 (0x279)
1566#define SPR_BOOKE_PID2 (0x27A)
1567#define SPR_MPC_DPDR (0x280)
1568#define SPR_MPC_IMMR (0x288)
1569#define SPR_BOOKE_TLB0CFG (0x2B0)
1570#define SPR_BOOKE_TLB1CFG (0x2B1)
1571#define SPR_BOOKE_TLB2CFG (0x2B2)
1572#define SPR_BOOKE_TLB3CFG (0x2B3)
1573#define SPR_BOOKE_EPR (0x2BE)
1574#define SPR_PERF0 (0x300)
1575#define SPR_RCPU_MI_RBA0 (0x300)
1576#define SPR_MPC_MI_CTR (0x300)
14646457 1577#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1578#define SPR_PERF1 (0x301)
1579#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1580#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1581#define SPR_PERF2 (0x302)
1582#define SPR_RCPU_MI_RBA2 (0x302)
1583#define SPR_MPC_MI_AP (0x302)
75b9c321 1584#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1585#define SPR_PERF3 (0x303)
1586#define SPR_RCPU_MI_RBA3 (0x303)
1587#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1588#define SPR_POWER_UPMC1 (0x303)
80d11f44 1589#define SPR_PERF4 (0x304)
fd51ff63 1590#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1591#define SPR_PERF5 (0x305)
1592#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1593#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1594#define SPR_PERF6 (0x306)
1595#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1596#define SPR_POWER_UPMC4 (0x306)
80d11f44 1597#define SPR_PERF7 (0x307)
fd51ff63 1598#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1599#define SPR_PERF8 (0x308)
1600#define SPR_RCPU_L2U_RBA0 (0x308)
1601#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1602#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1603#define SPR_PERF9 (0x309)
1604#define SPR_RCPU_L2U_RBA1 (0x309)
1605#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1606#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1607#define SPR_PERFA (0x30A)
1608#define SPR_RCPU_L2U_RBA2 (0x30A)
1609#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1610#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1611#define SPR_PERFB (0x30B)
1612#define SPR_RCPU_L2U_RBA3 (0x30B)
1613#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1614#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1615#define SPR_PERFC (0x30C)
1616#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1617#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1618#define SPR_PERFD (0x30D)
1619#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1620#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1621#define SPR_PERFE (0x30E)
1622#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1623#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1624#define SPR_PERFF (0x30F)
1625#define SPR_MPC_MD_TW (0x30F)
1626#define SPR_UPERF0 (0x310)
14646457 1627#define SPR_POWER_SIER (0x310)
80d11f44 1628#define SPR_UPERF1 (0x311)
70c53407 1629#define SPR_POWER_MMCR2 (0x311)
80d11f44 1630#define SPR_UPERF2 (0x312)
75b9c321 1631#define SPR_POWER_MMCRA (0X312)
80d11f44 1632#define SPR_UPERF3 (0x313)
fd51ff63 1633#define SPR_POWER_PMC1 (0X313)
80d11f44 1634#define SPR_UPERF4 (0x314)
fd51ff63 1635#define SPR_POWER_PMC2 (0X314)
80d11f44 1636#define SPR_UPERF5 (0x315)
fd51ff63 1637#define SPR_POWER_PMC3 (0X315)
80d11f44 1638#define SPR_UPERF6 (0x316)
fd51ff63 1639#define SPR_POWER_PMC4 (0X316)
80d11f44 1640#define SPR_UPERF7 (0x317)
fd51ff63 1641#define SPR_POWER_PMC5 (0X317)
80d11f44 1642#define SPR_UPERF8 (0x318)
fd51ff63 1643#define SPR_POWER_PMC6 (0X318)
80d11f44 1644#define SPR_UPERF9 (0x319)
c36c97f8 1645#define SPR_970_PMC7 (0X319)
80d11f44 1646#define SPR_UPERFA (0x31A)
c36c97f8 1647#define SPR_970_PMC8 (0X31A)
80d11f44 1648#define SPR_UPERFB (0x31B)
fd51ff63 1649#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1650#define SPR_UPERFC (0x31C)
fd51ff63 1651#define SPR_POWER_SIAR (0X31C)
80d11f44 1652#define SPR_UPERFD (0x31D)
fd51ff63 1653#define SPR_POWER_SDAR (0X31D)
80d11f44 1654#define SPR_UPERFE (0x31E)
fd51ff63 1655#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1656#define SPR_UPERFF (0x31F)
1657#define SPR_RCPU_MI_RA0 (0x320)
1658#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1659#define SPR_BESCRS (0x320)
80d11f44
JM		 1660#define SPR_RCPU_MI_RA1 (0x321)
1661#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1662#define SPR_BESCRSU (0x321)
80d11f44
JM		 1663#define SPR_RCPU_MI_RA2 (0x322)
1664#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1665#define SPR_BESCRR (0x322)
80d11f44 1666#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1667#define SPR_BESCRRU (0x323)
1668#define SPR_EBBHR (0x324)
1669#define SPR_EBBRR (0x325)
1670#define SPR_BESCR (0x326)
80d11f44
JM		 1671#define SPR_RCPU_L2U_RA0 (0x328)
1672#define SPR_MPC_MD_DBCAM (0x328)
1673#define SPR_RCPU_L2U_RA1 (0x329)
1674#define SPR_MPC_MD_DBRAM0 (0x329)
1675#define SPR_RCPU_L2U_RA2 (0x32A)
1676#define SPR_MPC_MD_DBRAM1 (0x32A)
1677#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1678#define SPR_TAR (0x32F)
21a558be 1679#define SPR_IC (0x350)
3ba55e39 1680#define SPR_VTB (0x351)
1488270e 1681#define SPR_MMCRC (0x353)
80d11f44
JM		 1682#define SPR_440_INV0 (0x370)
1683#define SPR_440_INV1 (0x371)
1684#define SPR_440_INV2 (0x372)
1685#define SPR_440_INV3 (0x373)
1686#define SPR_440_ITV0 (0x374)
1687#define SPR_440_ITV1 (0x375)
1688#define SPR_440_ITV2 (0x376)
1689#define SPR_440_ITV3 (0x377)
1690#define SPR_440_CCR1 (0x378)
14646457
BH		 1691#define SPR_TACR (0x378)
1692#define SPR_TCSCR (0x379)
1693#define SPR_CSIGR (0x37a)
80d11f44 1694#define SPR_DCRIPR (0x37B)
14646457
BH		 1695#define SPR_POWER_SPMC1 (0x37C)
1696#define SPR_POWER_SPMC2 (0x37D)
70c53407 1697#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1698#define SPR_WORT (0x37F)
80d11f44 1699#define SPR_PPR (0x380)
bd928eba 1700#define SPR_750_GQR0 (0x390)
80d11f44 1701#define SPR_440_DNV0 (0x390)
bd928eba 1702#define SPR_750_GQR1 (0x391)
80d11f44 1703#define SPR_440_DNV1 (0x391)
bd928eba 1704#define SPR_750_GQR2 (0x392)
80d11f44 1705#define SPR_440_DNV2 (0x392)
bd928eba 1706#define SPR_750_GQR3 (0x393)
80d11f44 1707#define SPR_440_DNV3 (0x393)
bd928eba 1708#define SPR_750_GQR4 (0x394)
80d11f44 1709#define SPR_440_DTV0 (0x394)
bd928eba 1710#define SPR_750_GQR5 (0x395)
80d11f44 1711#define SPR_440_DTV1 (0x395)
bd928eba 1712#define SPR_750_GQR6 (0x396)
80d11f44 1713#define SPR_440_DTV2 (0x396)
bd928eba 1714#define SPR_750_GQR7 (0x397)
80d11f44 1715#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1716#define SPR_750_THRM4 (0x398)
1717#define SPR_750CL_HID2 (0x398)
80d11f44 1718#define SPR_440_DVLIM (0x398)
bd928eba 1719#define SPR_750_WPAR (0x399)
80d11f44 1720#define SPR_440_IVLIM (0x399)
1488270e 1721#define SPR_TSCR (0x399)
bd928eba
JM		 1722#define SPR_750_DMAU (0x39A)
1723#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1724#define SPR_440_RSTCFG (0x39B)
1725#define SPR_BOOKE_DCDBTRL (0x39C)
1726#define SPR_BOOKE_DCDBTRH (0x39D)
1727#define SPR_BOOKE_ICDBTRL (0x39E)
1728#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1729#define SPR_74XX_UMMCR2 (0x3A0)
1730#define SPR_7XX_UPMC5 (0x3A1)
1731#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1732#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1733#define SPR_7XX_UMMCR0 (0x3A8)
1734#define SPR_7XX_UPMC1 (0x3A9)
1735#define SPR_7XX_UPMC2 (0x3AA)
1736#define SPR_7XX_USIAR (0x3AB)
1737#define SPR_7XX_UMMCR1 (0x3AC)
1738#define SPR_7XX_UPMC3 (0x3AD)
1739#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1740#define SPR_USDA (0x3AF)
1741#define SPR_40x_ZPR (0x3B0)
1742#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1743#define SPR_74XX_MMCR2 (0x3B0)
1744#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1745#define SPR_40x_PID (0x3B1)
cb8b8bf8 1746#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1747#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1748#define SPR_4xx_CCR0 (0x3B3)
1749#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1750#define SPR_405_IAC3 (0x3B4)
1751#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1752#define SPR_405_IAC4 (0x3B5)
80d11f44 1753#define SPR_405_DVC1 (0x3B6)
80d11f44 1754#define SPR_405_DVC2 (0x3B7)
80d11f44 1755#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1756#define SPR_7XX_MMCR0 (0x3B8)
1757#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1758#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1759#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1760#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1761#define SPR_7XX_SIAR (0x3BB)
80d11f44 1762#define SPR_405_SLER (0x3BB)
cb8b8bf8 1763#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1764#define SPR_405_SU0R (0x3BC)
80d11f44 1765#define SPR_401_SKR (0x3BC)
cb8b8bf8 1766#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1767#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1768#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1769#define SPR_SDA (0x3BF)
80d11f44
JM		 1770#define SPR_403_VTBL (0x3CC)
1771#define SPR_403_VTBU (0x3CD)
1772#define SPR_DMISS (0x3D0)
1773#define SPR_DCMP (0x3D1)
1774#define SPR_HASH1 (0x3D2)
1775#define SPR_HASH2 (0x3D3)
1776#define SPR_BOOKE_ICDBDR (0x3D3)
1777#define SPR_TLBMISS (0x3D4)
1778#define SPR_IMISS (0x3D4)
1779#define SPR_40x_ESR (0x3D4)
1780#define SPR_PTEHI (0x3D5)
1781#define SPR_ICMP (0x3D5)
1782#define SPR_40x_DEAR (0x3D5)
1783#define SPR_PTELO (0x3D6)
1784#define SPR_RPA (0x3D6)
1785#define SPR_40x_EVPR (0x3D6)
1786#define SPR_L3PM (0x3D7)
1787#define SPR_403_CDBCR (0x3D7)
4e777442 1788#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1789#define SPR_TCR (0x3D8)
1790#define SPR_40x_TSR (0x3D8)
1791#define SPR_IBR (0x3DA)
1792#define SPR_40x_TCR (0x3DA)
1793#define SPR_ESASRR (0x3DB)
1794#define SPR_40x_PIT (0x3DB)
1795#define SPR_403_TBL (0x3DC)
1796#define SPR_403_TBU (0x3DD)
1797#define SPR_SEBR (0x3DE)
1798#define SPR_40x_SRR2 (0x3DE)
1799#define SPR_SER (0x3DF)
1800#define SPR_40x_SRR3 (0x3DF)
4e777442 1801#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1802#define SPR_L3ITCR1 (0x3E9)
1803#define SPR_L3ITCR2 (0x3EA)
1804#define SPR_L3ITCR3 (0x3EB)
1805#define SPR_HID0 (0x3F0)
1806#define SPR_40x_DBSR (0x3F0)
1807#define SPR_HID1 (0x3F1)
1808#define SPR_IABR (0x3F2)
1809#define SPR_40x_DBCR0 (0x3F2)
1810#define SPR_601_HID2 (0x3F2)
1811#define SPR_Exxx_L1CSR0 (0x3F2)
1812#define SPR_ICTRL (0x3F3)
1813#define SPR_HID2 (0x3F3)
bd928eba 1814#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1815#define SPR_Exxx_L1CSR1 (0x3F3)
1816#define SPR_440_DBDR (0x3F3)
1817#define SPR_LDSTDB (0x3F4)
bd928eba 1818#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1819#define SPR_40x_IAC1 (0x3F4)
1820#define SPR_MMUCSR0 (0x3F4)
ba881002 1821#define SPR_970_HID4 (0x3F4)
80d11f44 1822#define SPR_DABR (0x3F5)
3fc6c082 1823#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1824#define SPR_Exxx_BUCSR (0x3F5)
1825#define SPR_40x_IAC2 (0x3F5)
1826#define SPR_601_HID5 (0x3F5)
1827#define SPR_40x_DAC1 (0x3F6)
1828#define SPR_MSSCR0 (0x3F6)
1829#define SPR_970_HID5 (0x3F6)
1830#define SPR_MSSSR0 (0x3F7)
4e777442 1831#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1832#define SPR_DABRX (0x3F7)
1833#define SPR_40x_DAC2 (0x3F7)
1834#define SPR_MMUCFG (0x3F7)
1835#define SPR_LDSTCR (0x3F8)
1836#define SPR_L2PMCR (0x3F8)
bd928eba 1837#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1838#define SPR_Exxx_L1FINV0 (0x3F8)
1839#define SPR_L2CR (0x3F9)
80d11f44 1840#define SPR_L3CR (0x3FA)
bd928eba 1841#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1842#define SPR_IABR2 (0x3FA)
1843#define SPR_40x_DCCR (0x3FA)
1844#define SPR_ICTC (0x3FB)
1845#define SPR_40x_ICCR (0x3FB)
1846#define SPR_THRM1 (0x3FC)
1847#define SPR_403_PBL1 (0x3FC)
1848#define SPR_SP (0x3FD)
1849#define SPR_THRM2 (0x3FD)
1850#define SPR_403_PBU1 (0x3FD)
1851#define SPR_604_HID13 (0x3FD)
1852#define SPR_LT (0x3FE)
1853#define SPR_THRM3 (0x3FE)
1854#define SPR_RCPU_FPECR (0x3FE)
1855#define SPR_403_PBL2 (0x3FE)
1856#define SPR_PIR (0x3FF)
1857#define SPR_403_PBU2 (0x3FF)
1858#define SPR_601_HID15 (0x3FF)
1859#define SPR_604_HID15 (0x3FF)
1860#define SPR_E500_SVR (0x3FF)
79aceca5 1861
84755ed5
AG		 1862/* Disable MAS Interrupt Updates for Hypervisor */
1863#define EPCR_DMIUH (1 << 22)
1864/* Disable Guest TLB Management Instructions */
1865#define EPCR_DGTMI (1 << 23)
1866/* Guest Interrupt Computation Mode */
1867#define EPCR_GICM (1 << 24)
1868/* Interrupt Computation Mode */
1869#define EPCR_ICM (1 << 25)
1870/* Disable Embedded Hypervisor Debug */
1871#define EPCR_DUVD (1 << 26)
1872/* Instruction Storage Interrupt Directed to Guest State */
1873#define EPCR_ISIGS (1 << 27)
1874/* Data Storage Interrupt Directed to Guest State */
1875#define EPCR_DSIGS (1 << 28)
1876/* Instruction TLB Error Interrupt Directed to Guest State */
1877#define EPCR_ITLBGS (1 << 29)
1878/* Data TLB Error Interrupt Directed to Guest State */
1879#define EPCR_DTLBGS (1 << 30)
1880/* External Input Interrupt Directed to Guest State */
1881#define EPCR_EXTGS (1 << 31)
1882
ea71258d
AG		 1883#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1884#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1885#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1886#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1887#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1888
1889#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1890#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1891#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1892#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1893#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1894
bbc01ca7 1895/* HID0 bits */
1488270e
BH		 1896#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1897#define HID0_DOZE (1 << 23) /* pre-2.06 */
1898#define HID0_NAP (1 << 22) /* pre-2.06 */
1899#define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
bbc01ca7 1900
c29b735c
NF		 1901/*****************************************************************************/
1902/* PowerPC Instructions types definitions */
1903enum {
1904 PPC_NONE = 0x0000000000000000ULL,
1905 /* PowerPC base instructions set */
1906 PPC_INSNS_BASE = 0x0000000000000001ULL,
1907 /* integer operations instructions */
1908#define PPC_INTEGER PPC_INSNS_BASE
1909 /* flow control instructions */
1910#define PPC_FLOW PPC_INSNS_BASE
1911 /* virtual memory instructions */
1912#define PPC_MEM PPC_INSNS_BASE
1913 /* ld/st with reservation instructions */
1914#define PPC_RES PPC_INSNS_BASE
1915 /* spr/msr access instructions */
1916#define PPC_MISC PPC_INSNS_BASE
1917 /* Deprecated instruction sets */
1918 /* Original POWER instruction set */
1919 PPC_POWER = 0x0000000000000002ULL,
1920 /* POWER2 instruction set extension */
1921 PPC_POWER2 = 0x0000000000000004ULL,
1922 /* Power RTC support */
1923 PPC_POWER_RTC = 0x0000000000000008ULL,
1924 /* Power-to-PowerPC bridge (601) */
1925 PPC_POWER_BR = 0x0000000000000010ULL,
1926 /* 64 bits PowerPC instruction set */
1927 PPC_64B = 0x0000000000000020ULL,
1928 /* New 64 bits extensions (PowerPC 2.0x) */
1929 PPC_64BX = 0x0000000000000040ULL,
1930 /* 64 bits hypervisor extensions */
1931 PPC_64H = 0x0000000000000080ULL,
1932 /* New wait instruction (PowerPC 2.0x) */
1933 PPC_WAIT = 0x0000000000000100ULL,
1934 /* Time base mftb instruction */
1935 PPC_MFTB = 0x0000000000000200ULL,
1936
1937 /* Fixed-point unit extensions */
1938 /* PowerPC 602 specific */
1939 PPC_602_SPEC = 0x0000000000000400ULL,
1940 /* isel instruction */
1941 PPC_ISEL = 0x0000000000000800ULL,
1942 /* popcntb instruction */
1943 PPC_POPCNTB = 0x0000000000001000ULL,
1944 /* string load / store */
1945 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 1946 /* real mode cache inhibited load / store */
1947 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 1948
1949 /* Floating-point unit extensions */
1950 /* Optional floating point instructions */
1951 PPC_FLOAT = 0x0000000000010000ULL,
1952 /* New floating-point extensions (PowerPC 2.0x) */
1953 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1954 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1955 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1956 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1957 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1958 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1959 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1960
1961 /* Vector/SIMD extensions */
1962 /* Altivec support */
1963 PPC_ALTIVEC = 0x0000000001000000ULL,
1964 /* PowerPC 2.03 SPE extension */
1965 PPC_SPE = 0x0000000002000000ULL,
1966 /* PowerPC 2.03 SPE single-precision floating-point extension */
1967 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1968 /* PowerPC 2.03 SPE double-precision floating-point extension */
1969 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1970
1971 /* Optional memory control instructions */
1972 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1973 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1974 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1975 /* sync instruction */
1976 PPC_MEM_SYNC = 0x0000000080000000ULL,
1977 /* eieio instruction */
1978 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1979
1980 /* Cache control instructions */
1981 PPC_CACHE = 0x0000000200000000ULL,
1982 /* icbi instruction */
1983 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 1984 /* dcbz instruction */
c29b735c 1985 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 1986 /* dcba instruction */
1987 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1988 /* Freescale cache locking instructions */
1989 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1990
1991 /* MMU related extensions */
1992 /* external control instructions */
1993 PPC_EXTERN = 0x0000010000000000ULL,
1994 /* segment register access instructions */
1995 PPC_SEGMENT = 0x0000020000000000ULL,
1996 /* PowerPC 6xx TLB management instructions */
1997 PPC_6xx_TLB = 0x0000040000000000ULL,
1998 /* PowerPC 74xx TLB management instructions */
1999 PPC_74xx_TLB = 0x0000080000000000ULL,
2000 /* PowerPC 40x TLB management instructions */
2001 PPC_40x_TLB = 0x0000100000000000ULL,
2002 /* segment register access instructions for PowerPC 64 "bridge" */
2003 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2004 /* SLB management */
2005 PPC_SLBI = 0x0000400000000000ULL,
2006
2007 /* Embedded PowerPC dedicated instructions */
2008 PPC_WRTEE = 0x0001000000000000ULL,
2009 /* PowerPC 40x exception model */
2010 PPC_40x_EXCP = 0x0002000000000000ULL,
2011 /* PowerPC 405 Mac instructions */
2012 PPC_405_MAC = 0x0004000000000000ULL,
2013 /* PowerPC 440 specific instructions */
2014 PPC_440_SPEC = 0x0008000000000000ULL,
2015 /* BookE (embedded) PowerPC specification */
2016 PPC_BOOKE = 0x0010000000000000ULL,
2017 /* mfapidi instruction */
2018 PPC_MFAPIDI = 0x0020000000000000ULL,
2019 /* tlbiva instruction */
2020 PPC_TLBIVA = 0x0040000000000000ULL,
2021 /* tlbivax instruction */
2022 PPC_TLBIVAX = 0x0080000000000000ULL,
2023 /* PowerPC 4xx dedicated instructions */
2024 PPC_4xx_COMMON = 0x0100000000000000ULL,
2025 /* PowerPC 40x ibct instructions */
2026 PPC_40x_ICBT = 0x0200000000000000ULL,
2027 /* rfmci is not implemented in all BookE PowerPC */
2028 PPC_RFMCI = 0x0400000000000000ULL,
2029 /* rfdi instruction */
2030 PPC_RFDI = 0x0800000000000000ULL,
2031 /* DCR accesses */
2032 PPC_DCR = 0x1000000000000000ULL,
2033 /* DCR extended accesse */
2034 PPC_DCRX = 0x2000000000000000ULL,
2035 /* user-mode DCR access, implemented in PowerPC 460 */
2036 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2037 /* popcntw and popcntd instructions */
2038 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2039
02d4eae4
DG		 2040#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2041 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2042 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2043 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2044 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2045 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2046 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2047 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2048 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2049 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2050 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2051 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2052 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2053 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2054 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2055 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2056 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2057 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2058 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2059 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2060 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2061 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2062 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2063
01662f3e
AG		 2064 /* extended type values */
2065
2066 /* BookE 2.06 PowerPC specification */
2067 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2068 /* VSX (extensions to Altivec / VMX) */
2069 PPC2_VSX = 0x0000000000000002ULL,
2070 /* Decimal Floating Point (DFP) */
2071 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2072 /* Embedded.Processor Control */
2073 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2074 /* Byte-reversed, indexed, double-word load and store */
2075 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2076 /* Book I 2.05 PowerPC specification */
2077 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2078 /* VSX additions in ISA 2.07 */
2079 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2080 /* ISA 2.06B bpermd */
2081 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2082 /* ISA 2.06B divide extended variants */
2083 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2084 /* ISA 2.06B larx/stcx. instructions */
2085 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2086 /* ISA 2.06B floating point integer conversion */
2087 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2088 /* ISA 2.06B floating point test instructions */
2089 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2090 /* ISA 2.07 bctar instruction */
2091 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2092 /* ISA 2.07 load/store quadword */
2093 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2094 /* ISA 2.07 Altivec */
2095 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2096 /* PowerISA 2.07 Book3s specification */
2097 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2098 /* Double precision floating point conversion for signed integer 64 */
2099 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2100 /* Transactional Memory (ISA 2.07, Book II) */
2101 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2102 /* Server PM instructgions (ISA 2.06, Book III) */
2103 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2104 /* POWER ISA 3.0 */
2105 PPC2_ISA300 = 0x0000000000080000ULL,
02d4eae4 2106
74f23997 2107#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2108 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2109 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2110 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2111 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2112 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13
ND		 2113 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2114 PPC2_ISA300)
c29b735c
NF		 2115};
2116
76a66253 2117/*****************************************************************************/
9a64fbe4
FB		 2118/* Memory access type :
2119 * may be needed for precise access rights control and precise exceptions.
2120 */
79aceca5 2121enum {
9a64fbe4
FB		 2122 /* 1 bit to define user level / supervisor access */
2123 ACCESS_USER = 0x00,
2124 ACCESS_SUPER = 0x01,
2125 /* Type of instruction that generated the access */
2126 ACCESS_CODE = 0x10, /* Code fetch access */
2127 ACCESS_INT = 0x20, /* Integer load/store access */
2128 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2129 ACCESS_RES = 0x40, /* load/store with reservation */
2130 ACCESS_EXT = 0x50, /* external access */
2131 ACCESS_CACHE = 0x60, /* Cache manipulation */
2132};
2133
47103572
JM		 2134/* Hardware interruption sources:
2135 * all those exception can be raised simulteaneously
2136 */
e9df014c
JM		 2137/* Input pins definitions */
2138enum {
2139 /* 6xx bus input pins */
24be5ae3
JM		 2140 PPC6xx_INPUT_HRESET = 0,
2141 PPC6xx_INPUT_SRESET = 1,
2142 PPC6xx_INPUT_CKSTP_IN = 2,
2143 PPC6xx_INPUT_MCP = 3,
2144 PPC6xx_INPUT_SMI = 4,
2145 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2146 PPC6xx_INPUT_TBEN = 6,
2147 PPC6xx_INPUT_WAKEUP = 7,
2148 PPC6xx_INPUT_NB,
24be5ae3
JM		 2149};
2150
2151enum {
e9df014c 2152 /* Embedded PowerPC input pins */
24be5ae3
JM		 2153 PPCBookE_INPUT_HRESET = 0,
2154 PPCBookE_INPUT_SRESET = 1,
2155 PPCBookE_INPUT_CKSTP_IN = 2,
2156 PPCBookE_INPUT_MCP = 3,
2157 PPCBookE_INPUT_SMI = 4,
2158 PPCBookE_INPUT_INT = 5,
2159 PPCBookE_INPUT_CINT = 6,
d68f1306 2160 PPCBookE_INPUT_NB,
24be5ae3
JM		 2161};
2162
9fdc60bf
AJ		 2163enum {
2164 /* PowerPC E500 input pins */
2165 PPCE500_INPUT_RESET_CORE = 0,
2166 PPCE500_INPUT_MCK = 1,
2167 PPCE500_INPUT_CINT = 3,
2168 PPCE500_INPUT_INT = 4,
2169 PPCE500_INPUT_DEBUG = 6,
2170 PPCE500_INPUT_NB,
2171};
2172
a750fc0b 2173enum {
4e290a0b
JM		 2174 /* PowerPC 40x input pins */
2175 PPC40x_INPUT_RESET_CORE = 0,
2176 PPC40x_INPUT_RESET_CHIP = 1,
2177 PPC40x_INPUT_RESET_SYS = 2,
2178 PPC40x_INPUT_CINT = 3,
2179 PPC40x_INPUT_INT = 4,
2180 PPC40x_INPUT_HALT = 5,
2181 PPC40x_INPUT_DEBUG = 6,
2182 PPC40x_INPUT_NB,
e9df014c
JM		 2183};
2184
b4095fed
JM		 2185enum {
2186 /* RCPU input pins */
2187 PPCRCPU_INPUT_PORESET = 0,
2188 PPCRCPU_INPUT_HRESET = 1,
2189 PPCRCPU_INPUT_SRESET = 2,
2190 PPCRCPU_INPUT_IRQ0 = 3,
2191 PPCRCPU_INPUT_IRQ1 = 4,
2192 PPCRCPU_INPUT_IRQ2 = 5,
2193 PPCRCPU_INPUT_IRQ3 = 6,
2194 PPCRCPU_INPUT_IRQ4 = 7,
2195 PPCRCPU_INPUT_IRQ5 = 8,
2196 PPCRCPU_INPUT_IRQ6 = 9,
2197 PPCRCPU_INPUT_IRQ7 = 10,
2198 PPCRCPU_INPUT_NB,
2199};
2200
00af685f 2201#if defined(TARGET_PPC64)
d0dfae6e
JM		 2202enum {
2203 /* PowerPC 970 input pins */
2204 PPC970_INPUT_HRESET = 0,
2205 PPC970_INPUT_SRESET = 1,
2206 PPC970_INPUT_CKSTP = 2,
2207 PPC970_INPUT_TBEN = 3,
2208 PPC970_INPUT_MCP = 4,
2209 PPC970_INPUT_INT = 5,
2210 PPC970_INPUT_THINT = 6,
7b62a955 2211 PPC970_INPUT_NB,
9d52e907
DG		 2212};
2213
2214enum {
2215 /* POWER7 input pins */
2216 POWER7_INPUT_INT = 0,
2217 /* POWER7 probably has other inputs, but we don't care about them
2218 * for any existing machine. We can wire these up when we need
2219 * them */
2220 POWER7_INPUT_NB,
d0dfae6e 2221};
00af685f 2222#endif
d0dfae6e 2223
e9df014c 2224/* Hardware exceptions definitions */
47103572 2225enum {
e9df014c 2226 /* External hardware exception sources */
e1833e1f 2227 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2228 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2229 PPC_INTERRUPT_MCK, /* Machine check exception */
2230 PPC_INTERRUPT_EXT, /* External interrupt */
2231 PPC_INTERRUPT_SMI, /* System management interrupt */
2232 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2233 PPC_INTERRUPT_DEBUG, /* External debug exception */
2234 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2235 /* Internal hardware exception sources */
d68f1306
JM		 2236 PPC_INTERRUPT_DECR, /* Decrementer exception */
2237 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2238 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2239 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2240 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2241 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2242 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2243 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
f03a1af5
BH		 2244 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2245 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
47103572
JM		 2246};
2247
6d9412ea
AK		 2248/* Processor Compatibility mask (PCR) */
2249enum {
2250 PCR_COMPAT_2_05 = 1ull << (63-62),
2251 PCR_COMPAT_2_06 = 1ull << (63-61),
8cd2ce7a 2252 PCR_COMPAT_2_07 = 1ull << (63-60),
6d9412ea
AK		 2253 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2254 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2255 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2256};
2257
1488270e
BH		 2258/* HMER/HMEER */
2259enum {
2260 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2261 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2262 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2263 HMER_TFAC_ERROR = 1ull << (63 - 4),
2264 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2265 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2266 HMER_XSCOM_DONE = 1ull << (63 - 9),
2267 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2268 HMER_WARN_RISE = 1ull << (63 - 14),
2269 HMER_WARN_FALL = 1ull << (63 - 15),
2270 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2271 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2272 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2273 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2274 HMER_XSCOM_STATUS_LSH = (63 - 23),
2275};
2276
5c94b2a5
CLG		 2277/* Alternate Interrupt Location (AIL) */
2278enum {
2279 AIL_NONE = 0,
2280 AIL_RESERVED = 1,
2281 AIL_0001_8000 = 2,
2282 AIL_C000_0000_0000_4000 = 3,
2283};
2284
9a64fbe4
FB		 2285/*****************************************************************************/
2286
da91a00f
RH		 2287static inline target_ulong cpu_read_xer(CPUPPCState *env)
2288{
2289 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2290}
2291
2292static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2293{
2294 env->so = (xer >> XER_SO) & 1;
2295 env->ov = (xer >> XER_OV) & 1;
2296 env->ca = (xer >> XER_CA) & 1;
2297 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2298}
2299
1328c2bf 2300static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2301 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2302{
2303 *pc = env->nip;
2304 *cs_base = 0;
2305 *flags = env->hflags;
2306}
2307
db789c6c
BH		 2308void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2309void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2310 uintptr_t raddr);
2311void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2312 uint32_t error_code);
2313void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2314 uint32_t error_code, uintptr_t raddr);
2315
01662f3e 2316#if !defined(CONFIG_USER_ONLY)
1328c2bf 2317static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2318{
d1e256fe 2319 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2320 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2321
1c53accc 2322 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2323}
2324
1328c2bf 2325static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2326{
2327 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2328 int r = tlbncfg & TLBnCFG_N_ENTRY;
2329 return r;
2330}
2331
1328c2bf 2332static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2333{
2334 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2335 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2336 return r;
2337}
2338
1328c2bf 2339static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2340{
d1e256fe 2341 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2342 int end = 0;
2343 int i;
2344
2345 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2346 end += booke206_tlb_size(env, i);
2347 if (id < end) {
2348 return i;
2349 }
2350 }
2351
a47dddd7 2352 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2353 return 0;
2354}
2355
1328c2bf 2356static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2357{
d1e256fe
AG		 2358 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2359 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2360 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2361}
2362
1328c2bf 2363static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2364 target_ulong ea, int way)
2365{
2366 int r;
2367 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2368 int ways_bits = ctz32(ways);
2369 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2370 int i;
2371
2372 way &= ways - 1;
2373 ea >>= MAS2_EPN_SHIFT;
2374 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2375 r = (ea << ways_bits) | way;
2376
3f162d11
AG		 2377 if (r >= booke206_tlb_size(env, tlbn)) {
2378 return NULL;
2379 }
2380
01662f3e
AG		 2381 /* bump up to tlbn index */
2382 for (i = 0; i < tlbn; i++) {
2383 r += booke206_tlb_size(env, i);
2384 }
2385
1c53accc 2386 return &env->tlb.tlbm[r];
01662f3e
AG		 2387}
2388
a1ef618a 2389/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2390static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a
AG		 2391{
2392 bool mav2 = false;
2393 uint32_t ret = 0;
2394
2395 if (mav2) {
2396 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2397 } else {
2398 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2399 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2400 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2401 int i;
2402 for (i = min; i <= max; i++) {
2403 ret |= (1 << (i << 1));
2404 }
2405 }
2406
2407 return ret;
2408}
2409
01662f3e
AG		 2410#endif
2411
e42a61f1
AG		 2412static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2413{
2414 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2415 return msr & (1ULL << MSR_CM);
2416 }
2417
2418 return msr & (1ULL << MSR_SF);
2419}
2420
afbee712
TH		 2421/**
2422 * Check whether register rx is in the range between start and
2423 * start + nregs (as needed by the LSWX and LSWI instructions)
2424 */
2425static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2426{
2427 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2428 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2429}
2430
1b14670a 2431extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
d569956e 2432
1328c2bf 2433void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2434
0ce470cd
AK		 2435/**
2436 * ppc_get_vcpu_dt_id:
2437 * @cs: a PowerPCCPU struct.
2438 *
2439 * Returns a device-tree ID for a CPU.
2440 */
2441int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2442
2443/**
2444 * ppc_get_vcpu_by_dt_id:
2445 * @cpu_dt_id: a device tree id
2446 *
2447 * Searches for a CPU by @cpu_dt_id.
2448 *
2449 * Returns: a PowerPCCPU struct
2450 */
2451PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2452
376dbce0 2453void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
07f5a258 2454#endif /* PPC_CPU_H */
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