[qemu.git] / target-sh4 / helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
#include "hw/sh_intc.h"

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
  env->exception_index = -1;
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    env->tea = address;
    env->exception_index = 0;
    switch (rw) {
    case 0:
        env->exception_index = 0x0a0;
        break;
    case 1:
        env->exception_index = 0x0c0;
        break;
    case 2:
        env->exception_index = 0x0a0;
        break;
    }
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

#else /* !CONFIG_USER_ONLY */

#define MMU_OK                   0
#define MMU_ITLB_MISS            (-1)
#define MMU_ITLB_MULTIPLE        (-2)
#define MMU_ITLB_VIOLATION       (-3)
#define MMU_DTLB_MISS_READ       (-4)
#define MMU_DTLB_MISS_WRITE      (-5)
#define MMU_DTLB_INITIAL_WRITE   (-6)
#define MMU_DTLB_VIOLATION_READ  (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE        (-9)
#define MMU_DTLB_MISS            (-10)
#define MMU_IADDR_ERROR          (-11)
#define MMU_DADDR_ERROR_READ     (-12)
#define MMU_DADDR_ERROR_WRITE    (-13)

void do_interrupt(CPUState * env)
{
    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
    int do_exp, irq_vector = env->exception_index;

    /* prioritize exceptions over interrupts */

    do_exp = env->exception_index != -1;
    do_irq = do_irq && (env->exception_index == -1);

    if (env->sr & SR_BL) {
        if (do_exp && env->exception_index != 0x1e0) {
            env->exception_index = 0x000; /* masked exception -> reset */
        }
        if (do_irq && !env->intr_at_halt) {
            return; /* masked */
        }
        env->intr_at_halt = 0;
    }

    if (do_irq) {
        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
						(env->sr >> 4) & 0xf);
        if (irq_vector == -1) {
            return; /* masked */
	}
    }

    if (qemu_loglevel_mask(CPU_LOG_INT)) {
	const char *expname;
	switch (env->exception_index) {
	case 0x0e0:
	    expname = "addr_error";
	    break;
	case 0x040:
	    expname = "tlb_miss";
	    break;
	case 0x0a0:
	    expname = "tlb_violation";
	    break;
	case 0x180:
	    expname = "illegal_instruction";
	    break;
	case 0x1a0:
	    expname = "slot_illegal_instruction";
	    break;
	case 0x800:
	    expname = "fpu_disable";
	    break;
	case 0x820:
	    expname = "slot_fpu";
	    break;
	case 0x100:
	    expname = "data_write";
	    break;
	case 0x060:
	    expname = "dtlb_miss_write";
	    break;
	case 0x0c0:
	    expname = "dtlb_violation_write";
	    break;
	case 0x120:
	    expname = "fpu_exception";
	    break;
	case 0x080:
	    expname = "initial_page_write";
	    break;
	case 0x160:
	    expname = "trapa";
	    break;
	default:
            expname = do_irq ? "interrupt" : "???";
            break;
	}
	qemu_log("exception 0x%03x [%s] raised\n",
		  irq_vector, expname);
	log_cpu_state(env, 0);
    }

    env->ssr = env->sr;
    env->spc = env->pc;
    env->sgr = env->gregs[15];
    env->sr |= SR_BL | SR_MD | SR_RB;

    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
        /* Branch instruction should be executed again before delay slot. */
	env->spc -= 2;
	/* Clear flags for exception/interrupt routine. */
	env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
    }
    if (env->flags & DELAY_SLOT_CLEARME)
        env->flags = 0;

    if (do_exp) {
        env->expevt = env->exception_index;
        switch (env->exception_index) {
        case 0x000:
        case 0x020:
        case 0x140:
            env->sr &= ~SR_FD;
            env->sr |= 0xf << 4; /* IMASK */
            env->pc = 0xa0000000;
            break;
        case 0x040:
        case 0x060:
            env->pc = env->vbr + 0x400;
            break;
        case 0x160:
            env->spc += 2; /* special case for TRAPA */
            /* fall through */
        default:
            env->pc = env->vbr + 0x100;
            break;
        }
        return;
    }

    if (do_irq) {
        env->intevt = irq_vector;
        env->pc = env->vbr + 0x600;
        return;
    }
}

static void update_itlb_use(CPUState * env, int itlbnb)
{
    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;

    switch (itlbnb) {
    case 0:
	and_mask = 0x1f;
	break;
    case 1:
	and_mask = 0xe7;
	or_mask = 0x80;
	break;
    case 2:
	and_mask = 0xfb;
	or_mask = 0x50;
	break;
    case 3:
	or_mask = 0x2c;
	break;
    }

    env->mmucr &= (and_mask << 24) | 0x00ffffff;
    env->mmucr |= (or_mask << 24);
}

static int itlb_replacement(CPUState * env)
{
    if ((env->mmucr & 0xe0000000) == 0xe0000000)
	return 0;
    if ((env->mmucr & 0x98000000) == 0x18000000)
	return 1;
    if ((env->mmucr & 0x54000000) == 0x04000000)
	return 2;
    if ((env->mmucr & 0x2c000000) == 0x00000000)
	return 3;
    assert(0);
}

/* Find the corresponding entry in the right TLB
   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
			  tlb_t * entries, uint8_t nbtlb, int use_asid)
{
    int match = MMU_DTLB_MISS;
    uint32_t start, end;
    uint8_t asid;
    int i;

    asid = env->pteh & 0xff;

    for (i = 0; i < nbtlb; i++) {
	if (!entries[i].v)
	    continue;		/* Invalid entry */
	if (!entries[i].sh && use_asid && entries[i].asid != asid)
	    continue;		/* Bad ASID */
#if 0
	switch (entries[i].sz) {
	case 0:
	    size = 1024;	/* 1kB */
	    break;
	case 1:
	    size = 4 * 1024;	/* 4kB */
	    break;
	case 2:
	    size = 64 * 1024;	/* 64kB */
	    break;
	case 3:
	    size = 1024 * 1024;	/* 1MB */
	    break;
	default:
	    assert(0);
	}
#endif
	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	end = start + entries[i].size - 1;
	if (address >= start && address <= end) {	/* Match */
	    if (match != MMU_DTLB_MISS)
		return MMU_DTLB_MULTIPLE;	/* Multiple match */
	    match = i;
	}
    }
    return match;
}

static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
				 const tlb_t * needle)
{
    int i;
    for (i = 0; i < nbtlb; i++)
        if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	    return 1;
    return 0;
}

static void increment_urc(CPUState * env)
{
    uint8_t urb, urc;

    /* Increment URC */
    urb = ((env->mmucr) >> 18) & 0x3f;
    urc = ((env->mmucr) >> 10) & 0x3f;
    urc++;
    if (urc == urb || urc == UTLB_SIZE)
	urc = 0;
    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
}

/* Find itlb entry - update itlb from utlb if necessary and asked for
   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
   Update the itlb from utlb if update is not 0
*/
static int find_itlb_entry(CPUState * env, target_ulong address,
                           int use_asid, int update)
{
    int e, n;

    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
    if (e == MMU_DTLB_MULTIPLE)
	e = MMU_ITLB_MULTIPLE;
    else if (e == MMU_DTLB_MISS && update) {
	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	if (e >= 0) {
	    tlb_t * ientry;
	    n = itlb_replacement(env);
	    ientry = &env->itlb[n];
	    if (ientry->v) {
		if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
		    tlb_flush_page(env, ientry->vpn << 10);
	    }
	    *ientry = env->utlb[e];
	    e = n;
	} else if (e == MMU_DTLB_MISS)
	    e = MMU_ITLB_MISS;
    } else if (e == MMU_DTLB_MISS)
	e = MMU_ITLB_MISS;
    if (e >= 0)
	update_itlb_use(env, e);
    return e;
}

/* Find utlb entry
   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
    /* per utlb access */
    increment_urc(env);

    /* Return entry */
    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}

/* Match address against MMU
   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
   MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
			   int *prot, target_ulong address,
			   int rw, int access_type)
{
    int use_asid, n;
    tlb_t *matching = NULL;

    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;

    if (rw == 2) {
	n = find_itlb_entry(env, address, use_asid, 1);
	if (n >= 0) {
	    matching = &env->itlb[n];
	    if ((env->sr & SR_MD) & !(matching->pr & 2))
		n = MMU_ITLB_VIOLATION;
	    else
		*prot = PAGE_READ;
	}
    } else {
	n = find_utlb_entry(env, address, use_asid);
	if (n >= 0) {
	    matching = &env->utlb[n];
	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
	    case 0:		/* 000 */
	    case 2:		/* 010 */
		n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
		    MMU_DTLB_VIOLATION_READ;
		break;
	    case 1:		/* 001 */
	    case 4:		/* 100 */
	    case 5:		/* 101 */
		if (rw == 1)
		    n = MMU_DTLB_VIOLATION_WRITE;
		else
		    *prot = PAGE_READ;
		break;
	    case 3:		/* 011 */
	    case 6:		/* 110 */
	    case 7:		/* 111 */
		*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
		break;
	    }
	} else if (n == MMU_DTLB_MISS) {
	    n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
    }
    if (n >= 0) {
	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
	    (address & (matching->size - 1));
	if ((rw == 1) & !matching->d)
	    n = MMU_DTLB_INITIAL_WRITE;
	else
	    n = MMU_OK;
    }
    return n;
}

static int get_physical_address(CPUState * env, target_ulong * physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* P1, P2 and P4 areas do not use translation */
    if ((address >= 0x80000000 && address < 0xc0000000) ||
	address >= 0xe0000000) {
	if (!(env->sr & SR_MD)
	    && (address < 0xe0000000 || address > 0xe4000000)) {
	    /* Unauthorized access in user mode (only store queues are available) */
	    fprintf(stderr, "Unauthorized access\n");
	    if (rw == 0)
		return MMU_DADDR_ERROR_READ;
	    else if (rw == 1)
		return MMU_DADDR_ERROR_WRITE;
	    else
		return MMU_IADDR_ERROR;
	}
	if (address >= 0x80000000 && address < 0xc0000000) {
	    /* Mask upper 3 bits for P1 and P2 areas */
	    *physical = address & 0x1fffffff;
	} else {
	    *physical = address;
	}
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* If MMU is disabled, return the corresponding physical page */
    if (!env->mmucr & MMUCR_AT) {
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* We need to resort to the MMU */
    return get_mmu_address(env, physical, prot, address, rw, access_type);
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    target_ulong physical, page_offset, page_size;
    int prot, ret, access_type;

    access_type = ACCESS_INT;
    ret =
	get_physical_address(env, &physical, &prot, address, rw,
			     access_type);

    if (ret != MMU_OK) {
	env->tea = address;
	switch (ret) {
	case MMU_ITLB_MISS:
	case MMU_DTLB_MISS_READ:
	    env->exception_index = 0x040;
	    break;
	case MMU_DTLB_MULTIPLE:
	case MMU_ITLB_MULTIPLE:
	    env->exception_index = 0x140;
	    break;
	case MMU_ITLB_VIOLATION:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_MISS_WRITE:
	    env->exception_index = 0x060;
	    break;
	case MMU_DTLB_INITIAL_WRITE:
	    env->exception_index = 0x080;
	    break;
	case MMU_DTLB_VIOLATION_READ:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_VIOLATION_WRITE:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_IADDR_ERROR:
	case MMU_DADDR_ERROR_READ:
	    env->exception_index = 0x0c0;
	    break;
	case MMU_DADDR_ERROR_WRITE:
	    env->exception_index = 0x100;
	    break;
	default:
	    assert(0);
	}
	return 1;
    }

    page_size = TARGET_PAGE_SIZE;
    page_offset =
	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
    address = (address & TARGET_PAGE_MASK) + page_offset;
    physical = (physical & TARGET_PAGE_MASK) + page_offset;

    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong physical;
    int prot;

    get_physical_address(env, &physical, &prot, addr, 0, 0);
    return physical;
}

void cpu_load_tlb(CPUSH4State * env)
{
    int n = cpu_mmucr_urc(env->mmucr);
    tlb_t * entry = &env->utlb[n];

    if (entry->v) {
        /* Overwriting valid entry in utlb. */
        target_ulong address = entry->vpn << 10;
	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	    tlb_flush_page(env, address);
	}
    }

    /* Take values into cpu status from registers. */
    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
    entry->vpn  = cpu_pteh_vpn(env->pteh);
    entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
    entry->ppn  = cpu_ptel_ppn(env->ptel);
    entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
    switch (entry->sz) {
    case 0: /* 00 */
        entry->size = 1024; /* 1K */
        break;
    case 1: /* 01 */
        entry->size = 1024 * 4; /* 4K */
        break;
    case 2: /* 10 */
        entry->size = 1024 * 64; /* 64K */
        break;
    case 3: /* 11 */
        entry->size = 1024 * 1024; /* 1M */
        break;
    default:
        assert(0);
        break;
    }
    entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
    entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
    entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
    entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
    entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
    entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
    entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
}

void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value)
{
    int associate = addr & 0x0000080;
    uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
    uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
    uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
    uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
    int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;

    if (associate) {
        int i;
	tlb_t * utlb_match_entry = NULL;
	int needs_tlb_flush = 0;

	/* search UTLB */
	for (i = 0; i < UTLB_SIZE; i++) {
            tlb_t * entry = &s->utlb[i];
            if (!entry->v)
	        continue;

            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (utlb_match_entry) {
		    /* Multiple TLB Exception */
		    s->exception_index = 0x140;
		    s->tea = addr;
		    break;
	        }
		if (entry->v && !v)
		    needs_tlb_flush = 1;
		entry->v = v;
		entry->d = d;
	        utlb_match_entry = entry;
	    }
	    increment_urc(s); /* per utlb access */
	}

	/* search ITLB */
	for (i = 0; i < ITLB_SIZE; i++) {
            tlb_t * entry = &s->itlb[i];
            if (entry->vpn == vpn
                && (!use_asid || entry->asid == asid || entry->sh)) {
	        if (entry->v && !v)
		    needs_tlb_flush = 1;
	        if (utlb_match_entry)
		    *entry = *utlb_match_entry;
	        else
		    entry->v = v;
		break;
	    }
	}

	if (needs_tlb_flush)
	    tlb_flush_page(s, vpn << 10);
        
    } else {
        int index = (addr & 0x00003f00) >> 8;
        tlb_t * entry = &s->utlb[index];
	if (entry->v) {
	    /* Overwriting valid entry in utlb. */
            target_ulong address = entry->vpn << 10;
	    if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	        tlb_flush_page(s, address);
	    }
	}
	entry->asid = asid;
	entry->vpn = vpn;
	entry->d = d;
	entry->v = v;
	increment_urc(s);
    }
}

#endif
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
fad6cb1a	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
fdf9b3e8 FB	19	*/
	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e96e2044	30	#include "hw/sh_intc.h"
fdf9b3e8	31
355fb23d PB	32	#if defined(CONFIG_USER_ONLY)
	33
	34	void do_interrupt (CPUState *env)
	35	{
	36	env->exception_index = -1;
	37	}
	38
	39	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	40	int mmu_idx, int is_softmmu)
355fb23d PB	41	{
355fb23d PB	42	env->tea = address;
c3b5bc8a	43	env->exception_index = 0;
355fb23d PB	44	switch (rw) {
	45	case 0:
	46	env->exception_index = 0x0a0;
	47	break;
	48	case 1:
	49	env->exception_index = 0x0c0;
	50	break;
cf7055bd AJ	51	case 2:
	52	env->exception_index = 0x0a0;
	53	break;
355fb23d PB	54	}
	55	return 1;
	56	}
	57
9b3c35e0	58	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	59	{
	60	return addr;
	61	}
	62
	63	#else /* !CONFIG_USER_ONLY */
	64
fdf9b3e8 FB	65	#define MMU_OK 0
	66	#define MMU_ITLB_MISS (-1)
	67	#define MMU_ITLB_MULTIPLE (-2)
	68	#define MMU_ITLB_VIOLATION (-3)
	69	#define MMU_DTLB_MISS_READ (-4)
	70	#define MMU_DTLB_MISS_WRITE (-5)
	71	#define MMU_DTLB_INITIAL_WRITE (-6)
	72	#define MMU_DTLB_VIOLATION_READ (-7)
	73	#define MMU_DTLB_VIOLATION_WRITE (-8)
	74	#define MMU_DTLB_MULTIPLE (-9)
	75	#define MMU_DTLB_MISS (-10)
cf7055bd AJ	76	#define MMU_IADDR_ERROR (-11)
	77	#define MMU_DADDR_ERROR_READ (-12)
	78	#define MMU_DADDR_ERROR_WRITE (-13)
fdf9b3e8 FB	79
	80	void do_interrupt(CPUState * env)
	81	{
e96e2044 TS	82	int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
	83	int do_exp, irq_vector = env->exception_index;
	84
	85	/* prioritize exceptions over interrupts */
	86
	87	do_exp = env->exception_index != -1;
	88	do_irq = do_irq && (env->exception_index == -1);
	89
	90	if (env->sr & SR_BL) {
	91	if (do_exp && env->exception_index != 0x1e0) {
	92	env->exception_index = 0x000; /* masked exception -> reset */
	93	}
833ed386	94	if (do_irq && !env->intr_at_halt) {
e96e2044 TS	95	return; /* masked */
e96e2044 TS	96	}
833ed386	97	env->intr_at_halt = 0;
e96e2044 TS	98	}
	99
	100	if (do_irq) {
	101	irq_vector = sh_intc_get_pending_vector(env->intc_handle,
	102	(env->sr >> 4) & 0xf);
	103	if (irq_vector == -1) {
	104	return; /* masked */
	105	}
	106	}
	107
8fec2b8c	108	if (qemu_loglevel_mask(CPU_LOG_INT)) {
fdf9b3e8 FB	109	const char *expname;
	110	switch (env->exception_index) {
	111	case 0x0e0:
	112	expname = "addr_error";
	113	break;
	114	case 0x040:
	115	expname = "tlb_miss";
	116	break;
	117	case 0x0a0:
	118	expname = "tlb_violation";
	119	break;
	120	case 0x180:
	121	expname = "illegal_instruction";
	122	break;
	123	case 0x1a0:
	124	expname = "slot_illegal_instruction";
	125	break;
	126	case 0x800:
	127	expname = "fpu_disable";
	128	break;
	129	case 0x820:
	130	expname = "slot_fpu";
	131	break;
	132	case 0x100:
	133	expname = "data_write";
	134	break;
	135	case 0x060:
	136	expname = "dtlb_miss_write";
	137	break;
	138	case 0x0c0:
	139	expname = "dtlb_violation_write";
	140	break;
	141	case 0x120:
	142	expname = "fpu_exception";
	143	break;
	144	case 0x080:
	145	expname = "initial_page_write";
	146	break;
	147	case 0x160:
	148	expname = "trapa";
	149	break;
	150	default:
e96e2044 TS	151	expname = do_irq ? "interrupt" : "???";
e96e2044 TS	152	break;
fdf9b3e8	153	}
93fcfe39 AL	154	qemu_log("exception 0x%03x [%s] raised\n",
	155	irq_vector, expname);
	156	log_cpu_state(env, 0);
fdf9b3e8 FB	157	}
	158
	159	env->ssr = env->sr;
e96e2044	160	env->spc = env->pc;
fdf9b3e8 FB	161	env->sgr = env->gregs[15];
	162	env->sr \|= SR_BL \| SR_MD \| SR_RB;
	163
274a9e70 AJ	164	if (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL)) {
	165	/* Branch instruction should be executed again before delay slot. */
	166	env->spc -= 2;
	167	/* Clear flags for exception/interrupt routine. */
	168	env->flags &= ~(DELAY_SLOT \| DELAY_SLOT_CONDITIONAL \| DELAY_SLOT_TRUE);
	169	}
	170	if (env->flags & DELAY_SLOT_CLEARME)
	171	env->flags = 0;
	172
e96e2044 TS	173	if (do_exp) {
	174	env->expevt = env->exception_index;
	175	switch (env->exception_index) {
	176	case 0x000:
	177	case 0x020:
	178	case 0x140:
	179	env->sr &= ~SR_FD;
	180	env->sr \|= 0xf << 4; /* IMASK */
	181	env->pc = 0xa0000000;
	182	break;
	183	case 0x040:
	184	case 0x060:
	185	env->pc = env->vbr + 0x400;
	186	break;
	187	case 0x160:
	188	env->spc += 2; /* special case for TRAPA */
	189	/* fall through */
	190	default:
	191	env->pc = env->vbr + 0x100;
	192	break;
	193	}
	194	return;
	195	}
	196
	197	if (do_irq) {
	198	env->intevt = irq_vector;
	199	env->pc = env->vbr + 0x600;
	200	return;
fdf9b3e8 FB	201	}
	202	}
	203
	204	static void update_itlb_use(CPUState * env, int itlbnb)
	205	{
	206	uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
	207
	208	switch (itlbnb) {
	209	case 0:
ea2b542a	210	and_mask = 0x1f;
fdf9b3e8 FB	211	break;
	212	case 1:
	213	and_mask = 0xe7;
	214	or_mask = 0x80;
	215	break;
	216	case 2:
	217	and_mask = 0xfb;
	218	or_mask = 0x50;
	219	break;
	220	case 3:
	221	or_mask = 0x2c;
	222	break;
	223	}
	224
ea2b542a	225	env->mmucr &= (and_mask << 24) \| 0x00ffffff;
fdf9b3e8 FB	226	env->mmucr \|= (or_mask << 24);
	227	}
	228
	229	static int itlb_replacement(CPUState * env)
	230	{
	231	if ((env->mmucr & 0xe0000000) == 0xe0000000)
	232	return 0;
ea2b542a	233	if ((env->mmucr & 0x98000000) == 0x18000000)
fdf9b3e8 FB	234	return 1;
	235	if ((env->mmucr & 0x54000000) == 0x04000000)
	236	return 2;
	237	if ((env->mmucr & 0x2c000000) == 0x00000000)
	238	return 3;
	239	assert(0);
	240	}
	241
	242	/* Find the corresponding entry in the right TLB
	243	Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
	244	*/
	245	static int find_tlb_entry(CPUState * env, target_ulong address,
	246	tlb_t * entries, uint8_t nbtlb, int use_asid)
	247	{
	248	int match = MMU_DTLB_MISS;
	249	uint32_t start, end;
	250	uint8_t asid;
	251	int i;
	252
	253	asid = env->pteh & 0xff;
	254
	255	for (i = 0; i < nbtlb; i++) {
	256	if (!entries[i].v)
	257	continue; /* Invalid entry */
eeda6778	258	if (!entries[i].sh && use_asid && entries[i].asid != asid)
fdf9b3e8 FB	259	continue; /* Bad ASID */
	260	#if 0
	261	switch (entries[i].sz) {
	262	case 0:
	263	size = 1024; /* 1kB */
	264	break;
	265	case 1:
	266	size = 4 * 1024; /* 4kB */
	267	break;
	268	case 2:
	269	size = 64 * 1024; /* 64kB */
	270	break;
	271	case 3:
	272	size = 1024 * 1024; /* 1MB */
	273	break;
	274	default:
	275	assert(0);
	276	}
	277	#endif
	278	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	279	end = start + entries[i].size - 1;
	280	if (address >= start && address <= end) { /* Match */
ea2b542a	281	if (match != MMU_DTLB_MISS)
fdf9b3e8 FB	282	return MMU_DTLB_MULTIPLE; /* Multiple match */
	283	match = i;
	284	}
	285	}
	286	return match;
	287	}
	288
29e179bc AJ	289	static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
	290	const tlb_t * needle)
	291	{
	292	int i;
	293	for (i = 0; i < nbtlb; i++)
	294	if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
	295	return 1;
	296	return 0;
	297	}
	298
	299	static void increment_urc(CPUState * env)
	300	{
	301	uint8_t urb, urc;
	302
	303	/* Increment URC */
	304	urb = ((env->mmucr) >> 18) & 0x3f;
	305	urc = ((env->mmucr) >> 10) & 0x3f;
	306	urc++;
fb104582	307	if (urc == urb \|\| urc == UTLB_SIZE)
29e179bc AJ	308	urc = 0;
	309	env->mmucr = (env->mmucr & 0xffff03ff) \| (urc << 10);
	310	}
	311
fdf9b3e8 FB	312	/* Find itlb entry - update itlb from utlb if necessary and asked for
	313	Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
	314	Update the itlb from utlb if update is not 0
	315	*/
ef7ec1c1 AJ	316	static int find_itlb_entry(CPUState * env, target_ulong address,
ef7ec1c1 AJ	317	int use_asid, int update)
fdf9b3e8 FB	318	{
	319	int e, n;
	320
	321	e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
	322	if (e == MMU_DTLB_MULTIPLE)
	323	e = MMU_ITLB_MULTIPLE;
	324	else if (e == MMU_DTLB_MISS && update) {
	325	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	326	if (e >= 0) {
06afe2c8	327	tlb_t * ientry;
fdf9b3e8	328	n = itlb_replacement(env);
06afe2c8 AJ	329	ientry = &env->itlb[n];
	330	if (ientry->v) {
	331	if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
	332	tlb_flush_page(env, ientry->vpn << 10);
	333	}
	334	*ientry = env->utlb[e];
fdf9b3e8	335	e = n;
ea2b542a AJ	336	} else if (e == MMU_DTLB_MISS)
	337	e = MMU_ITLB_MISS;
	338	} else if (e == MMU_DTLB_MISS)
	339	e = MMU_ITLB_MISS;
fdf9b3e8 FB	340	if (e >= 0)
	341	update_itlb_use(env, e);
	342	return e;
	343	}
	344
	345	/* Find utlb entry
	346	Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
ef7ec1c1	347	static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
fdf9b3e8	348	{
29e179bc AJ	349	/* per utlb access */
29e179bc AJ	350	increment_urc(env);
fdf9b3e8 FB	351
	352	/* Return entry */
	353	return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	354	}
	355
	356	/* Match address against MMU
	357	Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
	358	MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
	359	MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
cf7055bd AJ	360	MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
cf7055bd AJ	361	MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
fdf9b3e8 FB	362	*/
	363	static int get_mmu_address(CPUState * env, target_ulong * physical,
	364	int *prot, target_ulong address,
	365	int rw, int access_type)
	366	{
cf7055bd	367	int use_asid, n;
fdf9b3e8 FB	368	tlb_t *matching = NULL;
fdf9b3e8 FB	369
06afe2c8	370	use_asid = (env->mmucr & MMUCR_SV) == 0 \|\| (env->sr & SR_MD) == 0;
fdf9b3e8	371
cf7055bd	372	if (rw == 2) {
fdf9b3e8 FB	373	n = find_itlb_entry(env, address, use_asid, 1);
	374	if (n >= 0) {
	375	matching = &env->itlb[n];
	376	if ((env->sr & SR_MD) & !(matching->pr & 2))
	377	n = MMU_ITLB_VIOLATION;
	378	else
	379	*prot = PAGE_READ;
	380	}
	381	} else {
	382	n = find_utlb_entry(env, address, use_asid);
	383	if (n >= 0) {
	384	matching = &env->utlb[n];
	385	switch ((matching->pr << 1) \| ((env->sr & SR_MD) ? 1 : 0)) {
	386	case 0: /* 000 */
	387	case 2: /* 010 */
cf7055bd	388	n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
fdf9b3e8 FB	389	MMU_DTLB_VIOLATION_READ;
	390	break;
	391	case 1: /* 001 */
	392	case 4: /* 100 */
	393	case 5: /* 101 */
cf7055bd	394	if (rw == 1)
fdf9b3e8 FB	395	n = MMU_DTLB_VIOLATION_WRITE;
	396	else
	397	*prot = PAGE_READ;
	398	break;
	399	case 3: /* 011 */
	400	case 6: /* 110 */
	401	case 7: /* 111 */
cf7055bd	402	*prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
fdf9b3e8 FB	403	break;
	404	}
	405	} else if (n == MMU_DTLB_MISS) {
cf7055bd	406	n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
fdf9b3e8 FB	407	MMU_DTLB_MISS_READ;
	408	}
	409	}
	410	if (n >= 0) {
	411	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) \|
	412	(address & (matching->size - 1));
cf7055bd	413	if ((rw == 1) & !matching->d)
fdf9b3e8 FB	414	n = MMU_DTLB_INITIAL_WRITE;
	415	else
	416	n = MMU_OK;
	417	}
	418	return n;
	419	}
	420
ef7ec1c1 AJ	421	static int get_physical_address(CPUState * env, target_ulong * physical,
	422	int *prot, target_ulong address,
	423	int rw, int access_type)
fdf9b3e8 FB	424	{
	425	/* P1, P2 and P4 areas do not use translation */
	426	if ((address >= 0x80000000 && address < 0xc0000000) \|\|
	427	address >= 0xe0000000) {
	428	if (!(env->sr & SR_MD)
	429	&& (address < 0xe0000000 \|\| address > 0xe4000000)) {
	430	/* Unauthorized access in user mode (only store queues are available) */
	431	fprintf(stderr, "Unauthorized access\n");
cf7055bd AJ	432	if (rw == 0)
	433	return MMU_DADDR_ERROR_READ;
	434	else if (rw == 1)
	435	return MMU_DADDR_ERROR_WRITE;
	436	else
	437	return MMU_IADDR_ERROR;
fdf9b3e8	438	}
29e179bc AJ	439	if (address >= 0x80000000 && address < 0xc0000000) {
	440	/* Mask upper 3 bits for P1 and P2 areas */
	441	*physical = address & 0x1fffffff;
29e179bc	442	} else {
29e179bc AJ	443	*physical = address;
29e179bc AJ	444	}
fdf9b3e8 FB	445	*prot = PAGE_READ \| PAGE_WRITE;
	446	return MMU_OK;
	447	}
	448
	449	/* If MMU is disabled, return the corresponding physical page */
	450	if (!env->mmucr & MMUCR_AT) {
	451	*physical = address & 0x1FFFFFFF;
	452	*prot = PAGE_READ \| PAGE_WRITE;
	453	return MMU_OK;
	454	}
	455
	456	/* We need to resort to the MMU */
	457	return get_mmu_address(env, physical, prot, address, rw, access_type);
	458	}
	459
	460	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	461	int mmu_idx, int is_softmmu)
fdf9b3e8 FB	462	{
	463	target_ulong physical, page_offset, page_size;
	464	int prot, ret, access_type;
	465
fdf9b3e8 FB	466	access_type = ACCESS_INT;
	467	ret =
	468	get_physical_address(env, &physical, &prot, address, rw,
	469	access_type);
	470
	471	if (ret != MMU_OK) {
	472	env->tea = address;
	473	switch (ret) {
	474	case MMU_ITLB_MISS:
	475	case MMU_DTLB_MISS_READ:
	476	env->exception_index = 0x040;
	477	break;
	478	case MMU_DTLB_MULTIPLE:
	479	case MMU_ITLB_MULTIPLE:
	480	env->exception_index = 0x140;
	481	break;
	482	case MMU_ITLB_VIOLATION:
	483	env->exception_index = 0x0a0;
	484	break;
	485	case MMU_DTLB_MISS_WRITE:
	486	env->exception_index = 0x060;
	487	break;
	488	case MMU_DTLB_INITIAL_WRITE:
	489	env->exception_index = 0x080;
	490	break;
	491	case MMU_DTLB_VIOLATION_READ:
	492	env->exception_index = 0x0a0;
	493	break;
	494	case MMU_DTLB_VIOLATION_WRITE:
	495	env->exception_index = 0x0c0;
	496	break;
cf7055bd AJ	497	case MMU_IADDR_ERROR:
	498	case MMU_DADDR_ERROR_READ:
	499	env->exception_index = 0x0c0;
	500	break;
	501	case MMU_DADDR_ERROR_WRITE:
	502	env->exception_index = 0x100;
	503	break;
fdf9b3e8 FB	504	default:
	505	assert(0);
	506	}
	507	return 1;
	508	}
	509
	510	page_size = TARGET_PAGE_SIZE;
	511	page_offset =
	512	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
	513	address = (address & TARGET_PAGE_MASK) + page_offset;
	514	physical = (physical & TARGET_PAGE_MASK) + page_offset;
	515
6ebbf390	516	return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
fdf9b3e8	517	}
355fb23d	518
9b3c35e0	519	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	520	{
	521	target_ulong physical;
	522	int prot;
	523
cf7055bd	524	get_physical_address(env, &physical, &prot, addr, 0, 0);
355fb23d PB	525	return physical;
	526	}
	527
ef7ec1c1	528	void cpu_load_tlb(CPUSH4State * env)
ea2b542a AJ	529	{
	530	int n = cpu_mmucr_urc(env->mmucr);
	531	tlb_t * entry = &env->utlb[n];
	532
06afe2c8 AJ	533	if (entry->v) {
	534	/* Overwriting valid entry in utlb. */
	535	target_ulong address = entry->vpn << 10;
	536	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
	537	tlb_flush_page(env, address);
	538	}
	539	}
	540
ea2b542a AJ	541	/* Take values into cpu status from registers. */
	542	entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
	543	entry->vpn = cpu_pteh_vpn(env->pteh);
	544	entry->v = (uint8_t)cpu_ptel_v(env->ptel);
	545	entry->ppn = cpu_ptel_ppn(env->ptel);
	546	entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
	547	switch (entry->sz) {
	548	case 0: /* 00 */
	549	entry->size = 1024; /* 1K */
	550	break;
	551	case 1: /* 01 */
	552	entry->size = 1024 * 4; /* 4K */
	553	break;
	554	case 2: /* 10 */
	555	entry->size = 1024 * 64; /* 64K */
	556	break;
	557	case 3: /* 11 */
	558	entry->size = 1024 * 1024; /* 1M */
	559	break;
	560	default:
	561	assert(0);
	562	break;
	563	}
	564	entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
	565	entry->c = (uint8_t)cpu_ptel_c(env->ptel);
	566	entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
	567	entry->d = (uint8_t)cpu_ptel_d(env->ptel);
	568	entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
	569	entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
	570	entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
	571	}
	572
29e179bc AJ	573	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
	574	uint32_t mem_value)
	575	{
	576	int associate = addr & 0x0000080;
	577	uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
	578	uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
	579	uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
	580	uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
eeda6778	581	int use_asid = (s->mmucr & MMUCR_SV) == 0 \|\| (s->sr & SR_MD) == 0;
29e179bc AJ	582
	583	if (associate) {
	584	int i;
	585	tlb_t * utlb_match_entry = NULL;
	586	int needs_tlb_flush = 0;
	587
	588	/* search UTLB */
	589	for (i = 0; i < UTLB_SIZE; i++) {
	590	tlb_t * entry = &s->utlb[i];
	591	if (!entry->v)
	592	continue;
	593
eeda6778 AJ	594	if (entry->vpn == vpn
eeda6778 AJ	595	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	596	if (utlb_match_entry) {
	597	/* Multiple TLB Exception */
	598	s->exception_index = 0x140;
	599	s->tea = addr;
	600	break;
	601	}
	602	if (entry->v && !v)
	603	needs_tlb_flush = 1;
	604	entry->v = v;
	605	entry->d = d;
	606	utlb_match_entry = entry;
	607	}
	608	increment_urc(s); /* per utlb access */
	609	}
	610
	611	/* search ITLB */
	612	for (i = 0; i < ITLB_SIZE; i++) {
	613	tlb_t * entry = &s->itlb[i];
eeda6778 AJ	614	if (entry->vpn == vpn
eeda6778 AJ	615	&& (!use_asid \|\| entry->asid == asid \|\| entry->sh)) {
29e179bc AJ	616	if (entry->v && !v)
	617	needs_tlb_flush = 1;
	618	if (utlb_match_entry)
	619	entry = utlb_match_entry;
	620	else
	621	entry->v = v;
	622	break;
	623	}
	624	}
	625
	626	if (needs_tlb_flush)
	627	tlb_flush_page(s, vpn << 10);
	628
	629	} else {
	630	int index = (addr & 0x00003f00) >> 8;
	631	tlb_t * entry = &s->utlb[index];
	632	if (entry->v) {
	633	/* Overwriting valid entry in utlb. */
	634	target_ulong address = entry->vpn << 10;
	635	if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
	636	tlb_flush_page(s, address);
	637	}
	638	}
	639	entry->asid = asid;
	640	entry->vpn = vpn;
	641	entry->d = d;
	642	entry->v = v;
	643	increment_urc(s);
	644	}
	645	}
	646
355fb23d	647	#endif