[qemu.git] / target-sh4 / helper.c

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"
#include "hw/sh_intc.h"

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
  env->exception_index = -1;
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    env->tea = address;
    env->exception_index = 0;
    switch (rw) {
    case 0:
	env->tea = address;
        env->exception_index = 0x0a0;
        break;
    case 1:
	env->tea = address;
        env->exception_index = 0x0c0;
        break;
    }
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

#else /* !CONFIG_USER_ONLY */

#define MMU_OK                   0
#define MMU_ITLB_MISS            (-1)
#define MMU_ITLB_MULTIPLE        (-2)
#define MMU_ITLB_VIOLATION       (-3)
#define MMU_DTLB_MISS_READ       (-4)
#define MMU_DTLB_MISS_WRITE      (-5)
#define MMU_DTLB_INITIAL_WRITE   (-6)
#define MMU_DTLB_VIOLATION_READ  (-7)
#define MMU_DTLB_VIOLATION_WRITE (-8)
#define MMU_DTLB_MULTIPLE        (-9)
#define MMU_DTLB_MISS            (-10)

void do_interrupt(CPUState * env)
{
    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
    int do_exp, irq_vector = env->exception_index;

    /* prioritize exceptions over interrupts */

    do_exp = env->exception_index != -1;
    do_irq = do_irq && (env->exception_index == -1);

    if (env->sr & SR_BL) {
        if (do_exp && env->exception_index != 0x1e0) {
            env->exception_index = 0x000; /* masked exception -> reset */
        }
        if (do_irq) {
            return; /* masked */
        }
    }

    if (do_irq) {
        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
						(env->sr >> 4) & 0xf);
        if (irq_vector == -1) {
            return; /* masked */
	}
    }

    if (loglevel & CPU_LOG_INT) {
	const char *expname;
	switch (env->exception_index) {
	case 0x0e0:
	    expname = "addr_error";
	    break;
	case 0x040:
	    expname = "tlb_miss";
	    break;
	case 0x0a0:
	    expname = "tlb_violation";
	    break;
	case 0x180:
	    expname = "illegal_instruction";
	    break;
	case 0x1a0:
	    expname = "slot_illegal_instruction";
	    break;
	case 0x800:
	    expname = "fpu_disable";
	    break;
	case 0x820:
	    expname = "slot_fpu";
	    break;
	case 0x100:
	    expname = "data_write";
	    break;
	case 0x060:
	    expname = "dtlb_miss_write";
	    break;
	case 0x0c0:
	    expname = "dtlb_violation_write";
	    break;
	case 0x120:
	    expname = "fpu_exception";
	    break;
	case 0x080:
	    expname = "initial_page_write";
	    break;
	case 0x160:
	    expname = "trapa";
	    break;
	default:
            expname = do_irq ? "interrupt" : "???";
            break;
	}
	fprintf(logfile, "exception 0x%03x [%s] raised\n",
		irq_vector, expname);
	cpu_dump_state(env, logfile, fprintf, 0);
    }

    env->ssr = env->sr;
    env->spc = env->pc;
    env->sgr = env->gregs[15];
    env->sr |= SR_BL | SR_MD | SR_RB;

    if (do_exp) {
        env->expevt = env->exception_index;
        switch (env->exception_index) {
        case 0x000:
        case 0x020:
        case 0x140:
            env->sr &= ~SR_FD;
            env->sr |= 0xf << 4; /* IMASK */
            env->pc = 0xa0000000;
            break;
        case 0x040:
        case 0x060:
            env->pc = env->vbr + 0x400;
            break;
        case 0x160:
            env->spc += 2; /* special case for TRAPA */
            /* fall through */
        default:
            env->pc = env->vbr + 0x100;
            break;
        }
        return;
    }

    if (do_irq) {
        env->intevt = irq_vector;
        env->pc = env->vbr + 0x600;
        return;
    }
}

static void update_itlb_use(CPUState * env, int itlbnb)
{
    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;

    switch (itlbnb) {
    case 0:
	and_mask = 0x7f;
	break;
    case 1:
	and_mask = 0xe7;
	or_mask = 0x80;
	break;
    case 2:
	and_mask = 0xfb;
	or_mask = 0x50;
	break;
    case 3:
	or_mask = 0x2c;
	break;
    }

    env->mmucr &= (and_mask << 24);
    env->mmucr |= (or_mask << 24);
}

static int itlb_replacement(CPUState * env)
{
    if ((env->mmucr & 0xe0000000) == 0xe0000000)
	return 0;
    if ((env->mmucr & 0x98000000) == 0x08000000)
	return 1;
    if ((env->mmucr & 0x54000000) == 0x04000000)
	return 2;
    if ((env->mmucr & 0x2c000000) == 0x00000000)
	return 3;
    assert(0);
}

/* Find the corresponding entry in the right TLB
   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
static int find_tlb_entry(CPUState * env, target_ulong address,
			  tlb_t * entries, uint8_t nbtlb, int use_asid)
{
    int match = MMU_DTLB_MISS;
    uint32_t start, end;
    uint8_t asid;
    int i;

    asid = env->pteh & 0xff;

    for (i = 0; i < nbtlb; i++) {
	if (!entries[i].v)
	    continue;		/* Invalid entry */
	if (use_asid && entries[i].asid != asid && !entries[i].sh)
	    continue;		/* Bad ASID */
#if 0
	switch (entries[i].sz) {
	case 0:
	    size = 1024;	/* 1kB */
	    break;
	case 1:
	    size = 4 * 1024;	/* 4kB */
	    break;
	case 2:
	    size = 64 * 1024;	/* 64kB */
	    break;
	case 3:
	    size = 1024 * 1024;	/* 1MB */
	    break;
	default:
	    assert(0);
	}
#endif
	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
	end = start + entries[i].size - 1;
	if (address >= start && address <= end) {	/* Match */
	    if (match != -1)
		return MMU_DTLB_MULTIPLE;	/* Multiple match */
	    match = i;
	}
    }
    return match;
}

/* Find itlb entry - update itlb from utlb if necessary and asked for
   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
   Update the itlb from utlb if update is not 0
*/
int find_itlb_entry(CPUState * env, target_ulong address,
		    int use_asid, int update)
{
    int e, n;

    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
    if (e == MMU_DTLB_MULTIPLE)
	e = MMU_ITLB_MULTIPLE;
    else if (e == MMU_DTLB_MISS && update) {
	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
	if (e >= 0) {
	    n = itlb_replacement(env);
	    env->itlb[n] = env->utlb[e];
	    e = n;
	}
    }
    if (e >= 0)
	update_itlb_use(env, e);
    return e;
}

/* Find utlb entry
   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
    uint8_t urb, urc;

    /* Increment URC */
    urb = ((env->mmucr) >> 18) & 0x3f;
    urc = ((env->mmucr) >> 10) & 0x3f;
    urc++;
    if (urc == urb || urc == UTLB_SIZE - 1)
	urc = 0;
    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);

    /* Return entry */
    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
}

/* Match address against MMU
   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
*/
static int get_mmu_address(CPUState * env, target_ulong * physical,
			   int *prot, target_ulong address,
			   int rw, int access_type)
{
    int use_asid, is_code, n;
    tlb_t *matching = NULL;

    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
    is_code = env->pc == address;	/* Hack */

    /* Use a hack to find if this is an instruction or data access */
    if (env->pc == address && !(rw & PAGE_WRITE)) {
	n = find_itlb_entry(env, address, use_asid, 1);
	if (n >= 0) {
	    matching = &env->itlb[n];
	    if ((env->sr & SR_MD) & !(matching->pr & 2))
		n = MMU_ITLB_VIOLATION;
	    else
		*prot = PAGE_READ;
	}
    } else {
	n = find_utlb_entry(env, address, use_asid);
	if (n >= 0) {
	    matching = &env->utlb[n];
	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
	    case 0:		/* 000 */
	    case 2:		/* 010 */
		n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
		    MMU_DTLB_VIOLATION_READ;
		break;
	    case 1:		/* 001 */
	    case 4:		/* 100 */
	    case 5:		/* 101 */
		if (rw & PAGE_WRITE)
		    n = MMU_DTLB_VIOLATION_WRITE;
		else
		    *prot = PAGE_READ;
		break;
	    case 3:		/* 011 */
	    case 6:		/* 110 */
	    case 7:		/* 111 */
		*prot = rw & (PAGE_READ | PAGE_WRITE);
		break;
	    }
	} else if (n == MMU_DTLB_MISS) {
	    n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
    }
    if (n >= 0) {
	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
	    (address & (matching->size - 1));
	if ((rw & PAGE_WRITE) & !matching->d)
	    n = MMU_DTLB_INITIAL_WRITE;
	else
	    n = MMU_OK;
    }
    return n;
}

int get_physical_address(CPUState * env, target_ulong * physical,
			 int *prot, target_ulong address,
			 int rw, int access_type)
{
    /* P1, P2 and P4 areas do not use translation */
    if ((address >= 0x80000000 && address < 0xc0000000) ||
	address >= 0xe0000000) {
	if (!(env->sr & SR_MD)
	    && (address < 0xe0000000 || address > 0xe4000000)) {
	    /* Unauthorized access in user mode (only store queues are available) */
	    fprintf(stderr, "Unauthorized access\n");
	    return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
		MMU_DTLB_MISS_READ;
	}
	/* Mask upper 3 bits */
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* If MMU is disabled, return the corresponding physical page */
    if (!env->mmucr & MMUCR_AT) {
	*physical = address & 0x1FFFFFFF;
	*prot = PAGE_READ | PAGE_WRITE;
	return MMU_OK;
    }

    /* We need to resort to the MMU */
    return get_mmu_address(env, physical, prot, address, rw, access_type);
}

int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu)
{
    target_ulong physical, page_offset, page_size;
    int prot, ret, access_type;

    /* XXXXX */
#if 0
    fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
	    __func__, env->pc, address, rw, mmu_idx, is_softmmu);
#endif

    access_type = ACCESS_INT;
    ret =
	get_physical_address(env, &physical, &prot, address, rw,
			     access_type);

    if (ret != MMU_OK) {
	env->tea = address;
	switch (ret) {
	case MMU_ITLB_MISS:
	case MMU_DTLB_MISS_READ:
	    env->exception_index = 0x040;
	    break;
	case MMU_DTLB_MULTIPLE:
	case MMU_ITLB_MULTIPLE:
	    env->exception_index = 0x140;
	    break;
	case MMU_ITLB_VIOLATION:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_MISS_WRITE:
	    env->exception_index = 0x060;
	    break;
	case MMU_DTLB_INITIAL_WRITE:
	    env->exception_index = 0x080;
	    break;
	case MMU_DTLB_VIOLATION_READ:
	    env->exception_index = 0x0a0;
	    break;
	case MMU_DTLB_VIOLATION_WRITE:
	    env->exception_index = 0x0c0;
	    break;
	default:
	    assert(0);
	}
	return 1;
    }

    page_size = TARGET_PAGE_SIZE;
    page_offset =
	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
    address = (address & TARGET_PAGE_MASK) + page_offset;
    physical = (physical & TARGET_PAGE_MASK) + page_offset;

    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong physical;
    int prot;

    get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
    return physical;
}

#endif
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e96e2044	30	#include "hw/sh_intc.h"
fdf9b3e8	31
355fb23d PB	32	#if defined(CONFIG_USER_ONLY)
	33
	34	void do_interrupt (CPUState *env)
	35	{
	36	env->exception_index = -1;
	37	}
	38
	39	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	40	int mmu_idx, int is_softmmu)
355fb23d PB	41	{
355fb23d PB	42	env->tea = address;
c3b5bc8a	43	env->exception_index = 0;
355fb23d PB	44	switch (rw) {
355fb23d PB	45	case 0:
c3b5bc8a	46	env->tea = address;
355fb23d PB	47	env->exception_index = 0x0a0;
	48	break;
	49	case 1:
c3b5bc8a	50	env->tea = address;
355fb23d PB	51	env->exception_index = 0x0c0;
355fb23d PB	52	break;
355fb23d PB	53	}
	54	return 1;
	55	}
	56
9b3c35e0	57	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	58	{
	59	return addr;
	60	}
	61
	62	#else /* !CONFIG_USER_ONLY */
	63
fdf9b3e8 FB	64	#define MMU_OK 0
	65	#define MMU_ITLB_MISS (-1)
	66	#define MMU_ITLB_MULTIPLE (-2)
	67	#define MMU_ITLB_VIOLATION (-3)
	68	#define MMU_DTLB_MISS_READ (-4)
	69	#define MMU_DTLB_MISS_WRITE (-5)
	70	#define MMU_DTLB_INITIAL_WRITE (-6)
	71	#define MMU_DTLB_VIOLATION_READ (-7)
	72	#define MMU_DTLB_VIOLATION_WRITE (-8)
	73	#define MMU_DTLB_MULTIPLE (-9)
	74	#define MMU_DTLB_MISS (-10)
	75
	76	void do_interrupt(CPUState * env)
	77	{
e96e2044 TS	78	int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
	79	int do_exp, irq_vector = env->exception_index;
	80
	81	/* prioritize exceptions over interrupts */
	82
	83	do_exp = env->exception_index != -1;
	84	do_irq = do_irq && (env->exception_index == -1);
	85
	86	if (env->sr & SR_BL) {
	87	if (do_exp && env->exception_index != 0x1e0) {
	88	env->exception_index = 0x000; /* masked exception -> reset */
	89	}
	90	if (do_irq) {
	91	return; /* masked */
	92	}
	93	}
	94
	95	if (do_irq) {
	96	irq_vector = sh_intc_get_pending_vector(env->intc_handle,
	97	(env->sr >> 4) & 0xf);
	98	if (irq_vector == -1) {
	99	return; /* masked */
	100	}
	101	}
	102
fdf9b3e8 FB	103	if (loglevel & CPU_LOG_INT) {
	104	const char *expname;
	105	switch (env->exception_index) {
	106	case 0x0e0:
	107	expname = "addr_error";
	108	break;
	109	case 0x040:
	110	expname = "tlb_miss";
	111	break;
	112	case 0x0a0:
	113	expname = "tlb_violation";
	114	break;
	115	case 0x180:
	116	expname = "illegal_instruction";
	117	break;
	118	case 0x1a0:
	119	expname = "slot_illegal_instruction";
	120	break;
	121	case 0x800:
	122	expname = "fpu_disable";
	123	break;
	124	case 0x820:
	125	expname = "slot_fpu";
	126	break;
	127	case 0x100:
	128	expname = "data_write";
	129	break;
	130	case 0x060:
	131	expname = "dtlb_miss_write";
	132	break;
	133	case 0x0c0:
	134	expname = "dtlb_violation_write";
	135	break;
	136	case 0x120:
	137	expname = "fpu_exception";
	138	break;
	139	case 0x080:
	140	expname = "initial_page_write";
	141	break;
	142	case 0x160:
	143	expname = "trapa";
	144	break;
	145	default:
e96e2044 TS	146	expname = do_irq ? "interrupt" : "???";
e96e2044 TS	147	break;
fdf9b3e8 FB	148	}
fdf9b3e8 FB	149	fprintf(logfile, "exception 0x%03x [%s] raised\n",
e96e2044	150	irq_vector, expname);
fdf9b3e8 FB	151	cpu_dump_state(env, logfile, fprintf, 0);
	152	}
	153
	154	env->ssr = env->sr;
e96e2044	155	env->spc = env->pc;
fdf9b3e8 FB	156	env->sgr = env->gregs[15];
	157	env->sr \|= SR_BL \| SR_MD \| SR_RB;
	158
e96e2044 TS	159	if (do_exp) {
	160	env->expevt = env->exception_index;
	161	switch (env->exception_index) {
	162	case 0x000:
	163	case 0x020:
	164	case 0x140:
	165	env->sr &= ~SR_FD;
	166	env->sr \|= 0xf << 4; /* IMASK */
	167	env->pc = 0xa0000000;
	168	break;
	169	case 0x040:
	170	case 0x060:
	171	env->pc = env->vbr + 0x400;
	172	break;
	173	case 0x160:
	174	env->spc += 2; /* special case for TRAPA */
	175	/* fall through */
	176	default:
	177	env->pc = env->vbr + 0x100;
	178	break;
	179	}
	180	return;
	181	}
	182
	183	if (do_irq) {
	184	env->intevt = irq_vector;
	185	env->pc = env->vbr + 0x600;
	186	return;
fdf9b3e8 FB	187	}
	188	}
	189
	190	static void update_itlb_use(CPUState * env, int itlbnb)
	191	{
	192	uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
	193
	194	switch (itlbnb) {
	195	case 0:
	196	and_mask = 0x7f;
	197	break;
	198	case 1:
	199	and_mask = 0xe7;
	200	or_mask = 0x80;
	201	break;
	202	case 2:
	203	and_mask = 0xfb;
	204	or_mask = 0x50;
	205	break;
	206	case 3:
	207	or_mask = 0x2c;
	208	break;
	209	}
	210
	211	env->mmucr &= (and_mask << 24);
	212	env->mmucr \|= (or_mask << 24);
	213	}
	214
	215	static int itlb_replacement(CPUState * env)
	216	{
	217	if ((env->mmucr & 0xe0000000) == 0xe0000000)
	218	return 0;
	219	if ((env->mmucr & 0x98000000) == 0x08000000)
	220	return 1;
	221	if ((env->mmucr & 0x54000000) == 0x04000000)
	222	return 2;
	223	if ((env->mmucr & 0x2c000000) == 0x00000000)
	224	return 3;
	225	assert(0);
	226	}
	227
	228	/* Find the corresponding entry in the right TLB
	229	Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
	230	*/
	231	static int find_tlb_entry(CPUState * env, target_ulong address,
	232	tlb_t * entries, uint8_t nbtlb, int use_asid)
	233	{
	234	int match = MMU_DTLB_MISS;
	235	uint32_t start, end;
	236	uint8_t asid;
	237	int i;
	238
	239	asid = env->pteh & 0xff;
	240
	241	for (i = 0; i < nbtlb; i++) {
	242	if (!entries[i].v)
	243	continue; /* Invalid entry */
	244	if (use_asid && entries[i].asid != asid && !entries[i].sh)
	245	continue; /* Bad ASID */
	246	#if 0
	247	switch (entries[i].sz) {
	248	case 0:
	249	size = 1024; /* 1kB */
	250	break;
251	case 1:
252	size = 4 * 1024; /* 4kB */
253	break;
254	case 2:
255	size = 64 * 1024; /* 64kB */
256	break;
257	case 3:
258	size = 1024 * 1024; /* 1MB */
259	break;
260	default:
261	assert(0);
262	}
263	#endif
264	start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
265	end = start + entries[i].size - 1;
266	if (address >= start && address <= end) { /* Match */
267	if (match != -1)
268	return MMU_DTLB_MULTIPLE; /* Multiple match */
269	match = i;
270	}
271	}
272	return match;
273	}
274
275	/* Find itlb entry - update itlb from utlb if necessary and asked for
276	Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
277	Update the itlb from utlb if update is not 0
278	*/
279	int find_itlb_entry(CPUState * env, target_ulong address,
280	int use_asid, int update)
281	{
282	int e, n;
283
284	e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
285	if (e == MMU_DTLB_MULTIPLE)
286	e = MMU_ITLB_MULTIPLE;
287	else if (e == MMU_DTLB_MISS && update) {
288	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
289	if (e >= 0) {
290	n = itlb_replacement(env);
291	env->itlb[n] = env->utlb[e];
292	e = n;
293	}
294	}
295	if (e >= 0)
296	update_itlb_use(env, e);
297	return e;
298	}
299
300	/* Find utlb entry
301	Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
302	int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
303	{
304	uint8_t urb, urc;
305
306	/* Increment URC */
307	urb = ((env->mmucr) >> 18) & 0x3f;
308	urc = ((env->mmucr) >> 10) & 0x3f;
309	urc++;
310	if (urc == urb \|\| urc == UTLB_SIZE - 1)
311	urc = 0;
312	env->mmucr = (env->mmucr & 0xffff03ff) \| (urc << 10);
313
314	/* Return entry */
315	return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
316	}
317
318	/* Match address against MMU
319	Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
320	MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
321	MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
322	MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
323	*/
324	static int get_mmu_address(CPUState * env, target_ulong * physical,
325	int *prot, target_ulong address,
326	int rw, int access_type)
327	{
328	int use_asid, is_code, n;
329	tlb_t *matching = NULL;
330
331	use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
332	is_code = env->pc == address; /* Hack */
333
334	/* Use a hack to find if this is an instruction or data access */
335	if (env->pc == address && !(rw & PAGE_WRITE)) {
336	n = find_itlb_entry(env, address, use_asid, 1);
337	if (n >= 0) {
338	matching = &env->itlb[n];
339	if ((env->sr & SR_MD) & !(matching->pr & 2))
340	n = MMU_ITLB_VIOLATION;
341	else
342	*prot = PAGE_READ;
343	}
344	} else {
345	n = find_utlb_entry(env, address, use_asid);
346	if (n >= 0) {
347	matching = &env->utlb[n];
348	switch ((matching->pr << 1) \| ((env->sr & SR_MD) ? 1 : 0)) {
349	case 0: /* 000 */
350	case 2: /* 010 */
351	n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
352	MMU_DTLB_VIOLATION_READ;
353	break;
354	case 1: /* 001 */
355	case 4: /* 100 */
356	case 5: /* 101 */
357	if (rw & PAGE_WRITE)
358	n = MMU_DTLB_VIOLATION_WRITE;
359	else
360	*prot = PAGE_READ;
361	break;
362	case 3: /* 011 */
363	case 6: /* 110 */
364	case 7: /* 111 */
365	*prot = rw & (PAGE_READ \| PAGE_WRITE);
366	break;
367	}
368	} else if (n == MMU_DTLB_MISS) {
369	n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
370	MMU_DTLB_MISS_READ;
371	}
372	}
373	if (n >= 0) {
374	*physical = ((matching->ppn << 10) & ~(matching->size - 1)) \|
375	(address & (matching->size - 1));
376	if ((rw & PAGE_WRITE) & !matching->d)
377	n = MMU_DTLB_INITIAL_WRITE;
378	else
379	n = MMU_OK;
380	}
381	return n;
382	}
383
384	int get_physical_address(CPUState * env, target_ulong * physical,
385	int *prot, target_ulong address,
386	int rw, int access_type)
387	{
388	/* P1, P2 and P4 areas do not use translation */
389	if ((address >= 0x80000000 && address < 0xc0000000) \|\|
390	address >= 0xe0000000) {
391	if (!(env->sr & SR_MD)
392	&& (address < 0xe0000000 \|\| address > 0xe4000000)) {
393	/* Unauthorized access in user mode (only store queues are available) */
394	fprintf(stderr, "Unauthorized access\n");
395	return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
396	MMU_DTLB_MISS_READ;
397	}
398	/* Mask upper 3 bits */
399	*physical = address & 0x1FFFFFFF;
400	*prot = PAGE_READ \| PAGE_WRITE;
401	return MMU_OK;
402	}
403
404	/* If MMU is disabled, return the corresponding physical page */
405	if (!env->mmucr & MMUCR_AT) {
406	*physical = address & 0x1FFFFFFF;
407	*prot = PAGE_READ \| PAGE_WRITE;
408	return MMU_OK;
409	}
410
411	/* We need to resort to the MMU */
412	return get_mmu_address(env, physical, prot, address, rw, access_type);
413	}
414
415	int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	416	int mmu_idx, int is_softmmu)
fdf9b3e8 FB	417	{
	418	target_ulong physical, page_offset, page_size;
	419	int prot, ret, access_type;
	420
	421	/* XXXXX */
	422	#if 0
6ebbf390 JM	423	fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
6ebbf390 JM	424	__func__, env->pc, address, rw, mmu_idx, is_softmmu);
fdf9b3e8 FB	425	#endif
	426
	427	access_type = ACCESS_INT;
	428	ret =
	429	get_physical_address(env, &physical, &prot, address, rw,
	430	access_type);
	431
	432	if (ret != MMU_OK) {
	433	env->tea = address;
	434	switch (ret) {
	435	case MMU_ITLB_MISS:
	436	case MMU_DTLB_MISS_READ:
	437	env->exception_index = 0x040;
	438	break;
	439	case MMU_DTLB_MULTIPLE:
	440	case MMU_ITLB_MULTIPLE:
	441	env->exception_index = 0x140;
	442	break;
	443	case MMU_ITLB_VIOLATION:
	444	env->exception_index = 0x0a0;
	445	break;
	446	case MMU_DTLB_MISS_WRITE:
	447	env->exception_index = 0x060;
	448	break;
	449	case MMU_DTLB_INITIAL_WRITE:
	450	env->exception_index = 0x080;
	451	break;
	452	case MMU_DTLB_VIOLATION_READ:
	453	env->exception_index = 0x0a0;
	454	break;
	455	case MMU_DTLB_VIOLATION_WRITE:
	456	env->exception_index = 0x0c0;
	457	break;
	458	default:
	459	assert(0);
	460	}
	461	return 1;
	462	}
	463
	464	page_size = TARGET_PAGE_SIZE;
	465	page_offset =
	466	(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
	467	address = (address & TARGET_PAGE_MASK) + page_offset;
	468	physical = (physical & TARGET_PAGE_MASK) + page_offset;
	469
6ebbf390	470	return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
fdf9b3e8	471	}
355fb23d	472
9b3c35e0	473	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
355fb23d PB	474	{
	475	target_ulong physical;
	476	int prot;
	477
	478	get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
	479	return physical;
	480	}
	481
	482	#endif