[qemu.git] / hw / eccmemctl.c

/*
 * QEMU Sparc Sun4m ECC memory controller emulation
 *
 * Copyright (c) 2007 Robert Reif
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"

//#define DEBUG_ECC

#ifdef DEBUG_ECC
#define DPRINTF(fmt, ...)                                       \
    do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

/* There are 3 versions of this chip used in SMP sun4m systems:
 * MCC (version 0, implementation 0) SS-600MP
 * EMC (version 0, implementation 1) SS-10
 * SMC (version 0, implementation 2) SS-10SX and SS-20
 *
 * Chipset docs:
 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
 */

#define ECC_MCC        0x00000000
#define ECC_EMC        0x10000000
#define ECC_SMC        0x20000000

/* Register indexes */
#define ECC_MER        0               /* Memory Enable Register */
#define ECC_MDR        1               /* Memory Delay Register */
#define ECC_MFSR       2               /* Memory Fault Status Register */
#define ECC_VCR        3               /* Video Configuration Register */
#define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
#define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
#define ECC_DR         6               /* Diagnostic Register */
#define ECC_ECR0       7               /* Event Count Register 0 */
#define ECC_ECR1       8               /* Event Count Register 1 */

/* ECC fault control register */
#define ECC_MER_EE     0x00000001      /* Enable ECC checking */
#define ECC_MER_EI     0x00000002      /* Enable Interrupts on
                                          correctable errors */
#define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
#define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
#define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
#define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
#define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
#define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
#define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
#define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
#define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
#define ECC_MER_MRR    0x000003fc      /* MRR mask */
#define ECC_MER_A      0x00000400      /* Memory controller addr map select */
#define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
#define ECC_MER_VER    0x0f000000      /* Version */
#define ECC_MER_IMPL   0xf0000000      /* Implementation */
#define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
#define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
#define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */

/* ECC memory delay register */
#define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
#define ECC_MDR_MI     0x00001c00      /* MIH Delay */
#define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
#define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
#define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
#define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
#define ECC_MDR_RSC    0x80000000      /* Refresh load control */
#define ECC_MDR_MASK   0x7fffffff

/* ECC fault status register */
#define ECC_MFSR_CE    0x00000001      /* Correctable error */
#define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
#define ECC_MFSR_TO    0x00000004      /* Timeout on write */
#define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
#define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
#define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
#define ECC_MFSR_ME    0x00010000      /* Multiple errors */
#define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */

/* ECC fault address register 0 */
#define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
#define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
#define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
#define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
#define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
#define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
#define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
#define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
#define ECC_MFARO_MID   0xf0000000     /* Module ID */

/* ECC diagnostic register */
#define ECC_DR_CBX     0x00000001
#define ECC_DR_CB0     0x00000002
#define ECC_DR_CB1     0x00000004
#define ECC_DR_CB2     0x00000008
#define ECC_DR_CB4     0x00000010
#define ECC_DR_CB8     0x00000020
#define ECC_DR_CB16    0x00000040
#define ECC_DR_CB32    0x00000080
#define ECC_DR_DMODE   0x00000c00

#define ECC_NREGS      9
#define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))

#define ECC_DIAG_SIZE  4
#define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)

typedef struct ECCState {
    SysBusDevice busdev;
    qemu_irq irq;
    uint32_t regs[ECC_NREGS];
    uint8_t diag[ECC_DIAG_SIZE];
    uint32_t version;
} ECCState;

static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    ECCState *s = opaque;

    switch (addr >> 2) {
    case ECC_MER:
        if (s->version == ECC_MCC)
            s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
        else if (s->version == ECC_EMC)
            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
        else if (s->version == ECC_SMC)
            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
        DPRINTF("Write memory enable %08x\n", val);
        break;
    case ECC_MDR:
        s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
        DPRINTF("Write memory delay %08x\n", val);
        break;
    case ECC_MFSR:
        s->regs[ECC_MFSR] =  val;
        qemu_irq_lower(s->irq);
        DPRINTF("Write memory fault status %08x\n", val);
        break;
    case ECC_VCR:
        s->regs[ECC_VCR] =  val;
        DPRINTF("Write slot configuration %08x\n", val);
        break;
    case ECC_DR:
        s->regs[ECC_DR] =  val;
        DPRINTF("Write diagnostic %08x\n", val);
        break;
    case ECC_ECR0:
        s->regs[ECC_ECR0] =  val;
        DPRINTF("Write event count 1 %08x\n", val);
        break;
    case ECC_ECR1:
        s->regs[ECC_ECR0] =  val;
        DPRINTF("Write event count 2 %08x\n", val);
        break;
    }
}

static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
{
    ECCState *s = opaque;
    uint32_t ret = 0;

    switch (addr >> 2) {
    case ECC_MER:
        ret = s->regs[ECC_MER];
        DPRINTF("Read memory enable %08x\n", ret);
        break;
    case ECC_MDR:
        ret = s->regs[ECC_MDR];
        DPRINTF("Read memory delay %08x\n", ret);
        break;
    case ECC_MFSR:
        ret = s->regs[ECC_MFSR];
        DPRINTF("Read memory fault status %08x\n", ret);
        break;
    case ECC_VCR:
        ret = s->regs[ECC_VCR];
        DPRINTF("Read slot configuration %08x\n", ret);
        break;
    case ECC_MFAR0:
        ret = s->regs[ECC_MFAR0];
        DPRINTF("Read memory fault address 0 %08x\n", ret);
        break;
    case ECC_MFAR1:
        ret = s->regs[ECC_MFAR1];
        DPRINTF("Read memory fault address 1 %08x\n", ret);
        break;
    case ECC_DR:
        ret = s->regs[ECC_DR];
        DPRINTF("Read diagnostic %08x\n", ret);
        break;
    case ECC_ECR0:
        ret = s->regs[ECC_ECR0];
        DPRINTF("Read event count 1 %08x\n", ret);
        break;
    case ECC_ECR1:
        ret = s->regs[ECC_ECR0];
        DPRINTF("Read event count 2 %08x\n", ret);
        break;
    }
    return ret;
}

static CPUReadMemoryFunc * const ecc_mem_read[3] = {
    NULL,
    NULL,
    ecc_mem_readl,
};

static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
    NULL,
    NULL,
    ecc_mem_writel,
};

static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    ECCState *s = opaque;

    DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
    s->diag[addr & ECC_DIAG_MASK] = val;
}

static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    ECCState *s = opaque;
    uint32_t ret = s->diag[(int)addr];

    DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
    return ret;
}

static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
    ecc_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
    ecc_diag_mem_writeb,
    NULL,
    NULL,
};

static const VMStateDescription vmstate_ecc = {
    .name ="ECC",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
        VMSTATE_BUFFER(diag, ECCState),
        VMSTATE_UINT32(version, ECCState),
        VMSTATE_END_OF_LIST()
    }
};

static void ecc_reset(DeviceState *d)
{
    ECCState *s = container_of(d, ECCState, busdev.qdev);

    if (s->version == ECC_MCC)
        s->regs[ECC_MER] &= ECC_MER_REU;
    else
        s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
                             ECC_MER_DCI);
    s->regs[ECC_MDR] = 0x20;
    s->regs[ECC_MFSR] = 0;
    s->regs[ECC_VCR] = 0;
    s->regs[ECC_MFAR0] = 0x07c00000;
    s->regs[ECC_MFAR1] = 0;
    s->regs[ECC_DR] = 0;
    s->regs[ECC_ECR0] = 0;
    s->regs[ECC_ECR1] = 0;
}

static int ecc_init1(SysBusDevice *dev)
{
    int ecc_io_memory;
    ECCState *s = FROM_SYSBUS(ECCState, dev);

    sysbus_init_irq(dev, &s->irq);
    s->regs[0] = s->version;
    ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
    sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);

    if (s->version == ECC_MCC) { // SS-600MP only
        ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
                                               ecc_diag_mem_write, s);
        sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
    }

    return 0;
}

static SysBusDeviceInfo ecc_info = {
    .init = ecc_init1,
    .qdev.name  = "eccmemctl",
    .qdev.size  = sizeof(ECCState),
    .qdev.vmsd  = &vmstate_ecc,
    .qdev.reset = ecc_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_HEX32("version", ECCState, version, -1),
        DEFINE_PROP_END_OF_LIST(),
    }
};


static void ecc_register_devices(void)
{
    sysbus_register_withprop(&ecc_info);
}

device_init(ecc_register_devices)
Commit	Line	Data
7eb0c8e8 BS	1	/*
	2	* QEMU Sparc Sun4m ECC memory controller emulation
	3	*
	4	* Copyright (c) 2007 Robert Reif
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
49e66373	24
49e66373	25	#include "sysbus.h"
7eb0c8e8 BS	26
	27	//#define DEBUG_ECC
	28
	29	#ifdef DEBUG_ECC
001faf32 BS	30	#define DPRINTF(fmt, ...) \
001faf32 BS	31	do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
7eb0c8e8	32	#else
001faf32	33	#define DPRINTF(fmt, ...)
7eb0c8e8 BS	34	#endif
	35
	36	/* There are 3 versions of this chip used in SMP sun4m systems:
	37	* MCC (version 0, implementation 0) SS-600MP
	38	* EMC (version 0, implementation 1) SS-10
	39	* SMC (version 0, implementation 2) SS-10SX and SS-20
5ac574c4 BS	40	*
	41	* Chipset docs:
	42	* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
	43	* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
7eb0c8e8 BS	44	*/
7eb0c8e8 BS	45
0bb3602c BS	46	#define ECC_MCC 0x00000000
	47	#define ECC_EMC 0x10000000
	48	#define ECC_SMC 0x20000000
	49
8f2ad0a3 BS	50	/* Register indexes */
	51	#define ECC_MER 0 /* Memory Enable Register */
	52	#define ECC_MDR 1 /* Memory Delay Register */
	53	#define ECC_MFSR 2 /* Memory Fault Status Register */
	54	#define ECC_VCR 3 /* Video Configuration Register */
	55	#define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
	56	#define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
	57	#define ECC_DR 6 /* Diagnostic Register */
	58	#define ECC_ECR0 7 /* Event Count Register 0 */
	59	#define ECC_ECR1 8 /* Event Count Register 1 */
7eb0c8e8 BS	60
7eb0c8e8 BS	61	/* ECC fault control register */
dd53ded3	62	#define ECC_MER_EE 0x00000001 /* Enable ECC checking */
77f193da BS	63	#define ECC_MER_EI 0x00000002 /* Enable Interrupts on
77f193da BS	64	correctable errors */
dd53ded3 BS	65	#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
	66	#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
	67	#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
	68	#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
	69	#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
	70	#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
	71	#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
	72	#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
0bb3602c	73	#define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
dd53ded3	74	#define ECC_MER_MRR 0x000003fc /* MRR mask */
0bb3602c	75	#define ECC_MER_A 0x00000400 /* Memory controller addr map select */
77f193da	76	#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
dd53ded3 BS	77	#define ECC_MER_VER 0x0f000000 /* Version */
dd53ded3 BS	78	#define ECC_MER_IMPL 0xf0000000 /* Implementation */
0bb3602c BS	79	#define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
	80	#define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
	81	#define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
dd53ded3 BS	82
	83	/* ECC memory delay register */
	84	#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
	85	#define ECC_MDR_MI 0x00001c00 /* MIH Delay */
	86	#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
	87	#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
	88	#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
	89	#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
	90	#define ECC_MDR_RSC 0x80000000 /* Refresh load control */
	91	#define ECC_MDR_MASK 0x7fffffff
7eb0c8e8 BS	92
7eb0c8e8 BS	93	/* ECC fault status register */
dd53ded3 BS	94	#define ECC_MFSR_CE 0x00000001 /* Correctable error */
	95	#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
	96	#define ECC_MFSR_TO 0x00000004 /* Timeout on write */
	97	#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
	98	#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
	99	#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
	100	#define ECC_MFSR_ME 0x00010000 /* Multiple errors */
	101	#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
7eb0c8e8 BS	102
7eb0c8e8 BS	103	/* ECC fault address register 0 */
dd53ded3 BS	104	#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
	105	#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
	106	#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
	107	#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
	108	#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
	109	#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
	110	#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
	111	#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
	112	#define ECC_MFARO_MID 0xf0000000 /* Module ID */
7eb0c8e8 BS	113
7eb0c8e8 BS	114	/* ECC diagnostic register */
dd53ded3 BS	115	#define ECC_DR_CBX 0x00000001
	116	#define ECC_DR_CB0 0x00000002
	117	#define ECC_DR_CB1 0x00000004
	118	#define ECC_DR_CB2 0x00000008
	119	#define ECC_DR_CB4 0x00000010
	120	#define ECC_DR_CB8 0x00000020
	121	#define ECC_DR_CB16 0x00000040
	122	#define ECC_DR_CB32 0x00000080
	123	#define ECC_DR_DMODE 0x00000c00
	124
	125	#define ECC_NREGS 9
7eb0c8e8	126	#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
dd53ded3 BS	127
	128	#define ECC_DIAG_SIZE 4
	129	#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
7eb0c8e8 BS	130
7eb0c8e8 BS	131	typedef struct ECCState {
49e66373	132	SysBusDevice busdev;
e42c20b4	133	qemu_irq irq;
7eb0c8e8	134	uint32_t regs[ECC_NREGS];
dd53ded3	135	uint8_t diag[ECC_DIAG_SIZE];
0bb3602c	136	uint32_t version;
7eb0c8e8 BS	137	} ECCState;
7eb0c8e8 BS	138
c227f099	139	static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
7eb0c8e8 BS	140	{
	141	ECCState *s = opaque;
	142
e64d7d59	143	switch (addr >> 2) {
dd53ded3	144	case ECC_MER:
0bb3602c BS	145	if (s->version == ECC_MCC)
	146	s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
	147	else if (s->version == ECC_EMC)
	148	s->regs[ECC_MER] = s->version \| (val & ECC_MER_MASK_1);
	149	else if (s->version == ECC_SMC)
	150	s->regs[ECC_MER] = s->version \| (val & ECC_MER_MASK_2);
dd53ded3	151	DPRINTF("Write memory enable %08x\n", val);
7eb0c8e8	152	break;
dd53ded3	153	case ECC_MDR:
8f2ad0a3	154	s->regs[ECC_MDR] = val & ECC_MDR_MASK;
dd53ded3	155	DPRINTF("Write memory delay %08x\n", val);
7eb0c8e8	156	break;
dd53ded3	157	case ECC_MFSR:
8f2ad0a3	158	s->regs[ECC_MFSR] = val;
0bb3602c	159	qemu_irq_lower(s->irq);
dd53ded3	160	DPRINTF("Write memory fault status %08x\n", val);
7eb0c8e8	161	break;
dd53ded3	162	case ECC_VCR:
8f2ad0a3	163	s->regs[ECC_VCR] = val;
dd53ded3	164	DPRINTF("Write slot configuration %08x\n", val);
7eb0c8e8	165	break;
dd53ded3	166	case ECC_DR:
8f2ad0a3	167	s->regs[ECC_DR] = val;
0bb3602c	168	DPRINTF("Write diagnostic %08x\n", val);
dd53ded3 BS	169	break;
dd53ded3 BS	170	case ECC_ECR0:
8f2ad0a3	171	s->regs[ECC_ECR0] = val;
dd53ded3	172	DPRINTF("Write event count 1 %08x\n", val);
7eb0c8e8	173	break;
dd53ded3	174	case ECC_ECR1:
8f2ad0a3	175	s->regs[ECC_ECR0] = val;
dd53ded3	176	DPRINTF("Write event count 2 %08x\n", val);
7eb0c8e8 BS	177	break;
	178	}
	179	}
	180
c227f099	181	static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
7eb0c8e8 BS	182	{
	183	ECCState *s = opaque;
	184	uint32_t ret = 0;
	185
e64d7d59	186	switch (addr >> 2) {
dd53ded3	187	case ECC_MER:
8f2ad0a3	188	ret = s->regs[ECC_MER];
dd53ded3	189	DPRINTF("Read memory enable %08x\n", ret);
7eb0c8e8	190	break;
dd53ded3	191	case ECC_MDR:
8f2ad0a3	192	ret = s->regs[ECC_MDR];
dd53ded3	193	DPRINTF("Read memory delay %08x\n", ret);
7eb0c8e8	194	break;
dd53ded3	195	case ECC_MFSR:
8f2ad0a3	196	ret = s->regs[ECC_MFSR];
dd53ded3	197	DPRINTF("Read memory fault status %08x\n", ret);
7eb0c8e8	198	break;
dd53ded3	199	case ECC_VCR:
8f2ad0a3	200	ret = s->regs[ECC_VCR];
dd53ded3	201	DPRINTF("Read slot configuration %08x\n", ret);
7eb0c8e8	202	break;
dd53ded3	203	case ECC_MFAR0:
8f2ad0a3	204	ret = s->regs[ECC_MFAR0];
dd53ded3	205	DPRINTF("Read memory fault address 0 %08x\n", ret);
7eb0c8e8	206	break;
dd53ded3	207	case ECC_MFAR1:
8f2ad0a3	208	ret = s->regs[ECC_MFAR1];
dd53ded3	209	DPRINTF("Read memory fault address 1 %08x\n", ret);
7eb0c8e8	210	break;
dd53ded3	211	case ECC_DR:
8f2ad0a3	212	ret = s->regs[ECC_DR];
dd53ded3	213	DPRINTF("Read diagnostic %08x\n", ret);
7eb0c8e8	214	break;
dd53ded3	215	case ECC_ECR0:
8f2ad0a3	216	ret = s->regs[ECC_ECR0];
dd53ded3 BS	217	DPRINTF("Read event count 1 %08x\n", ret);
	218	break;
	219	case ECC_ECR1:
8f2ad0a3	220	ret = s->regs[ECC_ECR0];
dd53ded3	221	DPRINTF("Read event count 2 %08x\n", ret);
7eb0c8e8 BS	222	break;
	223	}
	224	return ret;
	225	}
	226
d60efc6b	227	static CPUReadMemoryFunc * const ecc_mem_read[3] = {
7c560456 BS	228	NULL,
7c560456 BS	229	NULL,
7eb0c8e8 BS	230	ecc_mem_readl,
	231	};
	232
d60efc6b	233	static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
7c560456 BS	234	NULL,
7c560456 BS	235	NULL,
7eb0c8e8 BS	236	ecc_mem_writel,
	237	};
	238
c227f099	239	static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
dd53ded3 BS	240	uint32_t val)
	241	{
	242	ECCState *s = opaque;
	243
e64d7d59	244	DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
dd53ded3 BS	245	s->diag[addr & ECC_DIAG_MASK] = val;
	246	}
	247
c227f099	248	static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
dd53ded3 BS	249	{
dd53ded3 BS	250	ECCState *s = opaque;
e64d7d59 BS	251	uint32_t ret = s->diag[(int)addr];
	252
	253	DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
dd53ded3 BS	254	return ret;
	255	}
	256
d60efc6b	257	static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
dd53ded3 BS	258	ecc_diag_mem_readb,
	259	NULL,
	260	NULL,
	261	};
	262
d60efc6b	263	static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
dd53ded3 BS	264	ecc_diag_mem_writeb,
	265	NULL,
	266	NULL,
	267	};
	268
c21011a9 BS	269	static const VMStateDescription vmstate_ecc = {
	270	.name ="ECC",
	271	.version_id = 3,
	272	.minimum_version_id = 3,
	273	.minimum_version_id_old = 3,
	274	.fields = (VMStateField []) {
	275	VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
	276	VMSTATE_BUFFER(diag, ECCState),
	277	VMSTATE_UINT32(version, ECCState),
	278	VMSTATE_END_OF_LIST()
	279	}
	280	};
7eb0c8e8	281
0284dc54	282	static void ecc_reset(DeviceState *d)
7eb0c8e8	283	{
0284dc54	284	ECCState *s = container_of(d, ECCState, busdev.qdev);
7eb0c8e8	285
0bb3602c BS	286	if (s->version == ECC_MCC)
	287	s->regs[ECC_MER] &= ECC_MER_REU;
	288	else
	289	s->regs[ECC_MER] &= (ECC_MER_VER \| ECC_MER_IMPL \| ECC_MER_MRR \|
	290	ECC_MER_DCI);
dd53ded3 BS	291	s->regs[ECC_MDR] = 0x20;
	292	s->regs[ECC_MFSR] = 0;
	293	s->regs[ECC_VCR] = 0;
	294	s->regs[ECC_MFAR0] = 0x07c00000;
	295	s->regs[ECC_MFAR1] = 0;
	296	s->regs[ECC_DR] = 0;
	297	s->regs[ECC_ECR0] = 0;
	298	s->regs[ECC_ECR1] = 0;
7eb0c8e8 BS	299	}
7eb0c8e8 BS	300
81a322d4	301	static int ecc_init1(SysBusDevice *dev)
7eb0c8e8 BS	302	{
7eb0c8e8 BS	303	int ecc_io_memory;
49e66373	304	ECCState *s = FROM_SYSBUS(ECCState, dev);
7eb0c8e8	305
49e66373	306	sysbus_init_irq(dev, &s->irq);
49e66373	307	s->regs[0] = s->version;
1eed09cb	308	ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
49e66373 BS	309	sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
	310
	311	if (s->version == ECC_MCC) { // SS-600MP only
1eed09cb	312	ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
dd53ded3	313	ecc_diag_mem_write, s);
49e66373	314	sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
dd53ded3	315	}
0284dc54	316
81a322d4	317	return 0;
7eb0c8e8	318	}
49e66373	319
ee6847d1 GH	320	static SysBusDeviceInfo ecc_info = {
	321	.init = ecc_init1,
	322	.qdev.name = "eccmemctl",
	323	.qdev.size = sizeof(ECCState),
0284dc54 BS	324	.qdev.vmsd = &vmstate_ecc,
0284dc54 BS	325	.qdev.reset = ecc_reset,
ee6847d1	326	.qdev.props = (Property[]) {
d210a1b4 GH	327	DEFINE_PROP_HEX32("version", ECCState, version, -1),
d210a1b4 GH	328	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	329	}
	330	};
	331
	332
49e66373 BS	333	static void ecc_register_devices(void)
49e66373 BS	334	{
ee6847d1	335	sysbus_register_withprop(&ecc_info);
49e66373 BS	336	}
	337
	338	device_init(ecc_register_devices)