[qemu.git] / hw / eccmemctl.c

/*
 * QEMU Sparc Sun4m ECC memory controller emulation
 *
 * Copyright (c) 2007 Robert Reif
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "sysemu.h"

//#define DEBUG_ECC

#ifdef DEBUG_ECC
#define DPRINTF(fmt, args...)                           \
    do { printf("ECC: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/* There are 3 versions of this chip used in SMP sun4m systems:
 * MCC (version 0, implementation 0) SS-600MP
 * EMC (version 0, implementation 1) SS-10
 * SMC (version 0, implementation 2) SS-10SX and SS-20
 */

/* Register indexes */
#define ECC_MER        0               /* Memory Enable Register */
#define ECC_MDR        1               /* Memory Delay Register */
#define ECC_MFSR       2               /* Memory Fault Status Register */
#define ECC_VCR        3               /* Video Configuration Register */
#define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
#define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
#define ECC_DR         6               /* Diagnostic Register */
#define ECC_ECR0       7               /* Event Count Register 0 */
#define ECC_ECR1       8               /* Event Count Register 1 */

/* ECC fault control register */
#define ECC_MER_EE     0x00000001      /* Enable ECC checking */
#define ECC_MER_EI     0x00000002      /* Enable Interrupts on
                                          correctable errors */
#define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
#define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
#define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
#define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
#define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
#define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
#define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
#define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
#define ECC_MER_REU    0x00000200      /* Memory Refresh Enable (600MP) */
#define ECC_MER_MRR    0x000003fc      /* MRR mask */
#define ECC_MEM_A      0x00000400      /* Memory controller addr map select */
#define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
#define ECC_MER_VER    0x0f000000      /* Version */
#define ECC_MER_IMPL   0xf0000000      /* Implementation */

/* ECC memory delay register */
#define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
#define ECC_MDR_MI     0x00001c00      /* MIH Delay */
#define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
#define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
#define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
#define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
#define ECC_MDR_RSC    0x80000000      /* Refresh load control */
#define ECC_MDR_MASK   0x7fffffff

/* ECC fault status register */
#define ECC_MFSR_CE    0x00000001      /* Correctable error */
#define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
#define ECC_MFSR_TO    0x00000004      /* Timeout on write */
#define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
#define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
#define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
#define ECC_MFSR_ME    0x00010000      /* Multiple errors */
#define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */

/* ECC fault address register 0 */
#define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
#define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
#define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
#define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
#define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
#define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
#define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
#define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
#define ECC_MFARO_MID   0xf0000000     /* Module ID */

/* ECC diagnostic register */
#define ECC_DR_CBX     0x00000001
#define ECC_DR_CB0     0x00000002
#define ECC_DR_CB1     0x00000004
#define ECC_DR_CB2     0x00000008
#define ECC_DR_CB4     0x00000010
#define ECC_DR_CB8     0x00000020
#define ECC_DR_CB16    0x00000040
#define ECC_DR_CB32    0x00000080
#define ECC_DR_DMODE   0x00000c00

#define ECC_NREGS      9
#define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))

#define ECC_DIAG_SIZE  4
#define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)

typedef struct ECCState {
    qemu_irq irq;
    uint32_t regs[ECC_NREGS];
    uint8_t diag[ECC_DIAG_SIZE];
} ECCState;

static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    ECCState *s = opaque;

    switch (addr >> 2) {
    case ECC_MER:
        s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER | ECC_MER_IMPL)) |
            (val & ~(ECC_MER_VER | ECC_MER_IMPL));
        DPRINTF("Write memory enable %08x\n", val);
        break;
    case ECC_MDR:
        s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
        DPRINTF("Write memory delay %08x\n", val);
        break;
    case ECC_MFSR:
        s->regs[ECC_MFSR] =  val;
        DPRINTF("Write memory fault status %08x\n", val);
        break;
    case ECC_VCR:
        s->regs[ECC_VCR] =  val;
        DPRINTF("Write slot configuration %08x\n", val);
        break;
    case ECC_DR:
        s->regs[ECC_DR] =  val;
        DPRINTF("Write diagnosiic %08x\n", val);
        break;
    case ECC_ECR0:
        s->regs[ECC_ECR0] =  val;
        DPRINTF("Write event count 1 %08x\n", val);
        break;
    case ECC_ECR1:
        s->regs[ECC_ECR0] =  val;
        DPRINTF("Write event count 2 %08x\n", val);
        break;
    }
}

static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
{
    ECCState *s = opaque;
    uint32_t ret = 0;

    switch (addr >> 2) {
    case ECC_MER:
        ret = s->regs[ECC_MER];
        DPRINTF("Read memory enable %08x\n", ret);
        break;
    case ECC_MDR:
        ret = s->regs[ECC_MDR];
        DPRINTF("Read memory delay %08x\n", ret);
        break;
    case ECC_MFSR:
        ret = s->regs[ECC_MFSR];
        DPRINTF("Read memory fault status %08x\n", ret);
        break;
    case ECC_VCR:
        ret = s->regs[ECC_VCR];
        DPRINTF("Read slot configuration %08x\n", ret);
        break;
    case ECC_MFAR0:
        ret = s->regs[ECC_MFAR0];
        DPRINTF("Read memory fault address 0 %08x\n", ret);
        break;
    case ECC_MFAR1:
        ret = s->regs[ECC_MFAR1];
        DPRINTF("Read memory fault address 1 %08x\n", ret);
        break;
    case ECC_DR:
        ret = s->regs[ECC_DR];
        DPRINTF("Read diagnostic %08x\n", ret);
        break;
    case ECC_ECR0:
        ret = s->regs[ECC_ECR0];
        DPRINTF("Read event count 1 %08x\n", ret);
        break;
    case ECC_ECR1:
        ret = s->regs[ECC_ECR0];
        DPRINTF("Read event count 2 %08x\n", ret);
        break;
    }
    return ret;
}

static CPUReadMemoryFunc *ecc_mem_read[3] = {
    NULL,
    NULL,
    ecc_mem_readl,
};

static CPUWriteMemoryFunc *ecc_mem_write[3] = {
    NULL,
    NULL,
    ecc_mem_writel,
};

static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    ECCState *s = opaque;

    DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
    s->diag[addr & ECC_DIAG_MASK] = val;
}

static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
    ECCState *s = opaque;
    uint32_t ret = s->diag[(int)addr];

    DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
    return ret;
}

static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
    ecc_diag_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
    ecc_diag_mem_writeb,
    NULL,
    NULL,
};

static int ecc_load(QEMUFile *f, void *opaque, int version_id)
{
    ECCState *s = opaque;
    int i;

    if (version_id != 2)
        return -EINVAL;

    for (i = 0; i < ECC_NREGS; i++)
        qemu_get_be32s(f, &s->regs[i]);

    for (i = 0; i < ECC_DIAG_SIZE; i++)
        qemu_get_8s(f, &s->diag[i]);

    return 0;
}

static void ecc_save(QEMUFile *f, void *opaque)
{
    ECCState *s = opaque;
    int i;

    for (i = 0; i < ECC_NREGS; i++)
        qemu_put_be32s(f, &s->regs[i]);

    for (i = 0; i < ECC_DIAG_SIZE; i++)
        qemu_put_8s(f, &s->diag[i]);
}

static void ecc_reset(void *opaque)
{
    ECCState *s = opaque;

    s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL);
    s->regs[ECC_MER] |= ECC_MER_MRR;
    s->regs[ECC_MDR] = 0x20;
    s->regs[ECC_MFSR] = 0;
    s->regs[ECC_VCR] = 0;
    s->regs[ECC_MFAR0] = 0x07c00000;
    s->regs[ECC_MFAR1] = 0;
    s->regs[ECC_DR] = 0;
    s->regs[ECC_ECR0] = 0;
    s->regs[ECC_ECR1] = 0;
}

void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
{
    int ecc_io_memory;
    ECCState *s;

    s = qemu_mallocz(sizeof(ECCState));
    if (!s)
        return NULL;

    s->regs[0] = version;
    s->irq = irq;

    ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
    cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
    if (version == 0) { // SS-600MP only
        ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
                                               ecc_diag_mem_write, s);
        cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
                                     ecc_io_memory);
    }
    register_savevm("ECC", base, 2, ecc_save, ecc_load, s);
    qemu_register_reset(ecc_reset, s);
    ecc_reset(s);
    return s;
}
Commit	Line	Data
7eb0c8e8 BS	1	/*
	2	* QEMU Sparc Sun4m ECC memory controller emulation
	3	*
	4	* Copyright (c) 2007 Robert Reif
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "sysemu.h"
	27
	28	//#define DEBUG_ECC
	29
	30	#ifdef DEBUG_ECC
	31	#define DPRINTF(fmt, args...) \
	32	do { printf("ECC: " fmt , ##args); } while (0)
	33	#else
	34	#define DPRINTF(fmt, args...)
	35	#endif
	36
	37	/* There are 3 versions of this chip used in SMP sun4m systems:
	38	* MCC (version 0, implementation 0) SS-600MP
	39	* EMC (version 0, implementation 1) SS-10
	40	* SMC (version 0, implementation 2) SS-10SX and SS-20
	41	*/
	42
8f2ad0a3 BS	43	/* Register indexes */
	44	#define ECC_MER 0 /* Memory Enable Register */
	45	#define ECC_MDR 1 /* Memory Delay Register */
	46	#define ECC_MFSR 2 /* Memory Fault Status Register */
	47	#define ECC_VCR 3 /* Video Configuration Register */
	48	#define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
	49	#define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
	50	#define ECC_DR 6 /* Diagnostic Register */
	51	#define ECC_ECR0 7 /* Event Count Register 0 */
	52	#define ECC_ECR1 8 /* Event Count Register 1 */
7eb0c8e8 BS	53
7eb0c8e8 BS	54	/* ECC fault control register */
dd53ded3	55	#define ECC_MER_EE 0x00000001 /* Enable ECC checking */
77f193da BS	56	#define ECC_MER_EI 0x00000002 /* Enable Interrupts on
77f193da BS	57	correctable errors */
dd53ded3 BS	58	#define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
	59	#define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
	60	#define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
	61	#define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
	62	#define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
	63	#define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
	64	#define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
	65	#define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
	66	#define ECC_MER_REU 0x00000200 /* Memory Refresh Enable (600MP) */
	67	#define ECC_MER_MRR 0x000003fc /* MRR mask */
	68	#define ECC_MEM_A 0x00000400 /* Memory controller addr map select */
77f193da	69	#define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
dd53ded3 BS	70	#define ECC_MER_VER 0x0f000000 /* Version */
	71	#define ECC_MER_IMPL 0xf0000000 /* Implementation */
	72
	73	/* ECC memory delay register */
	74	#define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
	75	#define ECC_MDR_MI 0x00001c00 /* MIH Delay */
	76	#define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
	77	#define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
	78	#define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
	79	#define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
	80	#define ECC_MDR_RSC 0x80000000 /* Refresh load control */
	81	#define ECC_MDR_MASK 0x7fffffff
7eb0c8e8 BS	82
7eb0c8e8 BS	83	/* ECC fault status register */
dd53ded3 BS	84	#define ECC_MFSR_CE 0x00000001 /* Correctable error */
	85	#define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
	86	#define ECC_MFSR_TO 0x00000004 /* Timeout on write */
	87	#define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
	88	#define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
	89	#define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
	90	#define ECC_MFSR_ME 0x00010000 /* Multiple errors */
	91	#define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
7eb0c8e8 BS	92
7eb0c8e8 BS	93	/* ECC fault address register 0 */
dd53ded3 BS	94	#define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
	95	#define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
	96	#define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
	97	#define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
	98	#define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
	99	#define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
	100	#define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
	101	#define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
	102	#define ECC_MFARO_MID 0xf0000000 /* Module ID */
7eb0c8e8 BS	103
7eb0c8e8 BS	104	/* ECC diagnostic register */
dd53ded3 BS	105	#define ECC_DR_CBX 0x00000001
	106	#define ECC_DR_CB0 0x00000002
	107	#define ECC_DR_CB1 0x00000004
	108	#define ECC_DR_CB2 0x00000008
	109	#define ECC_DR_CB4 0x00000010
	110	#define ECC_DR_CB8 0x00000020
	111	#define ECC_DR_CB16 0x00000040
	112	#define ECC_DR_CB32 0x00000080
	113	#define ECC_DR_DMODE 0x00000c00
	114
	115	#define ECC_NREGS 9
7eb0c8e8	116	#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
dd53ded3 BS	117
	118	#define ECC_DIAG_SIZE 4
	119	#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
7eb0c8e8 BS	120
7eb0c8e8 BS	121	typedef struct ECCState {
e42c20b4	122	qemu_irq irq;
7eb0c8e8	123	uint32_t regs[ECC_NREGS];
dd53ded3	124	uint8_t diag[ECC_DIAG_SIZE];
7eb0c8e8 BS	125	} ECCState;
7eb0c8e8 BS	126
7eb0c8e8 BS	127	static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	128	{
	129	ECCState *s = opaque;
	130
e64d7d59	131	switch (addr >> 2) {
dd53ded3	132	case ECC_MER:
8f2ad0a3 BS	133	s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER \| ECC_MER_IMPL)) \|
8f2ad0a3 BS	134	(val & ~(ECC_MER_VER \| ECC_MER_IMPL));
dd53ded3	135	DPRINTF("Write memory enable %08x\n", val);
7eb0c8e8	136	break;
dd53ded3	137	case ECC_MDR:
8f2ad0a3	138	s->regs[ECC_MDR] = val & ECC_MDR_MASK;
dd53ded3	139	DPRINTF("Write memory delay %08x\n", val);
7eb0c8e8	140	break;
dd53ded3	141	case ECC_MFSR:
8f2ad0a3	142	s->regs[ECC_MFSR] = val;
dd53ded3	143	DPRINTF("Write memory fault status %08x\n", val);
7eb0c8e8	144	break;
dd53ded3	145	case ECC_VCR:
8f2ad0a3	146	s->regs[ECC_VCR] = val;
dd53ded3	147	DPRINTF("Write slot configuration %08x\n", val);
7eb0c8e8	148	break;
dd53ded3	149	case ECC_DR:
8f2ad0a3	150	s->regs[ECC_DR] = val;
dd53ded3 BS	151	DPRINTF("Write diagnosiic %08x\n", val);
	152	break;
	153	case ECC_ECR0:
8f2ad0a3	154	s->regs[ECC_ECR0] = val;
dd53ded3	155	DPRINTF("Write event count 1 %08x\n", val);
7eb0c8e8	156	break;
dd53ded3	157	case ECC_ECR1:
8f2ad0a3	158	s->regs[ECC_ECR0] = val;
dd53ded3	159	DPRINTF("Write event count 2 %08x\n", val);
7eb0c8e8 BS	160	break;
	161	}
	162	}
	163
	164	static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
	165	{
	166	ECCState *s = opaque;
	167	uint32_t ret = 0;
	168
e64d7d59	169	switch (addr >> 2) {
dd53ded3	170	case ECC_MER:
8f2ad0a3	171	ret = s->regs[ECC_MER];
dd53ded3	172	DPRINTF("Read memory enable %08x\n", ret);
7eb0c8e8	173	break;
dd53ded3	174	case ECC_MDR:
8f2ad0a3	175	ret = s->regs[ECC_MDR];
dd53ded3	176	DPRINTF("Read memory delay %08x\n", ret);
7eb0c8e8	177	break;
dd53ded3	178	case ECC_MFSR:
8f2ad0a3	179	ret = s->regs[ECC_MFSR];
dd53ded3	180	DPRINTF("Read memory fault status %08x\n", ret);
7eb0c8e8	181	break;
dd53ded3	182	case ECC_VCR:
8f2ad0a3	183	ret = s->regs[ECC_VCR];
dd53ded3	184	DPRINTF("Read slot configuration %08x\n", ret);
7eb0c8e8	185	break;
dd53ded3	186	case ECC_MFAR0:
8f2ad0a3	187	ret = s->regs[ECC_MFAR0];
dd53ded3	188	DPRINTF("Read memory fault address 0 %08x\n", ret);
7eb0c8e8	189	break;
dd53ded3	190	case ECC_MFAR1:
8f2ad0a3	191	ret = s->regs[ECC_MFAR1];
dd53ded3	192	DPRINTF("Read memory fault address 1 %08x\n", ret);
7eb0c8e8	193	break;
dd53ded3	194	case ECC_DR:
8f2ad0a3	195	ret = s->regs[ECC_DR];
dd53ded3	196	DPRINTF("Read diagnostic %08x\n", ret);
7eb0c8e8	197	break;
dd53ded3	198	case ECC_ECR0:
8f2ad0a3	199	ret = s->regs[ECC_ECR0];
dd53ded3 BS	200	DPRINTF("Read event count 1 %08x\n", ret);
	201	break;
	202	case ECC_ECR1:
8f2ad0a3	203	ret = s->regs[ECC_ECR0];
dd53ded3	204	DPRINTF("Read event count 2 %08x\n", ret);
7eb0c8e8 BS	205	break;
	206	}
	207	return ret;
	208	}
	209
	210	static CPUReadMemoryFunc *ecc_mem_read[3] = {
7c560456 BS	211	NULL,
7c560456 BS	212	NULL,
7eb0c8e8 BS	213	ecc_mem_readl,
	214	};
	215
	216	static CPUWriteMemoryFunc *ecc_mem_write[3] = {
7c560456 BS	217	NULL,
7c560456 BS	218	NULL,
7eb0c8e8 BS	219	ecc_mem_writel,
	220	};
	221
dd53ded3 BS	222	static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
	223	uint32_t val)
	224	{
	225	ECCState *s = opaque;
	226
e64d7d59	227	DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
dd53ded3 BS	228	s->diag[addr & ECC_DIAG_MASK] = val;
	229	}
	230
	231	static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
	232	{
	233	ECCState *s = opaque;
e64d7d59 BS	234	uint32_t ret = s->diag[(int)addr];
	235
	236	DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
dd53ded3 BS	237	return ret;
	238	}
	239
	240	static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
	241	ecc_diag_mem_readb,
	242	NULL,
	243	NULL,
	244	};
	245
	246	static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
	247	ecc_diag_mem_writeb,
	248	NULL,
	249	NULL,
	250	};
	251
7eb0c8e8 BS	252	static int ecc_load(QEMUFile f, void opaque, int version_id)
	253	{
	254	ECCState *s = opaque;
	255	int i;
	256
dd53ded3	257	if (version_id != 2)
7eb0c8e8 BS	258	return -EINVAL;
	259
	260	for (i = 0; i < ECC_NREGS; i++)
	261	qemu_get_be32s(f, &s->regs[i]);
	262
dd53ded3 BS	263	for (i = 0; i < ECC_DIAG_SIZE; i++)
	264	qemu_get_8s(f, &s->diag[i]);
	265
7eb0c8e8 BS	266	return 0;
	267	}
	268
	269	static void ecc_save(QEMUFile f, void opaque)
	270	{
	271	ECCState *s = opaque;
	272	int i;
	273
	274	for (i = 0; i < ECC_NREGS; i++)
	275	qemu_put_be32s(f, &s->regs[i]);
dd53ded3 BS	276
	277	for (i = 0; i < ECC_DIAG_SIZE; i++)
	278	qemu_put_8s(f, &s->diag[i]);
7eb0c8e8 BS	279	}
	280
	281	static void ecc_reset(void *opaque)
	282	{
	283	ECCState *s = opaque;
7eb0c8e8	284
dd53ded3 BS	285	s->regs[ECC_MER] &= (ECC_MER_VER \| ECC_MER_IMPL);
	286	s->regs[ECC_MER] \|= ECC_MER_MRR;
	287	s->regs[ECC_MDR] = 0x20;
	288	s->regs[ECC_MFSR] = 0;
	289	s->regs[ECC_VCR] = 0;
	290	s->regs[ECC_MFAR0] = 0x07c00000;
	291	s->regs[ECC_MFAR1] = 0;
	292	s->regs[ECC_DR] = 0;
	293	s->regs[ECC_ECR0] = 0;
	294	s->regs[ECC_ECR1] = 0;
7eb0c8e8 BS	295	}
7eb0c8e8 BS	296
e42c20b4	297	void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
7eb0c8e8 BS	298	{
	299	int ecc_io_memory;
	300	ECCState *s;
	301
	302	s = qemu_mallocz(sizeof(ECCState));
	303	if (!s)
	304	return NULL;
	305
	306	s->regs[0] = version;
e42c20b4	307	s->irq = irq;
7eb0c8e8 BS	308
	309	ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
	310	cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
dd53ded3 BS	311	if (version == 0) { // SS-600MP only
	312	ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
	313	ecc_diag_mem_write, s);
	314	cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
	315	ecc_io_memory);
	316	}
	317	register_savevm("ECC", base, 2, ecc_save, ecc_load, s);
7eb0c8e8 BS	318	qemu_register_reset(ecc_reset, s);
	319	ecc_reset(s);
	320	return s;
	321	}