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[qemu.git] / hw / rtl8139.c
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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
56#include "qemu-timer.h"
57#include "net.h"
254111ec 58#include "loader.h"
1ca4d09a 59#include "sysemu.h"
bf6b87a8 60#include "iov.h"
a41b2ff2 61
a41b2ff2
PB		 62/* debug RTL8139 card */
63//#define DEBUG_RTL8139 1
64
6cadb320
FB		 65#define PCI_FREQUENCY 33000000L
66
a41b2ff2
PB		 67/* debug RTL8139 card C+ mode only */
68//#define DEBUG_RTL8139CP 1
69
a41b2ff2
PB		 70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
18dabfd1
BP		 77#define ETHER_ADDR_LEN 6
78#define ETHER_TYPE_LEN 2
79#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80#define ETH_P_IP 0x0800 /* Internet Protocol packet */
81#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82#define ETH_MTU 1500
83
84#define VLAN_TCI_LEN 2
85#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
6cadb320 87#if defined (DEBUG_RTL8139)
7cdeb319
BP		 88# define DPRINTF(fmt, ...) \
89 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 90#else
c6a0487b 91static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 92{
93 return 0;
94}
6cadb320
FB		 95#endif
96
a41b2ff2
PB		 97/* Symbolic offsets to registers. */
98enum RTL8139_registers {
99 MAC0 = 0, /* Ethernet hardware address. */
100 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 101 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
102 /* Dump Tally Conter control register(64bit). C+ mode only */
103 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 104 RxBuf = 0x30,
105 ChipCmd = 0x37,
106 RxBufPtr = 0x38,
107 RxBufAddr = 0x3A,
108 IntrMask = 0x3C,
109 IntrStatus = 0x3E,
110 TxConfig = 0x40,
111 RxConfig = 0x44,
112 Timer = 0x48, /* A general-purpose counter. */
113 RxMissed = 0x4C, /* 24 bits valid, write clears. */
114 Cfg9346 = 0x50,
115 Config0 = 0x51,
116 Config1 = 0x52,
117 FlashReg = 0x54,
118 MediaStatus = 0x58,
119 Config3 = 0x59,
120 Config4 = 0x5A, /* absent on RTL-8139A */
121 HltClk = 0x5B,
122 MultiIntr = 0x5C,
123 PCIRevisionID = 0x5E,
124 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
125 BasicModeCtrl = 0x62,
126 BasicModeStatus = 0x64,
127 NWayAdvert = 0x66,
128 NWayLPAR = 0x68,
129 NWayExpansion = 0x6A,
130 /* Undocumented registers, but required for proper operation. */
131 FIFOTMS = 0x70, /* FIFO Control and test. */
132 CSCR = 0x74, /* Chip Status and Configuration Register. */
133 PARA78 = 0x78,
134 PARA7c = 0x7c, /* Magic transceiver parameter register. */
135 Config5 = 0xD8, /* absent on RTL-8139A */
136 /* C+ mode */
137 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
138 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
139 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
140 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
141 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
142 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
143 TxThresh = 0xEC, /* Early Tx threshold */
144};
145
146enum ClearBitMasks {
147 MultiIntrClear = 0xF000,
148 ChipCmdClear = 0xE2,
149 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
150};
151
152enum ChipCmdBits {
153 CmdReset = 0x10,
154 CmdRxEnb = 0x08,
155 CmdTxEnb = 0x04,
156 RxBufEmpty = 0x01,
157};
158
159/* C+ mode */
160enum CplusCmdBits {
6cadb320
FB		 161 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
162 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
163 CPlusRxEnb = 0x0002,
164 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 165};
166
167/* Interrupt register bits, using my own meaningful names. */
168enum IntrStatusBits {
169 PCIErr = 0x8000,
170 PCSTimeout = 0x4000,
171 RxFIFOOver = 0x40,
172 RxUnderrun = 0x20,
173 RxOverflow = 0x10,
174 TxErr = 0x08,
175 TxOK = 0x04,
176 RxErr = 0x02,
177 RxOK = 0x01,
178
179 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
180};
181
182enum TxStatusBits {
183 TxHostOwns = 0x2000,
184 TxUnderrun = 0x4000,
185 TxStatOK = 0x8000,
186 TxOutOfWindow = 0x20000000,
187 TxAborted = 0x40000000,
188 TxCarrierLost = 0x80000000,
189};
190enum RxStatusBits {
191 RxMulticast = 0x8000,
192 RxPhysical = 0x4000,
193 RxBroadcast = 0x2000,
194 RxBadSymbol = 0x0020,
195 RxRunt = 0x0010,
196 RxTooLong = 0x0008,
197 RxCRCErr = 0x0004,
198 RxBadAlign = 0x0002,
199 RxStatusOK = 0x0001,
200};
201
202/* Bits in RxConfig. */
203enum rx_mode_bits {
204 AcceptErr = 0x20,
205 AcceptRunt = 0x10,
206 AcceptBroadcast = 0x08,
207 AcceptMulticast = 0x04,
208 AcceptMyPhys = 0x02,
209 AcceptAllPhys = 0x01,
210};
211
212/* Bits in TxConfig. */
213enum tx_config_bits {
214
215 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
216 TxIFGShift = 24,
217 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
218 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
219 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
220 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
221
222 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
223 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
224 TxClearAbt = (1 << 0), /* Clear abort (WO) */
225 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
226 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227
228 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
229};
230
231
232/* Transmit Status of All Descriptors (TSAD) Register */
233enum TSAD_bits {
234 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
235 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
236 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
237 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
238 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
239 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
240 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
241 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
242 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
243 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
244 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
245 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
246 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
247 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
248 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
249 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
250};
251
252
253/* Bits in Config1 */
254enum Config1Bits {
255 Cfg1_PM_Enable = 0x01,
256 Cfg1_VPD_Enable = 0x02,
257 Cfg1_PIO = 0x04,
258 Cfg1_MMIO = 0x08,
259 LWAKE = 0x10, /* not on 8139, 8139A */
260 Cfg1_Driver_Load = 0x20,
261 Cfg1_LED0 = 0x40,
262 Cfg1_LED1 = 0x80,
263 SLEEP = (1 << 1), /* only on 8139, 8139A */
264 PWRDN = (1 << 0), /* only on 8139, 8139A */
265};
266
267/* Bits in Config3 */
268enum Config3Bits {
269 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
270 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
271 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
272 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
273 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
274 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
275 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
276 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
277};
278
279/* Bits in Config4 */
280enum Config4Bits {
281 LWPTN = (1 << 2), /* not on 8139, 8139A */
282};
283
284/* Bits in Config5 */
285enum Config5Bits {
286 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
287 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
288 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
289 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
290 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
291 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
292 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
293};
294
295enum RxConfigBits {
296 /* rx fifo threshold */
297 RxCfgFIFOShift = 13,
298 RxCfgFIFONone = (7 << RxCfgFIFOShift),
299
300 /* Max DMA burst */
301 RxCfgDMAShift = 8,
302 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
303
304 /* rx ring buffer length */
305 RxCfgRcv8K = 0,
306 RxCfgRcv16K = (1 << 11),
307 RxCfgRcv32K = (1 << 12),
308 RxCfgRcv64K = (1 << 11) | (1 << 12),
309
310 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
311 RxNoWrap = (1 << 7),
312};
313
314/* Twister tuning parameters from RealTek.
315 Completely undocumented, but required to tune bad links on some boards. */
316/*
317enum CSCRBits {
318 CSCR_LinkOKBit = 0x0400,
319 CSCR_LinkChangeBit = 0x0800,
320 CSCR_LinkStatusBits = 0x0f000,
321 CSCR_LinkDownOffCmd = 0x003c0,
322 CSCR_LinkDownCmd = 0x0f3c0,
323*/
324enum CSCRBits {
5fafdf24 325 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 326 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
327 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
328 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 329 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 330 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
331 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
332 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
333 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
334};
335
336enum Cfg9346Bits {
337 Cfg9346_Lock = 0x00,
338 Cfg9346_Unlock = 0xC0,
339};
340
341typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
c227f099 352} chip_t;
a41b2ff2
PB		 353
354enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357};
358
359#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
6cadb320
FB		 363#define RTL8139_PCI_REVID_8139 0x10
364#define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
a41b2ff2
PB		 368/* Size is 64 * 16bit words */
369#define EEPROM_9346_ADDR_BITS 6
370#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373enum Chip9346Operation
374{
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382};
383
384enum Chip9346Mode
385{
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392};
393
394typedef struct EEprom9346
395{
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407} EEprom9346;
408
6cadb320
FB		 409typedef struct RTL8139TallyCounters
410{
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425} RTL8139TallyCounters;
426
427/* Clears all tally counters */
428static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
430/* Writes tally counters to specified physical memory address */
c227f099 431static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 432
a41b2ff2 433typedef struct RTL8139State {
efd6dd45 434 PCIDevice dev;
a41b2ff2
PB		 435 uint8_t phys[8]; /* mac address */
436 uint8_t mult[8]; /* multicast mask array */
437
6cadb320 438 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 439 uint32_t TxAddr[4]; /* TxAddr0 */
440 uint32_t RxBuf; /* Receive buffer */
441 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
442 uint32_t RxBufPtr;
443 uint32_t RxBufAddr;
444
445 uint16_t IntrStatus;
446 uint16_t IntrMask;
447
448 uint32_t TxConfig;
449 uint32_t RxConfig;
450 uint32_t RxMissed;
451
452 uint16_t CSCR;
453
454 uint8_t Cfg9346;
455 uint8_t Config0;
456 uint8_t Config1;
457 uint8_t Config3;
458 uint8_t Config4;
459 uint8_t Config5;
460
461 uint8_t clock_enabled;
462 uint8_t bChipCmdState;
463
464 uint16_t MultiIntr;
465
466 uint16_t BasicModeCtrl;
467 uint16_t BasicModeStatus;
468 uint16_t NWayAdvert;
469 uint16_t NWayLPAR;
470 uint16_t NWayExpansion;
471
472 uint16_t CpCmd;
473 uint8_t TxThresh;
474
1673ad51 475 NICState *nic;
254111ec 476 NICConf conf;
a41b2ff2
PB		 477
478 /* C ring mode */
479 uint32_t currTxDesc;
480
481 /* C+ mode */
2c3891ab
AL		 482 uint32_t cplus_enabled;
483
a41b2ff2
PB		 484 uint32_t currCPlusRxDesc;
485 uint32_t currCPlusTxDesc;
486
487 uint32_t RxRingAddrLO;
488 uint32_t RxRingAddrHI;
489
490 EEprom9346 eeprom;
6cadb320
FB		 491
492 uint32_t TCTR;
493 uint32_t TimerInt;
494 int64_t TCTR_base;
495
496 /* Tally counters */
497 RTL8139TallyCounters tally_counters;
498
499 /* Non-persistent data */
500 uint8_t *cplus_txbuffer;
501 int cplus_txbuffer_len;
502 int cplus_txbuffer_offset;
503
504 /* PCI interrupt timer */
505 QEMUTimer *timer;
05447803 506 int64_t TimerExpire;
6cadb320 507
bd80f3fc
AK		 508 MemoryRegion bar_io;
509 MemoryRegion bar_mem;
510
c574ba5a
AW		 511 /* Support migration to/from old versions */
512 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 513} RTL8139State;
514
05447803
FZ		 515static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
516
9596ebb7 517static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 518{
7cdeb319 519 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 520
521 switch (command & Chip9346_op_mask)
522 {
523 case Chip9346_op_read:
524 {
525 eeprom->address = command & EEPROM_9346_ADDR_MASK;
526 eeprom->output = eeprom->contents[eeprom->address];
527 eeprom->eedo = 0;
528 eeprom->tick = 0;
529 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 530 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
531 eeprom->address, eeprom->output);
a41b2ff2
PB		 532 }
533 break;
534
535 case Chip9346_op_write:
536 {
537 eeprom->address = command & EEPROM_9346_ADDR_MASK;
538 eeprom->input = 0;
539 eeprom->tick = 0;
540 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 541 DPRINTF("eeprom begin write to address 0x%02x\n",
542 eeprom->address);
a41b2ff2
PB		 543 }
544 break;
545 default:
546 eeprom->mode = Chip9346_none;
547 switch (command & Chip9346_op_ext_mask)
548 {
549 case Chip9346_op_write_enable:
7cdeb319 550 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 551 break;
552 case Chip9346_op_write_all:
7cdeb319 553 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 554 break;
555 case Chip9346_op_write_disable:
7cdeb319 556 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 557 break;
558 }
559 break;
560 }
561}
562
9596ebb7 563static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 564{
565 int bit = eeprom->eedi?1:0;
566
567 ++ eeprom->tick;
568
7cdeb319
BP		 569 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
570 eeprom->eedo);
a41b2ff2
PB		 571
572 switch (eeprom->mode)
573 {
574 case Chip9346_enter_command_mode:
575 if (bit)
576 {
577 eeprom->mode = Chip9346_read_command;
578 eeprom->tick = 0;
579 eeprom->input = 0;
7cdeb319 580 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 581 }
582 break;
583
584 case Chip9346_read_command:
585 eeprom->input = (eeprom->input << 1) | (bit & 1);
586 if (eeprom->tick == 8)
587 {
588 prom9346_decode_command(eeprom, eeprom->input & 0xff);
589 }
590 break;
591
592 case Chip9346_data_read:
593 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
594 eeprom->output <<= 1;
595 if (eeprom->tick == 16)
596 {
6cadb320
FB		 597#if 1
598 // the FreeBSD drivers (rl and re) don't explicitly toggle
599 // CS between reads (or does setting Cfg9346 to 0 count too?),
600 // so we need to enter wait-for-command state here
601 eeprom->mode = Chip9346_enter_command_mode;
602 eeprom->input = 0;
603 eeprom->tick = 0;
604
7cdeb319 605 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 606#else
607 // original behaviour
a41b2ff2
PB		 608 ++eeprom->address;
609 eeprom->address &= EEPROM_9346_ADDR_MASK;
610 eeprom->output = eeprom->contents[eeprom->address];
611 eeprom->tick = 0;
612
7cdeb319
BP		 613 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
614 eeprom->address, eeprom->output);
a41b2ff2
PB		 615#endif
616 }
617 break;
618
619 case Chip9346_data_write:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
7cdeb319
BP		 623 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
624 eeprom->address, eeprom->input);
6cadb320 625
a41b2ff2
PB		 626 eeprom->contents[eeprom->address] = eeprom->input;
627 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 case Chip9346_data_write_all:
634 eeprom->input = (eeprom->input << 1) | (bit & 1);
635 if (eeprom->tick == 16)
636 {
637 int i;
638 for (i = 0; i < EEPROM_9346_SIZE; i++)
639 {
640 eeprom->contents[i] = eeprom->input;
641 }
7cdeb319 642 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 643
a41b2ff2
PB		 644 eeprom->mode = Chip9346_enter_command_mode;
645 eeprom->tick = 0;
646 eeprom->input = 0;
647 }
648 break;
649
650 default:
651 break;
652 }
653}
654
9596ebb7 655static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 656{
657 EEprom9346 *eeprom = &s->eeprom;
658 if (!eeprom->eecs)
659 return 0;
660
661 return eeprom->eedo;
662}
663
9596ebb7
PB		 664/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
665static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 666{
667 EEprom9346 *eeprom = &s->eeprom;
668 uint8_t old_eecs = eeprom->eecs;
669 uint8_t old_eesk = eeprom->eesk;
670
671 eeprom->eecs = eecs;
672 eeprom->eesk = eesk;
673 eeprom->eedi = eedi;
674
7cdeb319
BP		 675 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
676 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 677
678 if (!old_eecs && eecs)
679 {
680 /* Synchronize start */
681 eeprom->tick = 0;
682 eeprom->input = 0;
683 eeprom->output = 0;
684 eeprom->mode = Chip9346_enter_command_mode;
685
7cdeb319 686 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 687 }
688
689 if (!eecs)
690 {
7cdeb319 691 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 692 return;
693 }
694
695 if (!old_eesk && eesk)
696 {
697 /* SK front rules */
698 prom9346_shift_clock(eeprom);
699 }
700}
701
702static void rtl8139_update_irq(RTL8139State *s)
703{
704 int isr;
705 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 706
7cdeb319
BP		 707 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
708 s->IntrMask);
6cadb320 709
efd6dd45 710 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 711}
712
713#define POLYNOMIAL 0x04c11db6
714
715/* From FreeBSD */
716/* XXX: optimize */
717static int compute_mcast_idx(const uint8_t *ep)
718{
719 uint32_t crc;
720 int carry, i, j;
721 uint8_t b;
722
723 crc = 0xffffffff;
724 for (i = 0; i < 6; i++) {
725 b = *ep++;
726 for (j = 0; j < 8; j++) {
727 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
728 crc <<= 1;
729 b >>= 1;
730 if (carry)
731 crc = ((crc ^ POLYNOMIAL) | carry);
732 }
733 }
734 return (crc >> 26);
735}
736
737static int rtl8139_RxWrap(RTL8139State *s)
738{
739 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
740 return (s->RxConfig & (1 << 7));
741}
742
743static int rtl8139_receiver_enabled(RTL8139State *s)
744{
745 return s->bChipCmdState & CmdRxEnb;
746}
747
748static int rtl8139_transmitter_enabled(RTL8139State *s)
749{
750 return s->bChipCmdState & CmdTxEnb;
751}
752
753static int rtl8139_cp_receiver_enabled(RTL8139State *s)
754{
755 return s->CpCmd & CPlusRxEnb;
756}
757
758static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
759{
760 return s->CpCmd & CPlusTxEnb;
761}
762
763static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
764{
765 if (s->RxBufAddr + size > s->RxBufferSize)
766 {
767 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
768
769 /* write packet data */
ccf1d14a 770 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 771 {
7cdeb319 772 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 773
774 if (size > wrapped)
775 {
776 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
777 buf, size-wrapped );
778 }
779
780 /* reset buffer pointer */
781 s->RxBufAddr = 0;
782
783 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
784 buf + (size-wrapped), wrapped );
785
786 s->RxBufAddr = wrapped;
787
788 return;
789 }
790 }
791
792 /* non-wrapping path or overwrapping enabled */
793 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
794
795 s->RxBufAddr += size;
796}
797
798#define MIN_BUF_SIZE 60
c227f099 799static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 800{
801#if TARGET_PHYS_ADDR_BITS > 32
c227f099 802 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 803#else
804 return low;
805#endif
806}
807
1673ad51 808static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 809{
1673ad51 810 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 811 int avail;
812
aa1f17c1 813 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 814 if (!s->clock_enabled)
815 return 1;
816 if (!rtl8139_receiver_enabled(s))
817 return 1;
818
819 if (rtl8139_cp_receiver_enabled(s)) {
820 /* ??? Flow control not implemented in c+ mode.
821 This is a hack to work around slirp deficiencies anyway. */
822 return 1;
823 } else {
824 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
825 s->RxBufferSize);
826 return (avail == 0 || avail >= 1514);
827 }
828}
829
1673ad51 830static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 831{
1673ad51 832 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 833 /* size is the length of the buffer passed to the driver */
4f1c942b 834 int size = size_;
18dabfd1 835 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 836
837 uint32_t packet_header = 0;
838
18dabfd1 839 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 840 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 841 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
842
7cdeb319 843 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 844
845 /* test if board clock is stopped */
846 if (!s->clock_enabled)
847 {
7cdeb319 848 DPRINTF("stopped ==========================\n");
4f1c942b 849 return -1;
a41b2ff2
PB		 850 }
851
852 /* first check if receiver is enabled */
853
854 if (!rtl8139_receiver_enabled(s))
855 {
7cdeb319 856 DPRINTF("receiver disabled ================\n");
4f1c942b 857 return -1;
a41b2ff2
PB		 858 }
859
860 /* XXX: check this */
861 if (s->RxConfig & AcceptAllPhys) {
862 /* promiscuous: receive all */
7cdeb319 863 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 864
865 } else {
866 if (!memcmp(buf, broadcast_macaddr, 6)) {
867 /* broadcast address */
868 if (!(s->RxConfig & AcceptBroadcast))
869 {
7cdeb319 870 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 871
872 /* update tally counter */
873 ++s->tally_counters.RxERR;
874
4f1c942b 875 return size;
a41b2ff2
PB		 876 }
877
878 packet_header |= RxBroadcast;
879
7cdeb319 880 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 881
882 /* update tally counter */
883 ++s->tally_counters.RxOkBrd;
884
a41b2ff2
PB		 885 } else if (buf[0] & 0x01) {
886 /* multicast */
887 if (!(s->RxConfig & AcceptMulticast))
888 {
7cdeb319 889 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 890
891 /* update tally counter */
892 ++s->tally_counters.RxERR;
893
4f1c942b 894 return size;
a41b2ff2
PB		 895 }
896
897 int mcast_idx = compute_mcast_idx(buf);
898
899 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
900 {
7cdeb319 901 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 902
903 /* update tally counter */
904 ++s->tally_counters.RxERR;
905
4f1c942b 906 return size;
a41b2ff2
PB		 907 }
908
909 packet_header |= RxMulticast;
910
7cdeb319 911 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 912
913 /* update tally counter */
914 ++s->tally_counters.RxOkMul;
915
a41b2ff2 916 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 917 s->phys[1] == buf[1] &&
918 s->phys[2] == buf[2] &&
919 s->phys[3] == buf[3] &&
920 s->phys[4] == buf[4] &&
a41b2ff2
PB		 921 s->phys[5] == buf[5]) {
922 /* match */
923 if (!(s->RxConfig & AcceptMyPhys))
924 {
7cdeb319 925 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 926
927 /* update tally counter */
928 ++s->tally_counters.RxERR;
929
4f1c942b 930 return size;
a41b2ff2
PB		 931 }
932
933 packet_header |= RxPhysical;
934
7cdeb319 935 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 936
937 /* update tally counter */
938 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 939
940 } else {
941
7cdeb319 942 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 943
944 /* update tally counter */
945 ++s->tally_counters.RxERR;
946
4f1c942b 947 return size;
a41b2ff2
PB		 948 }
949 }
950
18dabfd1
BP		 951 /* if too small buffer, then expand it
952 * Include some tailroom in case a vlan tag is later removed. */
953 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 954 memcpy(buf1, buf, size);
18dabfd1 955 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 956 buf = buf1;
18dabfd1
BP		 957 if (size < MIN_BUF_SIZE) {
958 size = MIN_BUF_SIZE;
959 }
a41b2ff2
PB		 960 }
961
962 if (rtl8139_cp_receiver_enabled(s))
963 {
7cdeb319 964 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 965
966 /* begin C+ receiver mode */
967
968/* w0 ownership flag */
969#define CP_RX_OWN (1<<31)
970/* w0 end of ring flag */
971#define CP_RX_EOR (1<<30)
972/* w0 bits 0...12 : buffer size */
973#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
974/* w1 tag available flag */
975#define CP_RX_TAVA (1<<16)
976/* w1 bits 0...15 : VLAN tag */
977#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
978/* w2 low 32bit of Rx buffer ptr */
979/* w3 high 32bit of Rx buffer ptr */
980
981 int descriptor = s->currCPlusRxDesc;
c227f099 982 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 983
984 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
985 cplus_rx_ring_desc += 16 * descriptor;
986
7cdeb319
BP		 987 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
988 "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
989 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 990
991 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
992
993 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
994 rxdw0 = le32_to_cpu(val);
995 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
996 rxdw1 = le32_to_cpu(val);
997 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
998 rxbufLO = le32_to_cpu(val);
999 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
1000 rxbufHI = le32_to_cpu(val);
1001
7cdeb319
BP		 1002 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1003 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 1004
1005 if (!(rxdw0 & CP_RX_OWN))
1006 {
7cdeb319
BP		 1007 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1008 descriptor);
6cadb320 1009
a41b2ff2
PB		 1010 s->IntrStatus |= RxOverflow;
1011 ++s->RxMissed;
6cadb320
FB		 1012
1013 /* update tally counter */
1014 ++s->tally_counters.RxERR;
1015 ++s->tally_counters.MissPkt;
1016
a41b2ff2 1017 rtl8139_update_irq(s);
4f1c942b 1018 return size_;
a41b2ff2
PB		 1019 }
1020
1021 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1022
18dabfd1
BP		 1023 /* write VLAN info to descriptor variables. */
1024 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1025 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1026 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1027 size -= VLAN_HLEN;
1028 /* if too small buffer, use the tailroom added duing expansion */
1029 if (size < MIN_BUF_SIZE) {
1030 size = MIN_BUF_SIZE;
1031 }
1032
1033 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1034 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1035 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1036 &dot1q_buf[ETHER_TYPE_LEN]);
1037
7cdeb319
BP		 1038 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1039 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1040 } else {
1041 /* reset VLAN tag flag */
1042 rxdw1 &= ~CP_RX_TAVA;
1043 }
1044
6cadb320
FB		 1045 /* TODO: scatter the packet over available receive ring descriptors space */
1046
a41b2ff2
PB		 1047 if (size+4 > rx_space)
1048 {
7cdeb319
BP		 1049 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1050 descriptor, rx_space, size);
6cadb320 1051
a41b2ff2
PB		 1052 s->IntrStatus |= RxOverflow;
1053 ++s->RxMissed;
6cadb320
FB		 1054
1055 /* update tally counter */
1056 ++s->tally_counters.RxERR;
1057 ++s->tally_counters.MissPkt;
1058
a41b2ff2 1059 rtl8139_update_irq(s);
4f1c942b 1060 return size_;
a41b2ff2
PB		 1061 }
1062
c227f099 1063 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1064
1065 /* receive/copy to target memory */
18dabfd1
BP		 1066 if (dot1q_buf) {
1067 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1068 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1069 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1070 size - 2 * ETHER_ADDR_LEN);
1071 } else {
1072 cpu_physical_memory_write(rx_addr, buf, size);
1073 }
a41b2ff2 1074
6cadb320
FB		 1075 if (s->CpCmd & CPlusRxChkSum)
1076 {
1077 /* do some packet checksumming */
1078 }
1079
a41b2ff2 1080 /* write checksum */
18dabfd1 1081 val = cpu_to_le32(crc32(0, buf, size_));
a41b2ff2
PB		 1082 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1083
1084/* first segment of received packet flag */
1085#define CP_RX_STATUS_FS (1<<29)
1086/* last segment of received packet flag */
1087#define CP_RX_STATUS_LS (1<<28)
1088/* multicast packet flag */
1089#define CP_RX_STATUS_MAR (1<<26)
1090/* physical-matching packet flag */
1091#define CP_RX_STATUS_PAM (1<<25)
1092/* broadcast packet flag */
1093#define CP_RX_STATUS_BAR (1<<24)
1094/* runt packet flag */
1095#define CP_RX_STATUS_RUNT (1<<19)
1096/* crc error flag */
1097#define CP_RX_STATUS_CRC (1<<18)
1098/* IP checksum error flag */
1099#define CP_RX_STATUS_IPF (1<<15)
1100/* UDP checksum error flag */
1101#define CP_RX_STATUS_UDPF (1<<14)
1102/* TCP checksum error flag */
1103#define CP_RX_STATUS_TCPF (1<<13)
1104
1105 /* transfer ownership to target */
1106 rxdw0 &= ~CP_RX_OWN;
1107
1108 /* set first segment bit */
1109 rxdw0 |= CP_RX_STATUS_FS;
1110
1111 /* set last segment bit */
1112 rxdw0 |= CP_RX_STATUS_LS;
1113
1114 /* set received packet type flags */
1115 if (packet_header & RxBroadcast)
1116 rxdw0 |= CP_RX_STATUS_BAR;
1117 if (packet_header & RxMulticast)
1118 rxdw0 |= CP_RX_STATUS_MAR;
1119 if (packet_header & RxPhysical)
1120 rxdw0 |= CP_RX_STATUS_PAM;
1121
1122 /* set received size */
1123 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1124 rxdw0 |= (size+4);
1125
a41b2ff2
PB		 1126 /* update ring data */
1127 val = cpu_to_le32(rxdw0);
1128 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1129 val = cpu_to_le32(rxdw1);
1130 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1131
6cadb320
FB		 1132 /* update tally counter */
1133 ++s->tally_counters.RxOk;
1134
a41b2ff2
PB		 1135 /* seek to next Rx descriptor */
1136 if (rxdw0 & CP_RX_EOR)
1137 {
1138 s->currCPlusRxDesc = 0;
1139 }
1140 else
1141 {
1142 ++s->currCPlusRxDesc;
1143 }
1144
7cdeb319 1145 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1146
1147 }
1148 else
1149 {
7cdeb319 1150 DPRINTF("in ring Rx mode ================\n");
6cadb320 1151
a41b2ff2
PB		 1152 /* begin ring receiver mode */
1153 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1154
1155 /* if receiver buffer is empty then avail == 0 */
1156
1157 if (avail != 0 && size + 8 >= avail)
1158 {
7cdeb319
BP		 1159 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1160 "read 0x%04x === available 0x%04x need 0x%04x\n",
1161 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1162
a41b2ff2
PB		 1163 s->IntrStatus |= RxOverflow;
1164 ++s->RxMissed;
1165 rtl8139_update_irq(s);
4f1c942b 1166 return size_;
a41b2ff2
PB		 1167 }
1168
1169 packet_header |= RxStatusOK;
1170
1171 packet_header |= (((size+4) << 16) & 0xffff0000);
1172
1173 /* write header */
1174 uint32_t val = cpu_to_le32(packet_header);
1175
1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1177
1178 rtl8139_write_buffer(s, buf, size);
1179
1180 /* write checksum */
ccf1d14a 1181 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1182 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1183
1184 /* correct buffer write pointer */
1185 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1186
1187 /* now we can signal we have received something */
1188
7cdeb319
BP		 1189 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1190 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1191 }
1192
1193 s->IntrStatus |= RxOK;
6cadb320
FB		 1194
1195 if (do_interrupt)
1196 {
1197 rtl8139_update_irq(s);
1198 }
4f1c942b
MM		 1199
1200 return size_;
6cadb320
FB		 1201}
1202
1673ad51 1203static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1204{
1673ad51 1205 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1206}
1207
1208static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1209{
1210 s->RxBufferSize = bufferSize;
1211 s->RxBufPtr = 0;
1212 s->RxBufAddr = 0;
1213}
1214
7f23f812 1215static void rtl8139_reset(DeviceState *d)
a41b2ff2 1216{
7f23f812 1217 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1218 int i;
1219
1220 /* restore MAC address */
254111ec 1221 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1222
1223 /* reset interrupt mask */
1224 s->IntrStatus = 0;
1225 s->IntrMask = 0;
1226
1227 rtl8139_update_irq(s);
1228
a41b2ff2
PB		 1229 /* mark all status registers as owned by host */
1230 for (i = 0; i < 4; ++i)
1231 {
1232 s->TxStatus[i] = TxHostOwns;
1233 }
1234
1235 s->currTxDesc = 0;
1236 s->currCPlusRxDesc = 0;
1237 s->currCPlusTxDesc = 0;
1238
1239 s->RxRingAddrLO = 0;
1240 s->RxRingAddrHI = 0;
1241
1242 s->RxBuf = 0;
1243
1244 rtl8139_reset_rxring(s, 8192);
1245
1246 /* ACK the reset */
1247 s->TxConfig = 0;
1248
1249#if 0
1250// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1251 s->clock_enabled = 0;
1252#else
6cadb320 1253 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1254 s->clock_enabled = 1;
1255#endif
1256
1257 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1258
1259 /* set initial state data */
1260 s->Config0 = 0x0; /* No boot ROM */
1261 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1262 s->Config3 = 0x1; /* fast back-to-back compatible */
1263 s->Config5 = 0x0;
1264
5fafdf24 1265 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1266
1267 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1268 s->cplus_enabled = 0;
1269
a41b2ff2
PB		 1270
1271// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1272// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1273 s->BasicModeCtrl = 0x1000; // autonegotiation
1274
1275 s->BasicModeStatus = 0x7809;
1276 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1277 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1278 s->BasicModeStatus |= 0x0004; /* link is up */
1279
1280 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1281 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1282 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1283
1284 /* also reset timer and disable timer interrupt */
1285 s->TCTR = 0;
1286 s->TimerInt = 0;
1287 s->TCTR_base = 0;
1288
1289 /* reset tally counters */
1290 RTL8139TallyCounters_clear(&s->tally_counters);
1291}
1292
b1d8e52e 1293static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1294{
1295 counters->TxOk = 0;
1296 counters->RxOk = 0;
1297 counters->TxERR = 0;
1298 counters->RxERR = 0;
1299 counters->MissPkt = 0;
1300 counters->FAE = 0;
1301 counters->Tx1Col = 0;
1302 counters->TxMCol = 0;
1303 counters->RxOkPhy = 0;
1304 counters->RxOkBrd = 0;
1305 counters->RxOkMul = 0;
1306 counters->TxAbt = 0;
1307 counters->TxUndrn = 0;
1308}
1309
c227f099 1310static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1311{
1312 uint16_t val16;
1313 uint32_t val32;
1314 uint64_t val64;
1315
1316 val64 = cpu_to_le64(tally_counters->TxOk);
1317 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1318
1319 val64 = cpu_to_le64(tally_counters->RxOk);
1320 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1321
1322 val64 = cpu_to_le64(tally_counters->TxERR);
1323 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1324
1325 val32 = cpu_to_le32(tally_counters->RxERR);
1326 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1327
1328 val16 = cpu_to_le16(tally_counters->MissPkt);
1329 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1330
1331 val16 = cpu_to_le16(tally_counters->FAE);
1332 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1333
1334 val32 = cpu_to_le32(tally_counters->Tx1Col);
1335 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1336
1337 val32 = cpu_to_le32(tally_counters->TxMCol);
1338 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1339
1340 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1341 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1342
1343 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1344 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1345
1346 val32 = cpu_to_le32(tally_counters->RxOkMul);
1347 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1348
1349 val16 = cpu_to_le16(tally_counters->TxAbt);
1350 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1351
1352 val16 = cpu_to_le16(tally_counters->TxUndrn);
1353 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1354}
1355
1356/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1357
1358static const VMStateDescription vmstate_tally_counters = {
1359 .name = "tally_counters",
1360 .version_id = 1,
1361 .minimum_version_id = 1,
1362 .minimum_version_id_old = 1,
1363 .fields = (VMStateField []) {
1364 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1365 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1366 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1367 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1368 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1369 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1370 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1371 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1372 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1373 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1374 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1375 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1376 VMSTATE_END_OF_LIST()
1377 }
1378};
a41b2ff2
PB		 1379
1380static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1381{
1382 val &= 0xff;
1383
7cdeb319 1384 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1385
1386 if (val & CmdReset)
1387 {
7cdeb319 1388 DPRINTF("ChipCmd reset\n");
7f23f812 1389 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1390 }
1391 if (val & CmdRxEnb)
1392 {
7cdeb319 1393 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1394
1395 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1396 }
1397 if (val & CmdTxEnb)
1398 {
7cdeb319 1399 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1400
1401 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1402 }
1403
ebabb67a 1404 /* mask unwritable bits */
a41b2ff2
PB		 1405 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1406
1407 /* Deassert reset pin before next read */
1408 val &= ~CmdReset;
1409
1410 s->bChipCmdState = val;
1411}
1412
1413static int rtl8139_RxBufferEmpty(RTL8139State *s)
1414{
1415 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1416
1417 if (unread != 0)
1418 {
7cdeb319 1419 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1420 return 0;
1421 }
1422
7cdeb319 1423 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1424
1425 return 1;
1426}
1427
1428static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1429{
1430 uint32_t ret = s->bChipCmdState;
1431
1432 if (rtl8139_RxBufferEmpty(s))
1433 ret |= RxBufEmpty;
1434
7cdeb319 1435 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1436
1437 return ret;
1438}
1439
1440static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1441{
1442 val &= 0xffff;
1443
7cdeb319 1444 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1445
2c3891ab
AL		 1446 s->cplus_enabled = 1;
1447
ebabb67a 1448 /* mask unwritable bits */
a41b2ff2
PB		 1449 val = SET_MASKED(val, 0xff84, s->CpCmd);
1450
1451 s->CpCmd = val;
1452}
1453
1454static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1455{
1456 uint32_t ret = s->CpCmd;
1457
7cdeb319 1458 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1459
1460 return ret;
1461}
1462
1463static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1464{
7cdeb319 1465 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1466}
1467
1468static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1469{
1470 uint32_t ret = 0;
1471
7cdeb319 1472 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1473
1474 return ret;
1475}
1476
ebabb67a 1477static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2
PB		 1478{
1479 if (s->Cfg9346 & Cfg9346_Unlock)
1480 {
1481 return 1;
1482 }
1483
7cdeb319 1484 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1485
1486 return 0;
1487}
1488
1489static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1490{
1491 val &= 0xffff;
1492
7cdeb319 1493 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1494
ebabb67a 1495 /* mask unwritable bits */
e3d7e843 1496 uint32_t mask = 0x4cff;
a41b2ff2 1497
ebabb67a 1498 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1499 {
1500 /* Speed setting and autonegotiation enable bits are read-only */
1501 mask |= 0x3000;
1502 /* Duplex mode setting is read-only */
1503 mask |= 0x0100;
1504 }
1505
1506 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1507
1508 s->BasicModeCtrl = val;
1509}
1510
1511static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1512{
1513 uint32_t ret = s->BasicModeCtrl;
1514
7cdeb319 1515 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1516
1517 return ret;
1518}
1519
1520static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1521{
1522 val &= 0xffff;
1523
7cdeb319 1524 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1525
ebabb67a 1526 /* mask unwritable bits */
a41b2ff2
PB		 1527 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1528
1529 s->BasicModeStatus = val;
1530}
1531
1532static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1533{
1534 uint32_t ret = s->BasicModeStatus;
1535
7cdeb319 1536 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1537
1538 return ret;
1539}
1540
1541static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1542{
1543 val &= 0xff;
1544
7cdeb319 1545 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1546
ebabb67a 1547 /* mask unwritable bits */
a41b2ff2
PB		 1548 val = SET_MASKED(val, 0x31, s->Cfg9346);
1549
1550 uint32_t opmode = val & 0xc0;
1551 uint32_t eeprom_val = val & 0xf;
1552
1553 if (opmode == 0x80) {
1554 /* eeprom access */
1555 int eecs = (eeprom_val & 0x08)?1:0;
1556 int eesk = (eeprom_val & 0x04)?1:0;
1557 int eedi = (eeprom_val & 0x02)?1:0;
1558 prom9346_set_wire(s, eecs, eesk, eedi);
1559 } else if (opmode == 0x40) {
1560 /* Reset. */
1561 val = 0;
7f23f812 1562 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1563 }
1564
1565 s->Cfg9346 = val;
1566}
1567
1568static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1569{
1570 uint32_t ret = s->Cfg9346;
1571
1572 uint32_t opmode = ret & 0xc0;
1573
1574 if (opmode == 0x80)
1575 {
1576 /* eeprom access */
1577 int eedo = prom9346_get_wire(s);
1578 if (eedo)
1579 {
1580 ret |= 0x01;
1581 }
1582 else
1583 {
1584 ret &= ~0x01;
1585 }
1586 }
1587
7cdeb319 1588 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1589
1590 return ret;
1591}
1592
1593static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1594{
1595 val &= 0xff;
1596
7cdeb319 1597 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1598
ebabb67a 1599 if (!rtl8139_config_writable(s)) {
a41b2ff2 1600 return;
ebabb67a 1601 }
a41b2ff2 1602
ebabb67a 1603 /* mask unwritable bits */
a41b2ff2
PB		 1604 val = SET_MASKED(val, 0xf8, s->Config0);
1605
1606 s->Config0 = val;
1607}
1608
1609static uint32_t rtl8139_Config0_read(RTL8139State *s)
1610{
1611 uint32_t ret = s->Config0;
1612
7cdeb319 1613 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1614
1615 return ret;
1616}
1617
1618static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1619{
1620 val &= 0xff;
1621
7cdeb319 1622 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1623
ebabb67a 1624 if (!rtl8139_config_writable(s)) {
a41b2ff2 1625 return;
ebabb67a 1626 }
a41b2ff2 1627
ebabb67a 1628 /* mask unwritable bits */
a41b2ff2
PB		 1629 val = SET_MASKED(val, 0xC, s->Config1);
1630
1631 s->Config1 = val;
1632}
1633
1634static uint32_t rtl8139_Config1_read(RTL8139State *s)
1635{
1636 uint32_t ret = s->Config1;
1637
7cdeb319 1638 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1639
1640 return ret;
1641}
1642
1643static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1644{
1645 val &= 0xff;
1646
7cdeb319 1647 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1648
ebabb67a 1649 if (!rtl8139_config_writable(s)) {
a41b2ff2 1650 return;
ebabb67a 1651 }
a41b2ff2 1652
ebabb67a 1653 /* mask unwritable bits */
a41b2ff2
PB		 1654 val = SET_MASKED(val, 0x8F, s->Config3);
1655
1656 s->Config3 = val;
1657}
1658
1659static uint32_t rtl8139_Config3_read(RTL8139State *s)
1660{
1661 uint32_t ret = s->Config3;
1662
7cdeb319 1663 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1664
1665 return ret;
1666}
1667
1668static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1669{
1670 val &= 0xff;
1671
7cdeb319 1672 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1673
ebabb67a 1674 if (!rtl8139_config_writable(s)) {
a41b2ff2 1675 return;
ebabb67a 1676 }
a41b2ff2 1677
ebabb67a 1678 /* mask unwritable bits */
a41b2ff2
PB		 1679 val = SET_MASKED(val, 0x0a, s->Config4);
1680
1681 s->Config4 = val;
1682}
1683
1684static uint32_t rtl8139_Config4_read(RTL8139State *s)
1685{
1686 uint32_t ret = s->Config4;
1687
7cdeb319 1688 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1689
1690 return ret;
1691}
1692
1693static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1694{
1695 val &= 0xff;
1696
7cdeb319 1697 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1698
ebabb67a 1699 /* mask unwritable bits */
a41b2ff2
PB		 1700 val = SET_MASKED(val, 0x80, s->Config5);
1701
1702 s->Config5 = val;
1703}
1704
1705static uint32_t rtl8139_Config5_read(RTL8139State *s)
1706{
1707 uint32_t ret = s->Config5;
1708
7cdeb319 1709 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1710
1711 return ret;
1712}
1713
1714static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1715{
1716 if (!rtl8139_transmitter_enabled(s))
1717 {
7cdeb319 1718 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1719 return;
1720 }
1721
7cdeb319 1722 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1723
1724 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1725
1726 s->TxConfig = val;
1727}
1728
1729static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1730{
7cdeb319 1731 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1732
1733 uint32_t tc = s->TxConfig;
1734 tc &= 0xFFFFFF00;
1735 tc |= (val & 0x000000FF);
1736 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1737}
1738
1739static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1740{
1741 uint32_t ret = s->TxConfig;
1742
7cdeb319 1743 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1744
1745 return ret;
1746}
1747
1748static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1749{
7cdeb319 1750 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1751
ebabb67a 1752 /* mask unwritable bits */
a41b2ff2
PB		 1753 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1754
1755 s->RxConfig = val;
1756
1757 /* reset buffer size and read/write pointers */
1758 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1759
7cdeb319 1760 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1761}
1762
1763static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1764{
1765 uint32_t ret = s->RxConfig;
1766
7cdeb319 1767 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1768
1769 return ret;
1770}
1771
bf6b87a8
BP		 1772static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1773 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1774{
bf6b87a8
BP		 1775 struct iovec *iov = NULL;
1776
718da2b9
FB		 1777 if (!size)
1778 {
7cdeb319 1779 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1780 return;
1781 }
1782
bf6b87a8
BP		 1783 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1784 iov = (struct iovec[3]) {
1785 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1786 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1787 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1788 .iov_len = size - ETHER_ADDR_LEN * 2 },
1789 };
1790 }
1791
718da2b9
FB		 1792 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1793 {
bf6b87a8
BP		 1794 size_t buf2_size;
1795 uint8_t *buf2;
1796
1797 if (iov) {
1798 buf2_size = iov_size(iov, 3);
7267c094 1799 buf2 = g_malloc(buf2_size);
bf6b87a8
BP		 1800 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1801 buf = buf2;
1802 }
1803
7cdeb319 1804 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1805 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1806
1807 if (iov) {
7267c094 1808 g_free(buf2);
bf6b87a8 1809 }
718da2b9
FB		 1810 }
1811 else
1812 {
bf6b87a8
BP		 1813 if (iov) {
1814 qemu_sendv_packet(&s->nic->nc, iov, 3);
1815 } else {
1816 qemu_send_packet(&s->nic->nc, buf, size);
1817 }
718da2b9
FB		 1818 }
1819}
1820
a41b2ff2
PB		 1821static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1822{
1823 if (!rtl8139_transmitter_enabled(s))
1824 {
7cdeb319
BP		 1825 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1826 "disabled\n", descriptor);
a41b2ff2
PB		 1827 return 0;
1828 }
1829
1830 if (s->TxStatus[descriptor] & TxHostOwns)
1831 {
7cdeb319
BP		 1832 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1833 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1834 return 0;
1835 }
1836
7cdeb319 1837 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1838
1839 int txsize = s->TxStatus[descriptor] & 0x1fff;
1840 uint8_t txbuffer[0x2000];
1841
7cdeb319
BP		 1842 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1843 txsize, s->TxAddr[descriptor]);
a41b2ff2 1844
6cadb320 1845 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1846
1847 /* Mark descriptor as transferred */
1848 s->TxStatus[descriptor] |= TxHostOwns;
1849 s->TxStatus[descriptor] |= TxStatOK;
1850
bf6b87a8 1851 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1852
7cdeb319
BP		 1853 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1854 descriptor);
a41b2ff2
PB		 1855
1856 /* update interrupt */
1857 s->IntrStatus |= TxOK;
1858 rtl8139_update_irq(s);
1859
1860 return 1;
1861}
1862
718da2b9
FB		 1863/* structures and macros for task offloading */
1864typedef struct ip_header
1865{
1866 uint8_t ip_ver_len; /* version and header length */
1867 uint8_t ip_tos; /* type of service */
1868 uint16_t ip_len; /* total length */
1869 uint16_t ip_id; /* identification */
1870 uint16_t ip_off; /* fragment offset field */
1871 uint8_t ip_ttl; /* time to live */
1872 uint8_t ip_p; /* protocol */
1873 uint16_t ip_sum; /* checksum */
1874 uint32_t ip_src,ip_dst; /* source and dest address */
1875} ip_header;
1876
1877#define IP_HEADER_VERSION_4 4
1878#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1879#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1880
1881typedef struct tcp_header
1882{
1883 uint16_t th_sport; /* source port */
1884 uint16_t th_dport; /* destination port */
1885 uint32_t th_seq; /* sequence number */
1886 uint32_t th_ack; /* acknowledgement number */
1887 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1888 uint16_t th_win; /* window */
1889 uint16_t th_sum; /* checksum */
1890 uint16_t th_urp; /* urgent pointer */
1891} tcp_header;
1892
1893typedef struct udp_header
1894{
1895 uint16_t uh_sport; /* source port */
1896 uint16_t uh_dport; /* destination port */
1897 uint16_t uh_ulen; /* udp length */
1898 uint16_t uh_sum; /* udp checksum */
1899} udp_header;
1900
1901typedef struct ip_pseudo_header
1902{
1903 uint32_t ip_src;
1904 uint32_t ip_dst;
1905 uint8_t zeros;
1906 uint8_t ip_proto;
1907 uint16_t ip_payload;
1908} ip_pseudo_header;
1909
1910#define IP_PROTO_TCP 6
1911#define IP_PROTO_UDP 17
1912
1913#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1914#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1915#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1916
1917#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1918
1919#define TCP_FLAG_FIN 0x01
1920#define TCP_FLAG_PUSH 0x08
1921
1922/* produces ones' complement sum of data */
1923static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1924{
1925 uint32_t result = 0;
1926
1927 for (; len > 1; data+=2, len-=2)
1928 {
1929 result += *(uint16_t*)data;
1930 }
1931
1932 /* add the remainder byte */
1933 if (len)
1934 {
1935 uint8_t odd[2] = {*data, 0};
1936 result += *(uint16_t*)odd;
1937 }
1938
1939 while (result>>16)
1940 result = (result & 0xffff) + (result >> 16);
1941
1942 return result;
1943}
1944
1945static uint16_t ip_checksum(void *data, size_t len)
1946{
1947 return ~ones_complement_sum((uint8_t*)data, len);
1948}
1949
a41b2ff2
PB		 1950static int rtl8139_cplus_transmit_one(RTL8139State *s)
1951{
1952 if (!rtl8139_transmitter_enabled(s))
1953 {
7cdeb319 1954 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1955 return 0;
1956 }
1957
1958 if (!rtl8139_cp_transmitter_enabled(s))
1959 {
7cdeb319 1960 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1961 return 0 ;
1962 }
1963
1964 int descriptor = s->currCPlusTxDesc;
1965
c227f099 1966 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1967 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1968
1969 /* Normal priority ring */
1970 cplus_tx_ring_desc += 16 * descriptor;
1971
7cdeb319
BP		 1972 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1973 "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
1974 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1975
1976 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1977
1978 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1979 txdw0 = le32_to_cpu(val);
1980 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1981 txdw1 = le32_to_cpu(val);
1982 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1983 txbufLO = le32_to_cpu(val);
1984 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1985 txbufHI = le32_to_cpu(val);
1986
7cdeb319
BP		 1987 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1988 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1989
1990/* w0 ownership flag */
1991#define CP_TX_OWN (1<<31)
1992/* w0 end of ring flag */
1993#define CP_TX_EOR (1<<30)
1994/* first segment of received packet flag */
1995#define CP_TX_FS (1<<29)
1996/* last segment of received packet flag */
1997#define CP_TX_LS (1<<28)
1998/* large send packet flag */
1999#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 2000/* large send MSS mask, bits 16...25 */
2001#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2002
a41b2ff2
PB		 2003/* IP checksum offload flag */
2004#define CP_TX_IPCS (1<<18)
2005/* UDP checksum offload flag */
2006#define CP_TX_UDPCS (1<<17)
2007/* TCP checksum offload flag */
2008#define CP_TX_TCPCS (1<<16)
2009
2010/* w0 bits 0...15 : buffer size */
2011#define CP_TX_BUFFER_SIZE (1<<16)
2012#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2013/* w1 add tag flag */
2014#define CP_TX_TAGC (1<<17)
2015/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2016#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2017/* w2 low 32bit of Rx buffer ptr */
2018/* w3 high 32bit of Rx buffer ptr */
2019
2020/* set after transmission */
2021/* FIFO underrun flag */
2022#define CP_TX_STATUS_UNF (1<<25)
2023/* transmit error summary flag, valid if set any of three below */
2024#define CP_TX_STATUS_TES (1<<23)
2025/* out-of-window collision flag */
2026#define CP_TX_STATUS_OWC (1<<22)
2027/* link failure flag */
2028#define CP_TX_STATUS_LNKF (1<<21)
2029/* excessive collisions flag */
2030#define CP_TX_STATUS_EXC (1<<20)
2031
2032 if (!(txdw0 & CP_TX_OWN))
2033 {
7cdeb319 2034 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2035 return 0 ;
2036 }
2037
7cdeb319 2038 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2039
2040 if (txdw0 & CP_TX_FS)
2041 {
7cdeb319
BP		 2042 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2043 "descriptor\n", descriptor);
6cadb320
FB		 2044
2045 /* reset internal buffer offset */
2046 s->cplus_txbuffer_offset = 0;
2047 }
a41b2ff2
PB		 2048
2049 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 2050 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2051
6cadb320
FB		 2052 /* make sure we have enough space to assemble the packet */
2053 if (!s->cplus_txbuffer)
2054 {
2055 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2056 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2057 s->cplus_txbuffer_offset = 0;
718da2b9 2058
7cdeb319
BP		 2059 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2060 s->cplus_txbuffer_len);
6cadb320
FB		 2061 }
2062
2063 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2064 {
2065 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
7267c094 2066 s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2067
7cdeb319
BP		 2068 DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
2069 s->cplus_txbuffer_len);
6cadb320
FB		 2070 }
2071
2072 if (!s->cplus_txbuffer)
2073 {
2074 /* out of memory */
a41b2ff2 2075
7cdeb319
BP		 2076 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2077 s->cplus_txbuffer_len);
6cadb320
FB		 2078
2079 /* update tally counter */
2080 ++s->tally_counters.TxERR;
2081 ++s->tally_counters.TxAbt;
2082
2083 return 0;
2084 }
2085
2086 /* append more data to the packet */
2087
7cdeb319
BP		 2088 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2089 TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
2090 s->cplus_txbuffer_offset);
6cadb320
FB		 2091
2092 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2093 s->cplus_txbuffer_offset += txsize;
2094
2095 /* seek to next Rx descriptor */
2096 if (txdw0 & CP_TX_EOR)
2097 {
2098 s->currCPlusTxDesc = 0;
2099 }
2100 else
2101 {
2102 ++s->currCPlusTxDesc;
2103 if (s->currCPlusTxDesc >= 64)
2104 s->currCPlusTxDesc = 0;
2105 }
a41b2ff2
PB		 2106
2107 /* transfer ownership to target */
2108 txdw0 &= ~CP_RX_OWN;
2109
2110 /* reset error indicator bits */
2111 txdw0 &= ~CP_TX_STATUS_UNF;
2112 txdw0 &= ~CP_TX_STATUS_TES;
2113 txdw0 &= ~CP_TX_STATUS_OWC;
2114 txdw0 &= ~CP_TX_STATUS_LNKF;
2115 txdw0 &= ~CP_TX_STATUS_EXC;
2116
2117 /* update ring data */
2118 val = cpu_to_le32(txdw0);
2119 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2120
6cadb320
FB		 2121 /* Now decide if descriptor being processed is holding the last segment of packet */
2122 if (txdw0 & CP_TX_LS)
a41b2ff2 2123 {
bf6b87a8
BP		 2124 uint8_t dot1q_buffer_space[VLAN_HLEN];
2125 uint16_t *dot1q_buffer;
2126
7cdeb319
BP		 2127 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2128 descriptor);
6cadb320
FB		 2129
2130 /* can transfer fully assembled packet */
2131
2132 uint8_t *saved_buffer = s->cplus_txbuffer;
2133 int saved_size = s->cplus_txbuffer_offset;
2134 int saved_buffer_len = s->cplus_txbuffer_len;
2135
bf6b87a8
BP		 2136 /* create vlan tag */
2137 if (txdw1 & CP_TX_TAGC) {
2138 /* the vlan tag is in BE byte order in the descriptor
2139 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2140 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2141 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2142
2143 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2144 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2145 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2146 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2147 } else {
2148 dot1q_buffer = NULL;
2149 }
2150
6cadb320
FB		 2151 /* reset the card space to protect from recursive call */
2152 s->cplus_txbuffer = NULL;
2153 s->cplus_txbuffer_offset = 0;
2154 s->cplus_txbuffer_len = 0;
2155
718da2b9 2156 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2157 {
7cdeb319 2158 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2159
6cadb320 2160 /* ip packet header */
660f11be 2161 ip_header *ip = NULL;
6cadb320 2162 int hlen = 0;
718da2b9
FB		 2163 uint8_t ip_protocol = 0;
2164 uint16_t ip_data_len = 0;
6cadb320 2165
660f11be 2166 uint8_t *eth_payload_data = NULL;
718da2b9 2167 size_t eth_payload_len = 0;
6cadb320 2168
718da2b9 2169 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2170 if (proto == ETH_P_IP)
2171 {
7cdeb319 2172 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2173
2174 /* not aligned */
718da2b9
FB		 2175 eth_payload_data = saved_buffer + ETH_HLEN;
2176 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2177
718da2b9 2178 ip = (ip_header*)eth_payload_data;
6cadb320 2179
718da2b9 2180 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2181 DPRINTF("+++ C+ mode packet has bad IP version %d "
2182 "expected %d\n", IP_HEADER_VERSION(ip),
2183 IP_HEADER_VERSION_4);
6cadb320
FB		 2184 ip = NULL;
2185 } else {
718da2b9
FB		 2186 hlen = IP_HEADER_LENGTH(ip);
2187 ip_protocol = ip->ip_p;
2188 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2189 }
2190 }
2191
2192 if (ip)
2193 {
2194 if (txdw0 & CP_TX_IPCS)
2195 {
7cdeb319 2196 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2197
718da2b9 2198 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2199 /* bad packet header len */
2200 /* or packet too short */
2201 }
2202 else
2203 {
2204 ip->ip_sum = 0;
718da2b9 2205 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2206 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2207 hlen, ip->ip_sum);
6cadb320
FB		 2208 }
2209 }
2210
718da2b9 2211 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2212 {
718da2b9 2213 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2214
7cdeb319
BP		 2215 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2216 "frame data %d specified MSS=%d\n", ETH_MTU,
2217 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2218
718da2b9
FB		 2219 int tcp_send_offset = 0;
2220 int send_count = 0;
6cadb320
FB		 2221
2222 /* maximum IP header length is 60 bytes */
2223 uint8_t saved_ip_header[60];
6cadb320 2224
718da2b9
FB		 2225 /* save IP header template; data area is used in tcp checksum calculation */
2226 memcpy(saved_ip_header, eth_payload_data, hlen);
2227
2228 /* a placeholder for checksum calculation routine in tcp case */
2229 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2230 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2231
2232 /* pointer to TCP header */
2233 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2234
2235 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2236
2237 /* ETH_MTU = ip header len + tcp header len + payload */
2238 int tcp_data_len = ip_data_len - tcp_hlen;
2239 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2240
7cdeb319
BP		 2241 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2242 "data len %d TCP chunk size %d\n", ip_data_len,
2243 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2244
2245 /* note the cycle below overwrites IP header data,
2246 but restores it from saved_ip_header before sending packet */
2247
2248 int is_last_frame = 0;
2249
2250 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2251 {
2252 uint16_t chunk_size = tcp_chunk_size;
2253
2254 /* check if this is the last frame */
2255 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2256 {
2257 is_last_frame = 1;
2258 chunk_size = tcp_data_len - tcp_send_offset;
2259 }
2260
7cdeb319
BP		 2261 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2262 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2263
2264 /* add 4 TCP pseudoheader fields */
2265 /* copy IP source and destination fields */
2266 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2267
7cdeb319
BP		 2268 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2269 "packet with %d bytes data\n", tcp_hlen +
2270 chunk_size);
718da2b9
FB		 2271
2272 if (tcp_send_offset)
2273 {
2274 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2275 }
2276
2277 /* keep PUSH and FIN flags only for the last frame */
2278 if (!is_last_frame)
2279 {
2280 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2281 }
6cadb320 2282
718da2b9
FB		 2283 /* recalculate TCP checksum */
2284 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2285 p_tcpip_hdr->zeros = 0;
2286 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2287 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2288
2289 p_tcp_hdr->th_sum = 0;
2290
2291 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2292 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2293 tcp_checksum);
718da2b9
FB		 2294
2295 p_tcp_hdr->th_sum = tcp_checksum;
2296
2297 /* restore IP header */
2298 memcpy(eth_payload_data, saved_ip_header, hlen);
2299
2300 /* set IP data length and recalculate IP checksum */
2301 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2302
2303 /* increment IP id for subsequent frames */
2304 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2305
2306 ip->ip_sum = 0;
2307 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2308 DPRINTF("+++ C+ mode TSO IP header len=%d "
2309 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2310
2311 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2312 DPRINTF("+++ C+ mode TSO transferring packet size "
2313 "%d\n", tso_send_size);
bf6b87a8
BP		 2314 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2315 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2316
2317 /* add transferred count to TCP sequence number */
2318 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2319 ++send_count;
2320 }
2321
2322 /* Stop sending this frame */
2323 saved_size = 0;
2324 }
2325 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2326 {
7cdeb319 2327 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2328
2329 /* maximum IP header length is 60 bytes */
2330 uint8_t saved_ip_header[60];
2331 memcpy(saved_ip_header, eth_payload_data, hlen);
2332
2333 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2334 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2335
2336 /* add 4 TCP pseudoheader fields */
2337 /* copy IP source and destination fields */
718da2b9 2338 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2339
718da2b9 2340 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2341 {
7cdeb319
BP		 2342 DPRINTF("+++ C+ mode calculating TCP checksum for "
2343 "packet with %d bytes data\n", ip_data_len);
6cadb320 2344
718da2b9
FB		 2345 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2346 p_tcpip_hdr->zeros = 0;
2347 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2348 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2349
718da2b9 2350 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2351
2352 p_tcp_hdr->th_sum = 0;
2353
718da2b9 2354 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2355 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2356 tcp_checksum);
6cadb320
FB		 2357
2358 p_tcp_hdr->th_sum = tcp_checksum;
2359 }
718da2b9 2360 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2361 {
7cdeb319
BP		 2362 DPRINTF("+++ C+ mode calculating UDP checksum for "
2363 "packet with %d bytes data\n", ip_data_len);
6cadb320 2364
718da2b9
FB		 2365 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2366 p_udpip_hdr->zeros = 0;
2367 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2368 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2369
718da2b9 2370 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2371
6cadb320
FB		 2372 p_udp_hdr->uh_sum = 0;
2373
718da2b9 2374 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2375 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2376 udp_checksum);
6cadb320 2377
6cadb320
FB		 2378 p_udp_hdr->uh_sum = udp_checksum;
2379 }
2380
2381 /* restore IP header */
718da2b9 2382 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2383 }
2384 }
2385 }
2386
2387 /* update tally counter */
2388 ++s->tally_counters.TxOk;
2389
7cdeb319 2390 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2391
bf6b87a8
BP		 2392 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2393 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2394
2395 /* restore card space if there was no recursion and reset offset */
2396 if (!s->cplus_txbuffer)
2397 {
2398 s->cplus_txbuffer = saved_buffer;
2399 s->cplus_txbuffer_len = saved_buffer_len;
2400 s->cplus_txbuffer_offset = 0;
2401 }
2402 else
2403 {
7267c094 2404 g_free(saved_buffer);
6cadb320 2405 }
a41b2ff2
PB		 2406 }
2407 else
2408 {
7cdeb319 2409 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2410 }
2411
a41b2ff2
PB		 2412 return 1;
2413}
2414
2415static void rtl8139_cplus_transmit(RTL8139State *s)
2416{
2417 int txcount = 0;
2418
2419 while (rtl8139_cplus_transmit_one(s))
2420 {
2421 ++txcount;
2422 }
2423
2424 /* Mark transfer completed */
2425 if (!txcount)
2426 {
7cdeb319
BP		 2427 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2428 s->currCPlusTxDesc);
a41b2ff2
PB		 2429 }
2430 else
2431 {
2432 /* update interrupt status */
2433 s->IntrStatus |= TxOK;
2434 rtl8139_update_irq(s);
2435 }
2436}
2437
2438static void rtl8139_transmit(RTL8139State *s)
2439{
2440 int descriptor = s->currTxDesc, txcount = 0;
2441
2442 /*while*/
2443 if (rtl8139_transmit_one(s, descriptor))
2444 {
2445 ++s->currTxDesc;
2446 s->currTxDesc %= 4;
2447 ++txcount;
2448 }
2449
2450 /* Mark transfer completed */
2451 if (!txcount)
2452 {
7cdeb319
BP		 2453 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2454 s->currTxDesc);
a41b2ff2
PB		 2455 }
2456}
2457
2458static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2459{
2460
2461 int descriptor = txRegOffset/4;
6cadb320
FB		 2462
2463 /* handle C+ transmit mode register configuration */
2464
2c3891ab 2465 if (s->cplus_enabled)
6cadb320 2466 {
7cdeb319
BP		 2467 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2468 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2469
2470 /* handle Dump Tally Counters command */
2471 s->TxStatus[descriptor] = val;
2472
2473 if (descriptor == 0 && (val & 0x8))
2474 {
c227f099 2475 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2476
2477 /* dump tally counters to specified memory location */
2478 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2479
2480 /* mark dump completed */
2481 s->TxStatus[0] &= ~0x8;
2482 }
2483
2484 return;
2485 }
2486
7cdeb319
BP		 2487 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2488 txRegOffset, val, descriptor);
a41b2ff2
PB		 2489
2490 /* mask only reserved bits */
2491 val &= ~0xff00c000; /* these bits are reset on write */
2492 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2493
2494 s->TxStatus[descriptor] = val;
2495
2496 /* attempt to start transmission */
2497 rtl8139_transmit(s);
2498}
2499
2500static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2501{
2502 uint32_t ret = s->TxStatus[txRegOffset/4];
2503
7cdeb319 2504 DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
a41b2ff2
PB		 2505
2506 return ret;
2507}
2508
2509static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2510{
2511 uint16_t ret = 0;
2512
2513 /* Simulate TSAD, it is read only anyway */
2514
2515 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2516 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2517 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2518 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2519
2520 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2521 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2522 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2523 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2524
a41b2ff2
PB		 2525 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2526 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2527 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2528 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2529
a41b2ff2
PB		 2530 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2531 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2532 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2533 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2534
a41b2ff2 2535
7cdeb319 2536 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2537
2538 return ret;
2539}
2540
2541static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2542{
2543 uint16_t ret = s->CSCR;
2544
7cdeb319 2545 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2546
2547 return ret;
2548}
2549
2550static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2551{
7cdeb319 2552 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2553
290a0933 2554 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2555}
2556
2557static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2558{
290a0933 2559 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2560
7cdeb319 2561 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2562
2563 return ret;
2564}
2565
2566static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2567{
7cdeb319 2568 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2569
2570 /* this value is off by 16 */
2571 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2572
7cdeb319
BP		 2573 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2574 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2575}
2576
2577static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2578{
2579 /* this value is off by 16 */
2580 uint32_t ret = s->RxBufPtr - 0x10;
2581
7cdeb319 2582 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2583
2584 return ret;
2585}
2586
2587static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2588{
2589 /* this value is NOT off by 16 */
2590 uint32_t ret = s->RxBufAddr;
2591
7cdeb319 2592 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2593
2594 return ret;
2595}
2596
2597static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2598{
7cdeb319 2599 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2600
2601 s->RxBuf = val;
2602
2603 /* may need to reset rxring here */
2604}
2605
2606static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2607{
2608 uint32_t ret = s->RxBuf;
2609
7cdeb319 2610 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2611
2612 return ret;
2613}
2614
2615static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2616{
7cdeb319 2617 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2618
ebabb67a 2619 /* mask unwritable bits */
a41b2ff2
PB		 2620 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2621
2622 s->IntrMask = val;
2623
74475455 2624 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2625 rtl8139_update_irq(s);
05447803 2626
a41b2ff2
PB		 2627}
2628
2629static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2630{
2631 uint32_t ret = s->IntrMask;
2632
7cdeb319 2633 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2634
2635 return ret;
2636}
2637
2638static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2639{
7cdeb319 2640 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2641
2642#if 0
2643
2644 /* writing to ISR has no effect */
2645
2646 return;
2647
2648#else
2649 uint16_t newStatus = s->IntrStatus & ~val;
2650
ebabb67a 2651 /* mask unwritable bits */
a41b2ff2
PB		 2652 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2653
2654 /* writing 1 to interrupt status register bit clears it */
2655 s->IntrStatus = 0;
2656 rtl8139_update_irq(s);
2657
2658 s->IntrStatus = newStatus;
05447803
FZ		 2659 /*
2660 * Computing if we miss an interrupt here is not that correct but
2661 * considered that we should have had already an interrupt
2662 * and probably emulated is slower is better to assume this resetting was
2663 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2664 */
74475455 2665 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2666 rtl8139_update_irq(s);
05447803 2667
a41b2ff2
PB		 2668#endif
2669}
2670
2671static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2672{
74475455 2673 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2674
a41b2ff2
PB		 2675 uint32_t ret = s->IntrStatus;
2676
7cdeb319 2677 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2678
2679#if 0
2680
2681 /* reading ISR clears all interrupts */
2682 s->IntrStatus = 0;
2683
2684 rtl8139_update_irq(s);
2685
2686#endif
2687
2688 return ret;
2689}
2690
2691static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2692{
7cdeb319 2693 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2694
ebabb67a 2695 /* mask unwritable bits */
a41b2ff2
PB		 2696 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2697
2698 s->MultiIntr = val;
2699}
2700
2701static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2702{
2703 uint32_t ret = s->MultiIntr;
2704
7cdeb319 2705 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2706
2707 return ret;
2708}
2709
2710static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2711{
2712 RTL8139State *s = opaque;
2713
2714 addr &= 0xff;
2715
2716 switch (addr)
2717 {
2718 case MAC0 ... MAC0+5:
2719 s->phys[addr - MAC0] = val;
2720 break;
2721 case MAC0+6 ... MAC0+7:
2722 /* reserved */
2723 break;
2724 case MAR0 ... MAR0+7:
2725 s->mult[addr - MAR0] = val;
2726 break;
2727 case ChipCmd:
2728 rtl8139_ChipCmd_write(s, val);
2729 break;
2730 case Cfg9346:
2731 rtl8139_Cfg9346_write(s, val);
2732 break;
2733 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2734 rtl8139_TxConfig_writeb(s, val);
2735 break;
2736 case Config0:
2737 rtl8139_Config0_write(s, val);
2738 break;
2739 case Config1:
2740 rtl8139_Config1_write(s, val);
2741 break;
2742 case Config3:
2743 rtl8139_Config3_write(s, val);
2744 break;
2745 case Config4:
2746 rtl8139_Config4_write(s, val);
2747 break;
2748 case Config5:
2749 rtl8139_Config5_write(s, val);
2750 break;
2751 case MediaStatus:
2752 /* ignore */
7cdeb319
BP		 2753 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2754 val);
a41b2ff2
PB		 2755 break;
2756
2757 case HltClk:
7cdeb319 2758 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2759 if (val == 'R')
2760 {
2761 s->clock_enabled = 1;
2762 }
2763 else if (val == 'H')
2764 {
2765 s->clock_enabled = 0;
2766 }
2767 break;
2768
2769 case TxThresh:
7cdeb319 2770 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2771 s->TxThresh = val;
2772 break;
2773
2774 case TxPoll:
7cdeb319 2775 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2776 if (val & (1 << 7))
2777 {
7cdeb319
BP		 2778 DPRINTF("C+ TxPoll high priority transmission (not "
2779 "implemented)\n");
a41b2ff2
PB		 2780 //rtl8139_cplus_transmit(s);
2781 }
2782 if (val & (1 << 6))
2783 {
7cdeb319 2784 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2785 rtl8139_cplus_transmit(s);
2786 }
2787
2788 break;
2789
2790 default:
7cdeb319
BP		 2791 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2792 val);
a41b2ff2
PB		 2793 break;
2794 }
2795}
2796
2797static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2798{
2799 RTL8139State *s = opaque;
2800
2801 addr &= 0xfe;
2802
2803 switch (addr)
2804 {
2805 case IntrMask:
2806 rtl8139_IntrMask_write(s, val);
2807 break;
2808
2809 case IntrStatus:
2810 rtl8139_IntrStatus_write(s, val);
2811 break;
2812
2813 case MultiIntr:
2814 rtl8139_MultiIntr_write(s, val);
2815 break;
2816
2817 case RxBufPtr:
2818 rtl8139_RxBufPtr_write(s, val);
2819 break;
2820
2821 case BasicModeCtrl:
2822 rtl8139_BasicModeCtrl_write(s, val);
2823 break;
2824 case BasicModeStatus:
2825 rtl8139_BasicModeStatus_write(s, val);
2826 break;
2827 case NWayAdvert:
7cdeb319 2828 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2829 s->NWayAdvert = val;
2830 break;
2831 case NWayLPAR:
7cdeb319 2832 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2833 break;
2834 case NWayExpansion:
7cdeb319 2835 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2836 s->NWayExpansion = val;
2837 break;
2838
2839 case CpCmd:
2840 rtl8139_CpCmd_write(s, val);
2841 break;
2842
6cadb320
FB		 2843 case IntrMitigate:
2844 rtl8139_IntrMitigate_write(s, val);
2845 break;
2846
a41b2ff2 2847 default:
7cdeb319
BP		 2848 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2849 addr, val);
a41b2ff2 2850
a41b2ff2
PB		 2851 rtl8139_io_writeb(opaque, addr, val & 0xff);
2852 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2853 break;
2854 }
2855}
2856
05447803
FZ		 2857static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2858{
2859 int64_t pci_time, next_time;
2860 uint32_t low_pci;
2861
7cdeb319 2862 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2863
2864 if (s->TimerExpire && current_time >= s->TimerExpire) {
2865 s->IntrStatus |= PCSTimeout;
2866 rtl8139_update_irq(s);
2867 }
2868
2869 /* Set QEMU timer only if needed that is
2870 * - TimerInt <> 0 (we have a timer)
2871 * - mask = 1 (we want an interrupt timer)
2872 * - irq = 0 (irq is not already active)
2873 * If any of above change we need to compute timer again
2874 * Also we must check if timer is passed without QEMU timer
2875 */
2876 s->TimerExpire = 0;
2877 if (!s->TimerInt) {
2878 return;
2879 }
2880
2881 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2882 get_ticks_per_sec());
2883 low_pci = pci_time & 0xffffffff;
2884 pci_time = pci_time - low_pci + s->TimerInt;
2885 if (low_pci >= s->TimerInt) {
2886 pci_time += 0x100000000LL;
2887 }
2888 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2889 PCI_FREQUENCY);
2890 s->TimerExpire = next_time;
2891
2892 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2893 qemu_mod_timer(s->timer, next_time);
2894 }
2895}
2896
a41b2ff2
PB		 2897static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2898{
2899 RTL8139State *s = opaque;
2900
2901 addr &= 0xfc;
2902
2903 switch (addr)
2904 {
2905 case RxMissed:
7cdeb319 2906 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2907 s->RxMissed = 0;
2908 break;
2909
2910 case TxConfig:
2911 rtl8139_TxConfig_write(s, val);
2912 break;
2913
2914 case RxConfig:
2915 rtl8139_RxConfig_write(s, val);
2916 break;
2917
2918 case TxStatus0 ... TxStatus0+4*4-1:
2919 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2920 break;
2921
2922 case TxAddr0 ... TxAddr0+4*4-1:
2923 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2924 break;
2925
2926 case RxBuf:
2927 rtl8139_RxBuf_write(s, val);
2928 break;
2929
2930 case RxRingAddrLO:
7cdeb319 2931 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2932 s->RxRingAddrLO = val;
2933 break;
2934
2935 case RxRingAddrHI:
7cdeb319 2936 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2937 s->RxRingAddrHI = val;
2938 break;
2939
6cadb320 2940 case Timer:
7cdeb319 2941 DPRINTF("TCTR Timer reset on write\n");
74475455 2942 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2943 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2944 break;
2945
2946 case FlashReg:
7cdeb319 2947 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2948 if (s->TimerInt != val) {
2949 s->TimerInt = val;
74475455 2950 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2951 }
6cadb320
FB		 2952 break;
2953
a41b2ff2 2954 default:
7cdeb319
BP		 2955 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2956 addr, val);
a41b2ff2
PB		 2957 rtl8139_io_writeb(opaque, addr, val & 0xff);
2958 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2959 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2960 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2961 break;
2962 }
2963}
2964
2965static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2966{
2967 RTL8139State *s = opaque;
2968 int ret;
2969
2970 addr &= 0xff;
2971
2972 switch (addr)
2973 {
2974 case MAC0 ... MAC0+5:
2975 ret = s->phys[addr - MAC0];
2976 break;
2977 case MAC0+6 ... MAC0+7:
2978 ret = 0;
2979 break;
2980 case MAR0 ... MAR0+7:
2981 ret = s->mult[addr - MAR0];
2982 break;
2983 case ChipCmd:
2984 ret = rtl8139_ChipCmd_read(s);
2985 break;
2986 case Cfg9346:
2987 ret = rtl8139_Cfg9346_read(s);
2988 break;
2989 case Config0:
2990 ret = rtl8139_Config0_read(s);
2991 break;
2992 case Config1:
2993 ret = rtl8139_Config1_read(s);
2994 break;
2995 case Config3:
2996 ret = rtl8139_Config3_read(s);
2997 break;
2998 case Config4:
2999 ret = rtl8139_Config4_read(s);
3000 break;
3001 case Config5:
3002 ret = rtl8139_Config5_read(s);
3003 break;
3004
3005 case MediaStatus:
3006 ret = 0xd0;
7cdeb319 3007 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3008 break;
3009
3010 case HltClk:
3011 ret = s->clock_enabled;
7cdeb319 3012 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3013 break;
3014
3015 case PCIRevisionID:
6cadb320 3016 ret = RTL8139_PCI_REVID;
7cdeb319 3017 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3018 break;
3019
3020 case TxThresh:
3021 ret = s->TxThresh;
7cdeb319 3022 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3023 break;
3024
3025 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3026 ret = s->TxConfig >> 24;
7cdeb319 3027 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3028 break;
3029
3030 default:
7cdeb319 3031 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3032 ret = 0;
3033 break;
3034 }
3035
3036 return ret;
3037}
3038
3039static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3040{
3041 RTL8139State *s = opaque;
3042 uint32_t ret;
3043
3044 addr &= 0xfe; /* mask lower bit */
3045
3046 switch (addr)
3047 {
3048 case IntrMask:
3049 ret = rtl8139_IntrMask_read(s);
3050 break;
3051
3052 case IntrStatus:
3053 ret = rtl8139_IntrStatus_read(s);
3054 break;
3055
3056 case MultiIntr:
3057 ret = rtl8139_MultiIntr_read(s);
3058 break;
3059
3060 case RxBufPtr:
3061 ret = rtl8139_RxBufPtr_read(s);
3062 break;
3063
6cadb320
FB		 3064 case RxBufAddr:
3065 ret = rtl8139_RxBufAddr_read(s);
3066 break;
3067
a41b2ff2
PB		 3068 case BasicModeCtrl:
3069 ret = rtl8139_BasicModeCtrl_read(s);
3070 break;
3071 case BasicModeStatus:
3072 ret = rtl8139_BasicModeStatus_read(s);
3073 break;
3074 case NWayAdvert:
3075 ret = s->NWayAdvert;
7cdeb319 3076 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3077 break;
3078 case NWayLPAR:
3079 ret = s->NWayLPAR;
7cdeb319 3080 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3081 break;
3082 case NWayExpansion:
3083 ret = s->NWayExpansion;
7cdeb319 3084 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3085 break;
3086
3087 case CpCmd:
3088 ret = rtl8139_CpCmd_read(s);
3089 break;
3090
6cadb320
FB		 3091 case IntrMitigate:
3092 ret = rtl8139_IntrMitigate_read(s);
3093 break;
3094
a41b2ff2
PB		 3095 case TxSummary:
3096 ret = rtl8139_TSAD_read(s);
3097 break;
3098
3099 case CSCR:
3100 ret = rtl8139_CSCR_read(s);
3101 break;
3102
3103 default:
7cdeb319 3104 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3105
a41b2ff2
PB		 3106 ret = rtl8139_io_readb(opaque, addr);
3107 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3108
7cdeb319 3109 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3110 break;
3111 }
3112
3113 return ret;
3114}
3115
3116static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3117{
3118 RTL8139State *s = opaque;
3119 uint32_t ret;
3120
3121 addr &= 0xfc; /* also mask low 2 bits */
3122
3123 switch (addr)
3124 {
3125 case RxMissed:
3126 ret = s->RxMissed;
3127
7cdeb319 3128 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3129 break;
3130
3131 case TxConfig:
3132 ret = rtl8139_TxConfig_read(s);
3133 break;
3134
3135 case RxConfig:
3136 ret = rtl8139_RxConfig_read(s);
3137 break;
3138
3139 case TxStatus0 ... TxStatus0+4*4-1:
3140 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3141 break;
3142
3143 case TxAddr0 ... TxAddr0+4*4-1:
3144 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3145 break;
3146
3147 case RxBuf:
3148 ret = rtl8139_RxBuf_read(s);
3149 break;
3150
3151 case RxRingAddrLO:
3152 ret = s->RxRingAddrLO;
7cdeb319 3153 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3154 break;
3155
3156 case RxRingAddrHI:
3157 ret = s->RxRingAddrHI;
7cdeb319 3158 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3159 break;
3160
3161 case Timer:
74475455 3162 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3163 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3164 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3165 break;
3166
3167 case FlashReg:
3168 ret = s->TimerInt;
7cdeb319 3169 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3170 break;
3171
3172 default:
7cdeb319 3173 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3174
a41b2ff2
PB		 3175 ret = rtl8139_io_readb(opaque, addr);
3176 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3177 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3178 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3179
7cdeb319 3180 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3181 break;
3182 }
3183
3184 return ret;
3185}
3186
3187/* */
3188
3189static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3190{
3191 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3192}
3193
3194static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3195{
3196 rtl8139_io_writew(opaque, addr & 0xFF, val);
3197}
3198
3199static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3200{
3201 rtl8139_io_writel(opaque, addr & 0xFF, val);
3202}
3203
3204static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3205{
3206 return rtl8139_io_readb(opaque, addr & 0xFF);
3207}
3208
3209static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3210{
3211 return rtl8139_io_readw(opaque, addr & 0xFF);
3212}
3213
3214static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3215{
3216 return rtl8139_io_readl(opaque, addr & 0xFF);
3217}
3218
3219/* */
3220
c227f099 3221static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3222{
3223 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3224}
3225
c227f099 3226static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3227{
3228 rtl8139_io_writew(opaque, addr & 0xFF, val);
3229}
3230
c227f099 3231static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3232{
3233 rtl8139_io_writel(opaque, addr & 0xFF, val);
3234}
3235
c227f099 3236static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3237{
3238 return rtl8139_io_readb(opaque, addr & 0xFF);
3239}
3240
c227f099 3241static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3242{
5fedc612 3243 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3244 return val;
a41b2ff2
PB		 3245}
3246
c227f099 3247static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3248{
5fedc612 3249 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3250 return val;
a41b2ff2
PB		 3251}
3252
060110c3 3253static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3254{
6597ebbb 3255 RTL8139State* s = opaque;
74475455 3256 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3257 if (version_id < 4) {
2c3891ab
AL		 3258 s->cplus_enabled = s->CpCmd != 0;
3259 }
3260
a41b2ff2
PB		 3261 return 0;
3262}
3263
c574ba5a
AW		 3264static bool rtl8139_hotplug_ready_needed(void *opaque)
3265{
3266 return qdev_machine_modified();
3267}
3268
3269static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3270 .name = "rtl8139/hotplug_ready",
3271 .version_id = 1,
3272 .minimum_version_id = 1,
3273 .minimum_version_id_old = 1,
3274 .fields = (VMStateField []) {
3275 VMSTATE_END_OF_LIST()
3276 }
3277};
3278
05447803
FZ		 3279static void rtl8139_pre_save(void *opaque)
3280{
3281 RTL8139State* s = opaque;
74475455 3282 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3283
3284 /* set IntrStatus correctly */
3285 rtl8139_set_next_tctr_time(s, current_time);
3286 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3287 get_ticks_per_sec());
bd80f3fc 3288 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3289}
3290
060110c3
JQ		 3291static const VMStateDescription vmstate_rtl8139 = {
3292 .name = "rtl8139",
3293 .version_id = 4,
3294 .minimum_version_id = 3,
3295 .minimum_version_id_old = 3,
3296 .post_load = rtl8139_post_load,
05447803 3297 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3298 .fields = (VMStateField []) {
3299 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3300 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3301 VMSTATE_BUFFER(mult, RTL8139State),
3302 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3303 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3304
3305 VMSTATE_UINT32(RxBuf, RTL8139State),
3306 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3307 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3308 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3309
3310 VMSTATE_UINT16(IntrStatus, RTL8139State),
3311 VMSTATE_UINT16(IntrMask, RTL8139State),
3312
3313 VMSTATE_UINT32(TxConfig, RTL8139State),
3314 VMSTATE_UINT32(RxConfig, RTL8139State),
3315 VMSTATE_UINT32(RxMissed, RTL8139State),
3316 VMSTATE_UINT16(CSCR, RTL8139State),
3317
3318 VMSTATE_UINT8(Cfg9346, RTL8139State),
3319 VMSTATE_UINT8(Config0, RTL8139State),
3320 VMSTATE_UINT8(Config1, RTL8139State),
3321 VMSTATE_UINT8(Config3, RTL8139State),
3322 VMSTATE_UINT8(Config4, RTL8139State),
3323 VMSTATE_UINT8(Config5, RTL8139State),
3324
3325 VMSTATE_UINT8(clock_enabled, RTL8139State),
3326 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3327
3328 VMSTATE_UINT16(MultiIntr, RTL8139State),
3329
3330 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3331 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3332 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3333 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3334 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3335
3336 VMSTATE_UINT16(CpCmd, RTL8139State),
3337 VMSTATE_UINT8(TxThresh, RTL8139State),
3338
3339 VMSTATE_UNUSED(4),
3340 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3341 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3342
3343 VMSTATE_UINT32(currTxDesc, RTL8139State),
3344 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3345 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3346 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3347 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3348
3349 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3350 VMSTATE_INT32(eeprom.mode, RTL8139State),
3351 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3352 VMSTATE_UINT8(eeprom.address, RTL8139State),
3353 VMSTATE_UINT16(eeprom.input, RTL8139State),
3354 VMSTATE_UINT16(eeprom.output, RTL8139State),
3355
3356 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3357 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3358 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3359 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3360
3361 VMSTATE_UINT32(TCTR, RTL8139State),
3362 VMSTATE_UINT32(TimerInt, RTL8139State),
3363 VMSTATE_INT64(TCTR_base, RTL8139State),
3364
3365 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3366 vmstate_tally_counters, RTL8139TallyCounters),
3367
3368 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3369 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3370 },
3371 .subsections = (VMStateSubsection []) {
3372 {
3373 .vmsd = &vmstate_rtl8139_hotplug_ready,
3374 .needed = rtl8139_hotplug_ready_needed,
3375 }, {
3376 /* empty */
3377 }
060110c3
JQ		 3378 }
3379};
3380
a41b2ff2
PB		 3381/***********************************************************/
3382/* PCI RTL8139 definitions */
3383
bd80f3fc
AK		 3384static const MemoryRegionPortio rtl8139_portio[] = {
3385 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3386 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3387 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3388 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3389 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3390 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3391 PORTIO_END_OF_LIST()
3392};
a41b2ff2 3393
bd80f3fc
AK		 3394static const MemoryRegionOps rtl8139_io_ops = {
3395 .old_portio = rtl8139_portio,
3396 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3397};
3398
bd80f3fc
AK		 3399static const MemoryRegionOps rtl8139_mmio_ops = {
3400 .old_mmio = {
3401 .read = {
3402 rtl8139_mmio_readb,
3403 rtl8139_mmio_readw,
3404 rtl8139_mmio_readl,
3405 },
3406 .write = {
3407 rtl8139_mmio_writeb,
3408 rtl8139_mmio_writew,
3409 rtl8139_mmio_writel,
3410 },
3411 },
3412 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3413};
3414
6cadb320
FB		 3415static void rtl8139_timer(void *opaque)
3416{
3417 RTL8139State *s = opaque;
3418
6cadb320
FB		 3419 if (!s->clock_enabled)
3420 {
7cdeb319 3421 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3422 return;
3423 }
3424
05447803
FZ		 3425 s->IntrStatus |= PCSTimeout;
3426 rtl8139_update_irq(s);
74475455 3427 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3428}
6cadb320 3429
1673ad51 3430static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3431{
1673ad51 3432 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3433
1673ad51 3434 s->nic = NULL;
254111ec
GH		 3435}
3436
3437static int pci_rtl8139_uninit(PCIDevice *dev)
3438{
3439 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3440
bd80f3fc
AK		 3441 memory_region_destroy(&s->bar_io);
3442 memory_region_destroy(&s->bar_mem);
b946a153 3443 if (s->cplus_txbuffer) {
7267c094 3444 g_free(s->cplus_txbuffer);
b946a153
AL		 3445 s->cplus_txbuffer = NULL;
3446 }
b946a153
AL		 3447 qemu_del_timer(s->timer);
3448 qemu_free_timer(s->timer);
1673ad51 3449 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3450 return 0;
3451}
3452
1673ad51
MM		 3453static NetClientInfo net_rtl8139_info = {
3454 .type = NET_CLIENT_TYPE_NIC,
3455 .size = sizeof(NICState),
3456 .can_receive = rtl8139_can_receive,
3457 .receive = rtl8139_receive,
3458 .cleanup = rtl8139_cleanup,
3459};
3460
81a322d4 3461static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3462{
efd6dd45 3463 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3464 uint8_t *pci_conf;
3b46e624 3465
efd6dd45 3466 pci_conf = s->dev.config;
817e0b6f 3467 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3468 /* TODO: start of capability list, but no capability
3469 * list bit in status register, and offset 0xdc seems unused. */
3470 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3471
bd80f3fc
AK		 3472 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3473 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
e824b2cc
AK		 3474 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3475 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3476
254111ec 3477 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3478
7165448a
WD		 3479 /* prepare eeprom */
3480 s->eeprom.contents[0] = 0x8129;
3481#if 1
3482 /* PCI vendor and device ID should be mirrored here */
3483 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3484 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3485#endif
3486 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3487 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3488 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3489
1673ad51
MM		 3490 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3491 dev->qdev.info->name, dev->qdev.id, s);
3492 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3493
3494 s->cplus_txbuffer = NULL;
3495 s->cplus_txbuffer_len = 0;
3496 s->cplus_txbuffer_offset = 0;
3b46e624 3497
05447803 3498 s->TimerExpire = 0;
74475455
PB		 3499 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3500 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3501
3502 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3503
81a322d4 3504 return 0;
a41b2ff2 3505}
9d07d757 3506
0aab0d3a 3507static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3508 .qdev.name = "rtl8139",
3509 .qdev.size = sizeof(RTL8139State),
3510 .qdev.reset = rtl8139_reset,
be73cfe2 3511 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3512 .init = pci_rtl8139_init,
e3936fa5 3513 .exit = pci_rtl8139_uninit,
5ee8ad71 3514 .romfile = "pxe-rtl8139.rom",
7cba16a7
IY		 3515 .vendor_id = PCI_VENDOR_ID_REALTEK,
3516 .device_id = PCI_DEVICE_ID_REALTEK_8139,
3517 .revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
3518 .class_id = PCI_CLASS_NETWORK_ETHERNET,
254111ec
GH		 3519 .qdev.props = (Property[]) {
3520 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3521 DEFINE_PROP_END_OF_LIST(),
3522 }
0aab0d3a
GH		 3523};
3524
9d07d757
PB		 3525static void rtl8139_register_devices(void)
3526{
0aab0d3a 3527 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3528}
3529
3530device_init(rtl8139_register_devices)
Empty description
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