[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc/mac.h"
#include "pci/pci.h"
#include "pci/pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"

#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)

typedef struct UNINState {
    PCIHostState parent_obj;

    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth U3 AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth internal bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(s);
    d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, "pci",
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(h->bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return h->bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(dev);
    d = U3_AGP_HOST_BRIDGE(dev);

    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, "pci",
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(h->bus, 11 << 3, "u3-agp");

    return h->bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init      = unin_main_pci_host_init;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init      = u3_agp_pci_host_init;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init      = unin_agp_pci_host_init;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init      = unin_internal_pci_host_init;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_main_init_device;
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_u3_agp_init_device;
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_agp_init_device;
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_internal_init_device;
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b	24	#include "hw.h"
baec1910	25	#include "ppc/mac.h"
a2cb15b0 MT	26	#include "pci/pci.h"
a2cb15b0 MT	27	#include "pci/pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
57fd7b7f AF	41	#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
	42	#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
	43	#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
	44	#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
	45
	46	#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
	47	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
	48	#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
	49	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
	50	#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
	51	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
	52	#define U3_AGP_HOST_BRIDGE(obj) \
	53	OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
	54
2e29bd04	55	typedef struct UNINState {
67c332fd	56	PCIHostState parent_obj;
57fd7b7f	57
46f3069c BS	58	MemoryRegion pci_mmio;
46f3069c BS	59	MemoryRegion pci_hole;
2e29bd04	60	} UNINState;
502a5395	61
d2b59317	62	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	63	{
fa0be69a AG	64	int retval;
	65	int devfn = pci_dev->devfn & 0x00FFFFFF;
	66
	67	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	68
	69	return retval;
d2b59317 PB	70	}
d2b59317 PB	71
5d4e84c8	72	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	73	{
5d4e84c8 JQ	74	qemu_irq *pic = opaque;
5d4e84c8 JQ	75
fa0be69a AG	76	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	77	unin_irq_line[irq_num], level);
	78	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	79	}
502a5395 PB	80
d86f0e32 AG	81	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	82	{
	83	uint32_t retval;
	84
	85	if (reg & (1u << 31)) {
	86	/* XXX OpenBIOS compatibility hack */
	87	retval = reg \| (addr & 3);
	88	} else if (reg & 1) {
	89	/* CFA1 style */
	90	retval = (reg & ~7u) \| (addr & 7);
	91	} else {
	92	uint32_t slot, func;
	93
	94	/* Grab CFA0 style values */
	95	slot = ffs(reg & 0xfffff800) - 1;
	96	func = (reg >> 8) & 7;
	97
	98	/* ... and then convert them to x86 format */
	99	/* config pointer */
	100	retval = (reg & (0xff - 7)) \| (addr & 7);
	101	/* slot */
	102	retval \|= slot << 11;
	103	/* fn */
	104	retval \|= func << 8;
	105	}
	106
	107
	108	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	109	reg, addr, retval);
	110
	111	return retval;
	112	}
	113
a8170e5e	114	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	115	uint64_t val, unsigned len)
d86f0e32	116	{
d0ed8076	117	UNINState *s = opaque;
67c332fd	118	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d0ed8076 AK	119	UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
d0ed8076 AK	120	addr, len, val);
67c332fd AF	121	pci_data_write(phb->bus,
67c332fd AF	122	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	123	val, len);
	124	}
	125
a8170e5e	126	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	127	unsigned len)
d86f0e32	128	{
d0ed8076	129	UNINState *s = opaque;
67c332fd	130	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	131	uint32_t val;
d86f0e32 AG	132
67c332fd AF	133	val = pci_data_read(phb->bus,
67c332fd AF	134	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	135	len);
d0ed8076 AK	136	UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
d0ed8076 AK	137	addr, len, val);
d86f0e32 AG	138	return val;
	139	}
	140
d0ed8076 AK	141	static const MemoryRegionOps unin_data_ops = {
	142	.read = unin_data_read,
	143	.write = unin_data_write,
	144	.endianness = DEVICE_LITTLE_ENDIAN,
	145	};
	146
81a322d4	147	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	148	{
ff452ace	149	PCIHostState *h;
502a5395 PB	150
	151	/* Use values found on a real PowerMac */
	152	/* Uninorth main bus */
8558d942	153	h = PCI_HOST_BRIDGE(dev);
502a5395	154
57fd7b7f AF	155	memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
	156	dev, "pci-conf-idx", 0x1000);
	157	memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
d0ed8076	158	"pci-conf-data", 0x1000);
57fd7b7f AF	159	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	160	sysbus_init_mmio(dev, &h->data_mem);
2e29bd04	161
81a322d4	162	return 0;
2e29bd04 BS	163	}
2e29bd04 BS	164
d0ed8076	165
0f921197 AG	166	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	167	{
ff452ace	168	PCIHostState *h;
0f921197 AG	169
0f921197 AG	170	/* Uninorth U3 AGP bus */
8558d942	171	h = PCI_HOST_BRIDGE(dev);
0f921197	172
57fd7b7f AF	173	memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
	174	dev, "pci-conf-idx", 0x1000);
	175	memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
d0ed8076	176	"pci-conf-data", 0x1000);
57fd7b7f AF	177	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	178	sysbus_init_mmio(dev, &h->data_mem);
0f921197	179
0f921197 AG	180	return 0;
	181	}
	182
81a322d4	183	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	184	{
ff452ace	185	PCIHostState *h;
2e29bd04 BS	186
2e29bd04 BS	187	/* Uninorth AGP bus */
8558d942	188	h = PCI_HOST_BRIDGE(dev);
57fd7b7f AF	189
	190	memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
	191	dev, "pci-conf-idx", 0x1000);
	192	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
	193	dev, "pci-conf-data", 0x1000);
	194	sysbus_init_mmio(dev, &h->conf_mem);
	195	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	196	return 0;
2e29bd04 BS	197	}
2e29bd04 BS	198
81a322d4	199	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	200	{
ff452ace	201	PCIHostState *h;
2e29bd04 BS	202
2e29bd04 BS	203	/* Uninorth internal bus */
8558d942	204	h = PCI_HOST_BRIDGE(dev);
57fd7b7f AF	205
	206	memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
	207	dev, "pci-conf-idx", 0x1000);
	208	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
	209	dev, "pci-conf-data", 0x1000);
	210	sysbus_init_mmio(dev, &h->conf_mem);
	211	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	212	return 0;
2e29bd04 BS	213	}
2e29bd04 BS	214
aee97b84 AK	215	PCIBus pci_pmac_init(qemu_irq pic,
	216	MemoryRegion *address_space_mem,
	217	MemoryRegion *address_space_io)
2e29bd04 BS	218	{
	219	DeviceState *dev;
	220	SysBusDevice *s;
ff452ace	221	PCIHostState *h;
2e29bd04 BS	222	UNINState *d;
	223
	224	/* Use values found on a real PowerMac */
	225	/* Uninorth main bus */
57fd7b7f	226	dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33	227	qdev_init_nofail(dev);
57fd7b7f	228	s = SYS_BUS_DEVICE(dev);
8558d942	229	h = PCI_HOST_BRIDGE(s);
57fd7b7f	230	d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
46f3069c BS	231	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	232	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	233	0x80000000ULL, 0x70000000ULL);
	234	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	235	&d->pci_hole);
	236
57fd7b7f AF	237	h->bus = pci_register_bus(dev, "pci",
	238	pci_unin_set_irq, pci_unin_map_irq,
	239	pic,
	240	&d->pci_mmio,
	241	address_space_io,
	242	PCI_DEVFN(11, 0), 4);
2e29bd04	243
60398748	244	#if 0
57fd7b7f	245	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748	246	#endif
2e29bd04 BS	247
	248	sysbus_mmio_map(s, 0, 0xf2800000);
	249	sysbus_mmio_map(s, 1, 0xf2c00000);
	250
	251	/* DEC 21154 bridge */
	252	#if 0
	253	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f	254	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	255	#endif
	256
	257	/* Uninorth AGP bus */
57fd7b7f AF	258	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
57fd7b7f AF	259	dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2	260	qdev_init_nofail(dev);
57fd7b7f	261	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	262	sysbus_mmio_map(s, 0, 0xf0800000);
d27d06f2 BS	263	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	264
	265	/* Uninorth internal bus */
	266	#if 0
	267	/* XXX: not needed for now */
57fd7b7f	268	pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987	269	"uni-north-internal-pci");
57fd7b7f	270	dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2	271	qdev_init_nofail(dev);
57fd7b7f	272	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	273	sysbus_mmio_map(s, 0, 0xf4800000);
d27d06f2 BS	274	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	275	#endif
2e29bd04 BS	276
57fd7b7f	277	return h->bus;
2e29bd04 BS	278	}
2e29bd04 BS	279
aee97b84 AK	280	PCIBus pci_pmac_u3_init(qemu_irq pic,
	281	MemoryRegion *address_space_mem,
	282	MemoryRegion *address_space_io)
0f921197 AG	283	{
	284	DeviceState *dev;
	285	SysBusDevice *s;
ff452ace	286	PCIHostState *h;
0f921197 AG	287	UNINState *d;
	288
	289	/* Uninorth AGP bus */
	290
57fd7b7f	291	dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197	292	qdev_init_nofail(dev);
57fd7b7f	293	s = SYS_BUS_DEVICE(dev);
8558d942	294	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	295	d = U3_AGP_HOST_BRIDGE(dev);
0f921197	296
46f3069c BS	297	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	298	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	299	0x80000000ULL, 0x70000000ULL);
	300	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	301	&d->pci_hole);
	302
57fd7b7f AF	303	h->bus = pci_register_bus(dev, "pci",
	304	pci_unin_set_irq, pci_unin_map_irq,
	305	pic,
	306	&d->pci_mmio,
	307	address_space_io,
	308	PCI_DEVFN(11, 0), 4);
0f921197 AG	309
	310	sysbus_mmio_map(s, 0, 0xf0800000);
	311	sysbus_mmio_map(s, 1, 0xf0c00000);
	312
57fd7b7f	313	pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197	314
57fd7b7f	315	return h->bus;
0f921197 AG	316	}
0f921197 AG	317
81a322d4	318	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	319	{
502a5395 PB	320	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	321	d->config[0x0D] = 0x10; // latency_timer
502a5395	322	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	323	return 0;
2e29bd04	324	}
502a5395	325
81a322d4	326	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	327	{
502a5395 PB	328	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	329	d->config[0x0D] = 0x10; // latency_timer
502a5395	330	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	331	return 0;
2e29bd04	332	}
502a5395	333
0f921197 AG	334	static int u3_agp_pci_host_init(PCIDevice *d)
0f921197 AG	335	{
0f921197 AG	336	/* cache line size */
	337	d->config[0x0C] = 0x08;
	338	/* latency timer */
	339	d->config[0x0D] = 0x10;
0f921197 AG	340	return 0;
	341	}
	342
81a322d4	343	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	344	{
502a5395 PB	345	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	346	d->config[0x0D] = 0x10; // latency_timer
502a5395	347	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	348	return 0;
2e29bd04 BS	349	}
2e29bd04 BS	350
40021f08 AL	351	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	352	{
	353	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	354
	355	k->init = unin_main_pci_host_init;
	356	k->vendor_id = PCI_VENDOR_ID_APPLE;
	357	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	358	k->revision = 0x00;
	359	k->class_id = PCI_CLASS_BRIDGE_HOST;
	360	}
	361
4240abff	362	static const TypeInfo unin_main_pci_host_info = {
40021f08	363	.name = "uni-north-pci",
39bffca2 AL	364	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	365	.instance_size = sizeof(PCIDevice),
40021f08	366	.class_init = unin_main_pci_host_class_init,
2e29bd04 BS	367	};
2e29bd04 BS	368
40021f08 AL	369	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	370	{
	371	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	372
	373	k->init = u3_agp_pci_host_init;
	374	k->vendor_id = PCI_VENDOR_ID_APPLE;
	375	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	376	k->revision = 0x00;
	377	k->class_id = PCI_CLASS_BRIDGE_HOST;
	378	}
	379
4240abff	380	static const TypeInfo u3_agp_pci_host_info = {
40021f08	381	.name = "u3-agp",
39bffca2 AL	382	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	383	.instance_size = sizeof(PCIDevice),
40021f08	384	.class_init = u3_agp_pci_host_class_init,
0f921197 AG	385	};
0f921197 AG	386
40021f08 AL	387	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	388	{
	389	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	390
	391	k->init = unin_agp_pci_host_init;
	392	k->vendor_id = PCI_VENDOR_ID_APPLE;
	393	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	394	k->revision = 0x00;
	395	k->class_id = PCI_CLASS_BRIDGE_HOST;
	396	}
	397
4240abff	398	static const TypeInfo unin_agp_pci_host_info = {
40021f08	399	.name = "uni-north-agp",
39bffca2 AL	400	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	401	.instance_size = sizeof(PCIDevice),
40021f08	402	.class_init = unin_agp_pci_host_class_init,
2e29bd04 BS	403	};
2e29bd04 BS	404
40021f08 AL	405	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	406	{
	407	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	408
	409	k->init = unin_internal_pci_host_init;
	410	k->vendor_id = PCI_VENDOR_ID_APPLE;
	411	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	412	k->revision = 0x00;
	413	k->class_id = PCI_CLASS_BRIDGE_HOST;
	414	}
	415
4240abff	416	static const TypeInfo unin_internal_pci_host_info = {
40021f08	417	.name = "uni-north-internal-pci",
39bffca2 AL	418	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	419	.instance_size = sizeof(PCIDevice),
40021f08	420	.class_init = unin_internal_pci_host_class_init,
2e29bd04 BS	421	};
2e29bd04 BS	422
999e12bb AL	423	static void pci_unin_main_class_init(ObjectClass klass, void data)
	424	{
	425	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	426
	427	sbc->init = pci_unin_main_init_device;
	428	}
	429
4240abff	430	static const TypeInfo pci_unin_main_info = {
57fd7b7f	431	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	432	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	433	.instance_size = sizeof(UNINState),
39bffca2 AL	434	.class_init = pci_unin_main_class_init,
70f9c987 AF	435	};
70f9c987 AF	436
999e12bb AL	437	static void pci_u3_agp_class_init(ObjectClass klass, void data)
	438	{
	439	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	440
	441	sbc->init = pci_u3_agp_init_device;
	442	}
	443
4240abff	444	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	445	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	446	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	447	.instance_size = sizeof(UNINState),
39bffca2 AL	448	.class_init = pci_u3_agp_class_init,
70f9c987 AF	449	};
70f9c987 AF	450
999e12bb AL	451	static void pci_unin_agp_class_init(ObjectClass klass, void data)
	452	{
	453	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	454
	455	sbc->init = pci_unin_agp_init_device;
	456	}
	457
4240abff	458	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	459	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	460	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	461	.instance_size = sizeof(UNINState),
39bffca2 AL	462	.class_init = pci_unin_agp_class_init,
70f9c987 AF	463	};
70f9c987 AF	464
999e12bb AL	465	static void pci_unin_internal_class_init(ObjectClass klass, void data)
	466	{
	467	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	468
	469	sbc->init = pci_unin_internal_init_device;
	470	}
	471
4240abff	472	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	473	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	474	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	475	.instance_size = sizeof(UNINState),
39bffca2 AL	476	.class_init = pci_unin_internal_class_init,
70f9c987 AF	477	};
70f9c987 AF	478
83f7d43a	479	static void unin_register_types(void)
2e29bd04	480	{
39bffca2 AL	481	type_register_static(&unin_main_pci_host_info);
	482	type_register_static(&u3_agp_pci_host_info);
	483	type_register_static(&unin_agp_pci_host_info);
	484	type_register_static(&unin_internal_pci_host_info);
	485
	486	type_register_static(&pci_unin_main_info);
	487	type_register_static(&pci_u3_agp_info);
	488	type_register_static(&pci_unin_agp_info);
	489	type_register_static(&pci_unin_internal_info);
502a5395	490	}
2e29bd04	491
83f7d43a	492	type_init(unin_register_types)