[qemu.git] / hw / arm_sysctl.c

/*
 * Status and system control registers for ARM RealView/Versatile boards.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "qemu/timer.h"
#include "sysbus.h"
#include "primecell.h"
#include "sysemu/sysemu.h"

#define LOCK_VALUE 0xa05f

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    qemu_irq pl110_mux_ctrl;

    uint32_t sys_id;
    uint32_t leds;
    uint16_t lockval;
    uint32_t cfgdata1;
    uint32_t cfgdata2;
    uint32_t flags;
    uint32_t nvflags;
    uint32_t resetlevel;
    uint32_t proc_id;
    uint32_t sys_mci;
    uint32_t sys_cfgdata;
    uint32_t sys_cfgctrl;
    uint32_t sys_cfgstat;
    uint32_t sys_clcd;
} arm_sysctl_state;

static const VMStateDescription vmstate_arm_sysctl = {
    .name = "realview_sysctl",
    .version_id = 3,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(leds, arm_sysctl_state),
        VMSTATE_UINT16(lockval, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
        VMSTATE_UINT32(flags, arm_sysctl_state),
        VMSTATE_UINT32(nvflags, arm_sysctl_state),
        VMSTATE_UINT32(resetlevel, arm_sysctl_state),
        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
        VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
        VMSTATE_END_OF_LIST()
    }
};

/* The PB926 actually uses a different format for
 * its SYS_ID register. Fortunately the bits which are
 * board type on later boards are distinct.
 */
#define BOARD_ID_PB926 0x100
#define BOARD_ID_EB 0x140
#define BOARD_ID_PBA8 0x178
#define BOARD_ID_PBX 0x182
#define BOARD_ID_VEXPRESS 0x190

static int board_id(arm_sysctl_state *s)
{
    /* Extract the board ID field from the SYS_ID register value */
    return (s->sys_id >> 16) & 0xfff;
}

static void arm_sysctl_reset(DeviceState *d)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));

    s->leds = 0;
    s->lockval = 0;
    s->cfgdata1 = 0;
    s->cfgdata2 = 0;
    s->flags = 0;
    s->resetlevel = 0;
    if (board_id(s) == BOARD_ID_VEXPRESS) {
        /* On VExpress this register will RAZ/WI */
        s->sys_clcd = 0;
    } else {
        /* All others: CLCDID 0x1f, indicating VGA */
        s->sys_clcd = 0x1f00;
    }
}

static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x00: /* ID */
        return s->sys_id;
    case 0x04: /* SW */
        /* General purpose hardware switches.
           We don't have a useful way of exposing these to the user.  */
        return 0;
    case 0x08: /* LED */
        return s->leds;
    case 0x20: /* LOCK */
        return s->lockval;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
    case 0x24: /* 100HZ */
        /* ??? Implement these.  */
        return 0;
    case 0x28: /* CFGDATA1 */
        return s->cfgdata1;
    case 0x2c: /* CFGDATA2 */
        return s->cfgdata2;
    case 0x30: /* FLAGS */
        return s->flags;
    case 0x38: /* NVFLAGS */
        return s->nvflags;
    case 0x40: /* RESETCTL */
        if (board_id(s) == BOARD_ID_VEXPRESS) {
            /* reserved: RAZ/WI */
            return 0;
        }
        return s->resetlevel;
    case 0x44: /* PCICTL */
        return 1;
    case 0x48: /* MCI */
        return s->sys_mci;
    case 0x4c: /* FLASH */
        return 0;
    case 0x50: /* CLCD */
        return s->sys_clcd;
    case 0x54: /* CLCDSER */
        return 0;
    case 0x58: /* BOOTCS */
        return 0;
    case 0x5c: /* 24MHz */
        return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
    case 0x60: /* MISC */
        return 0;
    case 0x84: /* PROCID0 */
        return s->proc_id;
    case 0x88: /* PROCID1 */
        return 0xff000000;
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
    case 0xc0: /* SYS_TEST_OSC0 */
    case 0xc4: /* SYS_TEST_OSC1 */
    case 0xc8: /* SYS_TEST_OSC2 */
    case 0xcc: /* SYS_TEST_OSC3 */
    case 0xd0: /* SYS_TEST_OSC4 */
        return 0;
    case 0xa0: /* SYS_CFGDATA */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgdata;
    case 0xa4: /* SYS_CFGCTRL */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgctrl;
    case 0xa8: /* SYS_CFGSTAT */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        return s->sys_cfgstat;
    default:
    bad_reg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "arm_sysctl_read: Bad register offset 0x%x\n",
                      (int)offset);
        return 0;
    }
}

static void arm_sysctl_write(void *opaque, hwaddr offset,
                             uint64_t val, unsigned size)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x08: /* LED */
        s->leds = val;
        break;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
        /* ??? */
        break;
    case 0x20: /* LOCK */
        if (val == LOCK_VALUE)
            s->lockval = val;
        else
            s->lockval = val & 0x7fff;
        break;
    case 0x28: /* CFGDATA1 */
        /* ??? Need to implement this.  */
        s->cfgdata1 = val;
        break;
    case 0x2c: /* CFGDATA2 */
        /* ??? Need to implement this.  */
        s->cfgdata2 = val;
        break;
    case 0x30: /* FLAGSSET */
        s->flags |= val;
        break;
    case 0x34: /* FLAGSCLR */
        s->flags &= ~val;
        break;
    case 0x38: /* NVFLAGSSET */
        s->nvflags |= val;
        break;
    case 0x3c: /* NVFLAGSCLR */
        s->nvflags &= ~val;
        break;
    case 0x40: /* RESETCTL */
        switch (board_id(s)) {
        case BOARD_ID_PB926:
            if (s->lockval == LOCK_VALUE) {
                s->resetlevel = val;
                if (val & 0x100) {
                    qemu_system_reset_request();
                }
            }
            break;
        case BOARD_ID_PBX:
        case BOARD_ID_PBA8:
            if (s->lockval == LOCK_VALUE) {
                s->resetlevel = val;
                if (val & 0x04) {
                    qemu_system_reset_request();
                }
            }
            break;
        case BOARD_ID_VEXPRESS:
        case BOARD_ID_EB:
        default:
            /* reserved: RAZ/WI */
            break;
        }
        break;
    case 0x44: /* PCICTL */
        /* nothing to do.  */
        break;
    case 0x4c: /* FLASH */
        break;
    case 0x50: /* CLCD */
        switch (board_id(s)) {
        case BOARD_ID_PB926:
            /* On 926 bits 13:8 are R/O, bits 1:0 control
             * the mux that defines how to interpret the PL110
             * graphics format, and other bits are r/w but we
             * don't implement them to do anything.
             */
            s->sys_clcd &= 0x3f00;
            s->sys_clcd |= val & ~0x3f00;
            qemu_set_irq(s->pl110_mux_ctrl, val & 3);
            break;
        case BOARD_ID_EB:
            /* The EB is the same except that there is no mux since
             * the EB has a PL111.
             */
            s->sys_clcd &= 0x3f00;
            s->sys_clcd |= val & ~0x3f00;
            break;
        case BOARD_ID_PBA8:
        case BOARD_ID_PBX:
            /* On PBA8 and PBX bit 7 is r/w and all other bits
             * are either r/o or RAZ/WI.
             */
            s->sys_clcd &= (1 << 7);
            s->sys_clcd |= val & ~(1 << 7);
            break;
        case BOARD_ID_VEXPRESS:
        default:
            /* On VExpress this register is unimplemented and will RAZ/WI */
            break;
        }
        break;
    case 0x54: /* CLCDSER */
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x84: /* PROCID0 */
    case 0x88: /* PROCID1 */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
        break;
    case 0xa0: /* SYS_CFGDATA */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgdata = val;
        return;
    case 0xa4: /* SYS_CFGCTRL */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgctrl = val & ~(3 << 18);
        s->sys_cfgstat = 1;            /* complete */
        switch (s->sys_cfgctrl) {
        case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
            qemu_system_shutdown_request();
            break;
        case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
            qemu_system_reset_request();
            break;
        default:
            s->sys_cfgstat |= 2;        /* error */
        }
        s->sys_cfgctrl &= ~(1 << 31);
        return;
    case 0xa8: /* SYS_CFGSTAT */
        if (board_id(s) != BOARD_ID_VEXPRESS) {
            goto bad_reg;
        }
        s->sys_cfgstat = val & 3;
        return;
    default:
    bad_reg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "arm_sysctl_write: Bad register offset 0x%x\n",
                      (int)offset);
        return;
    }
}

static const MemoryRegionOps arm_sysctl_ops = {
    .read = arm_sysctl_read,
    .write = arm_sysctl_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void arm_sysctl_gpio_set(void *opaque, int line, int level)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
    switch (line) {
    case ARM_SYSCTL_GPIO_MMC_WPROT:
    {
        /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
         * for all later boards it is bit 1.
         */
        int bit = 2;
        if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
            bit = 4;
        }
        s->sys_mci &= ~bit;
        if (level) {
            s->sys_mci |= bit;
        }
        break;
    }
    case ARM_SYSCTL_GPIO_MMC_CARDIN:
        s->sys_mci &= ~1;
        if (level) {
            s->sys_mci |= 1;
        }
        break;
    }
}

static int arm_sysctl_init(SysBusDevice *dev)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);

    memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
    qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
    return 0;
}

static Property arm_sysctl_properties[] = {
    DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
    DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void arm_sysctl_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = arm_sysctl_init;
    dc->reset = arm_sysctl_reset;
    dc->vmsd = &vmstate_arm_sysctl;
    dc->props = arm_sysctl_properties;
}

static const TypeInfo arm_sysctl_info = {
    .name          = "realview_sysctl",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(arm_sysctl_state),
    .class_init    = arm_sysctl_class_init,
};

static void arm_sysctl_register_types(void)
{
    type_register_static(&arm_sysctl_info);
}

type_init(arm_sysctl_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* Status and system control registers for ARM RealView/Versatile boards.
e69954b9 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
e69954b9 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
e69954b9 PB	8	*/
e69954b9 PB	9
042eb37a	10	#include "hw.h"
1de7afc9	11	#include "qemu/timer.h"
82634c2d	12	#include "sysbus.h"
9596ebb7	13	#include "primecell.h"
9c17d615	14	#include "sysemu/sysemu.h"
e69954b9 PB	15
	16	#define LOCK_VALUE 0xa05f
	17
	18	typedef struct {
82634c2d	19	SysBusDevice busdev;
460d7c53	20	MemoryRegion iomem;
242ea2c6 PM	21	qemu_irq pl110_mux_ctrl;
242ea2c6 PM	22
e69954b9 PB	23	uint32_t sys_id;
	24	uint32_t leds;
	25	uint16_t lockval;
	26	uint32_t cfgdata1;
	27	uint32_t cfgdata2;
	28	uint32_t flags;
	29	uint32_t nvflags;
	30	uint32_t resetlevel;
26e92f65	31	uint32_t proc_id;
b50ff6f5	32	uint32_t sys_mci;
34933c8c PM	33	uint32_t sys_cfgdata;
	34	uint32_t sys_cfgctrl;
	35	uint32_t sys_cfgstat;
242ea2c6	36	uint32_t sys_clcd;
e69954b9 PB	37	} arm_sysctl_state;
e69954b9 PB	38
b5ad0ae7 PM	39	static const VMStateDescription vmstate_arm_sysctl = {
b5ad0ae7 PM	40	.name = "realview_sysctl",
242ea2c6	41	.version_id = 3,
b5ad0ae7 PM	42	.minimum_version_id = 1,
	43	.fields = (VMStateField[]) {
	44	VMSTATE_UINT32(leds, arm_sysctl_state),
	45	VMSTATE_UINT16(lockval, arm_sysctl_state),
	46	VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
	47	VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
	48	VMSTATE_UINT32(flags, arm_sysctl_state),
	49	VMSTATE_UINT32(nvflags, arm_sysctl_state),
	50	VMSTATE_UINT32(resetlevel, arm_sysctl_state),
34933c8c PM	51	VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
	52	VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
	53	VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
	54	VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
242ea2c6	55	VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
b5ad0ae7 PM	56	VMSTATE_END_OF_LIST()
	57	}
	58	};
	59
b50ff6f5 PM	60	/* The PB926 actually uses a different format for
	61	* its SYS_ID register. Fortunately the bits which are
	62	* board type on later boards are distinct.
	63	*/
	64	#define BOARD_ID_PB926 0x100
	65	#define BOARD_ID_EB 0x140
	66	#define BOARD_ID_PBA8 0x178
	67	#define BOARD_ID_PBX 0x182
34933c8c	68	#define BOARD_ID_VEXPRESS 0x190
b50ff6f5 PM	69
	70	static int board_id(arm_sysctl_state *s)
	71	{
	72	/* Extract the board ID field from the SYS_ID register value */
	73	return (s->sys_id >> 16) & 0xfff;
	74	}
	75
be0f204a PB	76	static void arm_sysctl_reset(DeviceState *d)
be0f204a PB	77	{
1356b98d	78	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
be0f204a PB	79
	80	s->leds = 0;
	81	s->lockval = 0;
	82	s->cfgdata1 = 0;
	83	s->cfgdata2 = 0;
	84	s->flags = 0;
	85	s->resetlevel = 0;
242ea2c6 PM	86	if (board_id(s) == BOARD_ID_VEXPRESS) {
	87	/* On VExpress this register will RAZ/WI */
	88	s->sys_clcd = 0;
	89	} else {
	90	/* All others: CLCDID 0x1f, indicating VGA */
	91	s->sys_clcd = 0x1f00;
	92	}
be0f204a PB	93	}
be0f204a PB	94
a8170e5e	95	static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
460d7c53	96	unsigned size)
e69954b9 PB	97	{
	98	arm_sysctl_state s = (arm_sysctl_state )opaque;
	99
e69954b9 PB	100	switch (offset) {
	101	case 0x00: /* ID */
	102	return s->sys_id;
	103	case 0x04: /* SW */
	104	/* General purpose hardware switches.
	105	We don't have a useful way of exposing these to the user. */
	106	return 0;
	107	case 0x08: /* LED */
	108	return s->leds;
	109	case 0x20: /* LOCK */
	110	return s->lockval;
	111	case 0x0c: /* OSC0 */
	112	case 0x10: /* OSC1 */
	113	case 0x14: /* OSC2 */
	114	case 0x18: /* OSC3 */
	115	case 0x1c: /* OSC4 */
	116	case 0x24: /* 100HZ */
	117	/* ??? Implement these. */
	118	return 0;
	119	case 0x28: /* CFGDATA1 */
	120	return s->cfgdata1;
	121	case 0x2c: /* CFGDATA2 */
	122	return s->cfgdata2;
	123	case 0x30: /* FLAGS */
	124	return s->flags;
	125	case 0x38: /* NVFLAGS */
	126	return s->nvflags;
	127	case 0x40: /* RESETCTL */
34933c8c PM	128	if (board_id(s) == BOARD_ID_VEXPRESS) {
	129	/* reserved: RAZ/WI */
	130	return 0;
	131	}
e69954b9 PB	132	return s->resetlevel;
	133	case 0x44: /* PCICTL */
	134	return 1;
	135	case 0x48: /* MCI */
b50ff6f5	136	return s->sys_mci;
e69954b9 PB	137	case 0x4c: /* FLASH */
	138	return 0;
	139	case 0x50: /* CLCD */
242ea2c6	140	return s->sys_clcd;
e69954b9 PB	141	case 0x54: /* CLCDSER */
	142	return 0;
	143	case 0x58: /* BOOTCS */
	144	return 0;
	145	case 0x5c: /* 24MHz */
74475455	146	return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
e69954b9 PB	147	case 0x60: /* MISC */
	148	return 0;
	149	case 0x84: /* PROCID0 */
26e92f65	150	return s->proc_id;
e69954b9 PB	151	case 0x88: /* PROCID1 */
	152	return 0xff000000;
	153	case 0x64: /* DMAPSR0 */
	154	case 0x68: /* DMAPSR1 */
	155	case 0x6c: /* DMAPSR2 */
	156	case 0x70: /* IOSEL */
	157	case 0x74: /* PLDCTL */
	158	case 0x80: /* BUSID */
	159	case 0x8c: /* OSCRESET0 */
	160	case 0x90: /* OSCRESET1 */
	161	case 0x94: /* OSCRESET2 */
	162	case 0x98: /* OSCRESET3 */
	163	case 0x9c: /* OSCRESET4 */
	164	case 0xc0: /* SYS_TEST_OSC0 */
	165	case 0xc4: /* SYS_TEST_OSC1 */
	166	case 0xc8: /* SYS_TEST_OSC2 */
	167	case 0xcc: /* SYS_TEST_OSC3 */
	168	case 0xd0: /* SYS_TEST_OSC4 */
	169	return 0;
34933c8c PM	170	case 0xa0: /* SYS_CFGDATA */
	171	if (board_id(s) != BOARD_ID_VEXPRESS) {
	172	goto bad_reg;
	173	}
	174	return s->sys_cfgdata;
	175	case 0xa4: /* SYS_CFGCTRL */
	176	if (board_id(s) != BOARD_ID_VEXPRESS) {
	177	goto bad_reg;
	178	}
	179	return s->sys_cfgctrl;
	180	case 0xa8: /* SYS_CFGSTAT */
	181	if (board_id(s) != BOARD_ID_VEXPRESS) {
	182	goto bad_reg;
	183	}
	184	return s->sys_cfgstat;
e69954b9	185	default:
34933c8c	186	bad_reg:
0c896f06 PM	187	qemu_log_mask(LOG_GUEST_ERROR,
	188	"arm_sysctl_read: Bad register offset 0x%x\n",
	189	(int)offset);
e69954b9 PB	190	return 0;
	191	}
	192	}
	193
a8170e5e	194	static void arm_sysctl_write(void *opaque, hwaddr offset,
460d7c53	195	uint64_t val, unsigned size)
e69954b9 PB	196	{
e69954b9 PB	197	arm_sysctl_state s = (arm_sysctl_state )opaque;
e69954b9 PB	198
	199	switch (offset) {
	200	case 0x08: /* LED */
	201	s->leds = val;
bf4229d3	202	break;
e69954b9 PB	203	case 0x0c: /* OSC0 */
	204	case 0x10: /* OSC1 */
	205	case 0x14: /* OSC2 */
	206	case 0x18: /* OSC3 */
	207	case 0x1c: /* OSC4 */
	208	/* ??? */
	209	break;
	210	case 0x20: /* LOCK */
	211	if (val == LOCK_VALUE)
	212	s->lockval = val;
	213	else
	214	s->lockval = val & 0x7fff;
	215	break;
	216	case 0x28: /* CFGDATA1 */
	217	/* ??? Need to implement this. */
	218	s->cfgdata1 = val;
	219	break;
	220	case 0x2c: /* CFGDATA2 */
	221	/* ??? Need to implement this. */
	222	s->cfgdata2 = val;
	223	break;
	224	case 0x30: /* FLAGSSET */
	225	s->flags \|= val;
	226	break;
	227	case 0x34: /* FLAGSCLR */
	228	s->flags &= ~val;
	229	break;
	230	case 0x38: /* NVFLAGSSET */
	231	s->nvflags \|= val;
	232	break;
	233	case 0x3c: /* NVFLAGSCLR */
	234	s->nvflags &= ~val;
	235	break;
	236	case 0x40: /* RESETCTL */
b2887c43 JCD	237	switch (board_id(s)) {
	238	case BOARD_ID_PB926:
	239	if (s->lockval == LOCK_VALUE) {
	240	s->resetlevel = val;
	241	if (val & 0x100) {
	242	qemu_system_reset_request();
	243	}
	244	}
	245	break;
	246	case BOARD_ID_PBX:
	247	case BOARD_ID_PBA8:
	248	if (s->lockval == LOCK_VALUE) {
	249	s->resetlevel = val;
	250	if (val & 0x04) {
	251	qemu_system_reset_request();
	252	}
	253	}
	254	break;
	255	case BOARD_ID_VEXPRESS:
	256	case BOARD_ID_EB:
	257	default:
34933c8c PM	258	/* reserved: RAZ/WI */
	259	break;
	260	}
e69954b9 PB	261	break;
	262	case 0x44: /* PCICTL */
	263	/* nothing to do. */
	264	break;
	265	case 0x4c: /* FLASH */
242ea2c6	266	break;
e69954b9	267	case 0x50: /* CLCD */
242ea2c6 PM	268	switch (board_id(s)) {
	269	case BOARD_ID_PB926:
	270	/* On 926 bits 13:8 are R/O, bits 1:0 control
	271	* the mux that defines how to interpret the PL110
	272	* graphics format, and other bits are r/w but we
	273	* don't implement them to do anything.
	274	*/
	275	s->sys_clcd &= 0x3f00;
	276	s->sys_clcd \|= val & ~0x3f00;
	277	qemu_set_irq(s->pl110_mux_ctrl, val & 3);
	278	break;
	279	case BOARD_ID_EB:
	280	/* The EB is the same except that there is no mux since
	281	* the EB has a PL111.
	282	*/
	283	s->sys_clcd &= 0x3f00;
	284	s->sys_clcd \|= val & ~0x3f00;
	285	break;
	286	case BOARD_ID_PBA8:
	287	case BOARD_ID_PBX:
	288	/* On PBA8 and PBX bit 7 is r/w and all other bits
	289	* are either r/o or RAZ/WI.
	290	*/
	291	s->sys_clcd &= (1 << 7);
	292	s->sys_clcd \|= val & ~(1 << 7);
	293	break;
	294	case BOARD_ID_VEXPRESS:
	295	default:
	296	/* On VExpress this register is unimplemented and will RAZ/WI */
	297	break;
	298	}
bf4229d3	299	break;
e69954b9 PB	300	case 0x54: /* CLCDSER */
	301	case 0x64: /* DMAPSR0 */
	302	case 0x68: /* DMAPSR1 */
	303	case 0x6c: /* DMAPSR2 */
	304	case 0x70: /* IOSEL */
	305	case 0x74: /* PLDCTL */
	306	case 0x80: /* BUSID */
	307	case 0x84: /* PROCID0 */
	308	case 0x88: /* PROCID1 */
	309	case 0x8c: /* OSCRESET0 */
	310	case 0x90: /* OSCRESET1 */
	311	case 0x94: /* OSCRESET2 */
	312	case 0x98: /* OSCRESET3 */
	313	case 0x9c: /* OSCRESET4 */
	314	break;
34933c8c PM	315	case 0xa0: /* SYS_CFGDATA */
	316	if (board_id(s) != BOARD_ID_VEXPRESS) {
	317	goto bad_reg;
	318	}
	319	s->sys_cfgdata = val;
	320	return;
	321	case 0xa4: /* SYS_CFGCTRL */
	322	if (board_id(s) != BOARD_ID_VEXPRESS) {
	323	goto bad_reg;
	324	}
	325	s->sys_cfgctrl = val & ~(3 << 18);
	326	s->sys_cfgstat = 1; /* complete */
	327	switch (s->sys_cfgctrl) {
	328	case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
	329	qemu_system_shutdown_request();
	330	break;
	331	case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
	332	qemu_system_reset_request();
	333	break;
	334	default:
	335	s->sys_cfgstat \|= 2; /* error */
	336	}
706872a5	337	s->sys_cfgctrl &= ~(1 << 31);
34933c8c PM	338	return;
	339	case 0xa8: /* SYS_CFGSTAT */
	340	if (board_id(s) != BOARD_ID_VEXPRESS) {
	341	goto bad_reg;
	342	}
	343	s->sys_cfgstat = val & 3;
	344	return;
e69954b9	345	default:
34933c8c	346	bad_reg:
0c896f06 PM	347	qemu_log_mask(LOG_GUEST_ERROR,
	348	"arm_sysctl_write: Bad register offset 0x%x\n",
	349	(int)offset);
e69954b9 PB	350	return;
	351	}
	352	}
	353
460d7c53 AK	354	static const MemoryRegionOps arm_sysctl_ops = {
	355	.read = arm_sysctl_read,
	356	.write = arm_sysctl_write,
	357	.endianness = DEVICE_NATIVE_ENDIAN,
e69954b9 PB	358	};
e69954b9 PB	359
b50ff6f5 PM	360	static void arm_sysctl_gpio_set(void *opaque, int line, int level)
	361	{
	362	arm_sysctl_state s = (arm_sysctl_state )opaque;
	363	switch (line) {
	364	case ARM_SYSCTL_GPIO_MMC_WPROT:
	365	{
	366	/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
	367	* for all later boards it is bit 1.
	368	*/
	369	int bit = 2;
	370	if ((board_id(s) == BOARD_ID_PB926) \|\| (board_id(s) == BOARD_ID_EB)) {
	371	bit = 4;
	372	}
	373	s->sys_mci &= ~bit;
	374	if (level) {
	375	s->sys_mci \|= bit;
	376	}
	377	break;
	378	}
	379	case ARM_SYSCTL_GPIO_MMC_CARDIN:
	380	s->sys_mci &= ~1;
	381	if (level) {
	382	s->sys_mci \|= 1;
	383	}
	384	break;
	385	}
	386	}
	387
54de1e5b	388	static int arm_sysctl_init(SysBusDevice *dev)
e69954b9	389	{
82634c2d	390	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
e69954b9	391
460d7c53	392	memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
750ecd44	393	sysbus_init_mmio(dev, &s->iomem);
b50ff6f5	394	qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
242ea2c6	395	qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
81a322d4	396	return 0;
e69954b9	397	}
82634c2d	398
999e12bb AL	399	static Property arm_sysctl_properties[] = {
	400	DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
	401	DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
	402	DEFINE_PROP_END_OF_LIST(),
	403	};
	404
	405	static void arm_sysctl_class_init(ObjectClass klass, void data)
	406	{
39bffca2	407	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	408	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
999e12bb AL	409
54de1e5b	410	k->init = arm_sysctl_init;
39bffca2 AL	411	dc->reset = arm_sysctl_reset;
	412	dc->vmsd = &vmstate_arm_sysctl;
	413	dc->props = arm_sysctl_properties;
999e12bb AL	414	}
999e12bb AL	415
8c43a6f0	416	static const TypeInfo arm_sysctl_info = {
39bffca2 AL	417	.name = "realview_sysctl",
	418	.parent = TYPE_SYS_BUS_DEVICE,
	419	.instance_size = sizeof(arm_sysctl_state),
	420	.class_init = arm_sysctl_class_init,
ee6847d1 GH	421	};
ee6847d1 GH	422
83f7d43a	423	static void arm_sysctl_register_types(void)
82634c2d	424	{
39bffca2	425	type_register_static(&arm_sysctl_info);
82634c2d PB	426	}
82634c2d PB	427
83f7d43a	428	type_init(arm_sysctl_register_types)