[qemu.git] / hw / arm_sysctl.c

/*
 * Status and system control registers for ARM RealView/Versatile boards.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysbus.h"
#include "primecell.h"
#include "sysemu.h"

#define LOCK_VALUE 0xa05f

typedef struct {
    SysBusDevice busdev;
    uint32_t sys_id;
    uint32_t leds;
    uint16_t lockval;
    uint32_t cfgdata1;
    uint32_t cfgdata2;
    uint32_t flags;
    uint32_t nvflags;
    uint32_t resetlevel;
    uint32_t proc_id;
} arm_sysctl_state;

static const VMStateDescription vmstate_arm_sysctl = {
    .name = "realview_sysctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(leds, arm_sysctl_state),
        VMSTATE_UINT16(lockval, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
        VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
        VMSTATE_UINT32(flags, arm_sysctl_state),
        VMSTATE_UINT32(nvflags, arm_sysctl_state),
        VMSTATE_UINT32(resetlevel, arm_sysctl_state),
        VMSTATE_END_OF_LIST()
    }
};

static void arm_sysctl_reset(DeviceState *d)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));

    s->leds = 0;
    s->lockval = 0;
    s->cfgdata1 = 0;
    s->cfgdata2 = 0;
    s->flags = 0;
    s->resetlevel = 0;
}

static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x00: /* ID */
        return s->sys_id;
    case 0x04: /* SW */
        /* General purpose hardware switches.
           We don't have a useful way of exposing these to the user.  */
        return 0;
    case 0x08: /* LED */
        return s->leds;
    case 0x20: /* LOCK */
        return s->lockval;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
    case 0x24: /* 100HZ */
        /* ??? Implement these.  */
        return 0;
    case 0x28: /* CFGDATA1 */
        return s->cfgdata1;
    case 0x2c: /* CFGDATA2 */
        return s->cfgdata2;
    case 0x30: /* FLAGS */
        return s->flags;
    case 0x38: /* NVFLAGS */
        return s->nvflags;
    case 0x40: /* RESETCTL */
        return s->resetlevel;
    case 0x44: /* PCICTL */
        return 1;
    case 0x48: /* MCI */
        return 0;
    case 0x4c: /* FLASH */
        return 0;
    case 0x50: /* CLCD */
        return 0x1000;
    case 0x54: /* CLCDSER */
        return 0;
    case 0x58: /* BOOTCS */
        return 0;
    case 0x5c: /* 24MHz */
        return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec());
    case 0x60: /* MISC */
        return 0;
    case 0x84: /* PROCID0 */
        return s->proc_id;
    case 0x88: /* PROCID1 */
        return 0xff000000;
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
    case 0xc0: /* SYS_TEST_OSC0 */
    case 0xc4: /* SYS_TEST_OSC1 */
    case 0xc8: /* SYS_TEST_OSC2 */
    case 0xcc: /* SYS_TEST_OSC3 */
    case 0xd0: /* SYS_TEST_OSC4 */
        return 0;
    default:
        printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
                          uint32_t val)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x08: /* LED */
        s->leds = val;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
        /* ??? */
        break;
    case 0x20: /* LOCK */
        if (val == LOCK_VALUE)
            s->lockval = val;
        else
            s->lockval = val & 0x7fff;
        break;
    case 0x28: /* CFGDATA1 */
        /* ??? Need to implement this.  */
        s->cfgdata1 = val;
        break;
    case 0x2c: /* CFGDATA2 */
        /* ??? Need to implement this.  */
        s->cfgdata2 = val;
        break;
    case 0x30: /* FLAGSSET */
        s->flags |= val;
        break;
    case 0x34: /* FLAGSCLR */
        s->flags &= ~val;
        break;
    case 0x38: /* NVFLAGSSET */
        s->nvflags |= val;
        break;
    case 0x3c: /* NVFLAGSCLR */
        s->nvflags &= ~val;
        break;
    case 0x40: /* RESETCTL */
        if (s->lockval == LOCK_VALUE) {
            s->resetlevel = val;
            if (val & 0x100)
                qemu_system_reset_request ();
        }
        break;
    case 0x44: /* PCICTL */
        /* nothing to do.  */
        break;
    case 0x4c: /* FLASH */
    case 0x50: /* CLCD */
    case 0x54: /* CLCDSER */
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x84: /* PROCID0 */
    case 0x88: /* PROCID1 */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
        break;
    default:
        printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
}

static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
   arm_sysctl_read,
   arm_sysctl_read,
   arm_sysctl_read
};

static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
   arm_sysctl_write,
   arm_sysctl_write,
   arm_sysctl_write
};

static int arm_sysctl_init1(SysBusDevice *dev)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
    int iomemtype;

    iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
                                       arm_sysctl_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* ??? Save/restore.  */
    return 0;
}

/* Legacy helper function.  */
void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(dev, "sys_id", sys_id);
    qdev_init_nofail(dev);
    qdev_prop_set_uint32(dev, "proc_id", proc_id);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}

static SysBusDeviceInfo arm_sysctl_info = {
    .init = arm_sysctl_init1,
    .qdev.name  = "realview_sysctl",
    .qdev.size  = sizeof(arm_sysctl_state),
    .qdev.vmsd = &vmstate_arm_sysctl,
    .qdev.reset = arm_sysctl_reset,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
        DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void arm_sysctl_register_devices(void)
{
    sysbus_register_withprop(&arm_sysctl_info);
}

device_init(arm_sysctl_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* Status and system control registers for ARM RealView/Versatile boards.
e69954b9 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
042eb37a DJ	10	#include "hw.h"
042eb37a DJ	11	#include "qemu-timer.h"
82634c2d	12	#include "sysbus.h"
9596ebb7	13	#include "primecell.h"
87ecb68b	14	#include "sysemu.h"
e69954b9 PB	15
	16	#define LOCK_VALUE 0xa05f
	17
	18	typedef struct {
82634c2d	19	SysBusDevice busdev;
e69954b9 PB	20	uint32_t sys_id;
	21	uint32_t leds;
	22	uint16_t lockval;
	23	uint32_t cfgdata1;
	24	uint32_t cfgdata2;
	25	uint32_t flags;
	26	uint32_t nvflags;
	27	uint32_t resetlevel;
26e92f65	28	uint32_t proc_id;
e69954b9 PB	29	} arm_sysctl_state;
e69954b9 PB	30
b5ad0ae7 PM	31	static const VMStateDescription vmstate_arm_sysctl = {
	32	.name = "realview_sysctl",
	33	.version_id = 1,
	34	.minimum_version_id = 1,
	35	.fields = (VMStateField[]) {
	36	VMSTATE_UINT32(leds, arm_sysctl_state),
	37	VMSTATE_UINT16(lockval, arm_sysctl_state),
	38	VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
	39	VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
	40	VMSTATE_UINT32(flags, arm_sysctl_state),
	41	VMSTATE_UINT32(nvflags, arm_sysctl_state),
	42	VMSTATE_UINT32(resetlevel, arm_sysctl_state),
	43	VMSTATE_END_OF_LIST()
	44	}
	45	};
	46
be0f204a PB	47	static void arm_sysctl_reset(DeviceState *d)
	48	{
	49	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
	50
	51	s->leds = 0;
	52	s->lockval = 0;
	53	s->cfgdata1 = 0;
	54	s->cfgdata2 = 0;
	55	s->flags = 0;
	56	s->resetlevel = 0;
	57	}
	58
c227f099	59	static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
e69954b9 PB	60	{
	61	arm_sysctl_state s = (arm_sysctl_state )opaque;
	62
e69954b9 PB	63	switch (offset) {
	64	case 0x00: /* ID */
	65	return s->sys_id;
	66	case 0x04: /* SW */
	67	/* General purpose hardware switches.
	68	We don't have a useful way of exposing these to the user. */
	69	return 0;
	70	case 0x08: /* LED */
	71	return s->leds;
	72	case 0x20: /* LOCK */
	73	return s->lockval;
	74	case 0x0c: /* OSC0 */
	75	case 0x10: /* OSC1 */
	76	case 0x14: /* OSC2 */
	77	case 0x18: /* OSC3 */
	78	case 0x1c: /* OSC4 */
	79	case 0x24: /* 100HZ */
	80	/* ??? Implement these. */
	81	return 0;
	82	case 0x28: /* CFGDATA1 */
	83	return s->cfgdata1;
	84	case 0x2c: /* CFGDATA2 */
	85	return s->cfgdata2;
	86	case 0x30: /* FLAGS */
	87	return s->flags;
	88	case 0x38: /* NVFLAGS */
	89	return s->nvflags;
	90	case 0x40: /* RESETCTL */
	91	return s->resetlevel;
	92	case 0x44: /* PCICTL */
	93	return 1;
	94	case 0x48: /* MCI */
	95	return 0;
	96	case 0x4c: /* FLASH */
	97	return 0;
	98	case 0x50: /* CLCD */
	99	return 0x1000;
	100	case 0x54: /* CLCDSER */
	101	return 0;
	102	case 0x58: /* BOOTCS */
	103	return 0;
	104	case 0x5c: /* 24MHz */
042eb37a	105	return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec());
e69954b9 PB	106	case 0x60: /* MISC */
	107	return 0;
	108	case 0x84: /* PROCID0 */
26e92f65	109	return s->proc_id;
e69954b9 PB	110	case 0x88: /* PROCID1 */
	111	return 0xff000000;
	112	case 0x64: /* DMAPSR0 */
	113	case 0x68: /* DMAPSR1 */
	114	case 0x6c: /* DMAPSR2 */
	115	case 0x70: /* IOSEL */
	116	case 0x74: /* PLDCTL */
	117	case 0x80: /* BUSID */
	118	case 0x8c: /* OSCRESET0 */
	119	case 0x90: /* OSCRESET1 */
	120	case 0x94: /* OSCRESET2 */
	121	case 0x98: /* OSCRESET3 */
	122	case 0x9c: /* OSCRESET4 */
	123	case 0xc0: /* SYS_TEST_OSC0 */
	124	case 0xc4: /* SYS_TEST_OSC1 */
	125	case 0xc8: /* SYS_TEST_OSC2 */
	126	case 0xcc: /* SYS_TEST_OSC3 */
	127	case 0xd0: /* SYS_TEST_OSC4 */
	128	return 0;
	129	default:
	130	printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
	131	return 0;
	132	}
	133	}
	134
c227f099	135	static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
e69954b9 PB	136	uint32_t val)
	137	{
	138	arm_sysctl_state s = (arm_sysctl_state )opaque;
e69954b9 PB	139
	140	switch (offset) {
	141	case 0x08: /* LED */
	142	s->leds = val;
	143	case 0x0c: /* OSC0 */
	144	case 0x10: /* OSC1 */
	145	case 0x14: /* OSC2 */
	146	case 0x18: /* OSC3 */
	147	case 0x1c: /* OSC4 */
	148	/* ??? */
	149	break;
	150	case 0x20: /* LOCK */
	151	if (val == LOCK_VALUE)
	152	s->lockval = val;
	153	else
	154	s->lockval = val & 0x7fff;
	155	break;
	156	case 0x28: /* CFGDATA1 */
	157	/* ??? Need to implement this. */
	158	s->cfgdata1 = val;
	159	break;
	160	case 0x2c: /* CFGDATA2 */
	161	/* ??? Need to implement this. */
	162	s->cfgdata2 = val;
	163	break;
	164	case 0x30: /* FLAGSSET */
	165	s->flags \|= val;
	166	break;
	167	case 0x34: /* FLAGSCLR */
	168	s->flags &= ~val;
	169	break;
	170	case 0x38: /* NVFLAGSSET */
	171	s->nvflags \|= val;
	172	break;
	173	case 0x3c: /* NVFLAGSCLR */
	174	s->nvflags &= ~val;
	175	break;
	176	case 0x40: /* RESETCTL */
	177	if (s->lockval == LOCK_VALUE) {
	178	s->resetlevel = val;
	179	if (val & 0x100)
f3d6b95e	180	qemu_system_reset_request ();
e69954b9 PB	181	}
	182	break;
	183	case 0x44: /* PCICTL */
	184	/* nothing to do. */
	185	break;
	186	case 0x4c: /* FLASH */
	187	case 0x50: /* CLCD */
	188	case 0x54: /* CLCDSER */
	189	case 0x64: /* DMAPSR0 */
	190	case 0x68: /* DMAPSR1 */
	191	case 0x6c: /* DMAPSR2 */
	192	case 0x70: /* IOSEL */
	193	case 0x74: /* PLDCTL */
	194	case 0x80: /* BUSID */
	195	case 0x84: /* PROCID0 */
	196	case 0x88: /* PROCID1 */
	197	case 0x8c: /* OSCRESET0 */
	198	case 0x90: /* OSCRESET1 */
	199	case 0x94: /* OSCRESET2 */
	200	case 0x98: /* OSCRESET3 */
	201	case 0x9c: /* OSCRESET4 */
	202	break;
	203	default:
	204	printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
	205	return;
	206	}
	207	}
	208
d60efc6b	209	static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
e69954b9 PB	210	arm_sysctl_read,
	211	arm_sysctl_read,
	212	arm_sysctl_read
	213	};
	214
d60efc6b	215	static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
e69954b9 PB	216	arm_sysctl_write,
	217	arm_sysctl_write,
	218	arm_sysctl_write
	219	};
	220
81a322d4	221	static int arm_sysctl_init1(SysBusDevice *dev)
e69954b9	222	{
82634c2d	223	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
e69954b9 PB	224	int iomemtype;
e69954b9 PB	225
1eed09cb	226	iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
2507c12a AG	227	arm_sysctl_writefn, s,
2507c12a AG	228	DEVICE_NATIVE_ENDIAN);
82634c2d	229	sysbus_init_mmio(dev, 0x1000, iomemtype);
e69954b9	230	/* ??? Save/restore. */
81a322d4	231	return 0;
e69954b9	232	}
82634c2d PB	233
82634c2d PB	234	/* Legacy helper function. */
26e92f65	235	void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
82634c2d PB	236	{
	237	DeviceState *dev;
	238
	239	dev = qdev_create(NULL, "realview_sysctl");
ee6847d1	240	qdev_prop_set_uint32(dev, "sys_id", sys_id);
e23a1b33	241	qdev_init_nofail(dev);
26e92f65	242	qdev_prop_set_uint32(dev, "proc_id", proc_id);
82634c2d PB	243	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
	244	}
	245
ee6847d1 GH	246	static SysBusDeviceInfo arm_sysctl_info = {
	247	.init = arm_sysctl_init1,
	248	.qdev.name = "realview_sysctl",
	249	.qdev.size = sizeof(arm_sysctl_state),
b5ad0ae7	250	.qdev.vmsd = &vmstate_arm_sysctl,
be0f204a	251	.qdev.reset = arm_sysctl_reset,
ee6847d1	252	.qdev.props = (Property[]) {
e325775b	253	DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
26e92f65	254	DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
e325775b	255	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	256	}
	257	};
	258
82634c2d PB	259	static void arm_sysctl_register_devices(void)
82634c2d PB	260	{
ee6847d1	261	sysbus_register_withprop(&arm_sysctl_info);
82634c2d PB	262	}
	263
	264	device_init(arm_sysctl_register_devices)