projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| a4633e16 AF |
1 | /* |
| 2 | * QEMU Xtensa CPU | |
| 3 | * | |
| 5087a72c | 4 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| a4633e16 AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 6 | * All rights reserved. | |
| 7 | * | |
| 8 | * Redistribution and use in source and binary forms, with or without | |
| 9 | * modification, are permitted provided that the following conditions are met: | |
| 10 | * * Redistributions of source code must retain the above copyright | |
| 11 | * notice, this list of conditions and the following disclaimer. | |
| 12 | * * Redistributions in binary form must reproduce the above copyright | |
| 13 | * notice, this list of conditions and the following disclaimer in the | |
| 14 | * documentation and/or other materials provided with the distribution. | |
| 15 | * * Neither the name of the Open Source and Linux Lab nor the | |
| 16 | * names of its contributors may be used to endorse or promote products | |
| 17 | * derived from this software without specific prior written permission. | |
| 18 | * | |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 29 | */ | |
| 30 | ||
| 31 | #include "cpu-qom.h" | |
| 32 | #include "qemu-common.h" | |
| 33 | ||
| 34 | ||
| 35 | /* CPUClass::reset() */ | |
| 36 | static void xtensa_cpu_reset(CPUState *s) | |
| 37 | { | |
| 38 | XtensaCPU *cpu = XTENSA_CPU(s); | |
| 39 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); | |
| 40 | CPUXtensaState *env = &cpu->env; | |
| 41 | ||
| 42 | xcc->parent_reset(s); | |
| 43 | ||
| 5087a72c AF |
44 | env->exception_taken = 0; |
| 45 | env->pc = env->config->exception_vector[EXC_RESET]; | |
| 46 | env->sregs[LITBASE] &= ~1; | |
| 47 | env->sregs[PS] = xtensa_option_enabled(env->config, | |
| 48 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; | |
| 49 | env->sregs[VECBASE] = env->config->vecbase; | |
| 50 | env->sregs[IBREAKENABLE] = 0; | |
| 51 | ||
| 52 | env->pending_irq_level = 0; | |
| 53 | reset_mmu(env); | |
| a4633e16 AF |
54 | } |
| 55 | ||
| e554bbc6 AF |
56 | static void xtensa_cpu_initfn(Object *obj) |
| 57 | { | |
| 58 | XtensaCPU *cpu = XTENSA_CPU(obj); | |
| 59 | CPUXtensaState *env = &cpu->env; | |
| 60 | ||
| 61 | cpu_exec_init(env); | |
| 62 | } | |
| 63 | ||
| a4633e16 AF |
64 | static void xtensa_cpu_class_init(ObjectClass *oc, void *data) |
| 65 | { | |
| 66 | CPUClass *cc = CPU_CLASS(oc); | |
| 67 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); | |
| 68 | ||
| 69 | xcc->parent_reset = cc->reset; | |
| 70 | cc->reset = xtensa_cpu_reset; | |
| 71 | } | |
| 72 | ||
| 73 | static const TypeInfo xtensa_cpu_type_info = { | |
| 74 | .name = TYPE_XTENSA_CPU, | |
| 75 | .parent = TYPE_CPU, | |
| 76 | .instance_size = sizeof(XtensaCPU), | |
| e554bbc6 | 77 | .instance_init = xtensa_cpu_initfn, |
| a4633e16 AF |
78 | .abstract = false, |
| 79 | .class_size = sizeof(XtensaCPUClass), | |
| 80 | .class_init = xtensa_cpu_class_init, | |
| 81 | }; | |
| 82 | ||
| 83 | static void xtensa_cpu_register_types(void) | |
| 84 | { | |
| 85 | type_register_static(&xtensa_cpu_type_info); | |
| 86 | } | |
| 87 | ||
| 88 | type_init(xtensa_cpu_register_types) |