projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| a4633e16 AF |
1 | /* |
| 2 | * QEMU Xtensa CPU | |
| 3 | * | |
| 4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
| 5 | * All rights reserved. | |
| 6 | * | |
| 7 | * Redistribution and use in source and binary forms, with or without | |
| 8 | * modification, are permitted provided that the following conditions are met: | |
| 9 | * * Redistributions of source code must retain the above copyright | |
| 10 | * notice, this list of conditions and the following disclaimer. | |
| 11 | * * Redistributions in binary form must reproduce the above copyright | |
| 12 | * notice, this list of conditions and the following disclaimer in the | |
| 13 | * documentation and/or other materials provided with the distribution. | |
| 14 | * * Neither the name of the Open Source and Linux Lab nor the | |
| 15 | * names of its contributors may be used to endorse or promote products | |
| 16 | * derived from this software without specific prior written permission. | |
| 17 | * | |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
| 22 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 23 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 24 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 25 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 27 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 28 | */ | |
| 29 | ||
| 30 | #include "cpu-qom.h" | |
| 31 | #include "qemu-common.h" | |
| 32 | ||
| 33 | ||
| 34 | /* CPUClass::reset() */ | |
| 35 | static void xtensa_cpu_reset(CPUState *s) | |
| 36 | { | |
| 37 | XtensaCPU *cpu = XTENSA_CPU(s); | |
| 38 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); | |
| 39 | CPUXtensaState *env = &cpu->env; | |
| 40 | ||
| 41 | xcc->parent_reset(s); | |
| 42 | ||
| 43 | cpu_state_reset(env); | |
| 44 | } | |
| 45 | ||
| 46 | static void xtensa_cpu_class_init(ObjectClass *oc, void *data) | |
| 47 | { | |
| 48 | CPUClass *cc = CPU_CLASS(oc); | |
| 49 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); | |
| 50 | ||
| 51 | xcc->parent_reset = cc->reset; | |
| 52 | cc->reset = xtensa_cpu_reset; | |
| 53 | } | |
| 54 | ||
| 55 | static const TypeInfo xtensa_cpu_type_info = { | |
| 56 | .name = TYPE_XTENSA_CPU, | |
| 57 | .parent = TYPE_CPU, | |
| 58 | .instance_size = sizeof(XtensaCPU), | |
| 59 | .abstract = false, | |
| 60 | .class_size = sizeof(XtensaCPUClass), | |
| 61 | .class_init = xtensa_cpu_class_init, | |
| 62 | }; | |
| 63 | ||
| 64 | static void xtensa_cpu_register_types(void) | |
| 65 | { | |
| 66 | type_register_static(&xtensa_cpu_type_info); | |
| 67 | } | |
| 68 | ||
| 69 | type_init(xtensa_cpu_register_types) |