[qemu.git] / hw / pl110.c

/*
 * Arm PrimeCell PL110 Color LCD Controller
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GNU LGPL
 */

#include "hw.h"
#include "primecell.h"
#include "console.h"

#define PL110_CR_EN   0x001
#define PL110_CR_BGR  0x100
#define PL110_CR_BEBO 0x200
#define PL110_CR_BEPO 0x400
#define PL110_CR_PWR  0x800

enum pl110_bppmode
{
    BPP_1,
    BPP_2,
    BPP_4,
    BPP_8,
    BPP_16,
    BPP_32
};

typedef struct {
    DisplayState *ds;

    /* The Versatile/PB uses a slightly modified PL110 controller.  */
    int versatile;
    uint32_t timing[4];
    uint32_t cr;
    uint32_t upbase;
    uint32_t lpbase;
    uint32_t int_status;
    uint32_t int_mask;
    int cols;
    int rows;
    enum pl110_bppmode bpp;
    int invalidate;
    uint32_t pallette[256];
    uint32_t raw_pallette[128];
    qemu_irq irq;
} pl110_state;

static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
   has a different ID.  However Linux only looks for the normal ID.  */
#if 0
static const unsigned char pl110_versatile_id[] =
{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#else
#define pl110_versatile_id pl110_id
#endif

static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
}

static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);

#define BITS 8
#include "pl110_template.h"
#define BITS 15
#include "pl110_template.h"
#define BITS 16
#include "pl110_template.h"
#define BITS 24
#include "pl110_template.h"
#define BITS 32
#include "pl110_template.h"

static int pl110_enabled(pl110_state *s)
{
  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}

static void pl110_update_display(void *opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    drawfn* fntable;
    drawfn fn;
    uint32_t *pallette;
    uint32_t addr;
    uint32_t base;
    int dest_width;
    int src_width;
    uint8_t *dest;
    uint8_t *src;
    int first, last = 0;
    int dirty, new_dirty;
    int i;
    int bpp_offset;

    if (!pl110_enabled(s))
        return;

    switch (ds_get_bits_per_pixel(s->ds)) {
    case 0:
        return;
    case 8:
        fntable = pl110_draw_fn_8;
        dest_width = 1;
        break;
    case 15:
        fntable = pl110_draw_fn_15;
        dest_width = 2;
        break;
    case 16:
        fntable = pl110_draw_fn_16;
        dest_width = 2;
        break;
    case 24:
        fntable = pl110_draw_fn_24;
        dest_width = 3;
        break;
    case 32:
        fntable = pl110_draw_fn_32;
        dest_width = 4;
        break;
    default:
        fprintf(stderr, "pl110: Bad color depth\n");
        exit(1);
    }
    if (s->cr & PL110_CR_BGR)
        bpp_offset = 0;
    else
        bpp_offset = 18;

    if (s->cr & PL110_CR_BEBO)
        fn = fntable[s->bpp + 6 + bpp_offset];
    else if (s->cr & PL110_CR_BEPO)
        fn = fntable[s->bpp + 12 + bpp_offset];
    else
        fn = fntable[s->bpp + bpp_offset];

    src_width = s->cols;
    switch (s->bpp) {
    case BPP_1:
        src_width >>= 3;
        break;
    case BPP_2:
        src_width >>= 2;
        break;
    case BPP_4:
        src_width >>= 1;
        break;
    case BPP_8:
        break;
    case BPP_16:
        src_width <<= 1;
        break;
    case BPP_32:
        src_width <<= 2;
        break;
    }
    dest_width *= s->cols;
    pallette = s->pallette;
    base = s->upbase;
    /* HACK: Arm aliases physical memory at 0x80000000.  */
    if (base > 0x80000000)
        base -= 0x80000000;
    src = phys_ram_base + base;
    dest = ds_get_data(s->ds);
    first = -1;
    addr = base;

    dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
    new_dirty = dirty;
    for (i = 0; i < s->rows; i++) {
        if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
            uint32_t tmp;
            new_dirty = 0;
            for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
                new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
                                                           VGA_DIRTY_FLAG);
            }
        }

        if (dirty || new_dirty || s->invalidate) {
            fn(pallette, dest, src, s->cols);
            if (first == -1)
                first = i;
            last = i;
        }
        dirty = new_dirty;
        addr += src_width;
        dest += dest_width;
        src += src_width;
    }
    if (first < 0)
      return;

    s->invalidate = 0;
    cpu_physical_memory_reset_dirty(base + first * src_width,
                                    base + (last + 1) * src_width,
                                    VGA_DIRTY_FLAG);
    dpy_update(s->ds, 0, first, s->cols, last - first + 1);
}

static void pl110_invalidate_display(void * opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    s->invalidate = 1;
}

static void pl110_update_pallette(pl110_state *s, int n)
{
    int i;
    uint32_t raw;
    unsigned int r, g, b;

    raw = s->raw_pallette[n];
    n <<= 1;
    for (i = 0; i < 2; i++) {
        r = (raw & 0x1f) << 3;
        raw >>= 5;
        g = (raw & 0x1f) << 3;
        raw >>= 5;
        b = (raw & 0x1f) << 3;
        /* The I bit is ignored.  */
        raw >>= 6;
        switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            s->pallette[n] = rgb_to_pixel8(r, g, b);
            break;
        case 15:
            s->pallette[n] = rgb_to_pixel15(r, g, b);
            break;
        case 16:
            s->pallette[n] = rgb_to_pixel16(r, g, b);
            break;
        case 24:
        case 32:
            s->pallette[n] = rgb_to_pixel32(r, g, b);
            break;
        }
        n++;
    }
}

static void pl110_resize(pl110_state *s, int width, int height)
{
    if (width != s->cols || height != s->rows) {
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, width, height);
        }
    }
    s->cols = width;
    s->rows = height;
}

/* Update interrupts.  */
static void pl110_update(pl110_state *s)
{
  /* TODO: Implement interrupts.  */
}

static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
{
    pl110_state *s = (pl110_state *)opaque;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->versatile)
            return pl110_versatile_id[(offset - 0xfe0) >> 2];
        else
            return pl110_id[(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x200 && offset < 0x400) {
        return s->raw_pallette[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        return s->timing[0];
    case 1: /* LCDTiming1 */
        return s->timing[1];
    case 2: /* LCDTiming2 */
        return s->timing[2];
    case 3: /* LCDTiming3 */
        return s->timing[3];
    case 4: /* LCDUPBASE */
        return s->upbase;
    case 5: /* LCDLPBASE */
        return s->lpbase;
    case 6: /* LCDIMSC */
	if (s->versatile)
	  return s->cr;
        return s->int_mask;
    case 7: /* LCDControl */
	if (s->versatile)
	  return s->int_mask;
        return s->cr;
    case 8: /* LCDRIS */
        return s->int_status;
    case 9: /* LCDMIS */
        return s->int_status & s->int_mask;
    case 11: /* LCDUPCURR */
        /* TODO: Implement vertical refresh.  */
        return s->upbase;
    case 12: /* LCDLPCURR */
        return s->lpbase;
    default:
        cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl110_write(void *opaque, target_phys_addr_t offset,
                        uint32_t val)
{
    pl110_state *s = (pl110_state *)opaque;
    int n;

    /* For simplicity invalidate the display whenever a control register
       is writen to.  */
    s->invalidate = 1;
    if (offset >= 0x200 && offset < 0x400) {
        /* Pallette.  */
        n = (offset - 0x200) >> 2;
        s->raw_pallette[(offset - 0x200) >> 2] = val;
        pl110_update_pallette(s, n);
        return;
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        s->timing[0] = val;
        n = ((val & 0xfc) + 4) * 4;
        pl110_resize(s, n, s->rows);
        break;
    case 1: /* LCDTiming1 */
        s->timing[1] = val;
        n = (val & 0x3ff) + 1;
        pl110_resize(s, s->cols, n);
        break;
    case 2: /* LCDTiming2 */
        s->timing[2] = val;
        break;
    case 3: /* LCDTiming3 */
        s->timing[3] = val;
        break;
    case 4: /* LCDUPBASE */
        s->upbase = val;
        break;
    case 5: /* LCDLPBASE */
        s->lpbase = val;
        break;
    case 6: /* LCDIMSC */
        if (s->versatile)
            goto control;
    imsc:
        s->int_mask = val;
        pl110_update(s);
        break;
    case 7: /* LCDControl */
        if (s->versatile)
            goto imsc;
    control:
        s->cr = val;
        s->bpp = (val >> 1) & 7;
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, s->cols, s->rows);
        }
        break;
    case 10: /* LCDICR */
        s->int_status &= ~val;
        pl110_update(s);
        break;
    default:
        cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
    }
}

static CPUReadMemoryFunc *pl110_readfn[] = {
   pl110_read,
   pl110_read,
   pl110_read
};

static CPUWriteMemoryFunc *pl110_writefn[] = {
   pl110_write,
   pl110_write,
   pl110_write
};

void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
{
    pl110_state *s;
    int iomemtype;

    s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
    iomemtype = cpu_register_io_memory(0, pl110_readfn,
                                       pl110_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    s->versatile = versatile;
    s->irq = irq;
    s->ds = graphic_console_init(pl110_update_display,
                                 pl110_invalidate_display,
                                 NULL, NULL, s);
    /* ??? Save/restore.  */
    return s;
}
Commit	Line	Data
5fafdf24	1	/*
bdd5003a PB	2	* Arm PrimeCell PL110 Color LCD Controller
bdd5003a PB	3	*
cdbdb648	4	* Copyright (c) 2005-2006 CodeSourcery.
bdd5003a PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GNU LGPL
	8	*/
	9
87ecb68b PB	10	#include "hw.h"
	11	#include "primecell.h"
	12	#include "console.h"
bdd5003a PB	13
bdd5003a PB	14	#define PL110_CR_EN 0x001
e9c05b42	15	#define PL110_CR_BGR 0x100
bdd5003a PB	16	#define PL110_CR_BEBO 0x200
	17	#define PL110_CR_BEPO 0x400
	18	#define PL110_CR_PWR 0x800
	19
	20	enum pl110_bppmode
	21	{
	22	BPP_1,
	23	BPP_2,
	24	BPP_4,
	25	BPP_8,
	26	BPP_16,
	27	BPP_32
	28	};
	29
	30	typedef struct {
bdd5003a	31	DisplayState *ds;
c60e08d9	32
cdbdb648 PB	33	/* The Versatile/PB uses a slightly modified PL110 controller. */
cdbdb648 PB	34	int versatile;
bdd5003a PB	35	uint32_t timing[4];
	36	uint32_t cr;
	37	uint32_t upbase;
	38	uint32_t lpbase;
	39	uint32_t int_status;
	40	uint32_t int_mask;
	41	int cols;
	42	int rows;
	43	enum pl110_bppmode bpp;
	44	int invalidate;
	45	uint32_t pallette[256];
	46	uint32_t raw_pallette[128];
d537cf6c	47	qemu_irq irq;
bdd5003a PB	48	} pl110_state;
	49
	50	static const unsigned char pl110_id[] =
	51	{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	52
cdbdb648 PB	53	/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
	54	has a different ID. However Linux only looks for the normal ID. */
	55	#if 0
	56	static const unsigned char pl110_versatile_id[] =
	57	{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	58	#else
	59	#define pl110_versatile_id pl110_id
	60	#endif
	61
bdd5003a PB	62	static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
	63	{
	64	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
	65	}
	66
	67	static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
	68	{
	69	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
	70	}
	71
	72	static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
	73	{
	74	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
	75	}
	76
	77	static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
	78	{
	79	return (r << 16) \| (g << 8) \| b;
	80	}
	81
	82	static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
	83	{
	84	return (r << 16) \| (g << 8) \| b;
	85	}
	86
	87	typedef void (drawfn)(uint32_t , uint8_t , const uint8_t , int);
	88
	89	#define BITS 8
	90	#include "pl110_template.h"
	91	#define BITS 15
	92	#include "pl110_template.h"
	93	#define BITS 16
	94	#include "pl110_template.h"
	95	#define BITS 24
	96	#include "pl110_template.h"
	97	#define BITS 32
	98	#include "pl110_template.h"
	99
	100	static int pl110_enabled(pl110_state *s)
	101	{
	102	return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
	103	}
	104
95219897	105	static void pl110_update_display(void *opaque)
bdd5003a PB	106	{
	107	pl110_state s = (pl110_state )opaque;
	108	drawfn* fntable;
	109	drawfn fn;
	110	uint32_t *pallette;
	111	uint32_t addr;
	112	uint32_t base;
	113	int dest_width;
	114	int src_width;
	115	uint8_t *dest;
	116	uint8_t *src;
cdbdb648	117	int first, last = 0;
bdd5003a PB	118	int dirty, new_dirty;
bdd5003a PB	119	int i;
e9c05b42	120	int bpp_offset;
bdd5003a PB	121
	122	if (!pl110_enabled(s))
	123	return;
3b46e624	124
0e1f5a0c	125	switch (ds_get_bits_per_pixel(s->ds)) {
af2f6733 PB	126	case 0:
af2f6733 PB	127	return;
bdd5003a PB	128	case 8:
	129	fntable = pl110_draw_fn_8;
	130	dest_width = 1;
	131	break;
	132	case 15:
	133	fntable = pl110_draw_fn_15;
	134	dest_width = 2;
	135	break;
	136	case 16:
	137	fntable = pl110_draw_fn_16;
	138	dest_width = 2;
	139	break;
	140	case 24:
	141	fntable = pl110_draw_fn_24;
	142	dest_width = 3;
	143	break;
	144	case 32:
	145	fntable = pl110_draw_fn_32;
	146	dest_width = 4;
	147	break;
	148	default:
af2f6733	149	fprintf(stderr, "pl110: Bad color depth\n");
bdd5003a PB	150	exit(1);
bdd5003a PB	151	}
e9c05b42 AZ	152	if (s->cr & PL110_CR_BGR)
	153	bpp_offset = 0;
	154	else
	155	bpp_offset = 18;
	156
bdd5003a	157	if (s->cr & PL110_CR_BEBO)
e9c05b42	158	fn = fntable[s->bpp + 6 + bpp_offset];
bdd5003a	159	else if (s->cr & PL110_CR_BEPO)
e9c05b42	160	fn = fntable[s->bpp + 12 + bpp_offset];
bdd5003a	161	else
e9c05b42	162	fn = fntable[s->bpp + bpp_offset];
3b46e624	163
bdd5003a PB	164	src_width = s->cols;
	165	switch (s->bpp) {
	166	case BPP_1:
	167	src_width >>= 3;
	168	break;
	169	case BPP_2:
	170	src_width >>= 2;
	171	break;
	172	case BPP_4:
	173	src_width >>= 1;
	174	break;
	175	case BPP_8:
	176	break;
	177	case BPP_16:
	178	src_width <<= 1;
	179	break;
	180	case BPP_32:
	181	src_width <<= 2;
	182	break;
	183	}
	184	dest_width *= s->cols;
	185	pallette = s->pallette;
	186	base = s->upbase;
	187	/* HACK: Arm aliases physical memory at 0x80000000. */
	188	if (base > 0x80000000)
	189	base -= 0x80000000;
	190	src = phys_ram_base + base;
0e1f5a0c	191	dest = ds_get_data(s->ds);
bdd5003a PB	192	first = -1;
	193	addr = base;
	194
	195	dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
e6e5906b	196	new_dirty = dirty;
bdd5003a	197	for (i = 0; i < s->rows; i++) {
e6e5906b	198	if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
bdd5003a	199	uint32_t tmp;
e6e5906b	200	new_dirty = 0;
bdd5003a PB	201	for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
	202	new_dirty \|= cpu_physical_memory_get_dirty(addr + tmp,
	203	VGA_DIRTY_FLAG);
	204	}
	205	}
	206
	207	if (dirty \|\| new_dirty \|\| s->invalidate) {
	208	fn(pallette, dest, src, s->cols);
	209	if (first == -1)
	210	first = i;
	211	last = i;
	212	}
	213	dirty = new_dirty;
	214	addr += src_width;
	215	dest += dest_width;
	216	src += src_width;
	217	}
	218	if (first < 0)
	219	return;
	220
	221	s->invalidate = 0;
	222	cpu_physical_memory_reset_dirty(base + first * src_width,
	223	base + (last + 1) * src_width,
	224	VGA_DIRTY_FLAG);
	225	dpy_update(s->ds, 0, first, s->cols, last - first + 1);
	226	}
	227
95219897	228	static void pl110_invalidate_display(void * opaque)
bdd5003a PB	229	{
	230	pl110_state s = (pl110_state )opaque;
	231	s->invalidate = 1;
	232	}
	233
	234	static void pl110_update_pallette(pl110_state *s, int n)
	235	{
	236	int i;
	237	uint32_t raw;
	238	unsigned int r, g, b;
	239
	240	raw = s->raw_pallette[n];
	241	n <<= 1;
	242	for (i = 0; i < 2; i++) {
	243	r = (raw & 0x1f) << 3;
	244	raw >>= 5;
	245	g = (raw & 0x1f) << 3;
	246	raw >>= 5;
	247	b = (raw & 0x1f) << 3;
	248	/* The I bit is ignored. */
	249	raw >>= 6;
0e1f5a0c	250	switch (ds_get_bits_per_pixel(s->ds)) {
bdd5003a PB	251	case 8:
	252	s->pallette[n] = rgb_to_pixel8(r, g, b);
	253	break;
	254	case 15:
	255	s->pallette[n] = rgb_to_pixel15(r, g, b);
	256	break;
	257	case 16:
	258	s->pallette[n] = rgb_to_pixel16(r, g, b);
	259	break;
	260	case 24:
	261	case 32:
	262	s->pallette[n] = rgb_to_pixel32(r, g, b);
	263	break;
	264	}
	265	n++;
	266	}
	267	}
	268
	269	static void pl110_resize(pl110_state *s, int width, int height)
	270	{
	271	if (width != s->cols \|\| height != s->rows) {
	272	if (pl110_enabled(s)) {
3023f332	273	qemu_console_resize(s->ds, width, height);
bdd5003a PB	274	}
	275	}
	276	s->cols = width;
	277	s->rows = height;
	278	}
	279
	280	/* Update interrupts. */
	281	static void pl110_update(pl110_state *s)
	282	{
	283	/* TODO: Implement interrupts. */
	284	}
	285
	286	static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
	287	{
	288	pl110_state s = (pl110_state )opaque;
	289
bdd5003a	290	if (offset >= 0xfe0 && offset < 0x1000) {
cdbdb648 PB	291	if (s->versatile)
	292	return pl110_versatile_id[(offset - 0xfe0) >> 2];
	293	else
	294	return pl110_id[(offset - 0xfe0) >> 2];
bdd5003a PB	295	}
	296	if (offset >= 0x200 && offset < 0x400) {
	297	return s->raw_pallette[(offset - 0x200) >> 2];
	298	}
	299	switch (offset >> 2) {
	300	case 0: /* LCDTiming0 */
	301	return s->timing[0];
	302	case 1: /* LCDTiming1 */
	303	return s->timing[1];
	304	case 2: /* LCDTiming2 */
	305	return s->timing[2];
	306	case 3: /* LCDTiming3 */
	307	return s->timing[3];
	308	case 4: /* LCDUPBASE */
	309	return s->upbase;
	310	case 5: /* LCDLPBASE */
	311	return s->lpbase;
	312	case 6: /* LCDIMSC */
64075cd7 PB	313	if (s->versatile)
64075cd7 PB	314	return s->cr;
bdd5003a PB	315	return s->int_mask;
bdd5003a PB	316	case 7: /* LCDControl */
64075cd7 PB	317	if (s->versatile)
64075cd7 PB	318	return s->int_mask;
bdd5003a PB	319	return s->cr;
	320	case 8: /* LCDRIS */
	321	return s->int_status;
	322	case 9: /* LCDMIS */
	323	return s->int_status & s->int_mask;
	324	case 11: /* LCDUPCURR */
	325	/* TODO: Implement vertical refresh. */
	326	return s->upbase;
	327	case 12: /* LCDLPCURR */
	328	return s->lpbase;
	329	default:
4d1165fa	330	cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
bdd5003a PB	331	return 0;
	332	}
	333	}
	334
	335	static void pl110_write(void *opaque, target_phys_addr_t offset,
	336	uint32_t val)
	337	{
	338	pl110_state s = (pl110_state )opaque;
	339	int n;
	340
	341	/* For simplicity invalidate the display whenever a control register
	342	is writen to. */
	343	s->invalidate = 1;
bdd5003a PB	344	if (offset >= 0x200 && offset < 0x400) {
	345	/* Pallette. */
	346	n = (offset - 0x200) >> 2;
	347	s->raw_pallette[(offset - 0x200) >> 2] = val;
	348	pl110_update_pallette(s, n);
e10c2bfb	349	return;
bdd5003a PB	350	}
	351	switch (offset >> 2) {
	352	case 0: /* LCDTiming0 */
	353	s->timing[0] = val;
	354	n = ((val & 0xfc) + 4) * 4;
	355	pl110_resize(s, n, s->rows);
	356	break;
	357	case 1: /* LCDTiming1 */
	358	s->timing[1] = val;
	359	n = (val & 0x3ff) + 1;
	360	pl110_resize(s, s->cols, n);
	361	break;
	362	case 2: /* LCDTiming2 */
	363	s->timing[2] = val;
	364	break;
	365	case 3: /* LCDTiming3 */
	366	s->timing[3] = val;
	367	break;
	368	case 4: /* LCDUPBASE */
	369	s->upbase = val;
	370	break;
	371	case 5: /* LCDLPBASE */
	372	s->lpbase = val;
	373	break;
	374	case 6: /* LCDIMSC */
cdbdb648 PB	375	if (s->versatile)
	376	goto control;
	377	imsc:
bdd5003a PB	378	s->int_mask = val;
	379	pl110_update(s);
	380	break;
	381	case 7: /* LCDControl */
cdbdb648 PB	382	if (s->versatile)
	383	goto imsc;
	384	control:
bdd5003a PB	385	s->cr = val;
	386	s->bpp = (val >> 1) & 7;
	387	if (pl110_enabled(s)) {
3023f332	388	qemu_console_resize(s->ds, s->cols, s->rows);
bdd5003a PB	389	}
	390	break;
	391	case 10: /* LCDICR */
	392	s->int_status &= ~val;
	393	pl110_update(s);
	394	break;
	395	default:
4d1165fa	396	cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
bdd5003a PB	397	}
	398	}
	399
	400	static CPUReadMemoryFunc *pl110_readfn[] = {
	401	pl110_read,
	402	pl110_read,
	403	pl110_read
	404	};
	405
	406	static CPUWriteMemoryFunc *pl110_writefn[] = {
	407	pl110_write,
	408	pl110_write,
	409	pl110_write
	410	};
	411
3023f332	412	void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
bdd5003a PB	413	{
	414	pl110_state *s;
	415	int iomemtype;
	416
	417	s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
	418	iomemtype = cpu_register_io_memory(0, pl110_readfn,
	419	pl110_writefn, s);
187337f8	420	cpu_register_physical_memory(base, 0x00001000, iomemtype);
cdbdb648	421	s->versatile = versatile;
bdd5003a	422	s->irq = irq;
3023f332 AL	423	s->ds = graphic_console_init(pl110_update_display,
	424	pl110_invalidate_display,
	425	NULL, NULL, s);
bdd5003a PB	426	/* ??? Save/restore. */
	427	return s;
	428	}