[qemu.git] / hw / pl110.c

/* 
 * Arm PrimeCell PL110 Color LCD Controller
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GNU LGPL
 */

#include "vl.h"

#define PL110_CR_EN   0x001
#define PL110_CR_BEBO 0x200
#define PL110_CR_BEPO 0x400
#define PL110_CR_PWR  0x800

enum pl110_bppmode
{
    BPP_1,
    BPP_2,
    BPP_4,
    BPP_8,
    BPP_16,
    BPP_32
};

typedef struct {
    uint32_t base;
    DisplayState *ds;
    /* The Versatile/PB uses a slightly modified PL110 controller.  */
    int versatile;
    uint32_t timing[4];
    uint32_t cr;
    uint32_t upbase;
    uint32_t lpbase;
    uint32_t int_status;
    uint32_t int_mask;
    int cols;
    int rows;
    enum pl110_bppmode bpp;
    int invalidate;
    uint32_t pallette[256];
    uint32_t raw_pallette[128];
    qemu_irq irq;
} pl110_state;

static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
   has a different ID.  However Linux only looks for the normal ID.  */
#if 0
static const unsigned char pl110_versatile_id[] =
{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#else
#define pl110_versatile_id pl110_id
#endif

static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
}

static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);

#define BITS 8
#include "pl110_template.h"
#define BITS 15
#include "pl110_template.h"
#define BITS 16
#include "pl110_template.h"
#define BITS 24
#include "pl110_template.h"
#define BITS 32
#include "pl110_template.h"

static int pl110_enabled(pl110_state *s)
{
  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}

static void pl110_update_display(void *opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    drawfn* fntable;
    drawfn fn;
    uint32_t *pallette;
    uint32_t addr;
    uint32_t base;
    int dest_width;
    int src_width;
    uint8_t *dest;
    uint8_t *src;
    int first, last = 0;
    int dirty, new_dirty;
    int i;

    if (!pl110_enabled(s))
        return;
    
    switch (s->ds->depth) {
    case 0:
        return;
    case 8:
        fntable = pl110_draw_fn_8;
        dest_width = 1;
        break;
    case 15:
        fntable = pl110_draw_fn_15;
        dest_width = 2;
        break;
    case 16:
        fntable = pl110_draw_fn_16;
        dest_width = 2;
        break;
    case 24:
        fntable = pl110_draw_fn_24;
        dest_width = 3;
        break;
    case 32:
        fntable = pl110_draw_fn_32;
        dest_width = 4;
        break;
    default:
        fprintf(stderr, "pl110: Bad color depth\n");
        exit(1);
    }
    if (s->cr & PL110_CR_BEBO)
      fn = fntable[s->bpp + 6];
    else if (s->cr & PL110_CR_BEPO)
      fn = fntable[s->bpp + 12];
    else
      fn = fntable[s->bpp];
    
    src_width = s->cols;
    switch (s->bpp) {
    case BPP_1:
        src_width >>= 3;
        break;
    case BPP_2:
        src_width >>= 2;
        break;
    case BPP_4:
        src_width >>= 1;
        break;
    case BPP_8:
        break;
    case BPP_16:
        src_width <<= 1;
        break;
    case BPP_32:
        src_width <<= 2;
        break;
    }
    dest_width *= s->cols;
    pallette = s->pallette;
    base = s->upbase;
    /* HACK: Arm aliases physical memory at 0x80000000.  */
    if (base > 0x80000000)
        base -= 0x80000000;
    src = phys_ram_base + base;
    dest = s->ds->data;
    first = -1;
    addr = base;

    dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
    new_dirty = dirty;
    for (i = 0; i < s->rows; i++) {
        if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
            uint32_t tmp;
            new_dirty = 0;
            for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
                new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
                                                           VGA_DIRTY_FLAG);
            }
        }

        if (dirty || new_dirty || s->invalidate) {
            fn(pallette, dest, src, s->cols);
            if (first == -1)
                first = i;
            last = i;
        }
        dirty = new_dirty;
        addr += src_width;
        dest += dest_width;
        src += src_width;
    }
    if (first < 0)
      return;

    s->invalidate = 0;
    cpu_physical_memory_reset_dirty(base + first * src_width,
                                    base + (last + 1) * src_width,
                                    VGA_DIRTY_FLAG);
    dpy_update(s->ds, 0, first, s->cols, last - first + 1);
}

static void pl110_invalidate_display(void * opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    s->invalidate = 1;
}

static void pl110_update_pallette(pl110_state *s, int n)
{
    int i;
    uint32_t raw;
    unsigned int r, g, b;

    raw = s->raw_pallette[n];
    n <<= 1;
    for (i = 0; i < 2; i++) {
        r = (raw & 0x1f) << 3;
        raw >>= 5;
        g = (raw & 0x1f) << 3;
        raw >>= 5;
        b = (raw & 0x1f) << 3;
        /* The I bit is ignored.  */
        raw >>= 6;
        switch (s->ds->depth) {
        case 8:
            s->pallette[n] = rgb_to_pixel8(r, g, b);
            break;
        case 15:
            s->pallette[n] = rgb_to_pixel15(r, g, b);
            break;
        case 16:
            s->pallette[n] = rgb_to_pixel16(r, g, b);
            break;
        case 24:
        case 32:
            s->pallette[n] = rgb_to_pixel32(r, g, b);
            break;
        }
        n++;
    }
}

static void pl110_resize(pl110_state *s, int width, int height)
{
    if (width != s->cols || height != s->rows) {
        if (pl110_enabled(s)) {
            dpy_resize(s->ds, width, height);
        }
    }
    s->cols = width;
    s->rows = height;
}

/* Update interrupts.  */
static void pl110_update(pl110_state *s)
{
  /* TODO: Implement interrupts.  */
}

static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
{
    pl110_state *s = (pl110_state *)opaque;

    offset -= s->base;
    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->versatile)
            return pl110_versatile_id[(offset - 0xfe0) >> 2];
        else
            return pl110_id[(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x200 && offset < 0x400) {
        return s->raw_pallette[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        return s->timing[0];
    case 1: /* LCDTiming1 */
        return s->timing[1];
    case 2: /* LCDTiming2 */
        return s->timing[2];
    case 3: /* LCDTiming3 */
        return s->timing[3];
    case 4: /* LCDUPBASE */
        return s->upbase;
    case 5: /* LCDLPBASE */
        return s->lpbase;
    case 6: /* LCDIMSC */
        return s->int_mask;
    case 7: /* LCDControl */
        return s->cr;
    case 8: /* LCDRIS */
        return s->int_status;
    case 9: /* LCDMIS */
        return s->int_status & s->int_mask;
    case 11: /* LCDUPCURR */
        /* TODO: Implement vertical refresh.  */
        return s->upbase;
    case 12: /* LCDLPCURR */
        return s->lpbase;
    default:
        cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
        return 0;
    }
}

static void pl110_write(void *opaque, target_phys_addr_t offset,
                        uint32_t val)
{
    pl110_state *s = (pl110_state *)opaque;
    int n;

    /* For simplicity invalidate the display whenever a control register
       is writen to.  */
    s->invalidate = 1;
    offset -= s->base;
    if (offset >= 0x200 && offset < 0x400) {
        /* Pallette.  */
        n = (offset - 0x200) >> 2;
        s->raw_pallette[(offset - 0x200) >> 2] = val;
        pl110_update_pallette(s, n);
        return;
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        s->timing[0] = val;
        n = ((val & 0xfc) + 4) * 4;
        pl110_resize(s, n, s->rows);
        break;
    case 1: /* LCDTiming1 */
        s->timing[1] = val;
        n = (val & 0x3ff) + 1;
        pl110_resize(s, s->cols, n);
        break;
    case 2: /* LCDTiming2 */
        s->timing[2] = val;
        break;
    case 3: /* LCDTiming3 */
        s->timing[3] = val;
        break;
    case 4: /* LCDUPBASE */
        s->upbase = val;
        break;
    case 5: /* LCDLPBASE */
        s->lpbase = val;
        break;
    case 6: /* LCDIMSC */
        if (s->versatile)
            goto control;
    imsc:
        s->int_mask = val;
        pl110_update(s);
        break;
    case 7: /* LCDControl */
        if (s->versatile)
            goto imsc;
    control:
        s->cr = val;
        s->bpp = (val >> 1) & 7;
        if (pl110_enabled(s)) {
            dpy_resize(s->ds, s->cols, s->rows);
        }
        break;
    case 10: /* LCDICR */
        s->int_status &= ~val;
        pl110_update(s);
        break;
    default:
        cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
    }
}

static CPUReadMemoryFunc *pl110_readfn[] = {
   pl110_read,
   pl110_read,
   pl110_read
};

static CPUWriteMemoryFunc *pl110_writefn[] = {
   pl110_write,
   pl110_write,
   pl110_write
};

void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
                 int versatile)
{
    pl110_state *s;
    int iomemtype;

    s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
    iomemtype = cpu_register_io_memory(0, pl110_readfn,
                                       pl110_writefn, s);
    cpu_register_physical_memory(base, 0x00000fff, iomemtype);
    s->base = base;
    s->ds = ds;
    s->versatile = versatile;
    s->irq = irq;
    graphic_console_init(ds, pl110_update_display, pl110_invalidate_display,
                         NULL, s);
    /* ??? Save/restore.  */
    return s;
}
Commit	Line	Data
bdd5003a PB	1	/*
	2	* Arm PrimeCell PL110 Color LCD Controller
	3	*
cdbdb648	4	* Copyright (c) 2005-2006 CodeSourcery.
bdd5003a PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GNU LGPL
	8	*/
	9
	10	#include "vl.h"
	11
	12	#define PL110_CR_EN 0x001
	13	#define PL110_CR_BEBO 0x200
	14	#define PL110_CR_BEPO 0x400
	15	#define PL110_CR_PWR 0x800
	16
	17	enum pl110_bppmode
	18	{
	19	BPP_1,
	20	BPP_2,
	21	BPP_4,
	22	BPP_8,
	23	BPP_16,
	24	BPP_32
	25	};
	26
	27	typedef struct {
	28	uint32_t base;
	29	DisplayState *ds;
cdbdb648 PB	30	/* The Versatile/PB uses a slightly modified PL110 controller. */
cdbdb648 PB	31	int versatile;
bdd5003a PB	32	uint32_t timing[4];
	33	uint32_t cr;
	34	uint32_t upbase;
	35	uint32_t lpbase;
	36	uint32_t int_status;
	37	uint32_t int_mask;
	38	int cols;
	39	int rows;
	40	enum pl110_bppmode bpp;
	41	int invalidate;
	42	uint32_t pallette[256];
	43	uint32_t raw_pallette[128];
d537cf6c	44	qemu_irq irq;
bdd5003a PB	45	} pl110_state;
	46
	47	static const unsigned char pl110_id[] =
	48	{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	49
cdbdb648 PB	50	/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
	51	has a different ID. However Linux only looks for the normal ID. */
	52	#if 0
	53	static const unsigned char pl110_versatile_id[] =
	54	{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	55	#else
	56	#define pl110_versatile_id pl110_id
	57	#endif
	58
bdd5003a PB	59	static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
	60	{
	61	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
	62	}
	63
	64	static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
	65	{
	66	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
	67	}
	68
	69	static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
	70	{
	71	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
	72	}
	73
	74	static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
	75	{
	76	return (r << 16) \| (g << 8) \| b;
	77	}
	78
	79	static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
	80	{
	81	return (r << 16) \| (g << 8) \| b;
	82	}
	83
	84	typedef void (drawfn)(uint32_t , uint8_t , const uint8_t , int);
	85
	86	#define BITS 8
	87	#include "pl110_template.h"
	88	#define BITS 15
	89	#include "pl110_template.h"
	90	#define BITS 16
	91	#include "pl110_template.h"
	92	#define BITS 24
	93	#include "pl110_template.h"
	94	#define BITS 32
	95	#include "pl110_template.h"
	96
	97	static int pl110_enabled(pl110_state *s)
	98	{
	99	return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
	100	}
	101
95219897	102	static void pl110_update_display(void *opaque)
bdd5003a PB	103	{
	104	pl110_state s = (pl110_state )opaque;
	105	drawfn* fntable;
	106	drawfn fn;
	107	uint32_t *pallette;
	108	uint32_t addr;
	109	uint32_t base;
	110	int dest_width;
	111	int src_width;
	112	uint8_t *dest;
	113	uint8_t *src;
cdbdb648	114	int first, last = 0;
bdd5003a PB	115	int dirty, new_dirty;
	116	int i;
	117
	118	if (!pl110_enabled(s))
	119	return;
	120
	121	switch (s->ds->depth) {
af2f6733 PB	122	case 0:
af2f6733 PB	123	return;
bdd5003a PB	124	case 8:
	125	fntable = pl110_draw_fn_8;
	126	dest_width = 1;
	127	break;
	128	case 15:
	129	fntable = pl110_draw_fn_15;
	130	dest_width = 2;
	131	break;
	132	case 16:
	133	fntable = pl110_draw_fn_16;
	134	dest_width = 2;
	135	break;
	136	case 24:
	137	fntable = pl110_draw_fn_24;
	138	dest_width = 3;
	139	break;
	140	case 32:
	141	fntable = pl110_draw_fn_32;
	142	dest_width = 4;
	143	break;
	144	default:
af2f6733	145	fprintf(stderr, "pl110: Bad color depth\n");
bdd5003a PB	146	exit(1);
	147	}
	148	if (s->cr & PL110_CR_BEBO)
	149	fn = fntable[s->bpp + 6];
	150	else if (s->cr & PL110_CR_BEPO)
	151	fn = fntable[s->bpp + 12];
	152	else
	153	fn = fntable[s->bpp];
	154
	155	src_width = s->cols;
	156	switch (s->bpp) {
	157	case BPP_1:
	158	src_width >>= 3;
	159	break;
	160	case BPP_2:
	161	src_width >>= 2;
	162	break;
	163	case BPP_4:
	164	src_width >>= 1;
	165	break;
	166	case BPP_8:
	167	break;
	168	case BPP_16:
	169	src_width <<= 1;
	170	break;
	171	case BPP_32:
	172	src_width <<= 2;
	173	break;
	174	}
	175	dest_width *= s->cols;
	176	pallette = s->pallette;
	177	base = s->upbase;
	178	/* HACK: Arm aliases physical memory at 0x80000000. */
	179	if (base > 0x80000000)
	180	base -= 0x80000000;
	181	src = phys_ram_base + base;
	182	dest = s->ds->data;
	183	first = -1;
	184	addr = base;
	185
	186	dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
e6e5906b	187	new_dirty = dirty;
bdd5003a	188	for (i = 0; i < s->rows; i++) {
e6e5906b	189	if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
bdd5003a	190	uint32_t tmp;
e6e5906b	191	new_dirty = 0;
bdd5003a PB	192	for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
	193	new_dirty \|= cpu_physical_memory_get_dirty(addr + tmp,
	194	VGA_DIRTY_FLAG);
	195	}
	196	}
	197
	198	if (dirty \|\| new_dirty \|\| s->invalidate) {
	199	fn(pallette, dest, src, s->cols);
	200	if (first == -1)
	201	first = i;
	202	last = i;
	203	}
	204	dirty = new_dirty;
	205	addr += src_width;
	206	dest += dest_width;
	207	src += src_width;
	208	}
	209	if (first < 0)
	210	return;
	211
	212	s->invalidate = 0;
	213	cpu_physical_memory_reset_dirty(base + first * src_width,
	214	base + (last + 1) * src_width,
	215	VGA_DIRTY_FLAG);
	216	dpy_update(s->ds, 0, first, s->cols, last - first + 1);
	217	}
	218
95219897	219	static void pl110_invalidate_display(void * opaque)
bdd5003a PB	220	{
	221	pl110_state s = (pl110_state )opaque;
	222	s->invalidate = 1;
	223	}
	224
	225	static void pl110_update_pallette(pl110_state *s, int n)
	226	{
	227	int i;
	228	uint32_t raw;
	229	unsigned int r, g, b;
	230
	231	raw = s->raw_pallette[n];
	232	n <<= 1;
	233	for (i = 0; i < 2; i++) {
	234	r = (raw & 0x1f) << 3;
	235	raw >>= 5;
	236	g = (raw & 0x1f) << 3;
	237	raw >>= 5;
	238	b = (raw & 0x1f) << 3;
	239	/* The I bit is ignored. */
	240	raw >>= 6;
	241	switch (s->ds->depth) {
	242	case 8:
	243	s->pallette[n] = rgb_to_pixel8(r, g, b);
	244	break;
	245	case 15:
	246	s->pallette[n] = rgb_to_pixel15(r, g, b);
	247	break;
	248	case 16:
	249	s->pallette[n] = rgb_to_pixel16(r, g, b);
	250	break;
	251	case 24:
	252	case 32:
	253	s->pallette[n] = rgb_to_pixel32(r, g, b);
	254	break;
	255	}
	256	n++;
	257	}
	258	}
	259
	260	static void pl110_resize(pl110_state *s, int width, int height)
	261	{
	262	if (width != s->cols \|\| height != s->rows) {
	263	if (pl110_enabled(s)) {
132ea32f	264	dpy_resize(s->ds, width, height);
bdd5003a PB	265	}
	266	}
	267	s->cols = width;
	268	s->rows = height;
	269	}
	270
	271	/* Update interrupts. */
	272	static void pl110_update(pl110_state *s)
	273	{
	274	/* TODO: Implement interrupts. */
	275	}
	276
	277	static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
	278	{
	279	pl110_state s = (pl110_state )opaque;
	280
	281	offset -= s->base;
	282	if (offset >= 0xfe0 && offset < 0x1000) {
cdbdb648 PB	283	if (s->versatile)
	284	return pl110_versatile_id[(offset - 0xfe0) >> 2];
	285	else
	286	return pl110_id[(offset - 0xfe0) >> 2];
bdd5003a PB	287	}
	288	if (offset >= 0x200 && offset < 0x400) {
	289	return s->raw_pallette[(offset - 0x200) >> 2];
	290	}
	291	switch (offset >> 2) {
	292	case 0: /* LCDTiming0 */
	293	return s->timing[0];
	294	case 1: /* LCDTiming1 */
	295	return s->timing[1];
	296	case 2: /* LCDTiming2 */
	297	return s->timing[2];
	298	case 3: /* LCDTiming3 */
	299	return s->timing[3];
	300	case 4: /* LCDUPBASE */
	301	return s->upbase;
	302	case 5: /* LCDLPBASE */
	303	return s->lpbase;
	304	case 6: /* LCDIMSC */
	305	return s->int_mask;
	306	case 7: /* LCDControl */
	307	return s->cr;
	308	case 8: /* LCDRIS */
	309	return s->int_status;
	310	case 9: /* LCDMIS */
	311	return s->int_status & s->int_mask;
	312	case 11: /* LCDUPCURR */
	313	/* TODO: Implement vertical refresh. */
	314	return s->upbase;
	315	case 12: /* LCDLPCURR */
	316	return s->lpbase;
	317	default:
	318	cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
	319	return 0;
	320	}
	321	}
	322
	323	static void pl110_write(void *opaque, target_phys_addr_t offset,
	324	uint32_t val)
	325	{
	326	pl110_state s = (pl110_state )opaque;
	327	int n;
	328
	329	/* For simplicity invalidate the display whenever a control register
	330	is writen to. */
	331	s->invalidate = 1;
	332	offset -= s->base;
	333	if (offset >= 0x200 && offset < 0x400) {
	334	/* Pallette. */
	335	n = (offset - 0x200) >> 2;
	336	s->raw_pallette[(offset - 0x200) >> 2] = val;
	337	pl110_update_pallette(s, n);
e10c2bfb	338	return;
bdd5003a PB	339	}
	340	switch (offset >> 2) {
	341	case 0: /* LCDTiming0 */
	342	s->timing[0] = val;
	343	n = ((val & 0xfc) + 4) * 4;
	344	pl110_resize(s, n, s->rows);
	345	break;
	346	case 1: /* LCDTiming1 */
	347	s->timing[1] = val;
	348	n = (val & 0x3ff) + 1;
	349	pl110_resize(s, s->cols, n);
	350	break;
	351	case 2: /* LCDTiming2 */
	352	s->timing[2] = val;
	353	break;
	354	case 3: /* LCDTiming3 */
	355	s->timing[3] = val;
	356	break;
	357	case 4: /* LCDUPBASE */
	358	s->upbase = val;
	359	break;
	360	case 5: /* LCDLPBASE */
	361	s->lpbase = val;
	362	break;
	363	case 6: /* LCDIMSC */
cdbdb648 PB	364	if (s->versatile)
	365	goto control;
	366	imsc:
bdd5003a PB	367	s->int_mask = val;
	368	pl110_update(s);
	369	break;
	370	case 7: /* LCDControl */
cdbdb648 PB	371	if (s->versatile)
	372	goto imsc;
	373	control:
bdd5003a PB	374	s->cr = val;
	375	s->bpp = (val >> 1) & 7;
	376	if (pl110_enabled(s)) {
	377	dpy_resize(s->ds, s->cols, s->rows);
	378	}
	379	break;
	380	case 10: /* LCDICR */
	381	s->int_status &= ~val;
	382	pl110_update(s);
	383	break;
	384	default:
	385	cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
	386	}
	387	}
	388
	389	static CPUReadMemoryFunc *pl110_readfn[] = {
	390	pl110_read,
	391	pl110_read,
	392	pl110_read
	393	};
	394
	395	static CPUWriteMemoryFunc *pl110_writefn[] = {
	396	pl110_write,
	397	pl110_write,
	398	pl110_write
	399	};
	400
d537cf6c	401	void pl110_init(DisplayState ds, uint32_t base, qemu_irq irq,
95219897	402	int versatile)
bdd5003a PB	403	{
	404	pl110_state *s;
	405	int iomemtype;
	406
	407	s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
	408	iomemtype = cpu_register_io_memory(0, pl110_readfn,
	409	pl110_writefn, s);
95219897	410	cpu_register_physical_memory(base, 0x00000fff, iomemtype);
bdd5003a PB	411	s->base = base;
bdd5003a PB	412	s->ds = ds;
cdbdb648	413	s->versatile = versatile;
bdd5003a	414	s->irq = irq;
95219897 PB	415	graphic_console_init(ds, pl110_update_display, pl110_invalidate_display,
95219897 PB	416	NULL, s);
bdd5003a PB	417	/* ??? Save/restore. */
	418	return s;
	419	}