[qemu.git] / hw / audio / milkymist-ac97.c

/*
 *  QEMU model of the Milkymist System Controller.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/ac97.pdf
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "audio/audio.h"
#include "qemu/error-report.h"

enum {
    R_AC97_CTRL = 0,
    R_AC97_ADDR,
    R_AC97_DATAOUT,
    R_AC97_DATAIN,
    R_D_CTRL,
    R_D_ADDR,
    R_D_REMAINING,
    R_RESERVED,
    R_U_CTRL,
    R_U_ADDR,
    R_U_REMAINING,
    R_MAX
};

enum {
    AC97_CTRL_RQEN  = (1<<0),
    AC97_CTRL_WRITE = (1<<1),
};

enum {
    CTRL_EN = (1<<0),
};

#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
#define MILKYMIST_AC97(obj) \
    OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)

struct MilkymistAC97State {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;

    QEMUSoundCard card;
    SWVoiceIn *voice_in;
    SWVoiceOut *voice_out;

    uint32_t regs[R_MAX];

    qemu_irq crrequest_irq;
    qemu_irq crreply_irq;
    qemu_irq dmar_irq;
    qemu_irq dmaw_irq;
};
typedef struct MilkymistAC97State MilkymistAC97State;

static void update_voices(MilkymistAC97State *s)
{
    if (s->regs[R_D_CTRL] & CTRL_EN) {
        AUD_set_active_out(s->voice_out, 1);
    } else {
        AUD_set_active_out(s->voice_out, 0);
    }

    if (s->regs[R_U_CTRL] & CTRL_EN) {
        AUD_set_active_in(s->voice_in, 1);
    } else {
        AUD_set_active_in(s->voice_in, 0);
    }
}

static uint64_t ac97_read(void *opaque, hwaddr addr,
                          unsigned size)
{
    MilkymistAC97State *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_AC97_CTRL:
    case R_AC97_ADDR:
    case R_AC97_DATAOUT:
    case R_AC97_DATAIN:
    case R_D_CTRL:
    case R_D_ADDR:
    case R_D_REMAINING:
    case R_U_CTRL:
    case R_U_ADDR:
    case R_U_REMAINING:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_ac97: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_ac97_memory_read(addr << 2, r);

    return r;
}

static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    MilkymistAC97State *s = opaque;

    trace_milkymist_ac97_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_AC97_CTRL:
        /* always raise an IRQ according to the direction */
        if (value & AC97_CTRL_RQEN) {
            if (value & AC97_CTRL_WRITE) {
                trace_milkymist_ac97_pulse_irq_crrequest();
                qemu_irq_pulse(s->crrequest_irq);
            } else {
                trace_milkymist_ac97_pulse_irq_crreply();
                qemu_irq_pulse(s->crreply_irq);
            }
        }

        /* RQEN is self clearing */
        s->regs[addr] = value & ~AC97_CTRL_RQEN;
        break;
    case R_D_CTRL:
    case R_U_CTRL:
        s->regs[addr] = value;
        update_voices(s);
        break;
    case R_AC97_ADDR:
    case R_AC97_DATAOUT:
    case R_AC97_DATAIN:
    case R_D_ADDR:
    case R_D_REMAINING:
    case R_U_ADDR:
    case R_U_REMAINING:
        s->regs[addr] = value;
        break;

    default:
        error_report("milkymist_ac97: write access to unknown register 0x"
                TARGET_FMT_plx, addr);
        break;
    }

}

static const MemoryRegionOps ac97_mmio_ops = {
    .read = ac97_read,
    .write = ac97_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void ac97_in_cb(void *opaque, int avail_b)
{
    MilkymistAC97State *s = opaque;
    uint8_t buf[4096];
    uint32_t remaining = s->regs[R_U_REMAINING];
    int temp = audio_MIN(remaining, avail_b);
    uint32_t addr = s->regs[R_U_ADDR];
    int transferred = 0;

    trace_milkymist_ac97_in_cb(avail_b, remaining);

    /* prevent from raising an IRQ */
    if (temp == 0) {
        return;
    }

    while (temp) {
        int acquired, to_copy;

        to_copy = audio_MIN(temp, sizeof(buf));
        acquired = AUD_read(s->voice_in, buf, to_copy);
        if (!acquired) {
            break;
        }

        cpu_physical_memory_write(addr, buf, acquired);

        temp -= acquired;
        addr += acquired;
        transferred += acquired;
    }

    trace_milkymist_ac97_in_cb_transferred(transferred);

    s->regs[R_U_ADDR] = addr;
    s->regs[R_U_REMAINING] -= transferred;

    if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) {
        trace_milkymist_ac97_pulse_irq_dmaw();
        qemu_irq_pulse(s->dmaw_irq);
    }
}

static void ac97_out_cb(void *opaque, int free_b)
{
    MilkymistAC97State *s = opaque;
    uint8_t buf[4096];
    uint32_t remaining = s->regs[R_D_REMAINING];
    int temp = audio_MIN(remaining, free_b);
    uint32_t addr = s->regs[R_D_ADDR];
    int transferred = 0;

    trace_milkymist_ac97_out_cb(free_b, remaining);

    /* prevent from raising an IRQ */
    if (temp == 0) {
        return;
    }

    while (temp) {
        int copied, to_copy;

        to_copy = audio_MIN(temp, sizeof(buf));
        cpu_physical_memory_read(addr, buf, to_copy);
        copied = AUD_write(s->voice_out, buf, to_copy);
        if (!copied) {
            break;
        }
        temp -= copied;
        addr += copied;
        transferred += copied;
    }

    trace_milkymist_ac97_out_cb_transferred(transferred);

    s->regs[R_D_ADDR] = addr;
    s->regs[R_D_REMAINING] -= transferred;

    if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) {
        trace_milkymist_ac97_pulse_irq_dmar();
        qemu_irq_pulse(s->dmar_irq);
    }
}

static void milkymist_ac97_reset(DeviceState *d)
{
    MilkymistAC97State *s = MILKYMIST_AC97(d);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    AUD_set_active_in(s->voice_in, 0);
    AUD_set_active_out(s->voice_out, 0);
}

static int ac97_post_load(void *opaque, int version_id)
{
    MilkymistAC97State *s = opaque;

    update_voices(s);

    return 0;
}

static void milkymist_ac97_init(Object *obj)
{
    MilkymistAC97State *s = MILKYMIST_AC97(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(dev, &s->crrequest_irq);
    sysbus_init_irq(dev, &s->crreply_irq);
    sysbus_init_irq(dev, &s->dmar_irq);
    sysbus_init_irq(dev, &s->dmaw_irq);

    memory_region_init_io(&s->regs_region, obj, &ac97_mmio_ops, s,
            "milkymist-ac97", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);
}

static void milkymist_ac97_realize(DeviceState *dev, Error **errp)
{
    MilkymistAC97State *s = MILKYMIST_AC97(dev);
    struct audsettings as;

    AUD_register_card("Milkymist AC'97", &s->card);

    as.freq = 48000;
    as.nchannels = 2;
    as.fmt = AUD_FMT_S16;
    as.endianness = 1;

    s->voice_in = AUD_open_in(&s->card, s->voice_in,
            "mm_ac97.in", s, ac97_in_cb, &as);
    s->voice_out = AUD_open_out(&s->card, s->voice_out,
            "mm_ac97.out", s, ac97_out_cb, &as);
}

static const VMStateDescription vmstate_milkymist_ac97 = {
    .name = "milkymist-ac97",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = ac97_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_ac97_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = milkymist_ac97_realize;
    dc->reset = milkymist_ac97_reset;
    dc->vmsd = &vmstate_milkymist_ac97;
}

static const TypeInfo milkymist_ac97_info = {
    .name          = TYPE_MILKYMIST_AC97,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistAC97State),
    .instance_init = milkymist_ac97_init,
    .class_init    = milkymist_ac97_class_init,
};

static void milkymist_ac97_register_types(void)
{
    type_register_static(&milkymist_ac97_info);
}

type_init(milkymist_ac97_register_types)
Commit	Line	Data
25a8bb96 MW	1	/*
	2	* QEMU model of the Milkymist System Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/ac97.pdf
25a8bb96 MW	22	*/
25a8bb96 MW	23
6086a565	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
25a8bb96 MW	27	#include "trace.h"
25a8bb96 MW	28	#include "audio/audio.h"
1de7afc9	29	#include "qemu/error-report.h"
25a8bb96 MW	30
	31	enum {
	32	R_AC97_CTRL = 0,
	33	R_AC97_ADDR,
	34	R_AC97_DATAOUT,
	35	R_AC97_DATAIN,
	36	R_D_CTRL,
	37	R_D_ADDR,
	38	R_D_REMAINING,
	39	R_RESERVED,
	40	R_U_CTRL,
	41	R_U_ADDR,
	42	R_U_REMAINING,
	43	R_MAX
	44	};
	45
	46	enum {
	47	AC97_CTRL_RQEN = (1<<0),
	48	AC97_CTRL_WRITE = (1<<1),
	49	};
	50
	51	enum {
	52	CTRL_EN = (1<<0),
	53	};
	54
922cc601 AF	55	#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
	56	#define MILKYMIST_AC97(obj) \
	57	OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)
	58
25a8bb96	59	struct MilkymistAC97State {
922cc601 AF	60	SysBusDevice parent_obj;
922cc601 AF	61
9496e1c3	62	MemoryRegion regs_region;
25a8bb96 MW	63
	64	QEMUSoundCard card;
	65	SWVoiceIn *voice_in;
	66	SWVoiceOut *voice_out;
	67
	68	uint32_t regs[R_MAX];
	69
	70	qemu_irq crrequest_irq;
	71	qemu_irq crreply_irq;
	72	qemu_irq dmar_irq;
	73	qemu_irq dmaw_irq;
	74	};
	75	typedef struct MilkymistAC97State MilkymistAC97State;
	76
	77	static void update_voices(MilkymistAC97State *s)
	78	{
	79	if (s->regs[R_D_CTRL] & CTRL_EN) {
	80	AUD_set_active_out(s->voice_out, 1);
	81	} else {
	82	AUD_set_active_out(s->voice_out, 0);
	83	}
	84
	85	if (s->regs[R_U_CTRL] & CTRL_EN) {
	86	AUD_set_active_in(s->voice_in, 1);
	87	} else {
	88	AUD_set_active_in(s->voice_in, 0);
	89	}
	90	}
	91
a8170e5e	92	static uint64_t ac97_read(void *opaque, hwaddr addr,
9496e1c3	93	unsigned size)
25a8bb96 MW	94	{
	95	MilkymistAC97State *s = opaque;
	96	uint32_t r = 0;
	97
	98	addr >>= 2;
	99	switch (addr) {
	100	case R_AC97_CTRL:
	101	case R_AC97_ADDR:
	102	case R_AC97_DATAOUT:
	103	case R_AC97_DATAIN:
	104	case R_D_CTRL:
	105	case R_D_ADDR:
	106	case R_D_REMAINING:
	107	case R_U_CTRL:
	108	case R_U_ADDR:
	109	case R_U_REMAINING:
	110	r = s->regs[addr];
	111	break;
	112
	113	default:
dd3d6775	114	error_report("milkymist_ac97: read access to unknown register 0x"
25a8bb96 MW	115	TARGET_FMT_plx, addr << 2);
	116	break;
	117	}
	118
	119	trace_milkymist_ac97_memory_read(addr << 2, r);
	120
	121	return r;
	122	}
	123
a8170e5e	124	static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
9496e1c3	125	unsigned size)
25a8bb96 MW	126	{
	127	MilkymistAC97State *s = opaque;
	128
	129	trace_milkymist_ac97_memory_write(addr, value);
	130
	131	addr >>= 2;
	132	switch (addr) {
	133	case R_AC97_CTRL:
	134	/* always raise an IRQ according to the direction */
	135	if (value & AC97_CTRL_RQEN) {
	136	if (value & AC97_CTRL_WRITE) {
	137	trace_milkymist_ac97_pulse_irq_crrequest();
	138	qemu_irq_pulse(s->crrequest_irq);
	139	} else {
	140	trace_milkymist_ac97_pulse_irq_crreply();
	141	qemu_irq_pulse(s->crreply_irq);
	142	}
	143	}
	144
	145	/* RQEN is self clearing */
	146	s->regs[addr] = value & ~AC97_CTRL_RQEN;
	147	break;
	148	case R_D_CTRL:
	149	case R_U_CTRL:
	150	s->regs[addr] = value;
	151	update_voices(s);
	152	break;
	153	case R_AC97_ADDR:
	154	case R_AC97_DATAOUT:
	155	case R_AC97_DATAIN:
	156	case R_D_ADDR:
	157	case R_D_REMAINING:
	158	case R_U_ADDR:
	159	case R_U_REMAINING:
	160	s->regs[addr] = value;
	161	break;
	162
	163	default:
dd3d6775	164	error_report("milkymist_ac97: write access to unknown register 0x"
25a8bb96 MW	165	TARGET_FMT_plx, addr);
	166	break;
	167	}
	168
	169	}
	170
9496e1c3 MW	171	static const MemoryRegionOps ac97_mmio_ops = {
	172	.read = ac97_read,
	173	.write = ac97_write,
	174	.valid = {
	175	.min_access_size = 4,
	176	.max_access_size = 4,
	177	},
	178	.endianness = DEVICE_NATIVE_ENDIAN,
25a8bb96 MW	179	};
	180
	181	static void ac97_in_cb(void *opaque, int avail_b)
	182	{
	183	MilkymistAC97State *s = opaque;
	184	uint8_t buf[4096];
	185	uint32_t remaining = s->regs[R_U_REMAINING];
	186	int temp = audio_MIN(remaining, avail_b);
	187	uint32_t addr = s->regs[R_U_ADDR];
	188	int transferred = 0;
	189
	190	trace_milkymist_ac97_in_cb(avail_b, remaining);
	191
	192	/* prevent from raising an IRQ */
	193	if (temp == 0) {
	194	return;
	195	}
	196
	197	while (temp) {
	198	int acquired, to_copy;
	199
	200	to_copy = audio_MIN(temp, sizeof(buf));
	201	acquired = AUD_read(s->voice_in, buf, to_copy);
	202	if (!acquired) {
	203	break;
	204	}
	205
	206	cpu_physical_memory_write(addr, buf, acquired);
	207
	208	temp -= acquired;
	209	addr += acquired;
	210	transferred += acquired;
	211	}
	212
	213	trace_milkymist_ac97_in_cb_transferred(transferred);
	214
	215	s->regs[R_U_ADDR] = addr;
	216	s->regs[R_U_REMAINING] -= transferred;
	217
	218	if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) {
	219	trace_milkymist_ac97_pulse_irq_dmaw();
	220	qemu_irq_pulse(s->dmaw_irq);
	221	}
	222	}
	223
	224	static void ac97_out_cb(void *opaque, int free_b)
	225	{
	226	MilkymistAC97State *s = opaque;
	227	uint8_t buf[4096];
	228	uint32_t remaining = s->regs[R_D_REMAINING];
	229	int temp = audio_MIN(remaining, free_b);
	230	uint32_t addr = s->regs[R_D_ADDR];
	231	int transferred = 0;
	232
	233	trace_milkymist_ac97_out_cb(free_b, remaining);
	234
	235	/* prevent from raising an IRQ */
	236	if (temp == 0) {
	237	return;
	238	}
	239
	240	while (temp) {
	241	int copied, to_copy;
	242
243	to_copy = audio_MIN(temp, sizeof(buf));
244	cpu_physical_memory_read(addr, buf, to_copy);
245	copied = AUD_write(s->voice_out, buf, to_copy);
246	if (!copied) {
247	break;
248	}
249	temp -= copied;
250	addr += copied;
251	transferred += copied;
252	}
253
254	trace_milkymist_ac97_out_cb_transferred(transferred);
255
256	s->regs[R_D_ADDR] = addr;
257	s->regs[R_D_REMAINING] -= transferred;
258
259	if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) {
260	trace_milkymist_ac97_pulse_irq_dmar();
261	qemu_irq_pulse(s->dmar_irq);
262	}
263	}
264
265	static void milkymist_ac97_reset(DeviceState *d)
266	{
922cc601	267	MilkymistAC97State *s = MILKYMIST_AC97(d);
25a8bb96 MW	268	int i;
	269
	270	for (i = 0; i < R_MAX; i++) {
	271	s->regs[i] = 0;
	272	}
	273
	274	AUD_set_active_in(s->voice_in, 0);
	275	AUD_set_active_out(s->voice_out, 0);
	276	}
	277
	278	static int ac97_post_load(void *opaque, int version_id)
	279	{
	280	MilkymistAC97State *s = opaque;
	281
	282	update_voices(s);
	283
	284	return 0;
	285	}
	286
07b9098d	287	static void milkymist_ac97_init(Object *obj)
25a8bb96	288	{
07b9098d XZ	289	MilkymistAC97State *s = MILKYMIST_AC97(obj);
07b9098d XZ	290	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
25a8bb96	291
25a8bb96 MW	292	sysbus_init_irq(dev, &s->crrequest_irq);
	293	sysbus_init_irq(dev, &s->crreply_irq);
	294	sysbus_init_irq(dev, &s->dmar_irq);
	295	sysbus_init_irq(dev, &s->dmaw_irq);
	296
07b9098d XZ	297	memory_region_init_io(&s->regs_region, obj, &ac97_mmio_ops, s,
	298	"milkymist-ac97", R_MAX * 4);
	299	sysbus_init_mmio(dev, &s->regs_region);
	300	}
	301
	302	static void milkymist_ac97_realize(DeviceState dev, Error *errp)
	303	{
	304	MilkymistAC97State *s = MILKYMIST_AC97(dev);
	305	struct audsettings as;
	306
25a8bb96 MW	307	AUD_register_card("Milkymist AC'97", &s->card);
	308
	309	as.freq = 48000;
	310	as.nchannels = 2;
	311	as.fmt = AUD_FMT_S16;
	312	as.endianness = 1;
	313
	314	s->voice_in = AUD_open_in(&s->card, s->voice_in,
	315	"mm_ac97.in", s, ac97_in_cb, &as);
	316	s->voice_out = AUD_open_out(&s->card, s->voice_out,
	317	"mm_ac97.out", s, ac97_out_cb, &as);
25a8bb96 MW	318	}
	319
	320	static const VMStateDescription vmstate_milkymist_ac97 = {
	321	.name = "milkymist-ac97",
	322	.version_id = 1,
	323	.minimum_version_id = 1,
25a8bb96	324	.post_load = ac97_post_load,
35d08458	325	.fields = (VMStateField[]) {
25a8bb96 MW	326	VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX),
	327	VMSTATE_END_OF_LIST()
	328	}
	329	};
	330
999e12bb AL	331	static void milkymist_ac97_class_init(ObjectClass klass, void data)
999e12bb AL	332	{
39bffca2	333	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	334
07b9098d	335	dc->realize = milkymist_ac97_realize;
39bffca2 AL	336	dc->reset = milkymist_ac97_reset;
39bffca2 AL	337	dc->vmsd = &vmstate_milkymist_ac97;
999e12bb AL	338	}
999e12bb AL	339
8c43a6f0	340	static const TypeInfo milkymist_ac97_info = {
922cc601	341	.name = TYPE_MILKYMIST_AC97,
39bffca2 AL	342	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	343	.instance_size = sizeof(MilkymistAC97State),
07b9098d	344	.instance_init = milkymist_ac97_init,
39bffca2	345	.class_init = milkymist_ac97_class_init,
25a8bb96 MW	346	};
25a8bb96 MW	347
83f7d43a	348	static void milkymist_ac97_register_types(void)
25a8bb96	349	{
39bffca2	350	type_register_static(&milkymist_ac97_info);
25a8bb96 MW	351	}
25a8bb96 MW	352
83f7d43a	353	type_init(milkymist_ac97_register_types)