[qemu.git] / hw / audio / milkymist-ac97.c

/*
 *  QEMU model of the Milkymist System Controller.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.milkymist.org/socdoc/ac97.pdf
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "audio/audio.h"
#include "qemu/error-report.h"

enum {
    R_AC97_CTRL = 0,
    R_AC97_ADDR,
    R_AC97_DATAOUT,
    R_AC97_DATAIN,
    R_D_CTRL,
    R_D_ADDR,
    R_D_REMAINING,
    R_RESERVED,
    R_U_CTRL,
    R_U_ADDR,
    R_U_REMAINING,
    R_MAX
};

enum {
    AC97_CTRL_RQEN  = (1<<0),
    AC97_CTRL_WRITE = (1<<1),
};

enum {
    CTRL_EN = (1<<0),
};

#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
#define MILKYMIST_AC97(obj) \
    OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)

struct MilkymistAC97State {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;

    QEMUSoundCard card;
    SWVoiceIn *voice_in;
    SWVoiceOut *voice_out;

    uint32_t regs[R_MAX];

    qemu_irq crrequest_irq;
    qemu_irq crreply_irq;
    qemu_irq dmar_irq;
    qemu_irq dmaw_irq;
};
typedef struct MilkymistAC97State MilkymistAC97State;

static void update_voices(MilkymistAC97State *s)
{
    if (s->regs[R_D_CTRL] & CTRL_EN) {
        AUD_set_active_out(s->voice_out, 1);
    } else {
        AUD_set_active_out(s->voice_out, 0);
    }

    if (s->regs[R_U_CTRL] & CTRL_EN) {
        AUD_set_active_in(s->voice_in, 1);
    } else {
        AUD_set_active_in(s->voice_in, 0);
    }
}

static uint64_t ac97_read(void *opaque, hwaddr addr,
                          unsigned size)
{
    MilkymistAC97State *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_AC97_CTRL:
    case R_AC97_ADDR:
    case R_AC97_DATAOUT:
    case R_AC97_DATAIN:
    case R_D_CTRL:
    case R_D_ADDR:
    case R_D_REMAINING:
    case R_U_CTRL:
    case R_U_ADDR:
    case R_U_REMAINING:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_ac97: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_ac97_memory_read(addr << 2, r);

    return r;
}

static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    MilkymistAC97State *s = opaque;

    trace_milkymist_ac97_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_AC97_CTRL:
        /* always raise an IRQ according to the direction */
        if (value & AC97_CTRL_RQEN) {
            if (value & AC97_CTRL_WRITE) {
                trace_milkymist_ac97_pulse_irq_crrequest();
                qemu_irq_pulse(s->crrequest_irq);
            } else {
                trace_milkymist_ac97_pulse_irq_crreply();
                qemu_irq_pulse(s->crreply_irq);
            }
        }

        /* RQEN is self clearing */
        s->regs[addr] = value & ~AC97_CTRL_RQEN;
        break;
    case R_D_CTRL:
    case R_U_CTRL:
        s->regs[addr] = value;
        update_voices(s);
        break;
    case R_AC97_ADDR:
    case R_AC97_DATAOUT:
    case R_AC97_DATAIN:
    case R_D_ADDR:
    case R_D_REMAINING:
    case R_U_ADDR:
    case R_U_REMAINING:
        s->regs[addr] = value;
        break;

    default:
        error_report("milkymist_ac97: write access to unknown register 0x"
                TARGET_FMT_plx, addr);
        break;
    }

}

static const MemoryRegionOps ac97_mmio_ops = {
    .read = ac97_read,
    .write = ac97_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void ac97_in_cb(void *opaque, int avail_b)
{
    MilkymistAC97State *s = opaque;
    uint8_t buf[4096];
    uint32_t remaining = s->regs[R_U_REMAINING];
    int temp = audio_MIN(remaining, avail_b);
    uint32_t addr = s->regs[R_U_ADDR];
    int transferred = 0;

    trace_milkymist_ac97_in_cb(avail_b, remaining);

    /* prevent from raising an IRQ */
    if (temp == 0) {
        return;
    }

    while (temp) {
        int acquired, to_copy;

        to_copy = audio_MIN(temp, sizeof(buf));
        acquired = AUD_read(s->voice_in, buf, to_copy);
        if (!acquired) {
            break;
        }

        cpu_physical_memory_write(addr, buf, acquired);

        temp -= acquired;
        addr += acquired;
        transferred += acquired;
    }

    trace_milkymist_ac97_in_cb_transferred(transferred);

    s->regs[R_U_ADDR] = addr;
    s->regs[R_U_REMAINING] -= transferred;

    if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) {
        trace_milkymist_ac97_pulse_irq_dmaw();
        qemu_irq_pulse(s->dmaw_irq);
    }
}

static void ac97_out_cb(void *opaque, int free_b)
{
    MilkymistAC97State *s = opaque;
    uint8_t buf[4096];
    uint32_t remaining = s->regs[R_D_REMAINING];
    int temp = audio_MIN(remaining, free_b);
    uint32_t addr = s->regs[R_D_ADDR];
    int transferred = 0;

    trace_milkymist_ac97_out_cb(free_b, remaining);

    /* prevent from raising an IRQ */
    if (temp == 0) {
        return;
    }

    while (temp) {
        int copied, to_copy;

        to_copy = audio_MIN(temp, sizeof(buf));
        cpu_physical_memory_read(addr, buf, to_copy);
        copied = AUD_write(s->voice_out, buf, to_copy);
        if (!copied) {
            break;
        }
        temp -= copied;
        addr += copied;
        transferred += copied;
    }

    trace_milkymist_ac97_out_cb_transferred(transferred);

    s->regs[R_D_ADDR] = addr;
    s->regs[R_D_REMAINING] -= transferred;

    if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) {
        trace_milkymist_ac97_pulse_irq_dmar();
        qemu_irq_pulse(s->dmar_irq);
    }
}

static void milkymist_ac97_reset(DeviceState *d)
{
    MilkymistAC97State *s = MILKYMIST_AC97(d);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    AUD_set_active_in(s->voice_in, 0);
    AUD_set_active_out(s->voice_out, 0);
}

static int ac97_post_load(void *opaque, int version_id)
{
    MilkymistAC97State *s = opaque;

    update_voices(s);

    return 0;
}

static int milkymist_ac97_init(SysBusDevice *dev)
{
    MilkymistAC97State *s = MILKYMIST_AC97(dev);

    struct audsettings as;
    sysbus_init_irq(dev, &s->crrequest_irq);
    sysbus_init_irq(dev, &s->crreply_irq);
    sysbus_init_irq(dev, &s->dmar_irq);
    sysbus_init_irq(dev, &s->dmaw_irq);

    AUD_register_card("Milkymist AC'97", &s->card);

    as.freq = 48000;
    as.nchannels = 2;
    as.fmt = AUD_FMT_S16;
    as.endianness = 1;

    s->voice_in = AUD_open_in(&s->card, s->voice_in,
            "mm_ac97.in", s, ac97_in_cb, &as);
    s->voice_out = AUD_open_out(&s->card, s->voice_out,
            "mm_ac97.out", s, ac97_out_cb, &as);

    memory_region_init_io(&s->regs_region, OBJECT(s), &ac97_mmio_ops, s,
            "milkymist-ac97", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    return 0;
}

static const VMStateDescription vmstate_milkymist_ac97 = {
    .name = "milkymist-ac97",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = ac97_post_load,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_ac97_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = milkymist_ac97_init;
    dc->reset = milkymist_ac97_reset;
    dc->vmsd = &vmstate_milkymist_ac97;
}

static const TypeInfo milkymist_ac97_info = {
    .name          = TYPE_MILKYMIST_AC97,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistAC97State),
    .class_init    = milkymist_ac97_class_init,
};

static void milkymist_ac97_register_types(void)
{
    type_register_static(&milkymist_ac97_info);
}

type_init(milkymist_ac97_register_types)
Commit	Line	Data
25a8bb96 MW	1	/*
	2	* QEMU model of the Milkymist System Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
	21	* http://www.milkymist.org/socdoc/ac97.pdf
	22	*/
	23
83c9f4ca PB	24	#include "hw/hw.h"
83c9f4ca PB	25	#include "hw/sysbus.h"
25a8bb96 MW	26	#include "trace.h"
25a8bb96 MW	27	#include "audio/audio.h"
1de7afc9	28	#include "qemu/error-report.h"
25a8bb96 MW	29
	30	enum {
	31	R_AC97_CTRL = 0,
	32	R_AC97_ADDR,
	33	R_AC97_DATAOUT,
	34	R_AC97_DATAIN,
	35	R_D_CTRL,
	36	R_D_ADDR,
	37	R_D_REMAINING,
	38	R_RESERVED,
	39	R_U_CTRL,
	40	R_U_ADDR,
	41	R_U_REMAINING,
	42	R_MAX
	43	};
	44
	45	enum {
	46	AC97_CTRL_RQEN = (1<<0),
	47	AC97_CTRL_WRITE = (1<<1),
	48	};
	49
	50	enum {
	51	CTRL_EN = (1<<0),
	52	};
	53
922cc601 AF	54	#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
	55	#define MILKYMIST_AC97(obj) \
	56	OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)
	57
25a8bb96	58	struct MilkymistAC97State {
922cc601 AF	59	SysBusDevice parent_obj;
922cc601 AF	60
9496e1c3	61	MemoryRegion regs_region;
25a8bb96 MW	62
	63	QEMUSoundCard card;
	64	SWVoiceIn *voice_in;
	65	SWVoiceOut *voice_out;
	66
	67	uint32_t regs[R_MAX];
	68
	69	qemu_irq crrequest_irq;
	70	qemu_irq crreply_irq;
	71	qemu_irq dmar_irq;
	72	qemu_irq dmaw_irq;
	73	};
	74	typedef struct MilkymistAC97State MilkymistAC97State;
	75
	76	static void update_voices(MilkymistAC97State *s)
	77	{
	78	if (s->regs[R_D_CTRL] & CTRL_EN) {
	79	AUD_set_active_out(s->voice_out, 1);
	80	} else {
	81	AUD_set_active_out(s->voice_out, 0);
	82	}
	83
	84	if (s->regs[R_U_CTRL] & CTRL_EN) {
	85	AUD_set_active_in(s->voice_in, 1);
	86	} else {
	87	AUD_set_active_in(s->voice_in, 0);
	88	}
	89	}
	90
a8170e5e	91	static uint64_t ac97_read(void *opaque, hwaddr addr,
9496e1c3	92	unsigned size)
25a8bb96 MW	93	{
	94	MilkymistAC97State *s = opaque;
	95	uint32_t r = 0;
	96
	97	addr >>= 2;
	98	switch (addr) {
	99	case R_AC97_CTRL:
	100	case R_AC97_ADDR:
	101	case R_AC97_DATAOUT:
	102	case R_AC97_DATAIN:
	103	case R_D_CTRL:
	104	case R_D_ADDR:
	105	case R_D_REMAINING:
	106	case R_U_CTRL:
	107	case R_U_ADDR:
	108	case R_U_REMAINING:
	109	r = s->regs[addr];
	110	break;
	111
	112	default:
dd3d6775	113	error_report("milkymist_ac97: read access to unknown register 0x"
25a8bb96 MW	114	TARGET_FMT_plx, addr << 2);
	115	break;
	116	}
	117
	118	trace_milkymist_ac97_memory_read(addr << 2, r);
	119
	120	return r;
	121	}
	122
a8170e5e	123	static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
9496e1c3	124	unsigned size)
25a8bb96 MW	125	{
	126	MilkymistAC97State *s = opaque;
	127
	128	trace_milkymist_ac97_memory_write(addr, value);
	129
	130	addr >>= 2;
	131	switch (addr) {
	132	case R_AC97_CTRL:
	133	/* always raise an IRQ according to the direction */
	134	if (value & AC97_CTRL_RQEN) {
	135	if (value & AC97_CTRL_WRITE) {
	136	trace_milkymist_ac97_pulse_irq_crrequest();
	137	qemu_irq_pulse(s->crrequest_irq);
	138	} else {
	139	trace_milkymist_ac97_pulse_irq_crreply();
	140	qemu_irq_pulse(s->crreply_irq);
	141	}
	142	}
	143
	144	/* RQEN is self clearing */
	145	s->regs[addr] = value & ~AC97_CTRL_RQEN;
	146	break;
	147	case R_D_CTRL:
	148	case R_U_CTRL:
	149	s->regs[addr] = value;
	150	update_voices(s);
	151	break;
	152	case R_AC97_ADDR:
	153	case R_AC97_DATAOUT:
	154	case R_AC97_DATAIN:
	155	case R_D_ADDR:
	156	case R_D_REMAINING:
	157	case R_U_ADDR:
	158	case R_U_REMAINING:
	159	s->regs[addr] = value;
	160	break;
	161
	162	default:
dd3d6775	163	error_report("milkymist_ac97: write access to unknown register 0x"
25a8bb96 MW	164	TARGET_FMT_plx, addr);
	165	break;
	166	}
	167
	168	}
	169
9496e1c3 MW	170	static const MemoryRegionOps ac97_mmio_ops = {
	171	.read = ac97_read,
	172	.write = ac97_write,
	173	.valid = {
	174	.min_access_size = 4,
	175	.max_access_size = 4,
	176	},
	177	.endianness = DEVICE_NATIVE_ENDIAN,
25a8bb96 MW	178	};
	179
	180	static void ac97_in_cb(void *opaque, int avail_b)
	181	{
	182	MilkymistAC97State *s = opaque;
	183	uint8_t buf[4096];
	184	uint32_t remaining = s->regs[R_U_REMAINING];
	185	int temp = audio_MIN(remaining, avail_b);
	186	uint32_t addr = s->regs[R_U_ADDR];
	187	int transferred = 0;
	188
	189	trace_milkymist_ac97_in_cb(avail_b, remaining);
	190
	191	/* prevent from raising an IRQ */
	192	if (temp == 0) {
	193	return;
	194	}
	195
	196	while (temp) {
	197	int acquired, to_copy;
	198
	199	to_copy = audio_MIN(temp, sizeof(buf));
	200	acquired = AUD_read(s->voice_in, buf, to_copy);
	201	if (!acquired) {
	202	break;
	203	}
	204
	205	cpu_physical_memory_write(addr, buf, acquired);
	206
	207	temp -= acquired;
	208	addr += acquired;
	209	transferred += acquired;
	210	}
	211
	212	trace_milkymist_ac97_in_cb_transferred(transferred);
	213
	214	s->regs[R_U_ADDR] = addr;
	215	s->regs[R_U_REMAINING] -= transferred;
	216
	217	if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) {
	218	trace_milkymist_ac97_pulse_irq_dmaw();
	219	qemu_irq_pulse(s->dmaw_irq);
	220	}
	221	}
	222
	223	static void ac97_out_cb(void *opaque, int free_b)
	224	{
	225	MilkymistAC97State *s = opaque;
	226	uint8_t buf[4096];
	227	uint32_t remaining = s->regs[R_D_REMAINING];
	228	int temp = audio_MIN(remaining, free_b);
	229	uint32_t addr = s->regs[R_D_ADDR];
	230	int transferred = 0;
	231
	232	trace_milkymist_ac97_out_cb(free_b, remaining);
	233
	234	/* prevent from raising an IRQ */
	235	if (temp == 0) {
	236	return;
	237	}
	238
	239	while (temp) {
	240	int copied, to_copy;
	241
242	to_copy = audio_MIN(temp, sizeof(buf));
243	cpu_physical_memory_read(addr, buf, to_copy);
244	copied = AUD_write(s->voice_out, buf, to_copy);
245	if (!copied) {
246	break;
247	}
248	temp -= copied;
249	addr += copied;
250	transferred += copied;
251	}
252
253	trace_milkymist_ac97_out_cb_transferred(transferred);
254
255	s->regs[R_D_ADDR] = addr;
256	s->regs[R_D_REMAINING] -= transferred;
257
258	if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) {
259	trace_milkymist_ac97_pulse_irq_dmar();
260	qemu_irq_pulse(s->dmar_irq);
261	}
262	}
263
264	static void milkymist_ac97_reset(DeviceState *d)
265	{
922cc601	266	MilkymistAC97State *s = MILKYMIST_AC97(d);
25a8bb96 MW	267	int i;
	268
	269	for (i = 0; i < R_MAX; i++) {
	270	s->regs[i] = 0;
	271	}
	272
	273	AUD_set_active_in(s->voice_in, 0);
	274	AUD_set_active_out(s->voice_out, 0);
	275	}
	276
	277	static int ac97_post_load(void *opaque, int version_id)
	278	{
	279	MilkymistAC97State *s = opaque;
	280
	281	update_voices(s);
	282
	283	return 0;
	284	}
	285
	286	static int milkymist_ac97_init(SysBusDevice *dev)
	287	{
922cc601	288	MilkymistAC97State *s = MILKYMIST_AC97(dev);
25a8bb96 MW	289
	290	struct audsettings as;
	291	sysbus_init_irq(dev, &s->crrequest_irq);
	292	sysbus_init_irq(dev, &s->crreply_irq);
	293	sysbus_init_irq(dev, &s->dmar_irq);
	294	sysbus_init_irq(dev, &s->dmaw_irq);
	295
	296	AUD_register_card("Milkymist AC'97", &s->card);
	297
	298	as.freq = 48000;
	299	as.nchannels = 2;
	300	as.fmt = AUD_FMT_S16;
	301	as.endianness = 1;
	302
	303	s->voice_in = AUD_open_in(&s->card, s->voice_in,
	304	"mm_ac97.in", s, ac97_in_cb, &as);
	305	s->voice_out = AUD_open_out(&s->card, s->voice_out,
	306	"mm_ac97.out", s, ac97_out_cb, &as);
	307
64bde0f3	308	memory_region_init_io(&s->regs_region, OBJECT(s), &ac97_mmio_ops, s,
9496e1c3	309	"milkymist-ac97", R_MAX * 4);
750ecd44	310	sysbus_init_mmio(dev, &s->regs_region);
25a8bb96 MW	311
	312	return 0;
	313	}
	314
	315	static const VMStateDescription vmstate_milkymist_ac97 = {
	316	.name = "milkymist-ac97",
	317	.version_id = 1,
	318	.minimum_version_id = 1,
	319	.minimum_version_id_old = 1,
	320	.post_load = ac97_post_load,
	321	.fields = (VMStateField[]) {
	322	VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX),
	323	VMSTATE_END_OF_LIST()
	324	}
	325	};
	326
999e12bb AL	327	static void milkymist_ac97_class_init(ObjectClass klass, void data)
999e12bb AL	328	{
39bffca2	329	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	330	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	331
	332	k->init = milkymist_ac97_init;
39bffca2 AL	333	dc->reset = milkymist_ac97_reset;
39bffca2 AL	334	dc->vmsd = &vmstate_milkymist_ac97;
999e12bb AL	335	}
999e12bb AL	336
8c43a6f0	337	static const TypeInfo milkymist_ac97_info = {
922cc601	338	.name = TYPE_MILKYMIST_AC97,
39bffca2 AL	339	.parent = TYPE_SYS_BUS_DEVICE,
	340	.instance_size = sizeof(MilkymistAC97State),
	341	.class_init = milkymist_ac97_class_init,
25a8bb96 MW	342	};
25a8bb96 MW	343
83f7d43a	344	static void milkymist_ac97_register_types(void)
25a8bb96	345	{
39bffca2	346	type_register_static(&milkymist_ac97_info);
25a8bb96 MW	347	}
25a8bb96 MW	348
83f7d43a	349	type_init(milkymist_ac97_register_types)