[qemu.git] / hw / net / xilinx_ethlite.c

/*
 * QEMU model of the Xilinx Ethernet Lite MAC.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "cpu.h" /* FIXME should not use tswap* */
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "net/net.h"

#define D(x)
#define R_TX_BUF0     0
#define R_TX_LEN0     (0x07f4 / 4)
#define R_TX_GIE0     (0x07f8 / 4)
#define R_TX_CTRL0    (0x07fc / 4)
#define R_TX_BUF1     (0x0800 / 4)
#define R_TX_LEN1     (0x0ff4 / 4)
#define R_TX_CTRL1    (0x0ffc / 4)

#define R_RX_BUF0     (0x1000 / 4)
#define R_RX_CTRL0    (0x17fc / 4)
#define R_RX_BUF1     (0x1800 / 4)
#define R_RX_CTRL1    (0x1ffc / 4)
#define R_MAX         (0x2000 / 4)

#define GIE_GIE    0x80000000

#define CTRL_I     0x8
#define CTRL_P     0x2
#define CTRL_S     0x1

#define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
#define XILINX_ETHLITE(obj) \
    OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE)

struct xlx_ethlite
{
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;

    uint32_t c_tx_pingpong;
    uint32_t c_rx_pingpong;
    unsigned int txbuf;
    unsigned int rxbuf;

    uint32_t regs[R_MAX];
};

static inline void eth_pulse_irq(struct xlx_ethlite *s)
{
    /* Only the first gie reg is active.  */
    if (s->regs[R_TX_GIE0] & GIE_GIE) {
        qemu_irq_pulse(s->irq);
    }
}

static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    uint32_t r = 0;

    addr >>= 2;

    switch (addr)
    {
        case R_TX_GIE0:
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_CTRL1:
        case R_TX_CTRL0:
        case R_RX_CTRL1:
        case R_RX_CTRL0:
            r = s->regs[addr];
            D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
            break;

        default:
            r = tswap32(s->regs[addr]);
            break;
    }
    return r;
}

static void
eth_write(void *opaque, hwaddr addr,
          uint64_t val64, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    unsigned int base = 0;
    uint32_t value = val64;

    addr >>= 2;
    switch (addr) 
    {
        case R_TX_CTRL0:
        case R_TX_CTRL1:
            if (addr == R_TX_CTRL1)
                base = 0x800 / 4;

            D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
                       __func__, addr * 4, value));
            if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
                qemu_send_packet(qemu_get_queue(s->nic),
                                 (void *) &s->regs[base],
                                 s->regs[base + R_TX_LEN0]);
                D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
                memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            }

            /* We are fast and get ready pretty much immediately so
               we actually never flip the S nor P bits to one.  */
            s->regs[addr] = value & ~(CTRL_P | CTRL_S);
            break;

        /* Keep these native.  */
        case R_RX_CTRL0:
        case R_RX_CTRL1:
            if (!(value & CTRL_S)) {
                qemu_flush_queued_packets(qemu_get_queue(s->nic));
            }
            /* fall through */
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_GIE0:
            D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
                       __func__, addr * 4, value));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = tswap32(value);
            break;
    }
}

static const MemoryRegionOps eth_ops = {
    .read = eth_read,
    .write = eth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static int eth_can_rx(NetClientState *nc)
{
    struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
}

static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
{
    struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    /* DA filter.  */
    if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
        return size;

    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
        D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
        return -1;
    }

    D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
    if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
        D(qemu_log("ethlite packet is too big, size=%x\n", size));
        return -1;
    }
    memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);

    s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
    if (s->regs[R_RX_CTRL0] & CTRL_I) {
        eth_pulse_irq(s);
    }

    /* If c_rx_pingpong was set flip buffers.  */
    s->rxbuf ^= s->c_rx_pingpong;
    return size;
}

static void xilinx_ethlite_reset(DeviceState *dev)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(dev);

    s->rxbuf = 0;
}

static NetClientInfo net_xilinx_ethlite_info = {
    .type = NET_CLIENT_DRIVER_NIC,
    .size = sizeof(NICState),
    .can_receive = eth_can_rx,
    .receive = eth_rx,
};

static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(dev);

    qemu_macaddr_default_if_unset(&s->conf.macaddr);
    s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->id, s);
    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
}

static void xilinx_ethlite_init(Object *obj)
{
    struct xlx_ethlite *s = XILINX_ETHLITE(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &eth_ops, s,
                          "xlnx.xps-ethernetlite", R_MAX * 4);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

static Property xilinx_ethlite_properties[] = {
    DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
    DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
    DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = xilinx_ethlite_realize;
    dc->reset = xilinx_ethlite_reset;
    dc->props = xilinx_ethlite_properties;
}

static const TypeInfo xilinx_ethlite_info = {
    .name          = TYPE_XILINX_ETHLITE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct xlx_ethlite),
    .instance_init = xilinx_ethlite_init,
    .class_init    = xilinx_ethlite_class_init,
};

static void xilinx_ethlite_register_types(void)
{
    type_register_static(&xilinx_ethlite_info);
}

type_init(xilinx_ethlite_register_types)
Commit	Line	Data
b43848a1 EI	1	/*
	2	* QEMU model of the Xilinx Ethernet Lite MAC.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
e8d40465	25	#include "qemu/osdep.h"
0b8fa32f	26	#include "qemu/module.h"
4771d756	27	#include "cpu.h" /* FIXME should not use tswap* */
83c9f4ca	28	#include "hw/sysbus.h"
64552b6b	29	#include "hw/irq.h"
a27bd6c7	30	#include "hw/qdev-properties.h"
1422e32d	31	#include "net/net.h"
b43848a1 EI	32
	33	#define D(x)
	34	#define R_TX_BUF0 0
	35	#define R_TX_LEN0 (0x07f4 / 4)
	36	#define R_TX_GIE0 (0x07f8 / 4)
	37	#define R_TX_CTRL0 (0x07fc / 4)
	38	#define R_TX_BUF1 (0x0800 / 4)
	39	#define R_TX_LEN1 (0x0ff4 / 4)
	40	#define R_TX_CTRL1 (0x0ffc / 4)
	41
	42	#define R_RX_BUF0 (0x1000 / 4)
	43	#define R_RX_CTRL0 (0x17fc / 4)
	44	#define R_RX_BUF1 (0x1800 / 4)
	45	#define R_RX_CTRL1 (0x1ffc / 4)
	46	#define R_MAX (0x2000 / 4)
	47
	48	#define GIE_GIE 0x80000000
	49
	50	#define CTRL_I 0x8
	51	#define CTRL_P 0x2
	52	#define CTRL_S 0x1
	53
91a28042 AF	54	#define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"
	55	#define XILINX_ETHLITE(obj) \
	56	OBJECT_CHECK(struct xlx_ethlite, (obj), TYPE_XILINX_ETHLITE)
	57
b43848a1 EI	58	struct xlx_ethlite
b43848a1 EI	59	{
91a28042 AF	60	SysBusDevice parent_obj;
91a28042 AF	61
010f3f5f	62	MemoryRegion mmio;
b43848a1	63	qemu_irq irq;
d7539ab4	64	NICState *nic;
17d1ae3c	65	NICConf conf;
b43848a1	66
ee6847d1 GH	67	uint32_t c_tx_pingpong;
ee6847d1 GH	68	uint32_t c_rx_pingpong;
b43848a1 EI	69	unsigned int txbuf;
	70	unsigned int rxbuf;
	71
b43848a1 EI	72	uint32_t regs[R_MAX];
	73	};
	74
	75	static inline void eth_pulse_irq(struct xlx_ethlite *s)
	76	{
	77	/* Only the first gie reg is active. */
	78	if (s->regs[R_TX_GIE0] & GIE_GIE) {
	79	qemu_irq_pulse(s->irq);
	80	}
	81	}
	82
010f3f5f	83	static uint64_t
a8170e5e	84	eth_read(void *opaque, hwaddr addr, unsigned int size)
b43848a1 EI	85	{
	86	struct xlx_ethlite *s = opaque;
	87	uint32_t r = 0;
	88
	89	addr >>= 2;
	90
	91	switch (addr)
	92	{
	93	case R_TX_GIE0:
	94	case R_TX_LEN0:
	95	case R_TX_LEN1:
	96	case R_TX_CTRL1:
	97	case R_TX_CTRL0:
	98	case R_RX_CTRL1:
	99	case R_RX_CTRL0:
	100	r = s->regs[addr];
6034fe7b	101	D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
b43848a1 EI	102	break;
b43848a1 EI	103
b43848a1	104	default:
d48751ed	105	r = tswap32(s->regs[addr]);
b43848a1 EI	106	break;
	107	}
	108	return r;
	109	}
	110
	111	static void
a8170e5e	112	eth_write(void *opaque, hwaddr addr,
010f3f5f	113	uint64_t val64, unsigned int size)
b43848a1 EI	114	{
	115	struct xlx_ethlite *s = opaque;
	116	unsigned int base = 0;
010f3f5f	117	uint32_t value = val64;
b43848a1 EI	118
	119	addr >>= 2;
	120	switch (addr)
	121	{
	122	case R_TX_CTRL0:
	123	case R_TX_CTRL1:
	124	if (addr == R_TX_CTRL1)
	125	base = 0x800 / 4;
	126
6034fe7b EI	127	D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
6034fe7b EI	128	__func__, addr * 4, value));
b43848a1	129	if ((value & (CTRL_P \| CTRL_S)) == CTRL_S) {
b356f76d	130	qemu_send_packet(qemu_get_queue(s->nic),
b43848a1 EI	131	(void *) &s->regs[base],
	132	s->regs[base + R_TX_LEN0]);
	133	D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
	134	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	135	eth_pulse_irq(s);
	136	} else if ((value & (CTRL_P \| CTRL_S)) == (CTRL_P \| CTRL_S)) {
17d1ae3c	137	memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
b43848a1 EI	138	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	139	eth_pulse_irq(s);
	140	}
	141
	142	/* We are fast and get ready pretty much immediately so
	143	we actually never flip the S nor P bits to one. */
	144	s->regs[addr] = value & ~(CTRL_P \| CTRL_S);
	145	break;
	146
	147	/* Keep these native. */
2f991adb PC	148	case R_RX_CTRL0:
	149	case R_RX_CTRL1:
	150	if (!(value & CTRL_S)) {
b356f76d	151	qemu_flush_queued_packets(qemu_get_queue(s->nic));
2f991adb	152	}
31da45ce	153	/* fall through */
b43848a1 EI	154	case R_TX_LEN0:
	155	case R_TX_LEN1:
	156	case R_TX_GIE0:
6034fe7b EI	157	D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
6034fe7b EI	158	__func__, addr * 4, value));
b43848a1 EI	159	s->regs[addr] = value;
	160	break;
	161
b43848a1	162	default:
d48751ed	163	s->regs[addr] = tswap32(value);
b43848a1 EI	164	break;
	165	}
	166	}
	167
010f3f5f EI	168	static const MemoryRegionOps eth_ops = {
	169	.read = eth_read,
	170	.write = eth_write,
	171	.endianness = DEVICE_NATIVE_ENDIAN,
	172	.valid = {
	173	.min_access_size = 4,
	174	.max_access_size = 4
	175	}
b43848a1 EI	176	};
b43848a1 EI	177
4e68f7a0	178	static int eth_can_rx(NetClientState *nc)
b43848a1	179	{
cc1f0f45	180	struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
808fb9f2 PC	181	unsigned int rxbase = s->rxbuf * (0x800 / 4);
	182
	183	return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
b43848a1 EI	184	}
b43848a1 EI	185
4e68f7a0	186	static ssize_t eth_rx(NetClientState nc, const uint8_t buf, size_t size)
b43848a1	187	{
cc1f0f45	188	struct xlx_ethlite *s = qemu_get_nic_opaque(nc);
b43848a1	189	unsigned int rxbase = s->rxbuf * (0x800 / 4);
b43848a1 EI	190
b43848a1 EI	191	/* DA filter. */
17d1ae3c	192	if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
df12c1f5	193	return size;
b43848a1 EI	194
	195	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
	196	D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
df12c1f5	197	return -1;
b43848a1 EI	198	}
b43848a1 EI	199
6034fe7b	200	D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase));
a0d1cbda	201	if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
	202	D(qemu_log("ethlite packet is too big, size=%x\n", size));
	203	return -1;
	204	}
b43848a1 EI	205	memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
b43848a1 EI	206
b43848a1	207	s->regs[rxbase + R_RX_CTRL0] \|= CTRL_S;
40e76f73	208	if (s->regs[R_RX_CTRL0] & CTRL_I) {
b43848a1	209	eth_pulse_irq(s);
40e76f73	210	}
b43848a1 EI	211
	212	/* If c_rx_pingpong was set flip buffers. */
	213	s->rxbuf ^= s->c_rx_pingpong;
df12c1f5	214	return size;
b43848a1 EI	215	}
b43848a1 EI	216
8c6d9672 PC	217	static void xilinx_ethlite_reset(DeviceState *dev)
	218	{
	219	struct xlx_ethlite *s = XILINX_ETHLITE(dev);
	220
	221	s->rxbuf = 0;
	222	}
	223
d7539ab4	224	static NetClientInfo net_xilinx_ethlite_info = {
f394b2e2	225	.type = NET_CLIENT_DRIVER_NIC,
d7539ab4 MM	226	.size = sizeof(NICState),
	227	.can_receive = eth_can_rx,
	228	.receive = eth_rx,
d7539ab4 MM	229	};
d7539ab4 MM	230
e8198f6e	231	static void xilinx_ethlite_realize(DeviceState dev, Error *errp)
b43848a1	232	{
91a28042	233	struct xlx_ethlite *s = XILINX_ETHLITE(dev);
b43848a1	234
17d1ae3c	235	qemu_macaddr_default_if_unset(&s->conf.macaddr);
d7539ab4	236	s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
91a28042	237	object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d	238	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
e8198f6e PC	239	}
	240
	241	static void xilinx_ethlite_init(Object *obj)
	242	{
	243	struct xlx_ethlite *s = XILINX_ETHLITE(obj);
	244
	245	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
	246
	247	memory_region_init_io(&s->mmio, obj, &eth_ops, s,
	248	"xlnx.xps-ethernetlite", R_MAX * 4);
	249	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
b43848a1 EI	250	}
b43848a1 EI	251
999e12bb	252	static Property xilinx_ethlite_properties[] = {
b2d85c34 PC	253	DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
b2d85c34 PC	254	DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
999e12bb AL	255	DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
	256	DEFINE_PROP_END_OF_LIST(),
	257	};
	258
	259	static void xilinx_ethlite_class_init(ObjectClass klass, void data)
	260	{
39bffca2	261	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	262
e8198f6e	263	dc->realize = xilinx_ethlite_realize;
8c6d9672	264	dc->reset = xilinx_ethlite_reset;
39bffca2	265	dc->props = xilinx_ethlite_properties;
999e12bb AL	266	}
999e12bb AL	267
8c43a6f0	268	static const TypeInfo xilinx_ethlite_info = {
91a28042	269	.name = TYPE_XILINX_ETHLITE,
39bffca2 AL	270	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	271	.instance_size = sizeof(struct xlx_ethlite),
e8198f6e	272	.instance_init = xilinx_ethlite_init,
39bffca2	273	.class_init = xilinx_ethlite_class_init,
ee6847d1 GH	274	};
ee6847d1 GH	275
83f7d43a	276	static void xilinx_ethlite_register_types(void)
b43848a1	277	{
39bffca2	278	type_register_static(&xilinx_ethlite_info);
b43848a1 EI	279	}
b43848a1 EI	280
83f7d43a	281	type_init(xilinx_ethlite_register_types)