[qemu.git] / hw / xilinx_ethlite.c

/*
 * QEMU model of the Xilinx Ethernet Lite MAC.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "hw.h"
#include "net/net.h"

#define D(x)
#define R_TX_BUF0     0
#define R_TX_LEN0     (0x07f4 / 4)
#define R_TX_GIE0     (0x07f8 / 4)
#define R_TX_CTRL0    (0x07fc / 4)
#define R_TX_BUF1     (0x0800 / 4)
#define R_TX_LEN1     (0x0ff4 / 4)
#define R_TX_CTRL1    (0x0ffc / 4)

#define R_RX_BUF0     (0x1000 / 4)
#define R_RX_CTRL0    (0x17fc / 4)
#define R_RX_BUF1     (0x1800 / 4)
#define R_RX_CTRL1    (0x1ffc / 4)
#define R_MAX         (0x2000 / 4)

#define GIE_GIE    0x80000000

#define CTRL_I     0x8
#define CTRL_P     0x2
#define CTRL_S     0x1

struct xlx_ethlite
{
    SysBusDevice busdev;
    MemoryRegion mmio;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;

    uint32_t c_tx_pingpong;
    uint32_t c_rx_pingpong;
    unsigned int txbuf;
    unsigned int rxbuf;

    uint32_t regs[R_MAX];
};

static inline void eth_pulse_irq(struct xlx_ethlite *s)
{
    /* Only the first gie reg is active.  */
    if (s->regs[R_TX_GIE0] & GIE_GIE) {
        qemu_irq_pulse(s->irq);
    }
}

static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    uint32_t r = 0;

    addr >>= 2;

    switch (addr)
    {
        case R_TX_GIE0:
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_CTRL1:
        case R_TX_CTRL0:
        case R_RX_CTRL1:
        case R_RX_CTRL0:
            r = s->regs[addr];
            D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
            break;

        default:
            r = tswap32(s->regs[addr]);
            break;
    }
    return r;
}

static void
eth_write(void *opaque, hwaddr addr,
          uint64_t val64, unsigned int size)
{
    struct xlx_ethlite *s = opaque;
    unsigned int base = 0;
    uint32_t value = val64;

    addr >>= 2;
    switch (addr) 
    {
        case R_TX_CTRL0:
        case R_TX_CTRL1:
            if (addr == R_TX_CTRL1)
                base = 0x800 / 4;

            D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
            if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
                qemu_send_packet(&s->nic->nc,
                                 (void *) &s->regs[base],
                                 s->regs[base + R_TX_LEN0]);
                D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
                memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            }

            /* We are fast and get ready pretty much immediately so
               we actually never flip the S nor P bits to one.  */
            s->regs[addr] = value & ~(CTRL_P | CTRL_S);
            break;

        /* Keep these native.  */
        case R_RX_CTRL0:
        case R_RX_CTRL1:
            if (!(value & CTRL_S)) {
                qemu_flush_queued_packets(&s->nic->nc);
            }
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_GIE0:
            D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = tswap32(value);
            break;
    }
}

static const MemoryRegionOps eth_ops = {
    .read = eth_read,
    .write = eth_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static int eth_can_rx(NetClientState *nc)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
}

static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
    unsigned int rxbase = s->rxbuf * (0x800 / 4);

    /* DA filter.  */
    if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
        return size;

    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
        D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
        return -1;
    }

    D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
    memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);

    s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
        eth_pulse_irq(s);

    /* If c_rx_pingpong was set flip buffers.  */
    s->rxbuf ^= s->c_rx_pingpong;
    return size;
}

static void eth_cleanup(NetClientState *nc)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;

    s->nic = NULL;
}

static NetClientInfo net_xilinx_ethlite_info = {
    .type = NET_CLIENT_OPTIONS_KIND_NIC,
    .size = sizeof(NICState),
    .can_receive = eth_can_rx,
    .receive = eth_rx,
    .cleanup = eth_cleanup,
};

static int xilinx_ethlite_init(SysBusDevice *dev)
{
    struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);

    sysbus_init_irq(dev, &s->irq);
    s->rxbuf = 0;

    memory_region_init_io(&s->mmio, &eth_ops, s, "xlnx.xps-ethernetlite",
                                                                    R_MAX * 4);
    sysbus_init_mmio(dev, &s->mmio);

    qemu_macaddr_default_if_unset(&s->conf.macaddr);
    s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
    return 0;
}

static Property xilinx_ethlite_properties[] = {
    DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
    DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
    DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void xilinx_ethlite_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = xilinx_ethlite_init;
    dc->props = xilinx_ethlite_properties;
}

static const TypeInfo xilinx_ethlite_info = {
    .name          = "xlnx.xps-ethernetlite",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct xlx_ethlite),
    .class_init    = xilinx_ethlite_class_init,
};

static void xilinx_ethlite_register_types(void)
{
    type_register_static(&xilinx_ethlite_info);
}

type_init(xilinx_ethlite_register_types)
Commit	Line	Data
b43848a1 EI	1	/*
	2	* QEMU model of the Xilinx Ethernet Lite MAC.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
	26	#include "hw.h"
1422e32d	27	#include "net/net.h"
b43848a1 EI	28
	29	#define D(x)
	30	#define R_TX_BUF0 0
	31	#define R_TX_LEN0 (0x07f4 / 4)
	32	#define R_TX_GIE0 (0x07f8 / 4)
	33	#define R_TX_CTRL0 (0x07fc / 4)
	34	#define R_TX_BUF1 (0x0800 / 4)
	35	#define R_TX_LEN1 (0x0ff4 / 4)
	36	#define R_TX_CTRL1 (0x0ffc / 4)
	37
	38	#define R_RX_BUF0 (0x1000 / 4)
	39	#define R_RX_CTRL0 (0x17fc / 4)
	40	#define R_RX_BUF1 (0x1800 / 4)
	41	#define R_RX_CTRL1 (0x1ffc / 4)
	42	#define R_MAX (0x2000 / 4)
	43
	44	#define GIE_GIE 0x80000000
	45
	46	#define CTRL_I 0x8
	47	#define CTRL_P 0x2
	48	#define CTRL_S 0x1
	49
	50	struct xlx_ethlite
	51	{
	52	SysBusDevice busdev;
010f3f5f	53	MemoryRegion mmio;
b43848a1	54	qemu_irq irq;
d7539ab4	55	NICState *nic;
17d1ae3c	56	NICConf conf;
b43848a1	57
ee6847d1 GH	58	uint32_t c_tx_pingpong;
ee6847d1 GH	59	uint32_t c_rx_pingpong;
b43848a1 EI	60	unsigned int txbuf;
	61	unsigned int rxbuf;
	62
b43848a1 EI	63	uint32_t regs[R_MAX];
	64	};
	65
	66	static inline void eth_pulse_irq(struct xlx_ethlite *s)
	67	{
	68	/* Only the first gie reg is active. */
	69	if (s->regs[R_TX_GIE0] & GIE_GIE) {
	70	qemu_irq_pulse(s->irq);
	71	}
	72	}
	73
010f3f5f	74	static uint64_t
a8170e5e	75	eth_read(void *opaque, hwaddr addr, unsigned int size)
b43848a1 EI	76	{
	77	struct xlx_ethlite *s = opaque;
	78	uint32_t r = 0;
	79
	80	addr >>= 2;
	81
	82	switch (addr)
	83	{
	84	case R_TX_GIE0:
	85	case R_TX_LEN0:
	86	case R_TX_LEN1:
	87	case R_TX_CTRL1:
	88	case R_TX_CTRL0:
	89	case R_RX_CTRL1:
	90	case R_RX_CTRL0:
	91	r = s->regs[addr];
	92	D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
	93	break;
	94
b43848a1	95	default:
d48751ed	96	r = tswap32(s->regs[addr]);
b43848a1 EI	97	break;
	98	}
	99	return r;
	100	}
	101
	102	static void
a8170e5e	103	eth_write(void *opaque, hwaddr addr,
010f3f5f	104	uint64_t val64, unsigned int size)
b43848a1 EI	105	{
	106	struct xlx_ethlite *s = opaque;
	107	unsigned int base = 0;
010f3f5f	108	uint32_t value = val64;
b43848a1 EI	109
	110	addr >>= 2;
	111	switch (addr)
	112	{
	113	case R_TX_CTRL0:
	114	case R_TX_CTRL1:
	115	if (addr == R_TX_CTRL1)
	116	base = 0x800 / 4;
	117
	118	D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
	119	if ((value & (CTRL_P \| CTRL_S)) == CTRL_S) {
d7539ab4	120	qemu_send_packet(&s->nic->nc,
b43848a1 EI	121	(void *) &s->regs[base],
	122	s->regs[base + R_TX_LEN0]);
	123	D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
	124	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	125	eth_pulse_irq(s);
	126	} else if ((value & (CTRL_P \| CTRL_S)) == (CTRL_P \| CTRL_S)) {
17d1ae3c	127	memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
b43848a1 EI	128	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	129	eth_pulse_irq(s);
	130	}
	131
	132	/* We are fast and get ready pretty much immediately so
	133	we actually never flip the S nor P bits to one. */
	134	s->regs[addr] = value & ~(CTRL_P \| CTRL_S);
	135	break;
	136
	137	/* Keep these native. */
2f991adb PC	138	case R_RX_CTRL0:
	139	case R_RX_CTRL1:
	140	if (!(value & CTRL_S)) {
	141	qemu_flush_queued_packets(&s->nic->nc);
	142	}
b43848a1 EI	143	case R_TX_LEN0:
	144	case R_TX_LEN1:
	145	case R_TX_GIE0:
b43848a1 EI	146	D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
	147	s->regs[addr] = value;
	148	break;
	149
b43848a1	150	default:
d48751ed	151	s->regs[addr] = tswap32(value);
b43848a1 EI	152	break;
	153	}
	154	}
	155
010f3f5f EI	156	static const MemoryRegionOps eth_ops = {
	157	.read = eth_read,
	158	.write = eth_write,
	159	.endianness = DEVICE_NATIVE_ENDIAN,
	160	.valid = {
	161	.min_access_size = 4,
	162	.max_access_size = 4
	163	}
b43848a1 EI	164	};
b43848a1 EI	165
4e68f7a0	166	static int eth_can_rx(NetClientState *nc)
b43848a1	167	{
d7539ab4	168	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
808fb9f2 PC	169	unsigned int rxbase = s->rxbuf * (0x800 / 4);
	170
	171	return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S);
b43848a1 EI	172	}
b43848a1 EI	173
4e68f7a0	174	static ssize_t eth_rx(NetClientState nc, const uint8_t buf, size_t size)
b43848a1	175	{
d7539ab4	176	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
b43848a1	177	unsigned int rxbase = s->rxbuf * (0x800 / 4);
b43848a1 EI	178
b43848a1 EI	179	/* DA filter. */
17d1ae3c	180	if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
df12c1f5	181	return size;
b43848a1 EI	182
	183	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
	184	D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
df12c1f5	185	return -1;
b43848a1 EI	186	}
	187
	188	D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
	189	memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
	190
b43848a1 EI	191	s->regs[rxbase + R_RX_CTRL0] \|= CTRL_S;
	192	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
	193	eth_pulse_irq(s);
	194
	195	/* If c_rx_pingpong was set flip buffers. */
	196	s->rxbuf ^= s->c_rx_pingpong;
df12c1f5	197	return size;
b43848a1 EI	198	}
b43848a1 EI	199
4e68f7a0	200	static void eth_cleanup(NetClientState *nc)
b43848a1	201	{
d7539ab4	202	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
17d1ae3c	203
d7539ab4	204	s->nic = NULL;
b43848a1 EI	205	}
b43848a1 EI	206
d7539ab4	207	static NetClientInfo net_xilinx_ethlite_info = {
2be64a68	208	.type = NET_CLIENT_OPTIONS_KIND_NIC,
d7539ab4 MM	209	.size = sizeof(NICState),
	210	.can_receive = eth_can_rx,
	211	.receive = eth_rx,
	212	.cleanup = eth_cleanup,
	213	};
	214
81a322d4	215	static int xilinx_ethlite_init(SysBusDevice *dev)
b43848a1 EI	216	{
b43848a1 EI	217	struct xlx_ethlite s = FROM_SYSBUS(typeof (s), dev);
b43848a1 EI	218
b43848a1 EI	219	sysbus_init_irq(dev, &s->irq);
b43848a1 EI	220	s->rxbuf = 0;
b43848a1 EI	221
7f4d6755 PC	222	memory_region_init_io(&s->mmio, &eth_ops, s, "xlnx.xps-ethernetlite",
7f4d6755 PC	223	R_MAX * 4);
750ecd44	224	sysbus_init_mmio(dev, &s->mmio);
b43848a1	225
17d1ae3c	226	qemu_macaddr_default_if_unset(&s->conf.macaddr);
d7539ab4	227	s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
f79f2bfc	228	object_get_typename(OBJECT(dev)), dev->qdev.id, s);
d7539ab4	229	qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
81a322d4	230	return 0;
b43848a1 EI	231	}
b43848a1 EI	232
999e12bb	233	static Property xilinx_ethlite_properties[] = {
b2d85c34 PC	234	DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1),
b2d85c34 PC	235	DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1),
999e12bb AL	236	DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
	237	DEFINE_PROP_END_OF_LIST(),
	238	};
	239
	240	static void xilinx_ethlite_class_init(ObjectClass klass, void data)
	241	{
39bffca2	242	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	243	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	244
	245	k->init = xilinx_ethlite_init;
39bffca2	246	dc->props = xilinx_ethlite_properties;
999e12bb AL	247	}
999e12bb AL	248
8c43a6f0	249	static const TypeInfo xilinx_ethlite_info = {
7f4d6755	250	.name = "xlnx.xps-ethernetlite",
39bffca2 AL	251	.parent = TYPE_SYS_BUS_DEVICE,
	252	.instance_size = sizeof(struct xlx_ethlite),
	253	.class_init = xilinx_ethlite_class_init,
ee6847d1 GH	254	};
ee6847d1 GH	255
83f7d43a	256	static void xilinx_ethlite_register_types(void)
b43848a1	257	{
39bffca2	258	type_register_static(&xilinx_ethlite_info);
b43848a1 EI	259	}
b43848a1 EI	260
83f7d43a	261	type_init(xilinx_ethlite_register_types)