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target-arm: Set CPU has_el3 prop during virt init
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
44b0c0bb
CB		 129 uint64_t gbea;
130 uint64_t pp;
131
4e836781
AG		 132 CPU_COMMON
133
bcec36ea
AG		 134 /* reset does memset(0) up to here */
135
bcec36ea
AG		 136 int cpu_num;
137 uint8_t *storage_keys;
138
139 uint64_t tod_offset;
140 uint64_t tod_basetime;
141 QEMUTimer *tod_timer;
142
143 QEMUTimer *cpu_timer;
75973bfe
DH		 144
145 /*
146 * The cpu state represents the logical state of a cpu. In contrast to other
147 * architectures, there is a difference between a halt and a stop on s390.
148 * If all cpus are either stopped (including check stop) or in the disabled
149 * wait state, the vm can be shut down.
150 */
151#define CPU_STATE_UNINITIALIZED 0x00
152#define CPU_STATE_STOPPED 0x01
153#define CPU_STATE_CHECK_STOP 0x02
154#define CPU_STATE_OPERATING 0x03
155#define CPU_STATE_LOAD 0x04
156 uint8_t cpu_state;
157
10ec5117
AG		 158} CPUS390XState;
159
564b863d 160#include "cpu-qom.h"
3d0a615f 161#include <sysemu/kvm.h>
564b863d 162
7b18aad5
CH		 163/* distinguish between 24 bit and 31 bit addressing */
164#define HIGH_ORDER_BIT 0x80000000
165
bcec36ea
AG		 166/* Interrupt Codes */
167/* Program Interrupts */
168#define PGM_OPERATION 0x0001
169#define PGM_PRIVILEGED 0x0002
170#define PGM_EXECUTE 0x0003
171#define PGM_PROTECTION 0x0004
172#define PGM_ADDRESSING 0x0005
173#define PGM_SPECIFICATION 0x0006
174#define PGM_DATA 0x0007
175#define PGM_FIXPT_OVERFLOW 0x0008
176#define PGM_FIXPT_DIVIDE 0x0009
177#define PGM_DEC_OVERFLOW 0x000a
178#define PGM_DEC_DIVIDE 0x000b
179#define PGM_HFP_EXP_OVERFLOW 0x000c
180#define PGM_HFP_EXP_UNDERFLOW 0x000d
181#define PGM_HFP_SIGNIFICANCE 0x000e
182#define PGM_HFP_DIVIDE 0x000f
183#define PGM_SEGMENT_TRANS 0x0010
184#define PGM_PAGE_TRANS 0x0011
185#define PGM_TRANS_SPEC 0x0012
186#define PGM_SPECIAL_OP 0x0013
187#define PGM_OPERAND 0x0015
188#define PGM_TRACE_TABLE 0x0016
189#define PGM_SPACE_SWITCH 0x001c
190#define PGM_HFP_SQRT 0x001d
191#define PGM_PC_TRANS_SPEC 0x001f
192#define PGM_AFX_TRANS 0x0020
193#define PGM_ASX_TRANS 0x0021
194#define PGM_LX_TRANS 0x0022
195#define PGM_EX_TRANS 0x0023
196#define PGM_PRIM_AUTH 0x0024
197#define PGM_SEC_AUTH 0x0025
198#define PGM_ALET_SPEC 0x0028
199#define PGM_ALEN_SPEC 0x0029
200#define PGM_ALE_SEQ 0x002a
201#define PGM_ASTE_VALID 0x002b
202#define PGM_ASTE_SEQ 0x002c
203#define PGM_EXT_AUTH 0x002d
204#define PGM_STACK_FULL 0x0030
205#define PGM_STACK_EMPTY 0x0031
206#define PGM_STACK_SPEC 0x0032
207#define PGM_STACK_TYPE 0x0033
208#define PGM_STACK_OP 0x0034
209#define PGM_ASCE_TYPE 0x0038
210#define PGM_REG_FIRST_TRANS 0x0039
211#define PGM_REG_SEC_TRANS 0x003a
212#define PGM_REG_THIRD_TRANS 0x003b
213#define PGM_MONITOR 0x0040
214#define PGM_PER 0x0080
215#define PGM_CRYPTO 0x0119
216
217/* External Interrupts */
218#define EXT_INTERRUPT_KEY 0x0040
219#define EXT_CLOCK_COMP 0x1004
220#define EXT_CPU_TIMER 0x1005
221#define EXT_MALFUNCTION 0x1200
222#define EXT_EMERGENCY 0x1201
223#define EXT_EXTERNAL_CALL 0x1202
224#define EXT_ETR 0x1406
225#define EXT_SERVICE 0x2401
226#define EXT_VIRTIO 0x2603
227
228/* PSW defines */
229#undef PSW_MASK_PER
230#undef PSW_MASK_DAT
231#undef PSW_MASK_IO
232#undef PSW_MASK_EXT
233#undef PSW_MASK_KEY
234#undef PSW_SHIFT_KEY
235#undef PSW_MASK_MCHECK
236#undef PSW_MASK_WAIT
237#undef PSW_MASK_PSTATE
238#undef PSW_MASK_ASC
239#undef PSW_MASK_CC
240#undef PSW_MASK_PM
241#undef PSW_MASK_64
29c6157c
CB		 242#undef PSW_MASK_32
243#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 244
245#define PSW_MASK_PER 0x4000000000000000ULL
246#define PSW_MASK_DAT 0x0400000000000000ULL
247#define PSW_MASK_IO 0x0200000000000000ULL
248#define PSW_MASK_EXT 0x0100000000000000ULL
249#define PSW_MASK_KEY 0x00F0000000000000ULL
250#define PSW_SHIFT_KEY 56
251#define PSW_MASK_MCHECK 0x0004000000000000ULL
252#define PSW_MASK_WAIT 0x0002000000000000ULL
253#define PSW_MASK_PSTATE 0x0001000000000000ULL
254#define PSW_MASK_ASC 0x0000C00000000000ULL
255#define PSW_MASK_CC 0x0000300000000000ULL
256#define PSW_MASK_PM 0x00000F0000000000ULL
257#define PSW_MASK_64 0x0000000100000000ULL
258#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 259#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 260
261#undef PSW_ASC_PRIMARY
262#undef PSW_ASC_ACCREG
263#undef PSW_ASC_SECONDARY
264#undef PSW_ASC_HOME
265
266#define PSW_ASC_PRIMARY 0x0000000000000000ULL
267#define PSW_ASC_ACCREG 0x0000400000000000ULL
268#define PSW_ASC_SECONDARY 0x0000800000000000ULL
269#define PSW_ASC_HOME 0x0000C00000000000ULL
270
271/* tb flags */
272
273#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
274#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
275#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
276#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
277#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
278#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
279#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
280#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
281#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
282#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
283#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
284#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
285#define FLAG_MASK_32 0x00001000
286
c4400206
TH		 287/* Control register 0 bits */
288#define CR0_EDAT 0x0000000000800000ULL
289
a4e3ad19 290static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 291{
bcec36ea
AG		 292 if (env->psw.mask & PSW_MASK_PSTATE) {
293 return 1;
294 }
295
10c339a0
AG		 296 return 0;
297}
298
a4e3ad19 299static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 300 target_ulong *cs_base, int *flags)
301{
302 *pc = env->psw.addr;
303 *cs_base = 0;
304 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
305 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
306}
307
d5a103cd
RH		 308/* While the PoO talks about ILC (a number between 1-3) what is actually
309 stored in LowCore is shifted left one bit (an even between 2-6). As
310 this is the actual length of the insn and therefore more useful, that
311 is what we want to pass around and manipulate. To make sure that we
312 have applied this distinction universally, rename the "ILC" to "ILEN". */
313static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 314{
315 switch (opc >> 6) {
316 case 0:
d5a103cd 317 return 2;
bcec36ea
AG		 318 case 1:
319 case 2:
d5a103cd
RH		 320 return 4;
321 default:
322 return 6;
bcec36ea 323 }
bcec36ea
AG		 324}
325
d5a103cd
RH		 326#ifndef CONFIG_USER_ONLY
327/* In several cases of runtime exceptions, we havn't recorded the true
328 instruction length. Use these codes when raising exceptions in order
329 to re-compute the length by examining the insn in memory. */
330#define ILEN_LATER 0x20
331#define ILEN_LATER_INC 0x21
332#endif
bcec36ea 333
564b863d 334S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 335void s390x_translate_init(void);
10ec5117 336int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 337
338/* you can call this signal handler from your SIGBUS and SIGSEGV
339 signal handlers to inform the virtual CPU of exceptions. non zero
340 is returned if the signal was handled by the virtual CPU. */
341int cpu_s390x_signal_handler(int host_signum, void *pinfo,
342 void *puc);
7510454e
AF		 343int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
344 int mmu_idx);
10ec5117 345
db1c8f53 346#include "ioinst.h"
52705890 347
10c339a0 348#ifndef CONFIG_USER_ONLY
38322ed6
CH		 349void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
350 int is_write);
351void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
352 int is_write);
7b18aad5
CH		 353static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
354{
355 hwaddr addr = 0;
356 uint8_t reg;
357
358 reg = ipb >> 28;
359 if (reg > 0) {
360 addr = env->regs[reg];
361 }
362 addr += (ipb >> 16) & 0xfff;
363
364 return addr;
365}
366
638129ff
CH		 367/* Base/displacement are at the same locations. */
368#define decode_basedisp_rs decode_basedisp_s
369
85ca3371
DH		 370/* helper functions for run_on_cpu() */
371static inline void s390_do_cpu_reset(void *arg)
372{
373 CPUState *cs = arg;
374 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
375
376 scc->cpu_reset(cs);
377}
378static inline void s390_do_cpu_full_reset(void *arg)
379{
380 CPUState *cs = arg;
381
382 cpu_reset(cs);
383}
384
8f22e0df
AF		 385void s390x_tod_timer(void *opaque);
386void s390x_cpu_timer(void *opaque);
387
28e942f8 388int s390_virtio_hypercall(CPUS390XState *env);
de13d216 389void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 390
1f206266 391#ifdef CONFIG_KVM
de13d216
CH		 392void kvm_s390_virtio_irq(int config_change, uint64_t token);
393void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 394void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
395void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 396int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
1f206266 397#else
de13d216 398static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 399{
400}
de13d216 401static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 402{
403}
1f206266 404#endif
45fa769b 405S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 406unsigned int s390_cpu_halt(S390CPU *cpu);
407void s390_cpu_unhalt(S390CPU *cpu);
408unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
bcec36ea 409
000a1a38
CB		 410/* service interrupts are floating therefore we must not pass an cpustate */
411void s390_sclp_extint(uint32_t parm);
412
d1ff903c 413/* from s390-virtio-bus */
a8170e5e 414extern const hwaddr virtio_size;
d1ff903c 415
ef81522b 416#else
eb24f7c6
DH		 417static inline unsigned int s390_cpu_halt(S390CPU *cpu)
418{
419 return 0;
420}
421
422static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 423{
424}
425
eb24f7c6 426static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 427{
428 return 0;
429}
10c339a0 430#endif
bcec36ea
AG		 431void cpu_lock(void);
432void cpu_unlock(void);
10c339a0 433
7b18aad5
CH		 434typedef struct SubchDev SubchDev;
435
df1fe5bb 436#ifndef CONFIG_USER_ONLY
4e872a3f 437extern void io_subsystem_reset(void);
df1fe5bb
CH		 438SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
439 uint16_t schid);
440bool css_subch_visible(SubchDev *sch);
441void css_conditional_io_interrupt(SubchDev *sch);
442int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 443bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 444int css_do_msch(SubchDev *sch, SCHIB *schib);
445int css_do_xsch(SubchDev *sch);
446int css_do_csch(SubchDev *sch);
447int css_do_hsch(SubchDev *sch);
448int css_do_ssch(SubchDev *sch, ORB *orb);
449int css_do_tsch(SubchDev *sch, IRB *irb);
450int css_do_stcrw(CRW *crw);
50c8d9bf 451int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 452int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
453 int rfmt, void *buf);
454void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
455int css_enable_mcsse(void);
456int css_enable_mss(void);
457int css_do_rsch(SubchDev *sch);
458int css_do_rchp(uint8_t cssid, uint8_t chpid);
459bool css_present(uint8_t cssid);
460#else
7b18aad5
CH		 461static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
462 uint16_t schid)
463{
464 return NULL;
465}
466static inline bool css_subch_visible(SubchDev *sch)
467{
468 return false;
469}
470static inline void css_conditional_io_interrupt(SubchDev *sch)
471{
472}
473static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
474{
475 return -ENODEV;
476}
477static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
478{
479 return true;
480}
481static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
482{
483 return -ENODEV;
484}
485static inline int css_do_xsch(SubchDev *sch)
486{
487 return -ENODEV;
488}
489static inline int css_do_csch(SubchDev *sch)
490{
491 return -ENODEV;
492}
493static inline int css_do_hsch(SubchDev *sch)
494{
495 return -ENODEV;
496}
497static inline int css_do_ssch(SubchDev *sch, ORB *orb)
498{
499 return -ENODEV;
500}
501static inline int css_do_tsch(SubchDev *sch, IRB *irb)
502{
503 return -ENODEV;
504}
505static inline int css_do_stcrw(CRW *crw)
506{
507 return 1;
508}
50c8d9bf 509static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 510{
511 return 0;
512}
513static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
514 int rfmt, uint8_t l_chpid, void *buf)
515{
516 return 0;
517}
518static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
519{
520}
521static inline int css_enable_mss(void)
522{
523 return -EINVAL;
524}
525static inline int css_enable_mcsse(void)
526{
527 return -EINVAL;
528}
529static inline int css_do_rsch(SubchDev *sch)
530{
531 return -ENODEV;
532}
533static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
534{
535 return -ENODEV;
536}
537static inline bool css_present(uint8_t cssid)
538{
539 return false;
540}
df1fe5bb 541#endif
7b18aad5 542
564b863d 543#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 544#define cpu_exec cpu_s390x_exec
545#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 546#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 547
904e5fd5
VM		 548void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
549#define cpu_list s390_cpu_list
550
022c62cb 551#include "exec/exec-all.h"
bcec36ea 552
bcec36ea
AG		 553#define EXCP_EXT 1 /* external interrupt */
554#define EXCP_SVC 2 /* supervisor call (syscall) */
555#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 556#define EXCP_IO 7 /* I/O interrupt */
557#define EXCP_MCHK 8 /* machine check */
bcec36ea 558
bcec36ea
AG		 559#define INTERRUPT_EXT (1 << 0)
560#define INTERRUPT_TOD (1 << 1)
561#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 562#define INTERRUPT_IO (1 << 3)
563#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 564
565/* Program Status Word. */
566#define S390_PSWM_REGNUM 0
567#define S390_PSWA_REGNUM 1
568/* General Purpose Registers. */
569#define S390_R0_REGNUM 2
570#define S390_R1_REGNUM 3
571#define S390_R2_REGNUM 4
572#define S390_R3_REGNUM 5
573#define S390_R4_REGNUM 6
574#define S390_R5_REGNUM 7
575#define S390_R6_REGNUM 8
576#define S390_R7_REGNUM 9
577#define S390_R8_REGNUM 10
578#define S390_R9_REGNUM 11
579#define S390_R10_REGNUM 12
580#define S390_R11_REGNUM 13
581#define S390_R12_REGNUM 14
582#define S390_R13_REGNUM 15
583#define S390_R14_REGNUM 16
584#define S390_R15_REGNUM 17
73d510c9
DH		 585/* Total Core Registers. */
586#define S390_NUM_CORE_REGS 18
10c339a0 587
bcec36ea
AG		 588/* CC optimization */
589
590enum cc_op {
591 CC_OP_CONST0 = 0, /* CC is 0 */
592 CC_OP_CONST1, /* CC is 1 */
593 CC_OP_CONST2, /* CC is 2 */
594 CC_OP_CONST3, /* CC is 3 */
595
596 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
597 CC_OP_STATIC, /* CC value is env->cc_op */
598
599 CC_OP_NZ, /* env->cc_dst != 0 */
600 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
601 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
602 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
603 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
604 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
605 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
606
607 CC_OP_ADD_64, /* overflow on add (64bit) */
608 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 609 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 610 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
611 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 612 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 613 CC_OP_ABS_64, /* sign eval on abs (64bit) */
614 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
615
616 CC_OP_ADD_32, /* overflow on add (32bit) */
617 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 618 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 619 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
620 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 621 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 622 CC_OP_ABS_32, /* sign eval on abs (64bit) */
623 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
624
625 CC_OP_COMP_32, /* complement */
626 CC_OP_COMP_64, /* complement */
627
628 CC_OP_TM_32, /* test under mask (32bit) */
629 CC_OP_TM_64, /* test under mask (64bit) */
630
bcec36ea
AG		 631 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
632 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 633 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 634
635 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 636 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
637 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 638 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 639 CC_OP_MAX
640};
641
642static const char *cc_names[] = {
643 [CC_OP_CONST0] = "CC_OP_CONST0",
644 [CC_OP_CONST1] = "CC_OP_CONST1",
645 [CC_OP_CONST2] = "CC_OP_CONST2",
646 [CC_OP_CONST3] = "CC_OP_CONST3",
647 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
648 [CC_OP_STATIC] = "CC_OP_STATIC",
649 [CC_OP_NZ] = "CC_OP_NZ",
650 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
651 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
652 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
653 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
654 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
655 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
656 [CC_OP_ADD_64] = "CC_OP_ADD_64",
657 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 658 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 659 [CC_OP_SUB_64] = "CC_OP_SUB_64",
660 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 661 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 662 [CC_OP_ABS_64] = "CC_OP_ABS_64",
663 [CC_OP_NABS_64] = "CC_OP_NABS_64",
664 [CC_OP_ADD_32] = "CC_OP_ADD_32",
665 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 666 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 667 [CC_OP_SUB_32] = "CC_OP_SUB_32",
668 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 669 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 670 [CC_OP_ABS_32] = "CC_OP_ABS_32",
671 [CC_OP_NABS_32] = "CC_OP_NABS_32",
672 [CC_OP_COMP_32] = "CC_OP_COMP_32",
673 [CC_OP_COMP_64] = "CC_OP_COMP_64",
674 [CC_OP_TM_32] = "CC_OP_TM_32",
675 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 676 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
677 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 678 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 679 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 680 [CC_OP_SLA_32] = "CC_OP_SLA_32",
681 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 682 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 683};
684
685static inline const char *cc_name(int cc_op)
686{
687 return cc_names[cc_op];
688}
689
3d0a615f
TH		 690static inline void setcc(S390CPU *cpu, uint64_t cc)
691{
692 CPUS390XState *env = &cpu->env;
693
694 env->psw.mask &= ~(3ull << 44);
695 env->psw.mask |= (cc & 3) << 44;
696}
697
bcec36ea
AG		 698typedef struct LowCore
699{
700 /* prefix area: defined by architecture */
701 uint32_t ccw1[2]; /* 0x000 */
702 uint32_t ccw2[4]; /* 0x008 */
703 uint8_t pad1[0x80-0x18]; /* 0x018 */
704 uint32_t ext_params; /* 0x080 */
705 uint16_t cpu_addr; /* 0x084 */
706 uint16_t ext_int_code; /* 0x086 */
d5a103cd 707 uint16_t svc_ilen; /* 0x088 */
bcec36ea 708 uint16_t svc_code; /* 0x08a */
d5a103cd 709 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 710 uint16_t pgm_code; /* 0x08e */
711 uint32_t data_exc_code; /* 0x090 */
712 uint16_t mon_class_num; /* 0x094 */
713 uint16_t per_perc_atmid; /* 0x096 */
714 uint64_t per_address; /* 0x098 */
715 uint8_t exc_access_id; /* 0x0a0 */
716 uint8_t per_access_id; /* 0x0a1 */
717 uint8_t op_access_id; /* 0x0a2 */
718 uint8_t ar_access_id; /* 0x0a3 */
719 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
720 uint64_t trans_exc_code; /* 0x0a8 */
721 uint64_t monitor_code; /* 0x0b0 */
722 uint16_t subchannel_id; /* 0x0b8 */
723 uint16_t subchannel_nr; /* 0x0ba */
724 uint32_t io_int_parm; /* 0x0bc */
725 uint32_t io_int_word; /* 0x0c0 */
726 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
727 uint32_t stfl_fac_list; /* 0x0c8 */
728 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
729 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
730 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
731 uint32_t external_damage_code; /* 0x0f4 */
732 uint64_t failing_storage_address; /* 0x0f8 */
733 uint8_t pad6[0x120-0x100]; /* 0x100 */
734 PSW restart_old_psw; /* 0x120 */
735 PSW external_old_psw; /* 0x130 */
736 PSW svc_old_psw; /* 0x140 */
737 PSW program_old_psw; /* 0x150 */
738 PSW mcck_old_psw; /* 0x160 */
739 PSW io_old_psw; /* 0x170 */
740 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
741 PSW restart_psw; /* 0x1a0 */
742 PSW external_new_psw; /* 0x1b0 */
743 PSW svc_new_psw; /* 0x1c0 */
744 PSW program_new_psw; /* 0x1d0 */
745 PSW mcck_new_psw; /* 0x1e0 */
746 PSW io_new_psw; /* 0x1f0 */
747 PSW return_psw; /* 0x200 */
748 uint8_t irb[64]; /* 0x210 */
749 uint64_t sync_enter_timer; /* 0x250 */
750 uint64_t async_enter_timer; /* 0x258 */
751 uint64_t exit_timer; /* 0x260 */
752 uint64_t last_update_timer; /* 0x268 */
753 uint64_t user_timer; /* 0x270 */
754 uint64_t system_timer; /* 0x278 */
755 uint64_t last_update_clock; /* 0x280 */
756 uint64_t steal_clock; /* 0x288 */
757 PSW return_mcck_psw; /* 0x290 */
758 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
759 /* System info area */
760 uint64_t save_area[16]; /* 0xc00 */
761 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
762 uint64_t kernel_stack; /* 0xd40 */
763 uint64_t thread_info; /* 0xd48 */
764 uint64_t async_stack; /* 0xd50 */
765 uint64_t kernel_asce; /* 0xd58 */
766 uint64_t user_asce; /* 0xd60 */
767 uint64_t panic_stack; /* 0xd68 */
768 uint64_t user_exec_asce; /* 0xd70 */
769 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
770
771 /* SMP info area: defined by DJB */
772 uint64_t clock_comparator; /* 0xdc0 */
773 uint64_t ext_call_fast; /* 0xdc8 */
774 uint64_t percpu_offset; /* 0xdd0 */
775 uint64_t current_task; /* 0xdd8 */
776 uint32_t softirq_pending; /* 0xde0 */
777 uint32_t pad_0x0de4; /* 0xde4 */
778 uint64_t int_clock; /* 0xde8 */
779 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
780
781 /* 0xe00 is used as indicator for dump tools */
782 /* whether the kernel died with panic() or not */
783 uint32_t panic_magic; /* 0xe00 */
784
785 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
786
787 /* 64 bit extparam used for pfault, diag 250 etc */
788 uint64_t ext_params2; /* 0x11B8 */
789
790 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
791
792 /* System info area */
793
794 uint64_t floating_pt_save_area[16]; /* 0x1200 */
795 uint64_t gpregs_save_area[16]; /* 0x1280 */
796 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
797 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
798 uint32_t prefixreg_save_area; /* 0x1318 */
799 uint32_t fpt_creg_save_area; /* 0x131c */
800 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
801 uint32_t tod_progreg_save_area; /* 0x1324 */
802 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
803 uint32_t clock_comp_save_area[2]; /* 0x1330 */
804 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
805 uint32_t access_regs_save_area[16]; /* 0x1340 */
806 uint64_t cregs_save_area[16]; /* 0x1380 */
807
808 /* align to the top of the prefix area */
809
810 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 811} QEMU_PACKED LowCore;
bcec36ea
AG		 812
813/* STSI */
814#define STSI_LEVEL_MASK 0x00000000f0000000ULL
815#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
816#define STSI_LEVEL_1 0x0000000010000000ULL
817#define STSI_LEVEL_2 0x0000000020000000ULL
818#define STSI_LEVEL_3 0x0000000030000000ULL
819#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
820#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
821#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
822#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
823
824/* Basic Machine Configuration */
825struct sysib_111 {
826 uint32_t res1[8];
827 uint8_t manuf[16];
828 uint8_t type[4];
829 uint8_t res2[12];
830 uint8_t model[16];
831 uint8_t sequence[16];
832 uint8_t plant[4];
833 uint8_t res3[156];
834};
835
836/* Basic Machine CPU */
837struct sysib_121 {
838 uint32_t res1[80];
839 uint8_t sequence[16];
840 uint8_t plant[4];
841 uint8_t res2[2];
842 uint16_t cpu_addr;
843 uint8_t res3[152];
844};
845
846/* Basic Machine CPUs */
847struct sysib_122 {
848 uint8_t res1[32];
849 uint32_t capability;
850 uint16_t total_cpus;
851 uint16_t active_cpus;
852 uint16_t standby_cpus;
853 uint16_t reserved_cpus;
854 uint16_t adjustments[2026];
855};
856
857/* LPAR CPU */
858struct sysib_221 {
859 uint32_t res1[80];
860 uint8_t sequence[16];
861 uint8_t plant[4];
862 uint16_t cpu_id;
863 uint16_t cpu_addr;
864 uint8_t res3[152];
865};
866
867/* LPAR CPUs */
868struct sysib_222 {
869 uint32_t res1[32];
870 uint16_t lpar_num;
871 uint8_t res2;
872 uint8_t lcpuc;
873 uint16_t total_cpus;
874 uint16_t conf_cpus;
875 uint16_t standby_cpus;
876 uint16_t reserved_cpus;
877 uint8_t name[8];
878 uint32_t caf;
879 uint8_t res3[16];
880 uint16_t dedicated_cpus;
881 uint16_t shared_cpus;
882 uint8_t res4[180];
883};
884
885/* VM CPUs */
886struct sysib_322 {
887 uint8_t res1[31];
888 uint8_t count;
889 struct {
890 uint8_t res2[4];
891 uint16_t total_cpus;
892 uint16_t conf_cpus;
893 uint16_t standby_cpus;
894 uint16_t reserved_cpus;
895 uint8_t name[8];
896 uint32_t caf;
897 uint8_t cpi[16];
898 uint8_t res3[24];
899 } vm[8];
900 uint8_t res4[3552];
901};
902
903/* MMU defines */
904#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
905#define _ASCE_SUBSPACE 0x200 /* subspace group control */
906#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
907#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
908#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
909#define _ASCE_REAL_SPACE 0x20 /* real space control */
910#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
911#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
912#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
913#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
914#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
915#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
916
917#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
918#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
919#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
920#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
921#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
922#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
923#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
924
925#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 926#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 927#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
928#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
929
930#define _PAGE_RO 0x200 /* HW read-only bit */
931#define _PAGE_INVALID 0x400 /* HW invalid bit */
932
b9959138
AG		 933#define SK_C (0x1 << 1)
934#define SK_R (0x1 << 2)
935#define SK_F (0x1 << 3)
936#define SK_ACC_MASK (0xf << 4)
bcec36ea 937
bcec36ea
AG		 938#define SIGP_SENSE 0x01
939#define SIGP_EXTERNAL_CALL 0x02
940#define SIGP_EMERGENCY 0x03
941#define SIGP_START 0x04
942#define SIGP_STOP 0x05
943#define SIGP_RESTART 0x06
944#define SIGP_STOP_STORE_STATUS 0x09
945#define SIGP_INITIAL_CPU_RESET 0x0b
946#define SIGP_CPU_RESET 0x0c
947#define SIGP_SET_PREFIX 0x0d
948#define SIGP_STORE_STATUS_ADDR 0x0e
949#define SIGP_SET_ARCH 0x12
950
951/* cpu status bits */
952#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
953#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
954#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
955#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
956#define SIGP_STAT_STOPPED 0x00000040UL
957#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
958#define SIGP_STAT_CHECK_STOP 0x00000010UL
959#define SIGP_STAT_INOPERATIVE 0x00000004UL
960#define SIGP_STAT_INVALID_ORDER 0x00000002UL
961#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
962
a4e3ad19
AF		 963void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
964int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 965 target_ulong *raddr, int *flags);
6e252802 966int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 967uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 968 uint64_t vr);
969
970#define TARGET_HAS_ICE 1
971
972/* The value of the TOD clock for 1.1.1970. */
973#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
974
975/* Converts ns to s390's clock format */
976static inline uint64_t time2tod(uint64_t ns) {
977 return (ns << 9) / 125;
978}
979
f9466733 980static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 981 uint64_t param64)
982{
f9466733
AF		 983 CPUS390XState *env = &cpu->env;
984
bcec36ea
AG		 985 if (env->ext_index == MAX_EXT_QUEUE - 1) {
986 /* ugh - can't queue anymore. Let's drop. */
987 return;
988 }
989
990 env->ext_index++;
991 assert(env->ext_index < MAX_EXT_QUEUE);
992
993 env->ext_queue[env->ext_index].code = code;
994 env->ext_queue[env->ext_index].param = param;
995 env->ext_queue[env->ext_index].param64 = param64;
996
997 env->pending_int |= INTERRUPT_EXT;
c3affe56 998 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 999}
10c339a0 1000
f9466733 1001static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 1002 uint16_t subchannel_number,
1003 uint32_t io_int_parm, uint32_t io_int_word)
1004{
f9466733 1005 CPUS390XState *env = &cpu->env;
91b0a8f3 1006 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1007
1008 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1009 /* ugh - can't queue anymore. Let's drop. */
1010 return;
1011 }
1012
1013 env->io_index[isc]++;
1014 assert(env->io_index[isc] < MAX_IO_QUEUE);
1015
1016 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1017 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1018 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1019 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1020
1021 env->pending_int |= INTERRUPT_IO;
c3affe56 1022 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1023}
1024
f9466733 1025static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1026{
f9466733
AF		 1027 CPUS390XState *env = &cpu->env;
1028
5d69c547
CH		 1029 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1030 /* ugh - can't queue anymore. Let's drop. */
1031 return;
1032 }
1033
1034 env->mchk_index++;
1035 assert(env->mchk_index < MAX_MCHK_QUEUE);
1036
1037 env->mchk_queue[env->mchk_index].type = 1;
1038
1039 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1040 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1041}
1042
b6fe0124
MR		 1043/* from s390-virtio-ccw */
1044#define MEM_SECTION_SIZE 0x10000000UL
1def6656 1045#define MAX_AVAIL_SLOTS 32
b6fe0124 1046
e72ca652 1047/* fpu_helper.c */
e72ca652
BS		 1048uint32_t set_cc_nz_f32(float32 v);
1049uint32_t set_cc_nz_f64(float64 v);
587626f8 1050uint32_t set_cc_nz_f128(float128 v);
e72ca652 1051
aea1e885 1052/* misc_helper.c */
268846ba
ED		 1053#ifndef CONFIG_USER_ONLY
1054void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1055#endif
d5a103cd 1056void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1057void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1058 uintptr_t retaddr);
a78b0504 1059
09b99878 1060#ifdef CONFIG_KVM
de13d216 1061void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 1062 uint16_t subchannel_nr, uint32_t io_int_parm,
1063 uint32_t io_int_word);
de13d216 1064void kvm_s390_crw_mchk(void);
09b99878 1065void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1066int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1067 int vq, bool assign);
7f7f9752 1068int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1069int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 1070void kvm_s390_clear_cmma_callback(void *opaque);
c9e659c9 1071int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 1072void kvm_s390_reset_vcpu(S390CPU *cpu);
09b99878 1073#else
de13d216 1074static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 1075 uint16_t subchannel_nr,
1076 uint32_t io_int_parm,
1077 uint32_t io_int_word)
1078{
1079}
de13d216 1080static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1081{
1082}
09b99878
CH		 1083static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1084{
1085}
cc3ac9c4
CH		 1086static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1087 uint32_t sch, int vq,
b4436a0b
CH		 1088 bool assign)
1089{
1090 return -ENOSYS;
1091}
7f7f9752
ED		 1092static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1093{
1094 return -ENOSYS;
1095}
4cb88c3c
DD		 1096static inline void kvm_s390_clear_cmma_callback(void *opaque)
1097{
1098}
1def6656
MR		 1099static inline int kvm_s390_get_memslot_count(KVMState *s)
1100{
1101 return MAX_AVAIL_SLOTS;
1102}
c9e659c9
DH		 1103static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1104{
1105 return -ENOSYS;
1106}
99607144
DH		 1107static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1108{
1109}
09b99878 1110#endif
df1fe5bb 1111
4cb88c3c
DD		 1112static inline void cmma_reset(S390CPU *cpu)
1113{
1114 if (kvm_enabled()) {
1115 CPUState *cs = CPU(cpu);
1116 kvm_s390_clear_cmma_callback(cs->kvm_state);
1117 }
1118}
1119
7f7f9752
ED		 1120static inline int s390_cpu_restart(S390CPU *cpu)
1121{
1122 if (kvm_enabled()) {
1123 return kvm_s390_cpu_restart(cpu);
1124 }
1125 return -ENOSYS;
1126}
1127
1def6656
MR		 1128static inline int s390_get_memslot_count(KVMState *s)
1129{
1130 if (kvm_enabled()) {
1131 return kvm_s390_get_memslot_count(s);
1132 } else {
1133 return MAX_AVAIL_SLOTS;
1134 }
1135}
1136
de13d216
CH		 1137void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1138 uint32_t io_int_parm, uint32_t io_int_word);
1139void s390_crw_mchk(void);
df1fe5bb 1140
cc3ac9c4
CH		 1141static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1142 uint32_t sch_id, int vq,
b4436a0b
CH		 1143 bool assign)
1144{
1145 if (kvm_enabled()) {
cc3ac9c4 1146 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1147 } else {
1148 return -ENOSYS;
1149 }
1150}
1151
10ec5117 1152#endif
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