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s390x/kvm: proper use of the cpu states OPERATING and STOPPED
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
44b0c0bb
CB		 129 uint64_t gbea;
130 uint64_t pp;
131
4e836781
AG		 132 CPU_COMMON
133
bcec36ea
AG		 134 /* reset does memset(0) up to here */
135
bcec36ea
AG		 136 int cpu_num;
137 uint8_t *storage_keys;
138
139 uint64_t tod_offset;
140 uint64_t tod_basetime;
141 QEMUTimer *tod_timer;
142
143 QEMUTimer *cpu_timer;
75973bfe
DH		 144
145 /*
146 * The cpu state represents the logical state of a cpu. In contrast to other
147 * architectures, there is a difference between a halt and a stop on s390.
148 * If all cpus are either stopped (including check stop) or in the disabled
149 * wait state, the vm can be shut down.
150 */
151#define CPU_STATE_UNINITIALIZED 0x00
152#define CPU_STATE_STOPPED 0x01
153#define CPU_STATE_CHECK_STOP 0x02
154#define CPU_STATE_OPERATING 0x03
155#define CPU_STATE_LOAD 0x04
156 uint8_t cpu_state;
157
10ec5117
AG		 158} CPUS390XState;
159
564b863d 160#include "cpu-qom.h"
3d0a615f 161#include <sysemu/kvm.h>
564b863d 162
7b18aad5
CH		 163/* distinguish between 24 bit and 31 bit addressing */
164#define HIGH_ORDER_BIT 0x80000000
165
bcec36ea
AG		 166/* Interrupt Codes */
167/* Program Interrupts */
168#define PGM_OPERATION 0x0001
169#define PGM_PRIVILEGED 0x0002
170#define PGM_EXECUTE 0x0003
171#define PGM_PROTECTION 0x0004
172#define PGM_ADDRESSING 0x0005
173#define PGM_SPECIFICATION 0x0006
174#define PGM_DATA 0x0007
175#define PGM_FIXPT_OVERFLOW 0x0008
176#define PGM_FIXPT_DIVIDE 0x0009
177#define PGM_DEC_OVERFLOW 0x000a
178#define PGM_DEC_DIVIDE 0x000b
179#define PGM_HFP_EXP_OVERFLOW 0x000c
180#define PGM_HFP_EXP_UNDERFLOW 0x000d
181#define PGM_HFP_SIGNIFICANCE 0x000e
182#define PGM_HFP_DIVIDE 0x000f
183#define PGM_SEGMENT_TRANS 0x0010
184#define PGM_PAGE_TRANS 0x0011
185#define PGM_TRANS_SPEC 0x0012
186#define PGM_SPECIAL_OP 0x0013
187#define PGM_OPERAND 0x0015
188#define PGM_TRACE_TABLE 0x0016
189#define PGM_SPACE_SWITCH 0x001c
190#define PGM_HFP_SQRT 0x001d
191#define PGM_PC_TRANS_SPEC 0x001f
192#define PGM_AFX_TRANS 0x0020
193#define PGM_ASX_TRANS 0x0021
194#define PGM_LX_TRANS 0x0022
195#define PGM_EX_TRANS 0x0023
196#define PGM_PRIM_AUTH 0x0024
197#define PGM_SEC_AUTH 0x0025
198#define PGM_ALET_SPEC 0x0028
199#define PGM_ALEN_SPEC 0x0029
200#define PGM_ALE_SEQ 0x002a
201#define PGM_ASTE_VALID 0x002b
202#define PGM_ASTE_SEQ 0x002c
203#define PGM_EXT_AUTH 0x002d
204#define PGM_STACK_FULL 0x0030
205#define PGM_STACK_EMPTY 0x0031
206#define PGM_STACK_SPEC 0x0032
207#define PGM_STACK_TYPE 0x0033
208#define PGM_STACK_OP 0x0034
209#define PGM_ASCE_TYPE 0x0038
210#define PGM_REG_FIRST_TRANS 0x0039
211#define PGM_REG_SEC_TRANS 0x003a
212#define PGM_REG_THIRD_TRANS 0x003b
213#define PGM_MONITOR 0x0040
214#define PGM_PER 0x0080
215#define PGM_CRYPTO 0x0119
216
217/* External Interrupts */
218#define EXT_INTERRUPT_KEY 0x0040
219#define EXT_CLOCK_COMP 0x1004
220#define EXT_CPU_TIMER 0x1005
221#define EXT_MALFUNCTION 0x1200
222#define EXT_EMERGENCY 0x1201
223#define EXT_EXTERNAL_CALL 0x1202
224#define EXT_ETR 0x1406
225#define EXT_SERVICE 0x2401
226#define EXT_VIRTIO 0x2603
227
228/* PSW defines */
229#undef PSW_MASK_PER
230#undef PSW_MASK_DAT
231#undef PSW_MASK_IO
232#undef PSW_MASK_EXT
233#undef PSW_MASK_KEY
234#undef PSW_SHIFT_KEY
235#undef PSW_MASK_MCHECK
236#undef PSW_MASK_WAIT
237#undef PSW_MASK_PSTATE
238#undef PSW_MASK_ASC
239#undef PSW_MASK_CC
240#undef PSW_MASK_PM
241#undef PSW_MASK_64
29c6157c
CB		 242#undef PSW_MASK_32
243#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 244
245#define PSW_MASK_PER 0x4000000000000000ULL
246#define PSW_MASK_DAT 0x0400000000000000ULL
247#define PSW_MASK_IO 0x0200000000000000ULL
248#define PSW_MASK_EXT 0x0100000000000000ULL
249#define PSW_MASK_KEY 0x00F0000000000000ULL
250#define PSW_SHIFT_KEY 56
251#define PSW_MASK_MCHECK 0x0004000000000000ULL
252#define PSW_MASK_WAIT 0x0002000000000000ULL
253#define PSW_MASK_PSTATE 0x0001000000000000ULL
254#define PSW_MASK_ASC 0x0000C00000000000ULL
255#define PSW_MASK_CC 0x0000300000000000ULL
256#define PSW_MASK_PM 0x00000F0000000000ULL
257#define PSW_MASK_64 0x0000000100000000ULL
258#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 259#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 260
261#undef PSW_ASC_PRIMARY
262#undef PSW_ASC_ACCREG
263#undef PSW_ASC_SECONDARY
264#undef PSW_ASC_HOME
265
266#define PSW_ASC_PRIMARY 0x0000000000000000ULL
267#define PSW_ASC_ACCREG 0x0000400000000000ULL
268#define PSW_ASC_SECONDARY 0x0000800000000000ULL
269#define PSW_ASC_HOME 0x0000C00000000000ULL
270
271/* tb flags */
272
273#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
274#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
275#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
276#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
277#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
278#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
279#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
280#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
281#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
282#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
283#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
284#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
285#define FLAG_MASK_32 0x00001000
286
c4400206
TH		 287/* Control register 0 bits */
288#define CR0_EDAT 0x0000000000800000ULL
289
a4e3ad19 290static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 291{
bcec36ea
AG		 292 if (env->psw.mask & PSW_MASK_PSTATE) {
293 return 1;
294 }
295
10c339a0
AG		 296 return 0;
297}
298
a4e3ad19 299static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 300 target_ulong *cs_base, int *flags)
301{
302 *pc = env->psw.addr;
303 *cs_base = 0;
304 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
305 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
306}
307
d5a103cd
RH		 308/* While the PoO talks about ILC (a number between 1-3) what is actually
309 stored in LowCore is shifted left one bit (an even between 2-6). As
310 this is the actual length of the insn and therefore more useful, that
311 is what we want to pass around and manipulate. To make sure that we
312 have applied this distinction universally, rename the "ILC" to "ILEN". */
313static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 314{
315 switch (opc >> 6) {
316 case 0:
d5a103cd 317 return 2;
bcec36ea
AG		 318 case 1:
319 case 2:
d5a103cd
RH		 320 return 4;
321 default:
322 return 6;
bcec36ea 323 }
bcec36ea
AG		 324}
325
d5a103cd
RH		 326#ifndef CONFIG_USER_ONLY
327/* In several cases of runtime exceptions, we havn't recorded the true
328 instruction length. Use these codes when raising exceptions in order
329 to re-compute the length by examining the insn in memory. */
330#define ILEN_LATER 0x20
331#define ILEN_LATER_INC 0x21
332#endif
bcec36ea 333
564b863d 334S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 335void s390x_translate_init(void);
10ec5117 336int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 337
338/* you can call this signal handler from your SIGBUS and SIGSEGV
339 signal handlers to inform the virtual CPU of exceptions. non zero
340 is returned if the signal was handled by the virtual CPU. */
341int cpu_s390x_signal_handler(int host_signum, void *pinfo,
342 void *puc);
7510454e
AF		 343int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
344 int mmu_idx);
10ec5117 345
db1c8f53 346#include "ioinst.h"
52705890 347
10c339a0 348#ifndef CONFIG_USER_ONLY
38322ed6
CH		 349void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
350 int is_write);
351void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
352 int is_write);
7b18aad5
CH		 353static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
354{
355 hwaddr addr = 0;
356 uint8_t reg;
357
358 reg = ipb >> 28;
359 if (reg > 0) {
360 addr = env->regs[reg];
361 }
362 addr += (ipb >> 16) & 0xfff;
363
364 return addr;
365}
366
638129ff
CH		 367/* Base/displacement are at the same locations. */
368#define decode_basedisp_rs decode_basedisp_s
369
85ca3371
DH		 370/* helper functions for run_on_cpu() */
371static inline void s390_do_cpu_reset(void *arg)
372{
373 CPUState *cs = arg;
374 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
375
376 scc->cpu_reset(cs);
377}
378static inline void s390_do_cpu_full_reset(void *arg)
379{
380 CPUState *cs = arg;
381
382 cpu_reset(cs);
383}
384
8f22e0df
AF		 385void s390x_tod_timer(void *opaque);
386void s390x_cpu_timer(void *opaque);
387
28e942f8 388int s390_virtio_hypercall(CPUS390XState *env);
de13d216 389void s390_virtio_irq(int config_change, uint64_t token);
bcec36ea 390
1f206266 391#ifdef CONFIG_KVM
50a2c6e5 392void kvm_s390_reset_vcpu(S390CPU *cpu);
de13d216
CH		 393void kvm_s390_virtio_irq(int config_change, uint64_t token);
394void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH		 395void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
396void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 397int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
1f206266 398#else
50a2c6e5
PB		 399static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
400{
401}
de13d216 402static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
1f206266
AG		 403{
404}
de13d216 405static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH		 406{
407}
1f206266 408#endif
45fa769b 409S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH		 410unsigned int s390_cpu_halt(S390CPU *cpu);
411void s390_cpu_unhalt(S390CPU *cpu);
412unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
bcec36ea 413
000a1a38
CB		 414/* service interrupts are floating therefore we must not pass an cpustate */
415void s390_sclp_extint(uint32_t parm);
416
d1ff903c 417/* from s390-virtio-bus */
a8170e5e 418extern const hwaddr virtio_size;
d1ff903c 419
ef81522b 420#else
eb24f7c6
DH		 421static inline unsigned int s390_cpu_halt(S390CPU *cpu)
422{
423 return 0;
424}
425
426static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG		 427{
428}
429
eb24f7c6 430static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG		 431{
432 return 0;
433}
10c339a0 434#endif
bcec36ea
AG		 435void cpu_lock(void);
436void cpu_unlock(void);
10c339a0 437
7b18aad5
CH		 438typedef struct SubchDev SubchDev;
439
df1fe5bb 440#ifndef CONFIG_USER_ONLY
4e872a3f 441extern void io_subsystem_reset(void);
df1fe5bb
CH		 442SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
443 uint16_t schid);
444bool css_subch_visible(SubchDev *sch);
445void css_conditional_io_interrupt(SubchDev *sch);
446int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 447bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 448int css_do_msch(SubchDev *sch, SCHIB *schib);
449int css_do_xsch(SubchDev *sch);
450int css_do_csch(SubchDev *sch);
451int css_do_hsch(SubchDev *sch);
452int css_do_ssch(SubchDev *sch, ORB *orb);
453int css_do_tsch(SubchDev *sch, IRB *irb);
454int css_do_stcrw(CRW *crw);
50c8d9bf 455int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 456int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
457 int rfmt, void *buf);
458void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
459int css_enable_mcsse(void);
460int css_enable_mss(void);
461int css_do_rsch(SubchDev *sch);
462int css_do_rchp(uint8_t cssid, uint8_t chpid);
463bool css_present(uint8_t cssid);
464#else
7b18aad5
CH		 465static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
466 uint16_t schid)
467{
468 return NULL;
469}
470static inline bool css_subch_visible(SubchDev *sch)
471{
472 return false;
473}
474static inline void css_conditional_io_interrupt(SubchDev *sch)
475{
476}
477static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
478{
479 return -ENODEV;
480}
481static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
482{
483 return true;
484}
485static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
486{
487 return -ENODEV;
488}
489static inline int css_do_xsch(SubchDev *sch)
490{
491 return -ENODEV;
492}
493static inline int css_do_csch(SubchDev *sch)
494{
495 return -ENODEV;
496}
497static inline int css_do_hsch(SubchDev *sch)
498{
499 return -ENODEV;
500}
501static inline int css_do_ssch(SubchDev *sch, ORB *orb)
502{
503 return -ENODEV;
504}
505static inline int css_do_tsch(SubchDev *sch, IRB *irb)
506{
507 return -ENODEV;
508}
509static inline int css_do_stcrw(CRW *crw)
510{
511 return 1;
512}
50c8d9bf 513static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 514{
515 return 0;
516}
517static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
518 int rfmt, uint8_t l_chpid, void *buf)
519{
520 return 0;
521}
522static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
523{
524}
525static inline int css_enable_mss(void)
526{
527 return -EINVAL;
528}
529static inline int css_enable_mcsse(void)
530{
531 return -EINVAL;
532}
533static inline int css_do_rsch(SubchDev *sch)
534{
535 return -ENODEV;
536}
537static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
538{
539 return -ENODEV;
540}
541static inline bool css_present(uint8_t cssid)
542{
543 return false;
544}
df1fe5bb 545#endif
7b18aad5 546
564b863d 547#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 548#define cpu_exec cpu_s390x_exec
549#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 550#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 551
904e5fd5
VM		 552void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
553#define cpu_list s390_cpu_list
554
022c62cb 555#include "exec/exec-all.h"
bcec36ea 556
bcec36ea
AG		 557#define EXCP_EXT 1 /* external interrupt */
558#define EXCP_SVC 2 /* supervisor call (syscall) */
559#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 560#define EXCP_IO 7 /* I/O interrupt */
561#define EXCP_MCHK 8 /* machine check */
bcec36ea 562
bcec36ea
AG		 563#define INTERRUPT_EXT (1 << 0)
564#define INTERRUPT_TOD (1 << 1)
565#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 566#define INTERRUPT_IO (1 << 3)
567#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 568
569/* Program Status Word. */
570#define S390_PSWM_REGNUM 0
571#define S390_PSWA_REGNUM 1
572/* General Purpose Registers. */
573#define S390_R0_REGNUM 2
574#define S390_R1_REGNUM 3
575#define S390_R2_REGNUM 4
576#define S390_R3_REGNUM 5
577#define S390_R4_REGNUM 6
578#define S390_R5_REGNUM 7
579#define S390_R6_REGNUM 8
580#define S390_R7_REGNUM 9
581#define S390_R8_REGNUM 10
582#define S390_R9_REGNUM 11
583#define S390_R10_REGNUM 12
584#define S390_R11_REGNUM 13
585#define S390_R12_REGNUM 14
586#define S390_R13_REGNUM 15
587#define S390_R14_REGNUM 16
588#define S390_R15_REGNUM 17
73d510c9
DH		 589/* Total Core Registers. */
590#define S390_NUM_CORE_REGS 18
10c339a0 591
bcec36ea
AG		 592/* CC optimization */
593
594enum cc_op {
595 CC_OP_CONST0 = 0, /* CC is 0 */
596 CC_OP_CONST1, /* CC is 1 */
597 CC_OP_CONST2, /* CC is 2 */
598 CC_OP_CONST3, /* CC is 3 */
599
600 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
601 CC_OP_STATIC, /* CC value is env->cc_op */
602
603 CC_OP_NZ, /* env->cc_dst != 0 */
604 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
605 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
606 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
607 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
608 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
609 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
610
611 CC_OP_ADD_64, /* overflow on add (64bit) */
612 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 613 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 614 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
615 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 616 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 617 CC_OP_ABS_64, /* sign eval on abs (64bit) */
618 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
619
620 CC_OP_ADD_32, /* overflow on add (32bit) */
621 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 622 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 623 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
624 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 625 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 626 CC_OP_ABS_32, /* sign eval on abs (64bit) */
627 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
628
629 CC_OP_COMP_32, /* complement */
630 CC_OP_COMP_64, /* complement */
631
632 CC_OP_TM_32, /* test under mask (32bit) */
633 CC_OP_TM_64, /* test under mask (64bit) */
634
bcec36ea
AG		 635 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
636 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 637 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 638
639 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 640 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
641 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 642 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 643 CC_OP_MAX
644};
645
646static const char *cc_names[] = {
647 [CC_OP_CONST0] = "CC_OP_CONST0",
648 [CC_OP_CONST1] = "CC_OP_CONST1",
649 [CC_OP_CONST2] = "CC_OP_CONST2",
650 [CC_OP_CONST3] = "CC_OP_CONST3",
651 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
652 [CC_OP_STATIC] = "CC_OP_STATIC",
653 [CC_OP_NZ] = "CC_OP_NZ",
654 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
655 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
656 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
657 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
658 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
659 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
660 [CC_OP_ADD_64] = "CC_OP_ADD_64",
661 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 662 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 663 [CC_OP_SUB_64] = "CC_OP_SUB_64",
664 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 665 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 666 [CC_OP_ABS_64] = "CC_OP_ABS_64",
667 [CC_OP_NABS_64] = "CC_OP_NABS_64",
668 [CC_OP_ADD_32] = "CC_OP_ADD_32",
669 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 670 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 671 [CC_OP_SUB_32] = "CC_OP_SUB_32",
672 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 673 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 674 [CC_OP_ABS_32] = "CC_OP_ABS_32",
675 [CC_OP_NABS_32] = "CC_OP_NABS_32",
676 [CC_OP_COMP_32] = "CC_OP_COMP_32",
677 [CC_OP_COMP_64] = "CC_OP_COMP_64",
678 [CC_OP_TM_32] = "CC_OP_TM_32",
679 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 680 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
681 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 682 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 683 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 684 [CC_OP_SLA_32] = "CC_OP_SLA_32",
685 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 686 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 687};
688
689static inline const char *cc_name(int cc_op)
690{
691 return cc_names[cc_op];
692}
693
3d0a615f
TH		 694static inline void setcc(S390CPU *cpu, uint64_t cc)
695{
696 CPUS390XState *env = &cpu->env;
697
698 env->psw.mask &= ~(3ull << 44);
699 env->psw.mask |= (cc & 3) << 44;
700}
701
bcec36ea
AG		 702typedef struct LowCore
703{
704 /* prefix area: defined by architecture */
705 uint32_t ccw1[2]; /* 0x000 */
706 uint32_t ccw2[4]; /* 0x008 */
707 uint8_t pad1[0x80-0x18]; /* 0x018 */
708 uint32_t ext_params; /* 0x080 */
709 uint16_t cpu_addr; /* 0x084 */
710 uint16_t ext_int_code; /* 0x086 */
d5a103cd 711 uint16_t svc_ilen; /* 0x088 */
bcec36ea 712 uint16_t svc_code; /* 0x08a */
d5a103cd 713 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 714 uint16_t pgm_code; /* 0x08e */
715 uint32_t data_exc_code; /* 0x090 */
716 uint16_t mon_class_num; /* 0x094 */
717 uint16_t per_perc_atmid; /* 0x096 */
718 uint64_t per_address; /* 0x098 */
719 uint8_t exc_access_id; /* 0x0a0 */
720 uint8_t per_access_id; /* 0x0a1 */
721 uint8_t op_access_id; /* 0x0a2 */
722 uint8_t ar_access_id; /* 0x0a3 */
723 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
724 uint64_t trans_exc_code; /* 0x0a8 */
725 uint64_t monitor_code; /* 0x0b0 */
726 uint16_t subchannel_id; /* 0x0b8 */
727 uint16_t subchannel_nr; /* 0x0ba */
728 uint32_t io_int_parm; /* 0x0bc */
729 uint32_t io_int_word; /* 0x0c0 */
730 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
731 uint32_t stfl_fac_list; /* 0x0c8 */
732 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
733 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
734 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
735 uint32_t external_damage_code; /* 0x0f4 */
736 uint64_t failing_storage_address; /* 0x0f8 */
737 uint8_t pad6[0x120-0x100]; /* 0x100 */
738 PSW restart_old_psw; /* 0x120 */
739 PSW external_old_psw; /* 0x130 */
740 PSW svc_old_psw; /* 0x140 */
741 PSW program_old_psw; /* 0x150 */
742 PSW mcck_old_psw; /* 0x160 */
743 PSW io_old_psw; /* 0x170 */
744 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
745 PSW restart_psw; /* 0x1a0 */
746 PSW external_new_psw; /* 0x1b0 */
747 PSW svc_new_psw; /* 0x1c0 */
748 PSW program_new_psw; /* 0x1d0 */
749 PSW mcck_new_psw; /* 0x1e0 */
750 PSW io_new_psw; /* 0x1f0 */
751 PSW return_psw; /* 0x200 */
752 uint8_t irb[64]; /* 0x210 */
753 uint64_t sync_enter_timer; /* 0x250 */
754 uint64_t async_enter_timer; /* 0x258 */
755 uint64_t exit_timer; /* 0x260 */
756 uint64_t last_update_timer; /* 0x268 */
757 uint64_t user_timer; /* 0x270 */
758 uint64_t system_timer; /* 0x278 */
759 uint64_t last_update_clock; /* 0x280 */
760 uint64_t steal_clock; /* 0x288 */
761 PSW return_mcck_psw; /* 0x290 */
762 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
763 /* System info area */
764 uint64_t save_area[16]; /* 0xc00 */
765 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
766 uint64_t kernel_stack; /* 0xd40 */
767 uint64_t thread_info; /* 0xd48 */
768 uint64_t async_stack; /* 0xd50 */
769 uint64_t kernel_asce; /* 0xd58 */
770 uint64_t user_asce; /* 0xd60 */
771 uint64_t panic_stack; /* 0xd68 */
772 uint64_t user_exec_asce; /* 0xd70 */
773 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
774
775 /* SMP info area: defined by DJB */
776 uint64_t clock_comparator; /* 0xdc0 */
777 uint64_t ext_call_fast; /* 0xdc8 */
778 uint64_t percpu_offset; /* 0xdd0 */
779 uint64_t current_task; /* 0xdd8 */
780 uint32_t softirq_pending; /* 0xde0 */
781 uint32_t pad_0x0de4; /* 0xde4 */
782 uint64_t int_clock; /* 0xde8 */
783 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
784
785 /* 0xe00 is used as indicator for dump tools */
786 /* whether the kernel died with panic() or not */
787 uint32_t panic_magic; /* 0xe00 */
788
789 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
790
791 /* 64 bit extparam used for pfault, diag 250 etc */
792 uint64_t ext_params2; /* 0x11B8 */
793
794 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
795
796 /* System info area */
797
798 uint64_t floating_pt_save_area[16]; /* 0x1200 */
799 uint64_t gpregs_save_area[16]; /* 0x1280 */
800 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
801 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
802 uint32_t prefixreg_save_area; /* 0x1318 */
803 uint32_t fpt_creg_save_area; /* 0x131c */
804 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
805 uint32_t tod_progreg_save_area; /* 0x1324 */
806 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
807 uint32_t clock_comp_save_area[2]; /* 0x1330 */
808 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
809 uint32_t access_regs_save_area[16]; /* 0x1340 */
810 uint64_t cregs_save_area[16]; /* 0x1380 */
811
812 /* align to the top of the prefix area */
813
814 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 815} QEMU_PACKED LowCore;
bcec36ea
AG		 816
817/* STSI */
818#define STSI_LEVEL_MASK 0x00000000f0000000ULL
819#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
820#define STSI_LEVEL_1 0x0000000010000000ULL
821#define STSI_LEVEL_2 0x0000000020000000ULL
822#define STSI_LEVEL_3 0x0000000030000000ULL
823#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
824#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
825#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
826#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
827
828/* Basic Machine Configuration */
829struct sysib_111 {
830 uint32_t res1[8];
831 uint8_t manuf[16];
832 uint8_t type[4];
833 uint8_t res2[12];
834 uint8_t model[16];
835 uint8_t sequence[16];
836 uint8_t plant[4];
837 uint8_t res3[156];
838};
839
840/* Basic Machine CPU */
841struct sysib_121 {
842 uint32_t res1[80];
843 uint8_t sequence[16];
844 uint8_t plant[4];
845 uint8_t res2[2];
846 uint16_t cpu_addr;
847 uint8_t res3[152];
848};
849
850/* Basic Machine CPUs */
851struct sysib_122 {
852 uint8_t res1[32];
853 uint32_t capability;
854 uint16_t total_cpus;
855 uint16_t active_cpus;
856 uint16_t standby_cpus;
857 uint16_t reserved_cpus;
858 uint16_t adjustments[2026];
859};
860
861/* LPAR CPU */
862struct sysib_221 {
863 uint32_t res1[80];
864 uint8_t sequence[16];
865 uint8_t plant[4];
866 uint16_t cpu_id;
867 uint16_t cpu_addr;
868 uint8_t res3[152];
869};
870
871/* LPAR CPUs */
872struct sysib_222 {
873 uint32_t res1[32];
874 uint16_t lpar_num;
875 uint8_t res2;
876 uint8_t lcpuc;
877 uint16_t total_cpus;
878 uint16_t conf_cpus;
879 uint16_t standby_cpus;
880 uint16_t reserved_cpus;
881 uint8_t name[8];
882 uint32_t caf;
883 uint8_t res3[16];
884 uint16_t dedicated_cpus;
885 uint16_t shared_cpus;
886 uint8_t res4[180];
887};
888
889/* VM CPUs */
890struct sysib_322 {
891 uint8_t res1[31];
892 uint8_t count;
893 struct {
894 uint8_t res2[4];
895 uint16_t total_cpus;
896 uint16_t conf_cpus;
897 uint16_t standby_cpus;
898 uint16_t reserved_cpus;
899 uint8_t name[8];
900 uint32_t caf;
901 uint8_t cpi[16];
902 uint8_t res3[24];
903 } vm[8];
904 uint8_t res4[3552];
905};
906
907/* MMU defines */
908#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
909#define _ASCE_SUBSPACE 0x200 /* subspace group control */
910#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
911#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
912#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
913#define _ASCE_REAL_SPACE 0x20 /* real space control */
914#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
915#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
916#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
917#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
918#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
919#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
920
921#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
922#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
923#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
924#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
925#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
926#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
927#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
928
929#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 930#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG		 931#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
932#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
933
934#define _PAGE_RO 0x200 /* HW read-only bit */
935#define _PAGE_INVALID 0x400 /* HW invalid bit */
936
b9959138
AG		 937#define SK_C (0x1 << 1)
938#define SK_R (0x1 << 2)
939#define SK_F (0x1 << 3)
940#define SK_ACC_MASK (0xf << 4)
bcec36ea 941
bcec36ea
AG		 942#define SIGP_SENSE 0x01
943#define SIGP_EXTERNAL_CALL 0x02
944#define SIGP_EMERGENCY 0x03
945#define SIGP_START 0x04
946#define SIGP_STOP 0x05
947#define SIGP_RESTART 0x06
948#define SIGP_STOP_STORE_STATUS 0x09
949#define SIGP_INITIAL_CPU_RESET 0x0b
950#define SIGP_CPU_RESET 0x0c
951#define SIGP_SET_PREFIX 0x0d
952#define SIGP_STORE_STATUS_ADDR 0x0e
953#define SIGP_SET_ARCH 0x12
954
955/* cpu status bits */
956#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
957#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
958#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
959#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
960#define SIGP_STAT_STOPPED 0x00000040UL
961#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
962#define SIGP_STAT_CHECK_STOP 0x00000010UL
963#define SIGP_STAT_INOPERATIVE 0x00000004UL
964#define SIGP_STAT_INVALID_ORDER 0x00000002UL
965#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
966
a4e3ad19
AF		 967void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
968int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 969 target_ulong *raddr, int *flags);
6e252802 970int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 971uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 972 uint64_t vr);
973
974#define TARGET_HAS_ICE 1
975
976/* The value of the TOD clock for 1.1.1970. */
977#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
978
979/* Converts ns to s390's clock format */
980static inline uint64_t time2tod(uint64_t ns) {
981 return (ns << 9) / 125;
982}
983
f9466733 984static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 985 uint64_t param64)
986{
f9466733
AF		 987 CPUS390XState *env = &cpu->env;
988
bcec36ea
AG		 989 if (env->ext_index == MAX_EXT_QUEUE - 1) {
990 /* ugh - can't queue anymore. Let's drop. */
991 return;
992 }
993
994 env->ext_index++;
995 assert(env->ext_index < MAX_EXT_QUEUE);
996
997 env->ext_queue[env->ext_index].code = code;
998 env->ext_queue[env->ext_index].param = param;
999 env->ext_queue[env->ext_index].param64 = param64;
1000
1001 env->pending_int |= INTERRUPT_EXT;
c3affe56 1002 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 1003}
10c339a0 1004
f9466733 1005static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 1006 uint16_t subchannel_number,
1007 uint32_t io_int_parm, uint32_t io_int_word)
1008{
f9466733 1009 CPUS390XState *env = &cpu->env;
91b0a8f3 1010 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1011
1012 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1013 /* ugh - can't queue anymore. Let's drop. */
1014 return;
1015 }
1016
1017 env->io_index[isc]++;
1018 assert(env->io_index[isc] < MAX_IO_QUEUE);
1019
1020 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1021 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1022 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1023 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1024
1025 env->pending_int |= INTERRUPT_IO;
c3affe56 1026 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1027}
1028
f9466733 1029static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1030{
f9466733
AF		 1031 CPUS390XState *env = &cpu->env;
1032
5d69c547
CH		 1033 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1034 /* ugh - can't queue anymore. Let's drop. */
1035 return;
1036 }
1037
1038 env->mchk_index++;
1039 assert(env->mchk_index < MAX_MCHK_QUEUE);
1040
1041 env->mchk_queue[env->mchk_index].type = 1;
1042
1043 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1044 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1045}
1046
b6fe0124
MR		 1047/* from s390-virtio-ccw */
1048#define MEM_SECTION_SIZE 0x10000000UL
1def6656 1049#define MAX_AVAIL_SLOTS 32
b6fe0124 1050
e72ca652 1051/* fpu_helper.c */
e72ca652
BS		 1052uint32_t set_cc_nz_f32(float32 v);
1053uint32_t set_cc_nz_f64(float64 v);
587626f8 1054uint32_t set_cc_nz_f128(float128 v);
e72ca652 1055
aea1e885 1056/* misc_helper.c */
268846ba
ED		 1057#ifndef CONFIG_USER_ONLY
1058void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1059#endif
d5a103cd 1060void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1061void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1062 uintptr_t retaddr);
a78b0504 1063
09b99878 1064#ifdef CONFIG_KVM
de13d216 1065void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH		 1066 uint16_t subchannel_nr, uint32_t io_int_parm,
1067 uint32_t io_int_word);
de13d216 1068void kvm_s390_crw_mchk(void);
09b99878 1069void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1070int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1071 int vq, bool assign);
7f7f9752 1072int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1073int kvm_s390_get_memslot_count(KVMState *s);
4cb88c3c 1074void kvm_s390_clear_cmma_callback(void *opaque);
09b99878 1075#else
de13d216 1076static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH		 1077 uint16_t subchannel_nr,
1078 uint32_t io_int_parm,
1079 uint32_t io_int_word)
1080{
1081}
de13d216 1082static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH		 1083{
1084}
09b99878
CH		 1085static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1086{
1087}
cc3ac9c4
CH		 1088static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1089 uint32_t sch, int vq,
b4436a0b
CH		 1090 bool assign)
1091{
1092 return -ENOSYS;
1093}
7f7f9752
ED		 1094static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1095{
1096 return -ENOSYS;
1097}
4cb88c3c
DD		 1098static inline void kvm_s390_clear_cmma_callback(void *opaque)
1099{
1100}
1def6656
MR		 1101static inline int kvm_s390_get_memslot_count(KVMState *s)
1102{
1103 return MAX_AVAIL_SLOTS;
1104}
09b99878 1105#endif
df1fe5bb 1106
4cb88c3c
DD		 1107static inline void cmma_reset(S390CPU *cpu)
1108{
1109 if (kvm_enabled()) {
1110 CPUState *cs = CPU(cpu);
1111 kvm_s390_clear_cmma_callback(cs->kvm_state);
1112 }
1113}
1114
7f7f9752
ED		 1115static inline int s390_cpu_restart(S390CPU *cpu)
1116{
1117 if (kvm_enabled()) {
1118 return kvm_s390_cpu_restart(cpu);
1119 }
1120 return -ENOSYS;
1121}
1122
1def6656
MR		 1123static inline int s390_get_memslot_count(KVMState *s)
1124{
1125 if (kvm_enabled()) {
1126 return kvm_s390_get_memslot_count(s);
1127 } else {
1128 return MAX_AVAIL_SLOTS;
1129 }
1130}
1131
de13d216
CH		 1132void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1133 uint32_t io_int_parm, uint32_t io_int_word);
1134void s390_crw_mchk(void);
df1fe5bb 1135
cc3ac9c4
CH		 1136static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1137 uint32_t sch_id, int vq,
b4436a0b
CH		 1138 bool assign)
1139{
1140 if (kvm_enabled()) {
cc3ac9c4 1141 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1142 } else {
1143 return -ENOSYS;
1144 }
1145}
1146
10ec5117 1147#endif
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