[qemu.git] / hw / i386 / q35-acpi-dsdt.dsl

/*
 * Bochs/QEMU ACPI DSDT ASL definition
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
/*
 * Copyright (c) 2010 Isaku Yamahata
 *                    yamahata at valinux co jp
 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
 */

ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode

DefinitionBlock (
    "q35-acpi-dsdt.aml",// Output Filename
    "DSDT",             // Signature
    0x01,               // DSDT Compliance Revision
    "BXPC",             // OEMID
    "BXDSDT",           // TABLE ID
    0x2                 // OEM Revision
    )
{

#include "acpi-dsdt-dbug.dsl"

    Scope(\_SB) {
        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
            PCIB, 8,
        }
    }


/****************************************************************
 * PCI Bus definition
 ****************************************************************/
#define BOARD_SPECIFIC_PCI_RESOURSES \
     WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
         0x0000, \
         0x0000, \
         0x0CD7, \
         0x0000, \
         0x0CD8, \
         ,, , TypeStatic) \
     /* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
     WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
         0x0000, \
         0x0D00, \
         0xFFFF, \
         0x0000, \
         0xF300, \
         ,, , TypeStatic)

    Scope(\_SB) {
        Device(PCI0) {
            Name(_HID, EisaId("PNP0A08"))
            Name(_CID, EisaId("PNP0A03"))
            Name(_ADR, 0x00)
            Name(_UID, 1)

            // _OSC: based on sample of ACPI3.0b spec
            Name(SUPP, 0) // PCI _OSC Support Field value
            Name(CTRL, 0) // PCI _OSC Control Field value
            Method(_OSC, 4) {
                // Create DWORD-addressable fields from the Capabilities Buffer
                CreateDWordField(Arg3, 0, CDW1)

                // Check for proper UUID
                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
                    // Create DWORD-addressable fields from the Capabilities Buffer
                    CreateDWordField(Arg3, 4, CDW2)
                    CreateDWordField(Arg3, 8, CDW3)

                    // Save Capabilities DWORD2 & 3
                    Store(CDW2, SUPP)
                    Store(CDW3, CTRL)

                    // Always allow native PME, AER (no dependencies)
                    // Never allow SHPC (no SHPC controller in this system)
                    And(CTRL, 0x1D, CTRL)

#if 0 // For now, nothing to do
                    If (Not(And(CDW1, 1))) { // Query flag clear?
                        // Disable GPEs for features granted native control.
                        If (And(CTRL, 0x01)) { // Hot plug control granted?
                            Store(0, HPCE) // clear the hot plug SCI enable bit
                            Store(1, HPCS) // clear the hot plug SCI status bit
                        }
                        If (And(CTRL, 0x04)) { // PME control granted?
                            Store(0, PMCE) // clear the PME SCI enable bit
                            Store(1, PMCS) // clear the PME SCI status bit
                        }
                        If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
                            // Set status to not restore PCI Express cap structure
                            // upon resume from S3
                            Store(1, S3CR)
                        }
                    }
#endif
                    If (LNotEqual(Arg1, One)) {
                        // Unknown revision
                        Or(CDW1, 0x08, CDW1)
                    }
                    If (LNotEqual(CDW3, CTRL)) {
                        // Capabilities bits were masked
                        Or(CDW1, 0x10, CDW1)
                    }
                    // Update DWORD3 in the buffer
                    Store(CTRL, CDW3)
                } Else {
                    Or(CDW1, 4, CDW1) // Unrecognized UUID
                }
                Return (Arg3)
            }
        }
    }

#include "acpi-dsdt-pci-crs.dsl"
#include "acpi-dsdt-hpet.dsl"


/****************************************************************
 * VGA
 ****************************************************************/

    Scope(\_SB.PCI0) {
        Device(VGA) {
            Name(_ADR, 0x00010000)
            Method(_S1D, 0, NotSerialized) {
                Return (0x00)
            }
            Method(_S2D, 0, NotSerialized) {
                Return (0x00)
            }
            Method(_S3D, 0, NotSerialized) {
                Return (0x00)
            }
        }
    }


/****************************************************************
 * LPC ISA bridge
 ****************************************************************/

    Scope(\_SB.PCI0) {
        /* PCI D31:f0 LPC ISA bridge */
        Device(ISA) {
            /* PCI D31:f0 */
            Name(_ADR, 0x001f0000)

            /* ICH9 PCI to ISA irq remapping */
            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)

            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
            Field(LPCD, AnyAcc, NoLock, Preserve) {
                COMA,   3,
                    ,   1,
                COMB,   3,

                Offset(0x01),
                LPTD,   2,
                    ,   2,
                FDCD,   2
            }
            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
            Field(LPCE, AnyAcc, NoLock, Preserve) {
                CAEN,   1,
                CBEN,   1,
                LPEN,   1,
                FDEN,   1
            }
        }
    }

#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"


/****************************************************************
 * PCI IRQs
 ****************************************************************/

    /* Zero => PIC mode, One => APIC Mode */
    Name(\PICF, Zero)
    Method(\_PIC, 1, NotSerialized) {
        Store(Arg0, \PICF)
    }

    Scope(\_SB) {
        Scope(PCI0) {
#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
    Package() { nr##ffff, 0, lnk0, 0 },           \
    Package() { nr##ffff, 1, lnk1, 0 },           \
    Package() { nr##ffff, 2, lnk2, 0 },           \
    Package() { nr##ffff, 3, lnk3, 0 }

#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)

#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)

            Name(PRTP, package() {
                prt_slot_lnkE(0x0000),
                prt_slot_lnkF(0x0001),
                prt_slot_lnkG(0x0002),
                prt_slot_lnkH(0x0003),
                prt_slot_lnkE(0x0004),
                prt_slot_lnkF(0x0005),
                prt_slot_lnkG(0x0006),
                prt_slot_lnkH(0x0007),
                prt_slot_lnkE(0x0008),
                prt_slot_lnkF(0x0009),
                prt_slot_lnkG(0x000a),
                prt_slot_lnkH(0x000b),
                prt_slot_lnkE(0x000c),
                prt_slot_lnkF(0x000d),
                prt_slot_lnkG(0x000e),
                prt_slot_lnkH(0x000f),
                prt_slot_lnkE(0x0010),
                prt_slot_lnkF(0x0011),
                prt_slot_lnkG(0x0012),
                prt_slot_lnkH(0x0013),
                prt_slot_lnkE(0x0014),
                prt_slot_lnkF(0x0015),
                prt_slot_lnkG(0x0016),
                prt_slot_lnkH(0x0017),
                prt_slot_lnkE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31
                   see the default value of D<N>IR */
                prt_slot_lnkA(0x0019),
                prt_slot_lnkA(0x001a),
                prt_slot_lnkA(0x001b),
                prt_slot_lnkA(0x001c),
                prt_slot_lnkA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_lnkE(0x001e),

                prt_slot_lnkA(0x001f)
            })

#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
    Package() { nr##ffff, 0, gsi0, 0 },           \
    Package() { nr##ffff, 1, gsi1, 0 },           \
    Package() { nr##ffff, 2, gsi2, 0 },           \
    Package() { nr##ffff, 3, gsi3, 0 }

#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)

#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)

            Name(PRTA, package() {
                prt_slot_gsiE(0x0000),
                prt_slot_gsiF(0x0001),
                prt_slot_gsiG(0x0002),
                prt_slot_gsiH(0x0003),
                prt_slot_gsiE(0x0004),
                prt_slot_gsiF(0x0005),
                prt_slot_gsiG(0x0006),
                prt_slot_gsiH(0x0007),
                prt_slot_gsiE(0x0008),
                prt_slot_gsiF(0x0009),
                prt_slot_gsiG(0x000a),
                prt_slot_gsiH(0x000b),
                prt_slot_gsiE(0x000c),
                prt_slot_gsiF(0x000d),
                prt_slot_gsiG(0x000e),
                prt_slot_gsiH(0x000f),
                prt_slot_gsiE(0x0010),
                prt_slot_gsiF(0x0011),
                prt_slot_gsiG(0x0012),
                prt_slot_gsiH(0x0013),
                prt_slot_gsiE(0x0014),
                prt_slot_gsiF(0x0015),
                prt_slot_gsiG(0x0016),
                prt_slot_gsiH(0x0017),
                prt_slot_gsiE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31, but 30
                   see the default value of D<N>IR */
                prt_slot_gsiA(0x0019),
                prt_slot_gsiA(0x001a),
                prt_slot_gsiA(0x001b),
                prt_slot_gsiA(0x001c),
                prt_slot_gsiA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_gsiE(0x001e),

                prt_slot_gsiA(0x001f)
            })

            Method(_PRT, 0, NotSerialized) {
                /* PCI IRQ routing table, example from ACPI 2.0a specification,
                   section 6.2.8.1 */
                /* Note: we provide the same info as the PCI routing
                   table of the Bochs BIOS */
                If (LEqual(\PICF, Zero)) {
                    Return (PRTP)
                } Else {
                    Return (PRTA)
                }
            }
        }

        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
            PRQA,   8,
            PRQB,   8,
            PRQC,   8,
            PRQD,   8,

            Offset(0x08),
            PRQE,   8,
            PRQF,   8,
            PRQG,   8,
            PRQH,   8
        }

        Method(IQST, 1, NotSerialized) {
            // _STA method - get status
            If (And(0x80, Arg0)) {
                Return (0x09)
            }
            Return (0x0B)
        }
        Method(IQCR, 1, Serialized) {
            // _CRS method - get current settings
            Name(PRR0, ResourceTemplate() {
                Interrupt(, Level, ActiveHigh, Shared) { 0 }
            })
            CreateDWordField(PRR0, 0x05, PRRI)
            Store(And(Arg0, 0x0F), PRRI)
            Return (PRR0)
        }

#define define_link(link, uid, reg)                             \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    5, 10, 11                                   \
                }                                               \
            })                                                  \
            Method(_STA, 0, NotSerialized) {                    \
                Return (IQST(reg))                              \
            }                                                   \
            Method(_DIS, 0, NotSerialized) {                    \
                Or(reg, 0x80, reg)                              \
            }                                                   \
            Method(_CRS, 0, NotSerialized) {                    \
                Return (IQCR(reg))                              \
            }                                                   \
            Method(_SRS, 1, NotSerialized) {                    \
                CreateDWordField(Arg0, 0x05, PRRI)              \
                Store(PRRI, reg)                                \
            }                                                   \
        }

        define_link(LNKA, 0, PRQA)
        define_link(LNKB, 1, PRQB)
        define_link(LNKC, 2, PRQC)
        define_link(LNKD, 3, PRQD)
        define_link(LNKE, 4, PRQE)
        define_link(LNKF, 5, PRQF)
        define_link(LNKG, 6, PRQG)
        define_link(LNKH, 7, PRQH)

#define define_gsi_link(link, uid, gsi)                         \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Name(_CRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Method(_SRS, 1, NotSerialized) {                    \
            }                                                   \
        }

        define_gsi_link(GSIA, 0, 0x10)
        define_gsi_link(GSIB, 0, 0x11)
        define_gsi_link(GSIC, 0, 0x12)
        define_gsi_link(GSID, 0, 0x13)
        define_gsi_link(GSIE, 0, 0x14)
        define_gsi_link(GSIF, 0, 0x15)
        define_gsi_link(GSIG, 0, 0x16)
        define_gsi_link(GSIH, 0, 0x17)
    }

#include "hw/acpi/cpu_hotplug_defs.h"
#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
#include "acpi-dsdt-cpu-hotplug.dsl"


/****************************************************************
 * General purpose events
 ****************************************************************/

    Scope(\_GPE) {
        Name(_HID, "ACPI0006")

        Method(_L00) {
        }
        Method(_L01) {
        }
        Method(_E02) {
            // CPU hotplug event
            \_SB.PRSC()
        }
        Method(_L03) {
        }
        Method(_L04) {
        }
        Method(_L05) {
        }
        Method(_L06) {
        }
        Method(_L07) {
        }
        Method(_L08) {
        }
        Method(_L09) {
        }
        Method(_L0A) {
        }
        Method(_L0B) {
        }
        Method(_L0C) {
        }
        Method(_L0D) {
        }
        Method(_L0E) {
        }
        Method(_L0F) {
        }
    }
}
Commit	Line	Data
74523b85 MT	1	/*
	2	* Bochs/QEMU ACPI DSDT ASL definition
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	18	*/
	19	/*
	20	* Copyright (c) 2010 Isaku Yamahata
	21	* yamahata at valinux co jp
	22	* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
	23	*/
	24
	25	ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
	26
	27	DefinitionBlock (
	28	"q35-acpi-dsdt.aml",// Output Filename
	29	"DSDT", // Signature
	30	0x01, // DSDT Compliance Revision
	31	"BXPC", // OEMID
	32	"BXDSDT", // TABLE ID
	33	0x2 // OEM Revision
	34	)
	35	{
	36
	37	#include "acpi-dsdt-dbug.dsl"
	38
	39	Scope(\_SB) {
	40	OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
	41	OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
	42	Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
	43	PCIB, 8,
	44	}
	45	}
	46
	47
	48	/****************************************************************
	49	* PCI Bus definition
	50	****************************************************************/
1aa149b4	51	#define BOARD_SPECIFIC_PCI_RESOURSES \
562e56a9 IM	52	WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
	53	0x0000, \
	54	0x0000, \
	55	0x0CD7, \
	56	0x0000, \
	57	0x0CD8, \
	58	,, , TypeStatic) \
	59	/* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
1aa149b4 IM	60	WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
	61	0x0000, \
	62	0x0D00, \
	63	0xFFFF, \
	64	0x0000, \
	65	0xF300, \
	66	,, , TypeStatic)
74523b85 MT	67
	68	Scope(\_SB) {
	69	Device(PCI0) {
	70	Name(_HID, EisaId("PNP0A08"))
	71	Name(_CID, EisaId("PNP0A03"))
	72	Name(_ADR, 0x00)
	73	Name(_UID, 1)
	74
	75	// _OSC: based on sample of ACPI3.0b spec
	76	Name(SUPP, 0) // PCI _OSC Support Field value
	77	Name(CTRL, 0) // PCI _OSC Control Field value
	78	Method(_OSC, 4) {
	79	// Create DWORD-addressable fields from the Capabilities Buffer
	80	CreateDWordField(Arg3, 0, CDW1)
	81
	82	// Check for proper UUID
	83	If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
	84	// Create DWORD-addressable fields from the Capabilities Buffer
	85	CreateDWordField(Arg3, 4, CDW2)
	86	CreateDWordField(Arg3, 8, CDW3)
	87
	88	// Save Capabilities DWORD2 & 3
	89	Store(CDW2, SUPP)
	90	Store(CDW3, CTRL)
	91
	92	// Always allow native PME, AER (no dependencies)
	93	// Never allow SHPC (no SHPC controller in this system)
	94	And(CTRL, 0x1D, CTRL)
	95
	96	#if 0 // For now, nothing to do
	97	If (Not(And(CDW1, 1))) { // Query flag clear?
	98	// Disable GPEs for features granted native control.
	99	If (And(CTRL, 0x01)) { // Hot plug control granted?
	100	Store(0, HPCE) // clear the hot plug SCI enable bit
	101	Store(1, HPCS) // clear the hot plug SCI status bit
	102	}
	103	If (And(CTRL, 0x04)) { // PME control granted?
	104	Store(0, PMCE) // clear the PME SCI enable bit
	105	Store(1, PMCS) // clear the PME SCI status bit
	106	}
	107	If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
	108	// Set status to not restore PCI Express cap structure
	109	// upon resume from S3
	110	Store(1, S3CR)
	111	}
	112	}
	113	#endif
	114	If (LNotEqual(Arg1, One)) {
	115	// Unknown revision
	116	Or(CDW1, 0x08, CDW1)
	117	}
	118	If (LNotEqual(CDW3, CTRL)) {
	119	// Capabilities bits were masked
	120	Or(CDW1, 0x10, CDW1)
	121	}
	122	// Update DWORD3 in the buffer
	123	Store(CTRL, CDW3)
	124	} Else {
	125	Or(CDW1, 4, CDW1) // Unrecognized UUID
	126	}
	127	Return (Arg3)
	128	}
	129	}
	130	}
131
132	#include "acpi-dsdt-pci-crs.dsl"
133	#include "acpi-dsdt-hpet.dsl"
134
135
136	/****************************************************************
137	* VGA
138	****************************************************************/
139
140	Scope(\_SB.PCI0) {
141	Device(VGA) {
142	Name(_ADR, 0x00010000)
143	Method(_S1D, 0, NotSerialized) {
144	Return (0x00)
145	}
146	Method(_S2D, 0, NotSerialized) {
147	Return (0x00)
148	}
149	Method(_S3D, 0, NotSerialized) {
150	Return (0x00)
151	}
152	}
153	}
154
155
156	/****************************************************************
157	* LPC ISA bridge
158	****************************************************************/
159
160	Scope(\_SB.PCI0) {
161	/* PCI D31:f0 LPC ISA bridge */
162	Device(ISA) {
163	/* PCI D31:f0 */
164	Name(_ADR, 0x001f0000)
165
166	/* ICH9 PCI to ISA irq remapping */
167	OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
168
169	OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
170	Field(LPCD, AnyAcc, NoLock, Preserve) {
171	COMA, 3,
172	, 1,
173	COMB, 3,
174
175	Offset(0x01),
176	LPTD, 2,
177	, 2,
178	FDCD, 2
179	}
180	OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
181	Field(LPCE, AnyAcc, NoLock, Preserve) {
182	CAEN, 1,
183	CBEN, 1,
184	LPEN, 1,
185	FDEN, 1
186	}
187	}
188	}
189
15bce1b7	190	#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
74523b85 MT	191	#include "acpi-dsdt-isa.dsl"
	192
	193
	194	/****************************************************************
	195	* PCI IRQs
	196	****************************************************************/
	197
	198	/* Zero => PIC mode, One => APIC Mode */
	199	Name(\PICF, Zero)
	200	Method(\_PIC, 1, NotSerialized) {
	201	Store(Arg0, \PICF)
	202	}
	203
	204	Scope(\_SB) {
	205	Scope(PCI0) {
	206	#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
	207	Package() { nr##ffff, 0, lnk0, 0 }, \
	208	Package() { nr##ffff, 1, lnk1, 0 }, \
	209	Package() { nr##ffff, 2, lnk2, 0 }, \
	210	Package() { nr##ffff, 3, lnk3, 0 }
	211
	212	#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
	213	#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
	214	#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
	215	#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
	216
	217	#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
	218	#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
	219	#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
	220	#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
	221
	222	Name(PRTP, package() {
	223	prt_slot_lnkE(0x0000),
	224	prt_slot_lnkF(0x0001),
	225	prt_slot_lnkG(0x0002),
	226	prt_slot_lnkH(0x0003),
	227	prt_slot_lnkE(0x0004),
	228	prt_slot_lnkF(0x0005),
	229	prt_slot_lnkG(0x0006),
	230	prt_slot_lnkH(0x0007),
	231	prt_slot_lnkE(0x0008),
	232	prt_slot_lnkF(0x0009),
	233	prt_slot_lnkG(0x000a),
	234	prt_slot_lnkH(0x000b),
	235	prt_slot_lnkE(0x000c),
	236	prt_slot_lnkF(0x000d),
	237	prt_slot_lnkG(0x000e),
	238	prt_slot_lnkH(0x000f),
	239	prt_slot_lnkE(0x0010),
	240	prt_slot_lnkF(0x0011),
	241	prt_slot_lnkG(0x0012),
	242	prt_slot_lnkH(0x0013),
	243	prt_slot_lnkE(0x0014),
	244	prt_slot_lnkF(0x0015),
	245	prt_slot_lnkG(0x0016),
	246	prt_slot_lnkH(0x0017),
	247	prt_slot_lnkE(0x0018),
	248
	249	/* INTA -> PIRQA for slot 25 - 31
	250	see the default value of D<N>IR */
	251	prt_slot_lnkA(0x0019),
	252	prt_slot_lnkA(0x001a),
	253	prt_slot_lnkA(0x001b),
	254	prt_slot_lnkA(0x001c),
255	prt_slot_lnkA(0x001d),
256
257	/* PCIe->PCI bridge. use PIRQ[E-H] */
258	prt_slot_lnkE(0x001e),
259
260	prt_slot_lnkA(0x001f)
261	})
262
263	#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
264	Package() { nr##ffff, 0, gsi0, 0 }, \
265	Package() { nr##ffff, 1, gsi1, 0 }, \
266	Package() { nr##ffff, 2, gsi2, 0 }, \
267	Package() { nr##ffff, 3, gsi3, 0 }
268
269	#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
270	#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
271	#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
272	#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
273
274	#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
275	#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
276	#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
277	#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
278
279	Name(PRTA, package() {
280	prt_slot_gsiE(0x0000),
281	prt_slot_gsiF(0x0001),
282	prt_slot_gsiG(0x0002),
283	prt_slot_gsiH(0x0003),
284	prt_slot_gsiE(0x0004),
285	prt_slot_gsiF(0x0005),
286	prt_slot_gsiG(0x0006),
287	prt_slot_gsiH(0x0007),
288	prt_slot_gsiE(0x0008),
289	prt_slot_gsiF(0x0009),
290	prt_slot_gsiG(0x000a),
291	prt_slot_gsiH(0x000b),
292	prt_slot_gsiE(0x000c),
293	prt_slot_gsiF(0x000d),
294	prt_slot_gsiG(0x000e),
295	prt_slot_gsiH(0x000f),
296	prt_slot_gsiE(0x0010),
297	prt_slot_gsiF(0x0011),
298	prt_slot_gsiG(0x0012),
299	prt_slot_gsiH(0x0013),
300	prt_slot_gsiE(0x0014),
301	prt_slot_gsiF(0x0015),
302	prt_slot_gsiG(0x0016),
303	prt_slot_gsiH(0x0017),
304	prt_slot_gsiE(0x0018),
305
306	/* INTA -> PIRQA for slot 25 - 31, but 30
307	see the default value of D<N>IR */
308	prt_slot_gsiA(0x0019),
309	prt_slot_gsiA(0x001a),
310	prt_slot_gsiA(0x001b),
311	prt_slot_gsiA(0x001c),
312	prt_slot_gsiA(0x001d),
313
314	/* PCIe->PCI bridge. use PIRQ[E-H] */
315	prt_slot_gsiE(0x001e),
316
317	prt_slot_gsiA(0x001f)
318	})
319
320	Method(_PRT, 0, NotSerialized) {
321	/* PCI IRQ routing table, example from ACPI 2.0a specification,
322	section 6.2.8.1 */
323	/* Note: we provide the same info as the PCI routing
324	table of the Bochs BIOS */
325	If (LEqual(\PICF, Zero)) {
326	Return (PRTP)
327	} Else {
328	Return (PRTA)
329	}
330	}
331	}
332
333	Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
334	PRQA, 8,
335	PRQB, 8,
336	PRQC, 8,
337	PRQD, 8,
338
339	Offset(0x08),
340	PRQE, 8,
341	PRQF, 8,
342	PRQG, 8,
343	PRQH, 8
344	}
345
346	Method(IQST, 1, NotSerialized) {
347	// _STA method - get status
348	If (And(0x80, Arg0)) {
349	Return (0x09)
350	}
351	Return (0x0B)
352	}
6b9b4405	353	Method(IQCR, 1, Serialized) {
74523b85 MT	354	// _CRS method - get current settings
	355	Name(PRR0, ResourceTemplate() {
	356	Interrupt(, Level, ActiveHigh, Shared) { 0 }
	357	})
	358	CreateDWordField(PRR0, 0x05, PRRI)
	359	Store(And(Arg0, 0x0F), PRRI)
	360	Return (PRR0)
	361	}
	362
	363	#define define_link(link, uid, reg) \
	364	Device(link) { \
	365	Name(_HID, EISAID("PNP0C0F")) \
	366	Name(_UID, uid) \
	367	Name(_PRS, ResourceTemplate() { \
	368	Interrupt(, Level, ActiveHigh, Shared) { \
	369	5, 10, 11 \
	370	} \
	371	}) \
	372	Method(_STA, 0, NotSerialized) { \
	373	Return (IQST(reg)) \
	374	} \
	375	Method(_DIS, 0, NotSerialized) { \
	376	Or(reg, 0x80, reg) \
	377	} \
	378	Method(_CRS, 0, NotSerialized) { \
	379	Return (IQCR(reg)) \
	380	} \
	381	Method(_SRS, 1, NotSerialized) { \
	382	CreateDWordField(Arg0, 0x05, PRRI) \
	383	Store(PRRI, reg) \
	384	} \
	385	}
	386
	387	define_link(LNKA, 0, PRQA)
	388	define_link(LNKB, 1, PRQB)
	389	define_link(LNKC, 2, PRQC)
	390	define_link(LNKD, 3, PRQD)
	391	define_link(LNKE, 4, PRQE)
	392	define_link(LNKF, 5, PRQF)
	393	define_link(LNKG, 6, PRQG)
	394	define_link(LNKH, 7, PRQH)
	395
	396	#define define_gsi_link(link, uid, gsi) \
	397	Device(link) { \
	398	Name(_HID, EISAID("PNP0C0F")) \
	399	Name(_UID, uid) \
	400	Name(_PRS, ResourceTemplate() { \
	401	Interrupt(, Level, ActiveHigh, Shared) { \
	402	gsi \
	403	} \
	404	}) \
	405	Name(_CRS, ResourceTemplate() { \
	406	Interrupt(, Level, ActiveHigh, Shared) { \
	407	gsi \
	408	} \
	409	}) \
	410	Method(_SRS, 1, NotSerialized) { \
	411	} \
	412	}
	413
	414	define_gsi_link(GSIA, 0, 0x10)
	415	define_gsi_link(GSIB, 0, 0x11)
	416	define_gsi_link(GSIC, 0, 0x12)
	417	define_gsi_link(GSID, 0, 0x13)
418	define_gsi_link(GSIE, 0, 0x14)
419	define_gsi_link(GSIF, 0, 0x15)
420	define_gsi_link(GSIG, 0, 0x16)
421	define_gsi_link(GSIH, 0, 0x17)
422	}
423
e4cf8ed0 IM	424	#include "hw/acpi/cpu_hotplug_defs.h"
e4cf8ed0 IM	425	#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
74523b85 MT	426	#include "acpi-dsdt-cpu-hotplug.dsl"
	427
	428
	429	/****************************************************************
	430	* General purpose events
	431	****************************************************************/
	432
	433	Scope(\_GPE) {
	434	Name(_HID, "ACPI0006")
	435
	436	Method(_L00) {
	437	}
	438	Method(_L01) {
c1a1af87 IM	439	}
c1a1af87 IM	440	Method(_E02) {
74523b85 MT	441	// CPU hotplug event
	442	\_SB.PRSC()
	443	}
74523b85 MT	444	Method(_L03) {
	445	}
	446	Method(_L04) {
	447	}
	448	Method(_L05) {
	449	}
	450	Method(_L06) {
	451	}
	452	Method(_L07) {
	453	}
	454	Method(_L08) {
	455	}
	456	Method(_L09) {
	457	}
	458	Method(_L0A) {
	459	}
	460	Method(_L0B) {
	461	}
	462	Method(_L0C) {
	463	}
	464	Method(_L0D) {
	465	}
	466	Method(_L0E) {
	467	}
	468	Method(_L0F) {
	469	}
	470	}
	471	}