[qemu.git] / hw / i386 / q35-acpi-dsdt.dsl

/*
 * Bochs/QEMU ACPI DSDT ASL definition
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
/*
 * Copyright (c) 2010 Isaku Yamahata
 *                    yamahata at valinux co jp
 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
 */

ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode

DefinitionBlock (
    "q35-acpi-dsdt.aml",// Output Filename
    "DSDT",             // Signature
    0x01,               // DSDT Compliance Revision
    "BXPC",             // OEMID
    "BXDSDT",           // TABLE ID
    0x2                 // OEM Revision
    )
{

#include "acpi-dsdt-dbug.dsl"

    Scope(\_SB) {
        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
            PCIB, 8,
        }
    }


/****************************************************************
 * PCI Bus definition
 ****************************************************************/

    Scope(\_SB) {
        Device(PCI0) {
            Name(_HID, EisaId("PNP0A08"))
            Name(_CID, EisaId("PNP0A03"))
            Name(_ADR, 0x00)
            Name(_UID, 1)

            // _OSC: based on sample of ACPI3.0b spec
            Name(SUPP, 0) // PCI _OSC Support Field value
            Name(CTRL, 0) // PCI _OSC Control Field value
            Method(_OSC, 4) {
                // Create DWORD-addressable fields from the Capabilities Buffer
                CreateDWordField(Arg3, 0, CDW1)

                // Check for proper UUID
                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
                    // Create DWORD-addressable fields from the Capabilities Buffer
                    CreateDWordField(Arg3, 4, CDW2)
                    CreateDWordField(Arg3, 8, CDW3)

                    // Save Capabilities DWORD2 & 3
                    Store(CDW2, SUPP)
                    Store(CDW3, CTRL)

                    // Always allow native PME, AER (no dependencies)
                    // Never allow SHPC (no SHPC controller in this system)
                    And(CTRL, 0x1D, CTRL)

#if 0 // For now, nothing to do
                    If (Not(And(CDW1, 1))) { // Query flag clear?
                        // Disable GPEs for features granted native control.
                        If (And(CTRL, 0x01)) { // Hot plug control granted?
                            Store(0, HPCE) // clear the hot plug SCI enable bit
                            Store(1, HPCS) // clear the hot plug SCI status bit
                        }
                        If (And(CTRL, 0x04)) { // PME control granted?
                            Store(0, PMCE) // clear the PME SCI enable bit
                            Store(1, PMCS) // clear the PME SCI status bit
                        }
                        If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
                            // Set status to not restore PCI Express cap structure
                            // upon resume from S3
                            Store(1, S3CR)
                        }
                    }
#endif
                    If (LNotEqual(Arg1, One)) {
                        // Unknown revision
                        Or(CDW1, 0x08, CDW1)
                    }
                    If (LNotEqual(CDW3, CTRL)) {
                        // Capabilities bits were masked
                        Or(CDW1, 0x10, CDW1)
                    }
                    // Update DWORD3 in the buffer
                    Store(CTRL, CDW3)
                } Else {
                    Or(CDW1, 4, CDW1) // Unrecognized UUID
                }
                Return (Arg3)
            }
        }
    }

#include "acpi-dsdt-pci-crs.dsl"
#include "acpi-dsdt-hpet.dsl"


/****************************************************************
 * VGA
 ****************************************************************/

    Scope(\_SB.PCI0) {
        Device(VGA) {
            Name(_ADR, 0x00010000)
            Method(_S1D, 0, NotSerialized) {
                Return (0x00)
            }
            Method(_S2D, 0, NotSerialized) {
                Return (0x00)
            }
            Method(_S3D, 0, NotSerialized) {
                Return (0x00)
            }
        }
    }


/****************************************************************
 * LPC ISA bridge
 ****************************************************************/

    Scope(\_SB.PCI0) {
        /* PCI D31:f0 LPC ISA bridge */
        Device(ISA) {
            /* PCI D31:f0 */
            Name(_ADR, 0x001f0000)

            /* ICH9 PCI to ISA irq remapping */
            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)

            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
            Field(LPCD, AnyAcc, NoLock, Preserve) {
                COMA,   3,
                    ,   1,
                COMB,   3,

                Offset(0x01),
                LPTD,   2,
                    ,   2,
                FDCD,   2
            }
            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
            Field(LPCE, AnyAcc, NoLock, Preserve) {
                CAEN,   1,
                CBEN,   1,
                LPEN,   1,
                FDEN,   1
            }
        }
    }

#include "acpi-dsdt-isa.dsl"


/****************************************************************
 * PCI IRQs
 ****************************************************************/

    /* Zero => PIC mode, One => APIC Mode */
    Name(\PICF, Zero)
    Method(\_PIC, 1, NotSerialized) {
        Store(Arg0, \PICF)
    }

    Scope(\_SB) {
        Scope(PCI0) {
#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
    Package() { nr##ffff, 0, lnk0, 0 },           \
    Package() { nr##ffff, 1, lnk1, 0 },           \
    Package() { nr##ffff, 2, lnk2, 0 },           \
    Package() { nr##ffff, 3, lnk3, 0 }

#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)

#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)

            Name(PRTP, package() {
                prt_slot_lnkE(0x0000),
                prt_slot_lnkF(0x0001),
                prt_slot_lnkG(0x0002),
                prt_slot_lnkH(0x0003),
                prt_slot_lnkE(0x0004),
                prt_slot_lnkF(0x0005),
                prt_slot_lnkG(0x0006),
                prt_slot_lnkH(0x0007),
                prt_slot_lnkE(0x0008),
                prt_slot_lnkF(0x0009),
                prt_slot_lnkG(0x000a),
                prt_slot_lnkH(0x000b),
                prt_slot_lnkE(0x000c),
                prt_slot_lnkF(0x000d),
                prt_slot_lnkG(0x000e),
                prt_slot_lnkH(0x000f),
                prt_slot_lnkE(0x0010),
                prt_slot_lnkF(0x0011),
                prt_slot_lnkG(0x0012),
                prt_slot_lnkH(0x0013),
                prt_slot_lnkE(0x0014),
                prt_slot_lnkF(0x0015),
                prt_slot_lnkG(0x0016),
                prt_slot_lnkH(0x0017),
                prt_slot_lnkE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31
                   see the default value of D<N>IR */
                prt_slot_lnkA(0x0019),
                prt_slot_lnkA(0x001a),
                prt_slot_lnkA(0x001b),
                prt_slot_lnkA(0x001c),
                prt_slot_lnkA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_lnkE(0x001e),

                prt_slot_lnkA(0x001f)
            })

#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
    Package() { nr##ffff, 0, gsi0, 0 },           \
    Package() { nr##ffff, 1, gsi1, 0 },           \
    Package() { nr##ffff, 2, gsi2, 0 },           \
    Package() { nr##ffff, 3, gsi3, 0 }

#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)

#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)

            Name(PRTA, package() {
                prt_slot_gsiE(0x0000),
                prt_slot_gsiF(0x0001),
                prt_slot_gsiG(0x0002),
                prt_slot_gsiH(0x0003),
                prt_slot_gsiE(0x0004),
                prt_slot_gsiF(0x0005),
                prt_slot_gsiG(0x0006),
                prt_slot_gsiH(0x0007),
                prt_slot_gsiE(0x0008),
                prt_slot_gsiF(0x0009),
                prt_slot_gsiG(0x000a),
                prt_slot_gsiH(0x000b),
                prt_slot_gsiE(0x000c),
                prt_slot_gsiF(0x000d),
                prt_slot_gsiG(0x000e),
                prt_slot_gsiH(0x000f),
                prt_slot_gsiE(0x0010),
                prt_slot_gsiF(0x0011),
                prt_slot_gsiG(0x0012),
                prt_slot_gsiH(0x0013),
                prt_slot_gsiE(0x0014),
                prt_slot_gsiF(0x0015),
                prt_slot_gsiG(0x0016),
                prt_slot_gsiH(0x0017),
                prt_slot_gsiE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31, but 30
                   see the default value of D<N>IR */
                prt_slot_gsiA(0x0019),
                prt_slot_gsiA(0x001a),
                prt_slot_gsiA(0x001b),
                prt_slot_gsiA(0x001c),
                prt_slot_gsiA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_gsiE(0x001e),

                prt_slot_gsiA(0x001f)
            })

            Method(_PRT, 0, NotSerialized) {
                /* PCI IRQ routing table, example from ACPI 2.0a specification,
                   section 6.2.8.1 */
                /* Note: we provide the same info as the PCI routing
                   table of the Bochs BIOS */
                If (LEqual(\PICF, Zero)) {
                    Return (PRTP)
                } Else {
                    Return (PRTA)
                }
            }
        }

        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
            PRQA,   8,
            PRQB,   8,
            PRQC,   8,
            PRQD,   8,

            Offset(0x08),
            PRQE,   8,
            PRQF,   8,
            PRQG,   8,
            PRQH,   8
        }

        Method(IQST, 1, NotSerialized) {
            // _STA method - get status
            If (And(0x80, Arg0)) {
                Return (0x09)
            }
            Return (0x0B)
        }
        Method(IQCR, 1, Serialized) {
            // _CRS method - get current settings
            Name(PRR0, ResourceTemplate() {
                Interrupt(, Level, ActiveHigh, Shared) { 0 }
            })
            CreateDWordField(PRR0, 0x05, PRRI)
            Store(And(Arg0, 0x0F), PRRI)
            Return (PRR0)
        }

#define define_link(link, uid, reg)                             \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    5, 10, 11                                   \
                }                                               \
            })                                                  \
            Method(_STA, 0, NotSerialized) {                    \
                Return (IQST(reg))                              \
            }                                                   \
            Method(_DIS, 0, NotSerialized) {                    \
                Or(reg, 0x80, reg)                              \
            }                                                   \
            Method(_CRS, 0, NotSerialized) {                    \
                Return (IQCR(reg))                              \
            }                                                   \
            Method(_SRS, 1, NotSerialized) {                    \
                CreateDWordField(Arg0, 0x05, PRRI)              \
                Store(PRRI, reg)                                \
            }                                                   \
        }

        define_link(LNKA, 0, PRQA)
        define_link(LNKB, 1, PRQB)
        define_link(LNKC, 2, PRQC)
        define_link(LNKD, 3, PRQD)
        define_link(LNKE, 4, PRQE)
        define_link(LNKF, 5, PRQF)
        define_link(LNKG, 6, PRQG)
        define_link(LNKH, 7, PRQH)

#define define_gsi_link(link, uid, gsi)                         \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Name(_CRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Method(_SRS, 1, NotSerialized) {                    \
            }                                                   \
        }

        define_gsi_link(GSIA, 0, 0x10)
        define_gsi_link(GSIB, 0, 0x11)
        define_gsi_link(GSIC, 0, 0x12)
        define_gsi_link(GSID, 0, 0x13)
        define_gsi_link(GSIE, 0, 0x14)
        define_gsi_link(GSIF, 0, 0x15)
        define_gsi_link(GSIG, 0, 0x16)
        define_gsi_link(GSIH, 0, 0x17)
    }

#include "acpi-dsdt-cpu-hotplug.dsl"


/****************************************************************
 * General purpose events
 ****************************************************************/

    Scope(\_GPE) {
        Name(_HID, "ACPI0006")

        Method(_L00) {
        }
        Method(_L01) {
            // CPU hotplug event
            \_SB.PRSC()
        }
        Method(_L02) {
        }
        Method(_L03) {
        }
        Method(_L04) {
        }
        Method(_L05) {
        }
        Method(_L06) {
        }
        Method(_L07) {
        }
        Method(_L08) {
        }
        Method(_L09) {
        }
        Method(_L0A) {
        }
        Method(_L0B) {
        }
        Method(_L0C) {
        }
        Method(_L0D) {
        }
        Method(_L0E) {
        }
        Method(_L0F) {
        }
    }
}
Commit	Line	Data
74523b85 MT	1	/*
	2	* Bochs/QEMU ACPI DSDT ASL definition
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	18	*/
	19	/*
	20	* Copyright (c) 2010 Isaku Yamahata
	21	* yamahata at valinux co jp
	22	* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
	23	*/
	24
	25	ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
	26
	27	DefinitionBlock (
	28	"q35-acpi-dsdt.aml",// Output Filename
	29	"DSDT", // Signature
	30	0x01, // DSDT Compliance Revision
	31	"BXPC", // OEMID
	32	"BXDSDT", // TABLE ID
	33	0x2 // OEM Revision
	34	)
	35	{
	36
	37	#include "acpi-dsdt-dbug.dsl"
	38
	39	Scope(\_SB) {
	40	OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
	41	OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
	42	Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
	43	PCIB, 8,
	44	}
	45	}
	46
	47
	48	/****************************************************************
	49	* PCI Bus definition
	50	****************************************************************/
	51
	52	Scope(\_SB) {
	53	Device(PCI0) {
	54	Name(_HID, EisaId("PNP0A08"))
	55	Name(_CID, EisaId("PNP0A03"))
	56	Name(_ADR, 0x00)
	57	Name(_UID, 1)
	58
	59	// _OSC: based on sample of ACPI3.0b spec
	60	Name(SUPP, 0) // PCI _OSC Support Field value
	61	Name(CTRL, 0) // PCI _OSC Control Field value
	62	Method(_OSC, 4) {
	63	// Create DWORD-addressable fields from the Capabilities Buffer
	64	CreateDWordField(Arg3, 0, CDW1)
65
66	// Check for proper UUID
67	If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
68	// Create DWORD-addressable fields from the Capabilities Buffer
69	CreateDWordField(Arg3, 4, CDW2)
70	CreateDWordField(Arg3, 8, CDW3)
71
72	// Save Capabilities DWORD2 & 3
73	Store(CDW2, SUPP)
74	Store(CDW3, CTRL)
75
76	// Always allow native PME, AER (no dependencies)
77	// Never allow SHPC (no SHPC controller in this system)
78	And(CTRL, 0x1D, CTRL)
79
80	#if 0 // For now, nothing to do
81	If (Not(And(CDW1, 1))) { // Query flag clear?
82	// Disable GPEs for features granted native control.
83	If (And(CTRL, 0x01)) { // Hot plug control granted?
84	Store(0, HPCE) // clear the hot plug SCI enable bit
85	Store(1, HPCS) // clear the hot plug SCI status bit
86	}
87	If (And(CTRL, 0x04)) { // PME control granted?
88	Store(0, PMCE) // clear the PME SCI enable bit
89	Store(1, PMCS) // clear the PME SCI status bit
90	}
91	If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
92	// Set status to not restore PCI Express cap structure
93	// upon resume from S3
94	Store(1, S3CR)
95	}
96	}
97	#endif
98	If (LNotEqual(Arg1, One)) {
99	// Unknown revision
100	Or(CDW1, 0x08, CDW1)
101	}
102	If (LNotEqual(CDW3, CTRL)) {
103	// Capabilities bits were masked
104	Or(CDW1, 0x10, CDW1)
105	}
106	// Update DWORD3 in the buffer
107	Store(CTRL, CDW3)
108	} Else {
109	Or(CDW1, 4, CDW1) // Unrecognized UUID
110	}
111	Return (Arg3)
112	}
113	}
114	}
115
116	#include "acpi-dsdt-pci-crs.dsl"
117	#include "acpi-dsdt-hpet.dsl"
118
119
120	/****************************************************************
121	* VGA
122	****************************************************************/
123
124	Scope(\_SB.PCI0) {
125	Device(VGA) {
126	Name(_ADR, 0x00010000)
127	Method(_S1D, 0, NotSerialized) {
128	Return (0x00)
129	}
130	Method(_S2D, 0, NotSerialized) {
131	Return (0x00)
132	}
133	Method(_S3D, 0, NotSerialized) {
134	Return (0x00)
135	}
136	}
137	}
138
139
140	/****************************************************************
141	* LPC ISA bridge
142	****************************************************************/
143
144	Scope(\_SB.PCI0) {
145	/* PCI D31:f0 LPC ISA bridge */
146	Device(ISA) {
147	/* PCI D31:f0 */
148	Name(_ADR, 0x001f0000)
149
150	/* ICH9 PCI to ISA irq remapping */
151	OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
152
153	OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
154	Field(LPCD, AnyAcc, NoLock, Preserve) {
155	COMA, 3,
156	, 1,
157	COMB, 3,
158
159	Offset(0x01),
160	LPTD, 2,
161	, 2,
162	FDCD, 2
163	}
164	OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
165	Field(LPCE, AnyAcc, NoLock, Preserve) {
166	CAEN, 1,
167	CBEN, 1,
168	LPEN, 1,
169	FDEN, 1
170	}
171	}
172	}
173
174	#include "acpi-dsdt-isa.dsl"
175
176
177	/****************************************************************
178	* PCI IRQs
179	****************************************************************/
180
181	/* Zero => PIC mode, One => APIC Mode */
182	Name(\PICF, Zero)
183	Method(\_PIC, 1, NotSerialized) {
184	Store(Arg0, \PICF)
185	}
186
187	Scope(\_SB) {
188	Scope(PCI0) {
189	#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
190	Package() { nr##ffff, 0, lnk0, 0 }, \
191	Package() { nr##ffff, 1, lnk1, 0 }, \
192	Package() { nr##ffff, 2, lnk2, 0 }, \
193	Package() { nr##ffff, 3, lnk3, 0 }
194
195	#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
196	#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
197	#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
198	#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
199
200	#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
201	#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
202	#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
203	#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
204
205	Name(PRTP, package() {
206	prt_slot_lnkE(0x0000),
207	prt_slot_lnkF(0x0001),
208	prt_slot_lnkG(0x0002),
209	prt_slot_lnkH(0x0003),
210	prt_slot_lnkE(0x0004),
211	prt_slot_lnkF(0x0005),
212	prt_slot_lnkG(0x0006),
213	prt_slot_lnkH(0x0007),
214	prt_slot_lnkE(0x0008),
215	prt_slot_lnkF(0x0009),
216	prt_slot_lnkG(0x000a),
217	prt_slot_lnkH(0x000b),
218	prt_slot_lnkE(0x000c),
219	prt_slot_lnkF(0x000d),
220	prt_slot_lnkG(0x000e),
221	prt_slot_lnkH(0x000f),
222	prt_slot_lnkE(0x0010),
223	prt_slot_lnkF(0x0011),
224	prt_slot_lnkG(0x0012),
225	prt_slot_lnkH(0x0013),
226	prt_slot_lnkE(0x0014),
227	prt_slot_lnkF(0x0015),
228	prt_slot_lnkG(0x0016),
229	prt_slot_lnkH(0x0017),
230	prt_slot_lnkE(0x0018),
231
232	/* INTA -> PIRQA for slot 25 - 31
233	see the default value of D<N>IR */
234	prt_slot_lnkA(0x0019),
235	prt_slot_lnkA(0x001a),
236	prt_slot_lnkA(0x001b),
237	prt_slot_lnkA(0x001c),
238	prt_slot_lnkA(0x001d),
239
240	/* PCIe->PCI bridge. use PIRQ[E-H] */
241	prt_slot_lnkE(0x001e),
242
243	prt_slot_lnkA(0x001f)
244	})
245
246	#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
247	Package() { nr##ffff, 0, gsi0, 0 }, \
248	Package() { nr##ffff, 1, gsi1, 0 }, \
249	Package() { nr##ffff, 2, gsi2, 0 }, \
250	Package() { nr##ffff, 3, gsi3, 0 }
251
252	#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
253	#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
254	#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
255	#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
256
257	#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
258	#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
259	#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
260	#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
261
262	Name(PRTA, package() {
263	prt_slot_gsiE(0x0000),
264	prt_slot_gsiF(0x0001),
265	prt_slot_gsiG(0x0002),
266	prt_slot_gsiH(0x0003),
267	prt_slot_gsiE(0x0004),
268	prt_slot_gsiF(0x0005),
269	prt_slot_gsiG(0x0006),
270	prt_slot_gsiH(0x0007),
271	prt_slot_gsiE(0x0008),
272	prt_slot_gsiF(0x0009),
273	prt_slot_gsiG(0x000a),
274	prt_slot_gsiH(0x000b),
275	prt_slot_gsiE(0x000c),
276	prt_slot_gsiF(0x000d),
277	prt_slot_gsiG(0x000e),
278	prt_slot_gsiH(0x000f),
279	prt_slot_gsiE(0x0010),
280	prt_slot_gsiF(0x0011),
281	prt_slot_gsiG(0x0012),
282	prt_slot_gsiH(0x0013),
283	prt_slot_gsiE(0x0014),
284	prt_slot_gsiF(0x0015),
285	prt_slot_gsiG(0x0016),
286	prt_slot_gsiH(0x0017),
287	prt_slot_gsiE(0x0018),
288
289	/* INTA -> PIRQA for slot 25 - 31, but 30
290	see the default value of D<N>IR */
291	prt_slot_gsiA(0x0019),
292	prt_slot_gsiA(0x001a),
293	prt_slot_gsiA(0x001b),
294	prt_slot_gsiA(0x001c),
295	prt_slot_gsiA(0x001d),
296
297	/* PCIe->PCI bridge. use PIRQ[E-H] */
298	prt_slot_gsiE(0x001e),
299
300	prt_slot_gsiA(0x001f)
301	})
302
303	Method(_PRT, 0, NotSerialized) {
304	/* PCI IRQ routing table, example from ACPI 2.0a specification,
305	section 6.2.8.1 */
306	/* Note: we provide the same info as the PCI routing
307	table of the Bochs BIOS */
308	If (LEqual(\PICF, Zero)) {
309	Return (PRTP)
310	} Else {
311	Return (PRTA)
312	}
313	}
314	}
315
316	Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
317	PRQA, 8,
318	PRQB, 8,
319	PRQC, 8,
320	PRQD, 8,
321
322	Offset(0x08),
323	PRQE, 8,
324	PRQF, 8,
325	PRQG, 8,
326	PRQH, 8
327	}
328
329	Method(IQST, 1, NotSerialized) {
330	// _STA method - get status
331	If (And(0x80, Arg0)) {
332	Return (0x09)
333	}
334	Return (0x0B)
335	}
6b9b4405	336	Method(IQCR, 1, Serialized) {
74523b85 MT	337	// _CRS method - get current settings
	338	Name(PRR0, ResourceTemplate() {
	339	Interrupt(, Level, ActiveHigh, Shared) { 0 }
	340	})
	341	CreateDWordField(PRR0, 0x05, PRRI)
	342	Store(And(Arg0, 0x0F), PRRI)
	343	Return (PRR0)
	344	}
	345
	346	#define define_link(link, uid, reg) \
	347	Device(link) { \
	348	Name(_HID, EISAID("PNP0C0F")) \
	349	Name(_UID, uid) \
	350	Name(_PRS, ResourceTemplate() { \
	351	Interrupt(, Level, ActiveHigh, Shared) { \
	352	5, 10, 11 \
	353	} \
	354	}) \
	355	Method(_STA, 0, NotSerialized) { \
	356	Return (IQST(reg)) \
	357	} \
	358	Method(_DIS, 0, NotSerialized) { \
	359	Or(reg, 0x80, reg) \
	360	} \
	361	Method(_CRS, 0, NotSerialized) { \
	362	Return (IQCR(reg)) \
	363	} \
	364	Method(_SRS, 1, NotSerialized) { \
	365	CreateDWordField(Arg0, 0x05, PRRI) \
	366	Store(PRRI, reg) \
	367	} \
	368	}
	369
	370	define_link(LNKA, 0, PRQA)
	371	define_link(LNKB, 1, PRQB)
	372	define_link(LNKC, 2, PRQC)
	373	define_link(LNKD, 3, PRQD)
	374	define_link(LNKE, 4, PRQE)
	375	define_link(LNKF, 5, PRQF)
	376	define_link(LNKG, 6, PRQG)
	377	define_link(LNKH, 7, PRQH)
	378
	379	#define define_gsi_link(link, uid, gsi) \
	380	Device(link) { \
	381	Name(_HID, EISAID("PNP0C0F")) \
	382	Name(_UID, uid) \
	383	Name(_PRS, ResourceTemplate() { \
	384	Interrupt(, Level, ActiveHigh, Shared) { \
	385	gsi \
	386	} \
	387	}) \
	388	Name(_CRS, ResourceTemplate() { \
	389	Interrupt(, Level, ActiveHigh, Shared) { \
	390	gsi \
	391	} \
	392	}) \
	393	Method(_SRS, 1, NotSerialized) { \
	394	} \
	395	}
	396
	397	define_gsi_link(GSIA, 0, 0x10)
	398	define_gsi_link(GSIB, 0, 0x11)
	399	define_gsi_link(GSIC, 0, 0x12)
	400	define_gsi_link(GSID, 0, 0x13)
401	define_gsi_link(GSIE, 0, 0x14)
402	define_gsi_link(GSIF, 0, 0x15)
403	define_gsi_link(GSIG, 0, 0x16)
404	define_gsi_link(GSIH, 0, 0x17)
405	}
406
407	#include "acpi-dsdt-cpu-hotplug.dsl"
408
409
410	/****************************************************************
411	* General purpose events
412	****************************************************************/
413
414	Scope(\_GPE) {
415	Name(_HID, "ACPI0006")
416
417	Method(_L00) {
418	}
419	Method(_L01) {
420	// CPU hotplug event
421	\_SB.PRSC()
422	}
423	Method(_L02) {
424	}
425	Method(_L03) {
426	}
427	Method(_L04) {
428	}
429	Method(_L05) {
430	}
431	Method(_L06) {
432	}
433	Method(_L07) {
434	}
435	Method(_L08) {
436	}
437	Method(_L09) {
438	}
439	Method(_L0A) {
440	}
441	Method(_L0B) {
442	}
443	Method(_L0C) {
444	}
445	Method(_L0D) {
446	}
447	Method(_L0E) {
448	}
449	Method(_L0F) {
450	}
451	}
452	}