[qemu.git] / tests / m25p80-test.c

/*
 * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
 * Controller)
 *
 * Copyright (C) 2016 IBM Corp.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/bswap.h"
#include "libqtest.h"

/*
 * ASPEED SPI Controller registers
 */
#define R_CONF              0x00
#define   CONF_ENABLE_W0       (1 << 16)
#define R_CE_CTRL           0x04
#define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
#define R_CTRL0             0x10
#define   CTRL_CE_STOP_ACTIVE  (1 << 2)
#define   CTRL_READMODE        0x0
#define   CTRL_FREADMODE       0x1
#define   CTRL_WRITEMODE       0x2
#define   CTRL_USERMODE        0x3

#define ASPEED_FMC_BASE    0x1E620000
#define ASPEED_FLASH_BASE  0x20000000

/*
 * Flash commands
 */
enum {
    JEDEC_READ = 0x9f,
    BULK_ERASE = 0xc7,
    READ = 0x03,
    PP = 0x02,
    WREN = 0x6,
    RESET_ENABLE = 0x66,
    RESET_MEMORY = 0x99,
    EN_4BYTE_ADDR = 0xB7,
    ERASE_SECTOR = 0xd8,
};

#define FLASH_JEDEC         0x20ba19  /* n25q256a */
#define FLASH_SIZE          (32 * 1024 * 1024)

#define PAGE_SIZE           256

/*
 * Use an explicit bswap for the values read/wrote to the flash region
 * as they are BE and the Aspeed CPU is LE.
 */
static inline uint32_t make_be32(uint32_t data)
{
    return bswap32(data);
}

static void spi_conf(uint32_t value)
{
    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);

    conf |= value;
    writel(ASPEED_FMC_BASE + R_CONF, conf);
}

static void spi_conf_remove(uint32_t value)
{
    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);

    conf &= ~value;
    writel(ASPEED_FMC_BASE + R_CONF, conf);
}

static void spi_ce_ctrl(uint32_t value)
{
    uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);

    conf |= value;
    writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
}

static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
{
    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
    ctrl &= ~(CTRL_USERMODE | 0xff << 16);
    ctrl |= mode | (cmd << 16);
    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
}

static void spi_ctrl_start_user(void)
{
    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);

    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);

    ctrl &= ~CTRL_CE_STOP_ACTIVE;
    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
}

static void spi_ctrl_stop_user(void)
{
    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);

    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
}

static void flash_reset(void)
{
    spi_conf(CONF_ENABLE_W0);

    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
    writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
    spi_ctrl_stop_user();

    spi_conf_remove(CONF_ENABLE_W0);
}

static void test_read_jedec(void)
{
    uint32_t jedec = 0x0;

    spi_conf(CONF_ENABLE_W0);

    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, JEDEC_READ);
    jedec |= readb(ASPEED_FLASH_BASE) << 16;
    jedec |= readb(ASPEED_FLASH_BASE) << 8;
    jedec |= readb(ASPEED_FLASH_BASE);
    spi_ctrl_stop_user();

    flash_reset();

    g_assert_cmphex(jedec, ==, FLASH_JEDEC);
}

static void read_page(uint32_t addr, uint32_t *page)
{
    int i;

    spi_ctrl_start_user();

    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
    writeb(ASPEED_FLASH_BASE, READ);
    writel(ASPEED_FLASH_BASE, make_be32(addr));

    /* Continuous read are supported */
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        page[i] = make_be32(readl(ASPEED_FLASH_BASE));
    }
    spi_ctrl_stop_user();
}

static void read_page_mem(uint32_t addr, uint32_t *page)
{
    int i;

    /* move out USER mode to use direct reads from the AHB bus */
    spi_ctrl_setmode(CTRL_READMODE, READ);

    for (i = 0; i < PAGE_SIZE / 4; i++) {
        page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
    }
}

static void test_erase_sector(void)
{
    uint32_t some_page_addr = 0x600 * PAGE_SIZE;
    uint32_t page[PAGE_SIZE / 4];
    int i;

    spi_conf(CONF_ENABLE_W0);

    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, WREN);
    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
    writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
    spi_ctrl_stop_user();

    /* Previous page should be full of zeroes as backend is not
     * initialized */
    read_page(some_page_addr - PAGE_SIZE, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0x0);
    }

    /* But this one was erased */
    read_page(some_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0xffffffff);
    }

    flash_reset();
}

static void test_erase_all(void)
{
    uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
    uint32_t page[PAGE_SIZE / 4];
    int i;

    spi_conf(CONF_ENABLE_W0);

    /* Check some random page. Should be full of zeroes as backend is
     * not initialized */
    read_page(some_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0x0);
    }

    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, WREN);
    writeb(ASPEED_FLASH_BASE, BULK_ERASE);
    spi_ctrl_stop_user();

    /* Recheck that some random page */
    read_page(some_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0xffffffff);
    }

    flash_reset();
}

static void test_write_page(void)
{
    uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */
    uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
    uint32_t page[PAGE_SIZE / 4];
    int i;

    spi_conf(CONF_ENABLE_W0);

    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
    writeb(ASPEED_FLASH_BASE, WREN);
    writeb(ASPEED_FLASH_BASE, PP);
    writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));

    /* Fill the page with its own addresses */
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
    }
    spi_ctrl_stop_user();

    /* Check what was written */
    read_page(my_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
    }

    /* Check some other page. It should be full of 0xff */
    read_page(some_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0xffffffff);
    }

    flash_reset();
}

static void test_read_page_mem(void)
{
    uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */
    uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
    uint32_t page[PAGE_SIZE / 4];
    int i;

    /* Enable 4BYTE mode for controller. This is should be strapped by
     * HW for CE0 anyhow.
     */
    spi_ce_ctrl(1 << CRTL_EXTENDED0);

    /* Enable 4BYTE mode for flash. */
    spi_conf(CONF_ENABLE_W0);
    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
    spi_ctrl_stop_user();
    spi_conf_remove(CONF_ENABLE_W0);

    /* Check what was written */
    read_page_mem(my_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
    }

    /* Check some other page. It should be full of 0xff */
    read_page_mem(some_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, 0xffffffff);
    }

    flash_reset();
}

static void test_write_page_mem(void)
{
    uint32_t my_page_addr = 0x15000 * PAGE_SIZE;
    uint32_t page[PAGE_SIZE / 4];
    int i;

    /* Enable 4BYTE mode for controller. This is should be strapped by
     * HW for CE0 anyhow.
     */
    spi_ce_ctrl(1 << CRTL_EXTENDED0);

    /* Enable 4BYTE mode for flash. */
    spi_conf(CONF_ENABLE_W0);
    spi_ctrl_start_user();
    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
    writeb(ASPEED_FLASH_BASE, WREN);
    spi_ctrl_stop_user();

    /* move out USER mode to use direct writes to the AHB bus */
    spi_ctrl_setmode(CTRL_WRITEMODE, PP);

    for (i = 0; i < PAGE_SIZE / 4; i++) {
        writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
               make_be32(my_page_addr + i * 4));
    }

    /* Check what was written */
    read_page_mem(my_page_addr, page);
    for (i = 0; i < PAGE_SIZE / 4; i++) {
        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
    }

    flash_reset();
}

static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";

int main(int argc, char **argv)
{
    int ret;
    int fd;
    char *args;

    g_test_init(&argc, &argv, NULL);

    fd = mkstemp(tmp_path);
    g_assert(fd >= 0);
    ret = ftruncate(fd, FLASH_SIZE);
    g_assert(ret == 0);
    close(fd);

    args = g_strdup_printf("-m 256 -machine palmetto-bmc "
                           "-drive file=%s,format=raw,if=mtd",
                           tmp_path);
    qtest_start(args);

    qtest_add_func("/m25p80/read_jedec", test_read_jedec);
    qtest_add_func("/m25p80/erase_sector", test_erase_sector);
    qtest_add_func("/m25p80/erase_all",  test_erase_all);
    qtest_add_func("/m25p80/write_page", test_write_page);
    qtest_add_func("/m25p80/read_page_mem", test_read_page_mem);
    qtest_add_func("/m25p80/write_page_mem", test_write_page_mem);

    ret = g_test_run();

    qtest_quit(global_qtest);
    unlink(tmp_path);
    g_free(args);
    return ret;
}
Commit	Line	Data
7a2334f7 CLG	1	/*
	2	* QTest testcase for the M25P80 Flash (Using the Aspeed SPI
	3	* Controller)
	4	*
	5	* Copyright (C) 2016 IBM Corp.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
	26	#include "qemu/osdep.h"
	27	#include "qemu/bswap.h"
	28	#include "libqtest.h"
	29
	30	/*
	31	* ASPEED SPI Controller registers
	32	*/
	33	#define R_CONF 0x00
	34	#define CONF_ENABLE_W0 (1 << 16)
	35	#define R_CE_CTRL 0x04
	36	#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
	37	#define R_CTRL0 0x10
	38	#define CTRL_CE_STOP_ACTIVE (1 << 2)
371a3dd2 CLG	39	#define CTRL_READMODE 0x0
	40	#define CTRL_FREADMODE 0x1
	41	#define CTRL_WRITEMODE 0x2
7a2334f7 CLG	42	#define CTRL_USERMODE 0x3
	43
	44	#define ASPEED_FMC_BASE 0x1E620000
	45	#define ASPEED_FLASH_BASE 0x20000000
	46
	47	/*
	48	* Flash commands
	49	*/
	50	enum {
	51	JEDEC_READ = 0x9f,
	52	BULK_ERASE = 0xc7,
	53	READ = 0x03,
	54	PP = 0x02,
	55	WREN = 0x6,
bd9f5052 CLG	56	RESET_ENABLE = 0x66,
bd9f5052 CLG	57	RESET_MEMORY = 0x99,
7a2334f7 CLG	58	EN_4BYTE_ADDR = 0xB7,
	59	ERASE_SECTOR = 0xd8,
	60	};
	61
	62	#define FLASH_JEDEC 0x20ba19 /* n25q256a */
	63	#define FLASH_SIZE (32 * 1024 * 1024)
	64
	65	#define PAGE_SIZE 256
	66
	67	/*
	68	* Use an explicit bswap for the values read/wrote to the flash region
	69	* as they are BE and the Aspeed CPU is LE.
	70	*/
	71	static inline uint32_t make_be32(uint32_t data)
	72	{
	73	return bswap32(data);
	74	}
	75
	76	static void spi_conf(uint32_t value)
	77	{
	78	uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
	79
	80	conf \|= value;
	81	writel(ASPEED_FMC_BASE + R_CONF, conf);
	82	}
	83
bd9f5052 CLG	84	static void spi_conf_remove(uint32_t value)
	85	{
	86	uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
	87
	88	conf &= ~value;
	89	writel(ASPEED_FMC_BASE + R_CONF, conf);
	90	}
	91
371a3dd2 CLG	92	static void spi_ce_ctrl(uint32_t value)
	93	{
	94	uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);
	95
	96	conf \|= value;
	97	writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
	98	}
	99
	100	static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
	101	{
	102	uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
	103	ctrl &= ~(CTRL_USERMODE \| 0xff << 16);
	104	ctrl \|= mode \| (cmd << 16);
	105	writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
	106	}
	107
7a2334f7 CLG	108	static void spi_ctrl_start_user(void)
	109	{
	110	uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
	111
	112	ctrl \|= CTRL_USERMODE \| CTRL_CE_STOP_ACTIVE;
	113	writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
	114
	115	ctrl &= ~CTRL_CE_STOP_ACTIVE;
	116	writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
	117	}
	118
	119	static void spi_ctrl_stop_user(void)
	120	{
	121	uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
	122
	123	ctrl \|= CTRL_USERMODE \| CTRL_CE_STOP_ACTIVE;
	124	writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
	125	}
	126
bd9f5052 CLG	127	static void flash_reset(void)
	128	{
	129	spi_conf(CONF_ENABLE_W0);
	130
	131	spi_ctrl_start_user();
	132	writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
	133	writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
	134	spi_ctrl_stop_user();
	135
	136	spi_conf_remove(CONF_ENABLE_W0);
	137	}
	138
7a2334f7 CLG	139	static void test_read_jedec(void)
	140	{
	141	uint32_t jedec = 0x0;
	142
	143	spi_conf(CONF_ENABLE_W0);
	144
	145	spi_ctrl_start_user();
	146	writeb(ASPEED_FLASH_BASE, JEDEC_READ);
	147	jedec \|= readb(ASPEED_FLASH_BASE) << 16;
	148	jedec \|= readb(ASPEED_FLASH_BASE) << 8;
	149	jedec \|= readb(ASPEED_FLASH_BASE);
	150	spi_ctrl_stop_user();
	151
bd9f5052 CLG	152	flash_reset();
bd9f5052 CLG	153
7a2334f7 CLG	154	g_assert_cmphex(jedec, ==, FLASH_JEDEC);
	155	}
	156
	157	static void read_page(uint32_t addr, uint32_t *page)
	158	{
	159	int i;
	160
	161	spi_ctrl_start_user();
	162
	163	writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
	164	writeb(ASPEED_FLASH_BASE, READ);
	165	writel(ASPEED_FLASH_BASE, make_be32(addr));
	166
	167	/* Continuous read are supported */
	168	for (i = 0; i < PAGE_SIZE / 4; i++) {
	169	page[i] = make_be32(readl(ASPEED_FLASH_BASE));
	170	}
	171	spi_ctrl_stop_user();
	172	}
	173
371a3dd2 CLG	174	static void read_page_mem(uint32_t addr, uint32_t *page)
	175	{
	176	int i;
	177
	178	/* move out USER mode to use direct reads from the AHB bus */
	179	spi_ctrl_setmode(CTRL_READMODE, READ);
	180
	181	for (i = 0; i < PAGE_SIZE / 4; i++) {
	182	page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
	183	}
	184	}
	185
7a2334f7 CLG	186	static void test_erase_sector(void)
	187	{
	188	uint32_t some_page_addr = 0x600 * PAGE_SIZE;
	189	uint32_t page[PAGE_SIZE / 4];
	190	int i;
	191
	192	spi_conf(CONF_ENABLE_W0);
	193
	194	spi_ctrl_start_user();
	195	writeb(ASPEED_FLASH_BASE, WREN);
	196	writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
	197	writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
	198	writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
	199	spi_ctrl_stop_user();
	200
	201	/* Previous page should be full of zeroes as backend is not
	202	* initialized */
	203	read_page(some_page_addr - PAGE_SIZE, page);
	204	for (i = 0; i < PAGE_SIZE / 4; i++) {
	205	g_assert_cmphex(page[i], ==, 0x0);
	206	}
	207
	208	/* But this one was erased */
	209	read_page(some_page_addr, page);
	210	for (i = 0; i < PAGE_SIZE / 4; i++) {
	211	g_assert_cmphex(page[i], ==, 0xffffffff);
	212	}
bd9f5052 CLG	213
bd9f5052 CLG	214	flash_reset();
7a2334f7 CLG	215	}
	216
	217	static void test_erase_all(void)
	218	{
	219	uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
	220	uint32_t page[PAGE_SIZE / 4];
	221	int i;
	222
	223	spi_conf(CONF_ENABLE_W0);
	224
	225	/* Check some random page. Should be full of zeroes as backend is
	226	* not initialized */
	227	read_page(some_page_addr, page);
	228	for (i = 0; i < PAGE_SIZE / 4; i++) {
	229	g_assert_cmphex(page[i], ==, 0x0);
	230	}
	231
	232	spi_ctrl_start_user();
	233	writeb(ASPEED_FLASH_BASE, WREN);
	234	writeb(ASPEED_FLASH_BASE, BULK_ERASE);
	235	spi_ctrl_stop_user();
	236
	237	/* Recheck that some random page */
	238	read_page(some_page_addr, page);
	239	for (i = 0; i < PAGE_SIZE / 4; i++) {
	240	g_assert_cmphex(page[i], ==, 0xffffffff);
	241	}
bd9f5052 CLG	242
bd9f5052 CLG	243	flash_reset();
7a2334f7 CLG	244	}
	245
	246	static void test_write_page(void)
	247	{
	248	uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */
	249	uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
	250	uint32_t page[PAGE_SIZE / 4];
	251	int i;
	252
	253	spi_conf(CONF_ENABLE_W0);
	254
	255	spi_ctrl_start_user();
	256	writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
bd9f5052	257	writeb(ASPEED_FLASH_BASE, WREN);
7a2334f7 CLG	258	writeb(ASPEED_FLASH_BASE, PP);
	259	writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
	260
	261	/* Fill the page with its own addresses */
	262	for (i = 0; i < PAGE_SIZE / 4; i++) {
	263	writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
	264	}
	265	spi_ctrl_stop_user();
	266
	267	/* Check what was written */
	268	read_page(my_page_addr, page);
	269	for (i = 0; i < PAGE_SIZE / 4; i++) {
	270	g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
	271	}
	272
	273	/* Check some other page. It should be full of 0xff */
	274	read_page(some_page_addr, page);
	275	for (i = 0; i < PAGE_SIZE / 4; i++) {
	276	g_assert_cmphex(page[i], ==, 0xffffffff);
	277	}
bd9f5052 CLG	278
bd9f5052 CLG	279	flash_reset();
7a2334f7 CLG	280	}
7a2334f7 CLG	281
371a3dd2 CLG	282	static void test_read_page_mem(void)
	283	{
	284	uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */
	285	uint32_t some_page_addr = 0x15000 * PAGE_SIZE;
	286	uint32_t page[PAGE_SIZE / 4];
	287	int i;
	288
	289	/* Enable 4BYTE mode for controller. This is should be strapped by
	290	* HW for CE0 anyhow.
	291	*/
	292	spi_ce_ctrl(1 << CRTL_EXTENDED0);
	293
	294	/* Enable 4BYTE mode for flash. */
	295	spi_conf(CONF_ENABLE_W0);
	296	spi_ctrl_start_user();
	297	writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
	298	spi_ctrl_stop_user();
	299	spi_conf_remove(CONF_ENABLE_W0);
	300
	301	/* Check what was written */
	302	read_page_mem(my_page_addr, page);
	303	for (i = 0; i < PAGE_SIZE / 4; i++) {
	304	g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
	305	}
	306
	307	/* Check some other page. It should be full of 0xff */
	308	read_page_mem(some_page_addr, page);
	309	for (i = 0; i < PAGE_SIZE / 4; i++) {
	310	g_assert_cmphex(page[i], ==, 0xffffffff);
	311	}
	312
	313	flash_reset();
	314	}
	315
	316	static void test_write_page_mem(void)
	317	{
	318	uint32_t my_page_addr = 0x15000 * PAGE_SIZE;
	319	uint32_t page[PAGE_SIZE / 4];
	320	int i;
	321
	322	/* Enable 4BYTE mode for controller. This is should be strapped by
	323	* HW for CE0 anyhow.
	324	*/
	325	spi_ce_ctrl(1 << CRTL_EXTENDED0);
	326
	327	/* Enable 4BYTE mode for flash. */
	328	spi_conf(CONF_ENABLE_W0);
	329	spi_ctrl_start_user();
	330	writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
	331	writeb(ASPEED_FLASH_BASE, WREN);
	332	spi_ctrl_stop_user();
	333
	334	/* move out USER mode to use direct writes to the AHB bus */
	335	spi_ctrl_setmode(CTRL_WRITEMODE, PP);
	336
	337	for (i = 0; i < PAGE_SIZE / 4; i++) {
	338	writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
	339	make_be32(my_page_addr + i * 4));
	340	}
	341
	342	/* Check what was written */
	343	read_page_mem(my_page_addr, page);
	344	for (i = 0; i < PAGE_SIZE / 4; i++) {
	345	g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
346	}
347
348	flash_reset();
349	}
350
7a2334f7 CLG	351	static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
	352
	353	int main(int argc, char **argv)
	354	{
	355	int ret;
	356	int fd;
	357	char *args;
	358
	359	g_test_init(&argc, &argv, NULL);
	360
	361	fd = mkstemp(tmp_path);
	362	g_assert(fd >= 0);
	363	ret = ftruncate(fd, FLASH_SIZE);
	364	g_assert(ret == 0);
	365	close(fd);
	366
	367	args = g_strdup_printf("-m 256 -machine palmetto-bmc "
	368	"-drive file=%s,format=raw,if=mtd",
	369	tmp_path);
	370	qtest_start(args);
	371
	372	qtest_add_func("/m25p80/read_jedec", test_read_jedec);
	373	qtest_add_func("/m25p80/erase_sector", test_erase_sector);
	374	qtest_add_func("/m25p80/erase_all", test_erase_all);
	375	qtest_add_func("/m25p80/write_page", test_write_page);
371a3dd2 CLG	376	qtest_add_func("/m25p80/read_page_mem", test_read_page_mem);
371a3dd2 CLG	377	qtest_add_func("/m25p80/write_page_mem", test_write_page_mem);
7a2334f7 CLG	378
	379	ret = g_test_run();
	380
	381	qtest_quit(global_qtest);
	382	unlink(tmp_path);
	383	g_free(args);
	384	return ret;
	385	}