[qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "pci_host.h"
#include "isa.h"
#include "sysbus.h"
#include "range.h"
#include "xen.h"

/*
 * I440FX chipset data sheet.
 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
 */

typedef PCIHostState I440FXState;

#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
#define PIIX_PIRQC              0x60

typedef struct PIIX3State {
    PCIDevice dev;

    /*
     * bitmap to track pic levels.
     * The pic level is the logical OR of all the PCI irqs mapped to it
     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
     *
     * PIRQ is mapped to PIC pins, we track it by
     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
     * pic_irq * PIIX_NUM_PIRQS + pirq
     */
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
    uint64_t pic_levels;

    qemu_irq *pic;

    /* This member isn't used. Just for save/load compatibility */
    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;

struct PCII440FXState {
    PCIDevice dev;
    target_phys_addr_t isa_page_descs[384 / 4];
    uint8_t smm_enabled;
    PIIX3State *piix3;
};


#define I440FX_PAM      0x59
#define I440FX_PAM_SIZE 7
#define I440FX_SMRAM    0x72

static void piix3_set_irq(void *opaque, int pirq, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (pci_intx + slot_addend) & 3;
}

static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCII440FXState *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->dev.config[I440FX_SMRAM];
    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

static void i440fx_set_smm(int val, void *arg)
{
    PCII440FXState *d = arg;

    val = (val != 0);
    if (d->smm_enabled != val) {
        d->smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCII440FXState *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
        range_covers_byte(address, len, I440FX_SMRAM)) {
        i440fx_update_memory_mappings(d);
    }
}

static void i440fx_write_config_xen(PCIDevice *dev,
                                    uint32_t address, uint32_t val, int len)
{
    xen_piix_pci_write_config_client(address, val, len);
    i440fx_write_config(dev, address, val, len);
}

static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
    PCII440FXState *d = opaque;
    int ret, i;

    ret = pci_device_load(&d->dev, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &d->smm_enabled);

    if (version_id == 2) {
        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
            qemu_get_be32(f); /* dummy load for compatibility */
        }
    }

    return 0;
}

static int i440fx_post_load(void *opaque, int version_id)
{
    PCII440FXState *d = opaque;

    i440fx_update_memory_mappings(d);
    return 0;
}

static const VMStateDescription vmstate_i440fx = {
    .name = "I440FX",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = i440fx_load_old,
    .post_load = i440fx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
        VMSTATE_UINT8(smm_enabled, PCII440FXState),
        VMSTATE_END_OF_LIST()
    }
};

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    pci_host_conf_register_ioport(0xcf8, s);

    pci_host_data_register_ioport(0xcfc, s);
    return 0;
}

static int i440fx_initfn(PCIDevice *dev)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
    d->dev.config[0x08] = 0x02; // revision
    pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);

    d->dev.config[I440FX_SMRAM] = 0x02;

    cpu_smm_register(&i440fx_set_smm, d);
    return 0;
}

static PCIBus *i440fx_common_init(const char *device_name,
                                  PCII440FXState **pi440fx_state,
                                  int *piix3_devfn,
                                  qemu_irq *pic, ram_addr_t ram_size)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;
    PIIX3State *piix3;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    b = pci_bus_new(&s->busdev.qdev, NULL, 0);
    s->bus = b;
    qdev_init_nofail(dev);

    d = pci_create_simple(b, 0, device_name);
    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);

    piix3 = DO_UPCAST(PIIX3State, dev,
                      pci_create_simple_multifunction(b, -1, true, "PIIX3"));
    piix3->pic = pic;

    (*pi440fx_state)->piix3 = piix3;

    *piix3_devfn = piix3->dev.devfn;

    ram_size = ram_size / 8 / 1024 / 1024;
    if (ram_size > 255)
        ram_size = 255;
    (*pi440fx_state)->dev.config[0x57]=ram_size;

    return b;
}

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
                    qemu_irq *pic, ram_addr_t ram_size)
{
    PCIBus *b;

    b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
    pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, (*pi440fx_state)->piix3,
                 PIIX_NUM_PIRQS);

    return b;
}

PCIBus *i440fx_xen_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
                        qemu_irq *pic, ram_addr_t ram_size)
{
    PCIBus *b;

    b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic, ram_size);
    pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
                 (*pi440fx_state)->piix3, PIIX_NUM_PIRQS);

    return b;
}

/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
    qemu_set_irq(piix3->pic[pic_irq],
                 !!(piix3->pic_levels &
                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
                     (pic_irq * PIIX_NUM_PIRQS))));
}

static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
    int pic_irq;
    uint64_t mask;

    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
    piix3->pic_levels &= ~mask;
    piix3->pic_levels |= mask * !!level;

    piix3_set_irq_pic(piix3, pic_irq);
}

static void piix3_set_irq(void *opaque, int pirq, int level)
{
    PIIX3State *piix3 = opaque;
    piix3_set_irq_level(piix3, pirq, level);
}

/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
    int pirq;

    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level(piix3, pirq,
                            pci_bus_get_irq_level(piix3->dev.bus, pirq));
    }
}

static void piix3_write_config(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
        PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
        int pic_irq;
        piix3_update_irq_levels(piix3);
        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
            piix3_set_irq_pic(piix3, pic_irq);
        }
    }
}

static void piix3_reset(void *opaque)
{
    PIIX3State *d = opaque;
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    d->pic_levels = 0;
}

static int piix3_post_load(void *opaque, int version_id)
{
    PIIX3State *piix3 = opaque;
    piix3_update_irq_levels(piix3);
    return 0;
}

static void piix3_pre_save(void *opaque)
{
    int i;
    PIIX3State *piix3 = opaque;

    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
        piix3->pci_irq_levels_vmstate[i] =
            pci_bus_get_irq_level(piix3->dev.bus, i);
    }
}

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .post_load = piix3_post_load,
    .pre_save = piix3_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                              PIIX_NUM_PIRQS, 3),
        VMSTATE_END_OF_LIST()
    }
};

static int piix3_initfn(PCIDevice *dev)
{
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
    uint8_t *pci_conf;

    isa_bus_new(&d->dev.qdev);

    pci_conf = d->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);

    qemu_register_reset(piix3_reset, d);
    return 0;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.vmsd    = &vmstate_i440fx,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
    },{
        .qdev.name    = "i440FX-xen",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.vmsd    = &vmstate_i440fx,
        .qdev.no_user = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config_xen,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.fw_name = "pci",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
4f5e19e6	28	#include "pci_host.h"
f75247f1	29	#include "isa.h"
8a14daa5	30	#include "sysbus.h"
bf1b0071	31	#include "range.h"
41445300	32	#include "xen.h"
87ecb68b	33
56594fe3 IY	34	/*
	35	* I440FX chipset data sheet.
	36	* http://download.intel.com/design/chipsets/datashts/29054901.pdf
	37	*/
	38
502a5395 PB	39	typedef PCIHostState I440FXState;
502a5395 PB	40
ab431c28	41	#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
e735b55a	42	#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
ab431c28	43	#define PIIX_PIRQC 0x60
e735b55a	44
fd37d881 JQ	45	typedef struct PIIX3State {
fd37d881 JQ	46	PCIDevice dev;
ab431c28 IY	47
	48	/*
	49	* bitmap to track pic levels.
	50	* The pic level is the logical OR of all the PCI irqs mapped to it
	51	* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
	52	*
	53	* PIRQ is mapped to PIC pins, we track it by
	54	* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
	55	* pic_irq * PIIX_NUM_PIRQS + pirq
	56	*/
	57	#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
	58	#error "unable to encode pic state in 64bit in pic_levels."
	59	#endif
	60	uint64_t pic_levels;
	61
bd7dce87	62	qemu_irq *pic;
e735b55a IY	63
	64	/* This member isn't used. Just for save/load compatibility */
	65	int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
7cd9eee0	66	} PIIX3State;
bd7dce87	67
0a3bacf3 JQ	68	struct PCII440FXState {
0a3bacf3 JQ	69	PCIDevice dev;
c227f099	70	target_phys_addr_t isa_page_descs[384 / 4];
6c009fa4	71	uint8_t smm_enabled;
7cd9eee0	72	PIIX3State *piix3;
0a3bacf3 JQ	73	};
0a3bacf3 JQ	74
f2c688bb IY	75
	76	#define I440FX_PAM 0x59
	77	#define I440FX_PAM_SIZE 7
	78	#define I440FX_SMRAM 0x72
	79
ab431c28	80	static void piix3_set_irq(void *opaque, int pirq, int level);
d2b59317 PB	81
	82	/* return the global irq number corresponding to a given device irq
	83	pin. We could also use the bus number to have a more precise
	84	mapping. */
ab431c28	85	static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
d2b59317 PB	86	{
	87	int slot_addend;
	88	slot_addend = (pci_dev->devfn >> 3) - 1;
ab431c28	89	return (pci_intx + slot_addend) & 3;
d2b59317	90	}
502a5395	91
0a3bacf3	92	static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
84631fd7 FB	93	{
	94	uint32_t addr;
	95
	96	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	97	switch(r) {
	98	case 3:
	99	/* RAM */
5fafdf24	100	cpu_register_physical_memory(start, end - start,
84631fd7 FB	101	start);
	102	break;
	103	case 1:
	104	/* ROM (XXX: not quite correct) */
5fafdf24	105	cpu_register_physical_memory(start, end - start,
84631fd7 FB	106	start \| IO_MEM_ROM);
	107	break;
	108	case 2:
	109	case 0:
	110	/* XXX: should distinguish read/write cases */
	111	for(addr = start; addr < end; addr += 4096) {
5fafdf24	112	cpu_register_physical_memory(addr, 4096,
6c009fa4	113	d->isa_page_descs[(addr - 0xa0000) >> 12]);
84631fd7 FB	114	}
	115	break;
	116	}
	117	}
ee0ea1d0	118
0a3bacf3	119	static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	120	{
ee0ea1d0 FB	121	int i, r;
84631fd7 FB	122	uint32_t smram, addr;
84631fd7 FB	123
f2c688bb	124	update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
84631fd7	125	for(i = 0; i < 12; i++) {
f2c688bb	126	r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
84631fd7	127	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	128	}
f2c688bb	129	smram = d->dev.config[I440FX_SMRAM];
6c009fa4	130	if ((d->smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
84631fd7 FB	131	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	132	} else {
	133	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	134	cpu_register_physical_memory(addr, 4096,
6c009fa4	135	d->isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	136	}
	137	}
	138	}
	139
f885f1ea	140	static void i440fx_set_smm(int val, void *arg)
ee0ea1d0	141	{
f885f1ea IY	142	PCII440FXState *d = arg;
f885f1ea IY	143
ee0ea1d0	144	val = (val != 0);
6c009fa4 JQ	145	if (d->smm_enabled != val) {
6c009fa4 JQ	146	d->smm_enabled = val;
ee0ea1d0 FB	147	i440fx_update_memory_mappings(d);
	148	}
	149	}
	150
	151
	152	/* XXX: suppress when better memory API. We make the assumption that
	153	no device (in particular the VGA) changes the memory mappings in
	154	the 0xa0000-0x100000 range */
0a3bacf3	155	void i440fx_init_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	156	{
	157	int i;
	158	for(i = 0; i < 96; i++) {
6c009fa4	159	d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
ee0ea1d0 FB	160	}
	161	}
	162
0a3bacf3	163	static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0 FB	164	uint32_t address, uint32_t val, int len)
ee0ea1d0 FB	165	{
0a3bacf3 JQ	166	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
0a3bacf3 JQ	167
ee0ea1d0	168	/* XXX: implement SMRAM.D_LOCK */
0a3bacf3	169	pci_default_write_config(dev, address, val, len);
4da5fcd3 IY	170	if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) \|\|
4da5fcd3 IY	171	range_covers_byte(address, len, I440FX_SMRAM)) {
ee0ea1d0	172	i440fx_update_memory_mappings(d);
4da5fcd3	173	}
ee0ea1d0 FB	174	}
ee0ea1d0 FB	175
41445300 AP	176	static void i440fx_write_config_xen(PCIDevice *dev,
	177	uint32_t address, uint32_t val, int len)
	178	{
	179	xen_piix_pci_write_config_client(address, val, len);
	180	i440fx_write_config(dev, address, val, len);
	181	}
	182
0c7d19e5	183	static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
ee0ea1d0	184	{
0a3bacf3	185	PCII440FXState *d = opaque;
52fc1d83	186	int ret, i;
ee0ea1d0	187
0a3bacf3	188	ret = pci_device_load(&d->dev, f);
ee0ea1d0 FB	189	if (ret < 0)
	190	return ret;
	191	i440fx_update_memory_mappings(d);
6c009fa4	192	qemu_get_8s(f, &d->smm_enabled);
52fc1d83	193
e735b55a IY	194	if (version_id == 2) {
	195	for (i = 0; i < PIIX_NUM_PIRQS; i++) {
	196	qemu_get_be32(f); /* dummy load for compatibility */
	197	}
	198	}
52fc1d83	199
ee0ea1d0 FB	200	return 0;
	201	}
	202
e59fb374	203	static int i440fx_post_load(void *opaque, int version_id)
0c7d19e5 JQ	204	{
	205	PCII440FXState *d = opaque;
	206
	207	i440fx_update_memory_mappings(d);
	208	return 0;
	209	}
	210
	211	static const VMStateDescription vmstate_i440fx = {
	212	.name = "I440FX",
	213	.version_id = 3,
	214	.minimum_version_id = 3,
	215	.minimum_version_id_old = 1,
	216	.load_state_old = i440fx_load_old,
752ff2fa	217	.post_load = i440fx_post_load,
0c7d19e5 JQ	218	.fields = (VMStateField []) {
	219	VMSTATE_PCI_DEVICE(dev, PCII440FXState),
	220	VMSTATE_UINT8(smm_enabled, PCII440FXState),
	221	VMSTATE_END_OF_LIST()
	222	}
	223	};
	224
81a322d4	225	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	226	{
8a14daa5	227	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395	228
f08b32fe	229	pci_host_conf_register_ioport(0xcf8, s);
502a5395	230
4f5e19e6	231	pci_host_data_register_ioport(0xcfc, s);
81a322d4	232	return 0;
8a14daa5	233	}
502a5395	234
0a3bacf3	235	static int i440fx_initfn(PCIDevice *dev)
8a14daa5	236	{
0a3bacf3	237	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0	238
0a3bacf3 JQ	239	pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
	240	pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
	241	d->dev.config[0x08] = 0x02; // revision
	242	pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
0a3bacf3	243
f2c688bb	244	d->dev.config[I440FX_SMRAM] = 0x02;
ee0ea1d0	245
f885f1ea	246	cpu_smm_register(&i440fx_set_smm, d);
81a322d4	247	return 0;
8a14daa5 GH	248	}
8a14daa5 GH	249
41445300 AP	250	static PCIBus i440fx_common_init(const char device_name,
	251	PCII440FXState **pi440fx_state,
	252	int *piix3_devfn,
	253	qemu_irq *pic, ram_addr_t ram_size)
8a14daa5 GH	254	{
	255	DeviceState *dev;
	256	PCIBus *b;
	257	PCIDevice *d;
	258	I440FXState *s;
7cd9eee0	259	PIIX3State *piix3;
8a14daa5 GH	260
	261	dev = qdev_create(NULL, "i440FX-pcihost");
	262	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
7cd9eee0	263	b = pci_bus_new(&s->busdev.qdev, NULL, 0);
8a14daa5	264	s->bus = b;
e23a1b33	265	qdev_init_nofail(dev);
8a14daa5	266
41445300	267	d = pci_create_simple(b, 0, device_name);
0a3bacf3	268	*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
8a14daa5	269
7cd9eee0	270	piix3 = DO_UPCAST(PIIX3State, dev,
fecb93c4	271	pci_create_simple_multifunction(b, -1, true, "PIIX3"));
7cd9eee0	272	piix3->pic = pic;
41445300	273
7cd9eee0 GH	274	(*pi440fx_state)->piix3 = piix3;
	275
	276	*piix3_devfn = piix3->dev.devfn;
85a750ca	277
ec5f92ce BW	278	ram_size = ram_size / 8 / 1024 / 1024;
	279	if (ram_size > 255)
	280	ram_size = 255;
	281	(*pi440fx_state)->dev.config[0x57]=ram_size;
	282
502a5395 PB	283	return b;
	284	}
	285
41445300 AP	286	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix3_devfn,
	287	qemu_irq *pic, ram_addr_t ram_size)
	288	{
	289	PCIBus *b;
	290
	291	b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
	292	pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, (*pi440fx_state)->piix3,
	293	PIIX_NUM_PIRQS);
	294
	295	return b;
	296	}
	297
	298	PCIBus i440fx_xen_init(PCII440FXState pi440fx_state, int piix3_devfn,
	299	qemu_irq *pic, ram_addr_t ram_size)
	300	{
	301	PCIBus *b;
	302
	303	b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic, ram_size);
	304	pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
	305	(*pi440fx_state)->piix3, PIIX_NUM_PIRQS);
	306
	307	return b;
	308	}
	309
502a5395	310	/* PIIX3 PCI to ISA bridge */
ab431c28 IY	311	static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
	312	{
	313	qemu_set_irq(piix3->pic[pic_irq],
	314	!!(piix3->pic_levels &
09de0f46	315	(((1ULL << PIIX_NUM_PIRQS) - 1) <<
ab431c28 IY	316	(pic_irq * PIIX_NUM_PIRQS))));
ab431c28 IY	317	}
502a5395	318
afe3ef1d	319	static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
ab431c28 IY	320	{
	321	int pic_irq;
	322	uint64_t mask;
	323
	324	pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
	325	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	326	return;
	327	}
	328
	329	mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
	330	piix3->pic_levels &= ~mask;
	331	piix3->pic_levels \|= mask * !!level;
	332
afe3ef1d	333	piix3_set_irq_pic(piix3, pic_irq);
ab431c28 IY	334	}
	335
	336	static void piix3_set_irq(void *opaque, int pirq, int level)
502a5395	337	{
7cd9eee0	338	PIIX3State *piix3 = opaque;
afe3ef1d	339	piix3_set_irq_level(piix3, pirq, level);
ab431c28	340	}
502a5395	341
ab431c28 IY	342	/* irq routing is changed. so rebuild bitmap */
	343	static void piix3_update_irq_levels(PIIX3State *piix3)
	344	{
	345	int pirq;
	346
	347	piix3->pic_levels = 0;
	348	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
	349	piix3_set_irq_level(piix3, pirq,
afe3ef1d	350	pci_bus_get_irq_level(piix3->dev.bus, pirq));
ab431c28 IY	351	}
	352	}
	353
	354	static void piix3_write_config(PCIDevice *dev,
	355	uint32_t address, uint32_t val, int len)
	356	{
	357	pci_default_write_config(dev, address, val, len);
	358	if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
	359	PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
	360	int pic_irq;
	361	piix3_update_irq_levels(piix3);
	362	for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
	363	piix3_set_irq_pic(piix3, pic_irq);
d2b59317	364	}
502a5395 PB	365	}
	366	}
	367
15a1956a	368	static void piix3_reset(void *opaque)
502a5395	369	{
fd37d881 JQ	370	PIIX3State *d = opaque;
fd37d881 JQ	371	uint8_t *pci_conf = d->dev.config;
502a5395 PB	372
	373	pci_conf[0x04] = 0x07; // master, memory and I/O
	374	pci_conf[0x05] = 0x00;
	375	pci_conf[0x06] = 0x00;
	376	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	377	pci_conf[0x4c] = 0x4d;
	378	pci_conf[0x4e] = 0x03;
	379	pci_conf[0x4f] = 0x00;
	380	pci_conf[0x60] = 0x80;
477afee3 AJ	381	pci_conf[0x61] = 0x80;
	382	pci_conf[0x62] = 0x80;
	383	pci_conf[0x63] = 0x80;
502a5395 PB	384	pci_conf[0x69] = 0x02;
	385	pci_conf[0x70] = 0x80;
	386	pci_conf[0x76] = 0x0c;
	387	pci_conf[0x77] = 0x0c;
	388	pci_conf[0x78] = 0x02;
	389	pci_conf[0x79] = 0x00;
	390	pci_conf[0x80] = 0x00;
	391	pci_conf[0x82] = 0x00;
	392	pci_conf[0xa0] = 0x08;
502a5395 PB	393	pci_conf[0xa2] = 0x00;
	394	pci_conf[0xa3] = 0x00;
	395	pci_conf[0xa4] = 0x00;
	396	pci_conf[0xa5] = 0x00;
	397	pci_conf[0xa6] = 0x00;
	398	pci_conf[0xa7] = 0x00;
	399	pci_conf[0xa8] = 0x0f;
	400	pci_conf[0xaa] = 0x00;
	401	pci_conf[0xab] = 0x00;
	402	pci_conf[0xac] = 0x00;
	403	pci_conf[0xae] = 0x00;
ab431c28 IY	404
	405	d->pic_levels = 0;
	406	}
	407
	408	static int piix3_post_load(void *opaque, int version_id)
	409	{
	410	PIIX3State *piix3 = opaque;
	411	piix3_update_irq_levels(piix3);
	412	return 0;
e735b55a	413	}
15a1956a	414
e735b55a IY	415	static void piix3_pre_save(void *opaque)
	416	{
	417	int i;
	418	PIIX3State *piix3 = opaque;
	419
	420	for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
	421	piix3->pci_irq_levels_vmstate[i] =
	422	pci_bus_get_irq_level(piix3->dev.bus, i);
	423	}
502a5395 PB	424	}
502a5395 PB	425
d1f171bd JQ	426	static const VMStateDescription vmstate_piix3 = {
	427	.name = "PIIX3",
	428	.version_id = 3,
	429	.minimum_version_id = 2,
	430	.minimum_version_id_old = 2,
ab431c28	431	.post_load = piix3_post_load,
e735b55a	432	.pre_save = piix3_pre_save,
d1f171bd JQ	433	.fields = (VMStateField []) {
d1f171bd JQ	434	VMSTATE_PCI_DEVICE(dev, PIIX3State),
e735b55a IY	435	VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
e735b55a IY	436	PIIX_NUM_PIRQS, 3),
d1f171bd	437	VMSTATE_END_OF_LIST()
da64182c	438	}
d1f171bd	439	};
1941d19c	440
fd37d881	441	static int piix3_initfn(PCIDevice *dev)
502a5395	442	{
fd37d881	443	PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395 PB	444	uint8_t *pci_conf;
502a5395 PB	445
fd37d881	446	isa_bus_new(&d->dev.qdev);
502a5395	447
fd37d881	448	pci_conf = d->dev.config;
deb54399 AL	449	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	450	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b	451	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
502a5395	452
a08d4367	453	qemu_register_reset(piix3_reset, d);
81a322d4	454	return 0;
502a5395	455	}
5c2b87e3	456
8a14daa5 GH	457	static PCIDeviceInfo i440fx_info[] = {
	458	{
	459	.qdev.name = "i440FX",
	460	.qdev.desc = "Host bridge",
0a3bacf3	461	.qdev.size = sizeof(PCII440FXState),
be73cfe2	462	.qdev.vmsd = &vmstate_i440fx,
8a14daa5	463	.qdev.no_user = 1,
0965f12d	464	.no_hotplug = 1,
8a14daa5 GH	465	.init = i440fx_initfn,
8a14daa5 GH	466	.config_write = i440fx_write_config,
41445300 AP	467	},{
	468	.qdev.name = "i440FX-xen",
	469	.qdev.desc = "Host bridge",
	470	.qdev.size = sizeof(PCII440FXState),
	471	.qdev.vmsd = &vmstate_i440fx,
	472	.qdev.no_user = 1,
	473	.init = i440fx_initfn,
	474	.config_write = i440fx_write_config_xen,
8a14daa5 GH	475	},{
	476	.qdev.name = "PIIX3",
	477	.qdev.desc = "ISA bridge",
fd37d881	478	.qdev.size = sizeof(PIIX3State),
be73cfe2	479	.qdev.vmsd = &vmstate_piix3,
8a14daa5	480	.qdev.no_user = 1,
0965f12d	481	.no_hotplug = 1,
8a14daa5	482	.init = piix3_initfn,
ab431c28	483	.config_write = piix3_write_config,
8a14daa5 GH	484	},{
	485	/* end of list */
	486	}
	487	};
	488
	489	static SysBusDeviceInfo i440fx_pcihost_info = {
	490	.init = i440fx_pcihost_initfn,
	491	.qdev.name = "i440FX-pcihost",
779206de	492	.qdev.fw_name = "pci",
8a14daa5 GH	493	.qdev.size = sizeof(I440FXState),
	494	.qdev.no_user = 1,
	495	};
	496
	497	static void i440fx_register(void)
	498	{
	499	sysbus_register_withprop(&i440fx_pcihost_info);
	500	pci_qdev_register_many(i440fx_info);
	501	}
	502	device_init(i440fx_register);