]> Git Repo - qemu.git/blame - target-sparc/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Allow op_opt for all targets
[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0 48/* global register indexes */
dc99a3f2 49static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr;
f5069b26 50static TCGv cpu_gregs[8];
dc99a3f2
BS		 51#ifdef TARGET_SPARC64
52static TCGv cpu_xcc;
53#endif
1a2fb1c0
BS		 54/* local register indexes (only used inside old micro ops) */
55static TCGv cpu_tmp0;
56
7a3f1944 57typedef struct DisasContext {
0f8a249a
BS		 58 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
59 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 60 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 61 int is_br;
e8af50a3 62 int mem_idx;
a80dde08 63 int fpu_enabled;
cf495bcf 64 struct TranslationBlock *tb;
7a3f1944
FB		 65} DisasContext;
66
aaed909a
FB		 67typedef struct sparc_def_t sparc_def_t;
68
62724a37
BS		 69struct sparc_def_t {
70 const unsigned char *name;
71 target_ulong iu_version;
72 uint32_t fpu_version;
73 uint32_t mmu_version;
6d5f237a 74 uint32_t mmu_bm;
3deaeab7
BS		 75 uint32_t mmu_ctpr_mask;
76 uint32_t mmu_cxr_mask;
77 uint32_t mmu_sfsr_mask;
78 uint32_t mmu_trcr_mask;
62724a37
BS		 79};
80
aaed909a
FB		 81static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
82
7a3f1944
FB		 83extern FILE *logfile;
84extern int loglevel;
85
3475187d 86// This function uses non-native bit order
7a3f1944
FB		 87#define GET_FIELD(X, FROM, TO) \
88 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
89
3475187d
FB		 90// This function uses the order in the manuals, i.e. bit 0 is 2^0
91#define GET_FIELD_SP(X, FROM, TO) \
92 GET_FIELD(X, 31 - (TO), 31 - (FROM))
93
94#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 95#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 96
97#ifdef TARGET_SPARC64
19f329ad 98#define FFPREG(r) (r)
0387d928 99#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 100#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 101#else
19f329ad 102#define FFPREG(r) (r)
c185970a 103#define DFPREG(r) (r & 0x1e)
1f587329 104#define QFPREG(r) (r & 0x1c)
3475187d
FB		 105#endif
106
107static int sign_extend(int x, int len)
108{
109 len = 32 - len;
110 return (x << len) >> len;
111}
112
7a3f1944
FB		 113#define IS_IMM (insn & (1<<13))
114
cf495bcf 115static void disas_sparc_insn(DisasContext * dc);
7a3f1944 116
3475187d
FB		 117#ifdef TARGET_SPARC64
118#define GEN32(func, NAME) \
a68156d0 119static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 120NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
121NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
122NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
123NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
124NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
125NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
126NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
127NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
128NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
129NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
130NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
131NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
132}; \
133static inline void func(int n) \
134{ \
135 NAME ## _table[n](); \
136}
137#else
e8af50a3 138#define GEN32(func, NAME) \
a68156d0 139static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 140NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
141NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
142NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
143NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
144NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
145NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
146NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
147NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
148}; \
149static inline void func(int n) \
150{ \
151 NAME ## _table[n](); \
152}
3475187d 153#endif
e8af50a3
FB		 154
155/* floating point registers moves */
156GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
157GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 158GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
159GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 160
161GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
162GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 163GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
164GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 165
1f587329
BS		 166#if defined(CONFIG_USER_ONLY)
167GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
168GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
169GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
170GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
171#endif
172
81ad8ba2
BS		 173/* moves */
174#ifdef CONFIG_USER_ONLY
3475187d 175#define supervisor(dc) 0
81ad8ba2 176#ifdef TARGET_SPARC64
e9ebed4d 177#define hypervisor(dc) 0
81ad8ba2 178#endif
3475187d 179#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 180#else
6f27aba6 181#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 182#ifdef TARGET_SPARC64
183#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6
BS		 184#define OP_LD_TABLE(width) \
185 static GenOpFunc * const gen_op_##width[] = { \
186 &gen_op_##width##_user, \
187 &gen_op_##width##_kernel, \
188 &gen_op_##width##_hypv, \
189 };
190#else
0f8a249a 191#define OP_LD_TABLE(width) \
a68156d0 192 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 193 &gen_op_##width##_user, \
194 &gen_op_##width##_kernel, \
81ad8ba2 195 };
3475187d 196#endif
6f27aba6
BS		 197#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
198#endif
e8af50a3 199
81ad8ba2 200#ifndef CONFIG_USER_ONLY
b25deda7
BS		 201#ifdef __i386__
202OP_LD_TABLE(std);
203#endif /* __i386__ */
e8af50a3
FB		 204OP_LD_TABLE(stf);
205OP_LD_TABLE(stdf);
206OP_LD_TABLE(ldf);
207OP_LD_TABLE(lddf);
81ad8ba2
BS		 208#endif
209
1a2fb1c0
BS		 210#ifdef TARGET_ABI32
211#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
212#else
213#define ABI32_MASK(addr)
214#endif
3391c818 215
1a2fb1c0 216static inline void gen_movl_simm_T1(int32_t val)
81ad8ba2 217{
1a2fb1c0 218 tcg_gen_movi_tl(cpu_T[1], val);
81ad8ba2
BS		 219}
220
1a2fb1c0 221static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 222{
1a2fb1c0
BS		 223 if (reg == 0)
224 tcg_gen_movi_tl(tn, 0);
225 else if (reg < 8)
f5069b26 226 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
1a2fb1c0 227 else {
1a2fb1c0 228 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 229 }
230}
231
1a2fb1c0 232static inline void gen_movl_reg_T0(int reg)
81ad8ba2 233{
1a2fb1c0 234 gen_movl_reg_TN(reg, cpu_T[0]);
81ad8ba2
BS		 235}
236
1a2fb1c0 237static inline void gen_movl_reg_T1(int reg)
81ad8ba2 238{
1a2fb1c0 239 gen_movl_reg_TN(reg, cpu_T[1]);
81ad8ba2
BS		 240}
241
b25deda7
BS		 242#ifdef __i386__
243static inline void gen_movl_reg_T2(int reg)
244{
245 gen_movl_reg_TN(reg, cpu_T[2]);
246}
247
248#endif /* __i386__ */
1a2fb1c0 249static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 250{
1a2fb1c0
BS		 251 if (reg == 0)
252 return;
253 else if (reg < 8)
f5069b26 254 tcg_gen_mov_tl(cpu_gregs[reg], tn);
1a2fb1c0 255 else {
1a2fb1c0 256 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 257 }
258}
259
1a2fb1c0 260static inline void gen_movl_T0_reg(int reg)
3475187d 261{
1a2fb1c0 262 gen_movl_TN_reg(reg, cpu_T[0]);
3475187d
FB		 263}
264
1a2fb1c0 265static inline void gen_movl_T1_reg(int reg)
3475187d 266{
1a2fb1c0 267 gen_movl_TN_reg(reg, cpu_T[1]);
3475187d
FB		 268}
269
1a2fb1c0 270static inline void gen_op_movl_T0_env(size_t offset)
7a3f1944 271{
1a2fb1c0 272 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 273}
274
1a2fb1c0 275static inline void gen_op_movl_env_T0(size_t offset)
7a3f1944 276{
1a2fb1c0 277 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 278}
279
1a2fb1c0 280static inline void gen_op_movtl_T0_env(size_t offset)
7a3f1944 281{
1a2fb1c0 282 tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 283}
284
1a2fb1c0 285static inline void gen_op_movtl_env_T0(size_t offset)
7a3f1944 286{
1a2fb1c0 287 tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 288}
289
1a2fb1c0 290static inline void gen_op_add_T1_T0(void)
7a3f1944 291{
1a2fb1c0 292 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 293}
294
1a2fb1c0 295static inline void gen_op_or_T1_T0(void)
7a3f1944 296{
1a2fb1c0 297 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 298}
299
1a2fb1c0 300static inline void gen_op_xor_T1_T0(void)
7a3f1944 301{
1a2fb1c0 302 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 303}
304
3475187d
FB		 305static inline void gen_jmp_im(target_ulong pc)
306{
1a2fb1c0
BS		 307 tcg_gen_movi_tl(cpu_tmp0, pc);
308 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
3475187d
FB		 309}
310
311static inline void gen_movl_npc_im(target_ulong npc)
312{
1a2fb1c0
BS		 313 tcg_gen_movi_tl(cpu_tmp0, npc);
314 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
3475187d
FB		 315}
316
5fafdf24 317static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 318 target_ulong pc, target_ulong npc)
319{
320 TranslationBlock *tb;
321
322 tb = s->tb;
323 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
324 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
325 /* jump to same page: we can use a direct jump */
57fec1fe 326 tcg_gen_goto_tb(tb_num);
6e256c93
FB		 327 gen_jmp_im(pc);
328 gen_movl_npc_im(npc);
57fec1fe 329 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 330 } else {
331 /* jump to another page: currently not optimized */
332 gen_jmp_im(pc);
333 gen_movl_npc_im(npc);
57fec1fe 334 tcg_gen_exit_tb(0);
6e256c93
FB		 335 }
336}
337
19f329ad
BS		 338// XXX suboptimal
339static inline void gen_mov_reg_N(TCGv reg, TCGv src)
340{
341 tcg_gen_shri_i32(reg, src, 23);
342 tcg_gen_andi_tl(reg, reg, 0x1);
343}
344
345static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
346{
347 tcg_gen_shri_i32(reg, src, 22);
348 tcg_gen_andi_tl(reg, reg, 0x1);
349}
350
351static inline void gen_mov_reg_V(TCGv reg, TCGv src)
352{
353 tcg_gen_shri_i32(reg, src, 21);
354 tcg_gen_andi_tl(reg, reg, 0x1);
355}
356
357static inline void gen_mov_reg_C(TCGv reg, TCGv src)
358{
359 tcg_gen_shri_i32(reg, src, 20);
360 tcg_gen_andi_tl(reg, reg, 0x1);
361}
362
dc99a3f2
BS		 363static inline void gen_op_exception(int exception)
364{
365 TCGv r_except;
366
367 r_except = tcg_temp_new(TCG_TYPE_I32);
368 tcg_gen_movi_i32(r_except, exception);
369 tcg_gen_helper_0_1(raise_exception, r_except);
370}
371
372static inline void gen_cc_clear(void)
373{
374 tcg_gen_movi_i32(cpu_psr, 0);
375#ifdef TARGET_SPARC64
376 tcg_gen_movi_i32(cpu_xcc, 0);
377#endif
378}
379
380/* old op:
381 if (!T0)
382 env->psr |= PSR_ZERO;
383 if ((int32_t) T0 < 0)
384 env->psr |= PSR_NEG;
385*/
386static inline void gen_cc_NZ(TCGv dst)
387{
388 int l1, l2;
389 TCGv r_zero;
390
391 l1 = gen_new_label();
392 l2 = gen_new_label();
1ec6d2ea 393 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 394 tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
395 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
396 gen_set_label(l1);
397 tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
398 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
399 gen_set_label(l2);
400#ifdef TARGET_SPARC64
401 {
402 int l3, l4;
403
404 l3 = gen_new_label();
405 l4 = gen_new_label();
406 tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
407 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
408 gen_set_label(l3);
409 tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
410 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
411 gen_set_label(l4);
412 }
413#endif
414}
415
416/* old op:
417 if (T0 < src1)
418 env->psr |= PSR_CARRY;
419*/
420static inline void gen_cc_C_add(TCGv dst, TCGv src1)
421{
422 int l1;
423
424 l1 = gen_new_label();
425 tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
426 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
427 gen_set_label(l1);
428#ifdef TARGET_SPARC64
429 {
430 int l2;
431
432 l2 = gen_new_label();
433 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
434 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
435 gen_set_label(l2);
436 }
437#endif
438}
439
440/* old op:
441 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
442 env->psr |= PSR_OVF;
443*/
444static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
445{
446 TCGv r_temp, r_temp2, r_temp3, r_zero;
447 int l1;
448
449 l1 = gen_new_label();
450
451 r_temp = tcg_temp_new(TCG_TYPE_TL);
452 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
453 r_temp3 = tcg_temp_new(TCG_TYPE_TL);
1ec6d2ea 454 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 455 tcg_gen_xor_tl(r_temp, src1, src2);
456 tcg_gen_xori_tl(r_temp, r_temp, -1);
457 tcg_gen_xor_tl(r_temp2, src1, dst);
458 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
459 tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
460 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
461 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
462 gen_set_label(l1);
463#ifdef TARGET_SPARC64
464 {
465 int l2;
466
467 l2 = gen_new_label();
dc99a3f2
BS		 468 tcg_gen_xor_tl(r_temp, src1, src2);
469 tcg_gen_xori_tl(r_temp, r_temp, -1);
470 tcg_gen_xor_tl(r_temp2, src1, dst);
471 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
472 tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
473 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
474 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
475 gen_set_label(l2);
476 }
477#endif
478}
479
480static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
481{
482 TCGv r_temp, r_temp2, r_temp3, r_zero;
483 int l1;
484
485 l1 = gen_new_label();
486
487 r_temp = tcg_temp_new(TCG_TYPE_TL);
488 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
489 r_temp3 = tcg_temp_new(TCG_TYPE_TL);
1ec6d2ea 490 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 491 tcg_gen_xor_tl(r_temp, src1, src2);
492 tcg_gen_xori_tl(r_temp, r_temp, -1);
493 tcg_gen_xor_tl(r_temp2, src1, dst);
494 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
495 tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
496 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
497 gen_op_exception(TT_TOVF);
498 gen_set_label(l1);
499#ifdef TARGET_SPARC64
500 {
501 int l2;
502
503 l2 = gen_new_label();
dc99a3f2
BS		 504 tcg_gen_xor_tl(r_temp, src1, src2);
505 tcg_gen_xori_tl(r_temp, r_temp, -1);
506 tcg_gen_xor_tl(r_temp2, src1, dst);
507 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
508 tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
509 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
510 gen_op_exception(TT_TOVF);
511 gen_set_label(l2);
512 }
513#endif
514}
515
516static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
517{
518 int l1;
519 TCGv r_zero, r_temp;
520
521 l1 = gen_new_label();
1ec6d2ea 522 r_zero = tcg_const_tl(0);
dc99a3f2 523 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 524 tcg_gen_or_tl(r_temp, src1, src2);
525 tcg_gen_andi_tl(r_temp, r_temp, 0x3);
526 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
527 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
528 gen_set_label(l1);
529}
530
531static inline void gen_tag_tv(TCGv src1, TCGv src2)
532{
533 int l1;
534 TCGv r_zero, r_temp;
535
536 l1 = gen_new_label();
1ec6d2ea 537 r_zero = tcg_const_tl(0);
dc99a3f2 538 r_temp = tcg_temp_new(TCG_TYPE_TL);
dc99a3f2
BS		 539 tcg_gen_or_tl(r_temp, src1, src2);
540 tcg_gen_andi_tl(r_temp, r_temp, 0x3);
541 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
542 gen_op_exception(TT_TOVF);
543 gen_set_label(l1);
544}
545
546static inline void gen_op_add_T1_T0_cc(void)
547{
548 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
549 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
550 gen_cc_clear();
551 gen_cc_NZ(cpu_T[0]);
552 gen_cc_C_add(cpu_T[0], cpu_cc_src);
553 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
554}
555
556static inline void gen_op_addx_T1_T0_cc(void)
557{
558 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
559 gen_mov_reg_C(cpu_tmp0, cpu_psr);
560 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
561 gen_cc_clear();
562 gen_cc_C_add(cpu_T[0], cpu_cc_src);
563 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
564 gen_cc_C_add(cpu_T[0], cpu_cc_src);
565 gen_cc_NZ(cpu_T[0]);
566 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
567}
568
569static inline void gen_op_tadd_T1_T0_cc(void)
570{
571 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
572 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
573 gen_cc_clear();
574 gen_cc_NZ(cpu_T[0]);
575 gen_cc_C_add(cpu_T[0], cpu_cc_src);
576 gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
577 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
578}
579
580static inline void gen_op_tadd_T1_T0_ccTV(void)
581{
582 gen_tag_tv(cpu_T[0], cpu_T[1]);
583 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
584 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
585 gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
586 gen_cc_clear();
587 gen_cc_NZ(cpu_T[0]);
588 gen_cc_C_add(cpu_T[0], cpu_cc_src);
589}
590
591/* old op:
592 if (src1 < T1)
593 env->psr |= PSR_CARRY;
594*/
595static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
596{
597 int l1;
598
599 l1 = gen_new_label();
600 tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
601 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
602 gen_set_label(l1);
603#ifdef TARGET_SPARC64
604 {
605 int l2;
606
607 l2 = gen_new_label();
608 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
609 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
610 gen_set_label(l2);
611 }
612#endif
613}
614
615/* old op:
616 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
617 env->psr |= PSR_OVF;
618*/
619static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
620{
621 TCGv r_temp, r_temp2, r_temp3, r_zero;
622 int l1;
623
624 l1 = gen_new_label();
625
626 r_temp = tcg_temp_new(TCG_TYPE_TL);
627 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
628 r_temp3 = tcg_temp_new(TCG_TYPE_TL);
1ec6d2ea 629 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 630 tcg_gen_xor_tl(r_temp, src1, src2);
631 tcg_gen_xor_tl(r_temp2, src1, dst);
632 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
633 tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
634 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
635 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
636 gen_set_label(l1);
637#ifdef TARGET_SPARC64
638 {
639 int l2;
640
641 l2 = gen_new_label();
dc99a3f2
BS		 642 tcg_gen_xor_tl(r_temp, src1, src2);
643 tcg_gen_xor_tl(r_temp2, src1, dst);
644 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
645 tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
646 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
647 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
648 gen_set_label(l2);
649 }
650#endif
651}
652
653static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
654{
655 TCGv r_temp, r_temp2, r_temp3, r_zero;
656 int l1;
657
658 l1 = gen_new_label();
659
660 r_temp = tcg_temp_new(TCG_TYPE_TL);
661 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
662 r_temp3 = tcg_temp_new(TCG_TYPE_TL);
1ec6d2ea 663 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 664 tcg_gen_xor_tl(r_temp, src1, src2);
665 tcg_gen_xor_tl(r_temp2, src1, dst);
666 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
667 tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
668 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
669 gen_op_exception(TT_TOVF);
670 gen_set_label(l1);
671#ifdef TARGET_SPARC64
672 {
673 int l2;
674
675 l2 = gen_new_label();
dc99a3f2
BS		 676 tcg_gen_xor_tl(r_temp, src1, src2);
677 tcg_gen_xor_tl(r_temp2, src1, dst);
678 tcg_gen_and_tl(r_temp, r_temp, r_temp2);
679 tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
680 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
681 gen_op_exception(TT_TOVF);
682 gen_set_label(l2);
683 }
684#endif
685}
686
687static inline void gen_op_sub_T1_T0_cc(void)
688{
689 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
690 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
691 gen_cc_clear();
692 gen_cc_NZ(cpu_T[0]);
693 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
694 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
695}
696
697static inline void gen_op_subx_T1_T0_cc(void)
698{
699 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
700 gen_mov_reg_C(cpu_tmp0, cpu_psr);
701 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
702 gen_cc_clear();
703 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
704 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
705 gen_cc_C_sub(cpu_T[0], cpu_cc_src);
706 gen_cc_NZ(cpu_T[0]);
707 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
708}
709
710static inline void gen_op_tsub_T1_T0_cc(void)
711{
712 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
713 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
714 gen_cc_clear();
715 gen_cc_NZ(cpu_T[0]);
716 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
717 gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
718 gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
719}
720
721static inline void gen_op_tsub_T1_T0_ccTV(void)
722{
723 gen_tag_tv(cpu_T[0], cpu_T[1]);
724 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
725 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
726 gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
727 gen_cc_clear();
728 gen_cc_NZ(cpu_T[0]);
729 gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
730}
731
732static inline void gen_op_div_cc(void)
733{
734 int l1;
735 TCGv r_zero;
736
737 gen_cc_clear();
738 gen_cc_NZ(cpu_T[0]);
739 l1 = gen_new_label();
1ec6d2ea 740 r_zero = tcg_const_tl(0);
dc99a3f2
BS		 741 tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
742 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
743 gen_set_label(l1);
744}
745
746static inline void gen_op_logic_T0_cc(void)
747{
748 gen_cc_clear();
749 gen_cc_NZ(cpu_T[0]);
750}
751
19f329ad
BS		 752// 1
753static inline void gen_op_eval_ba(TCGv dst)
754{
755 tcg_gen_movi_tl(dst, 1);
756}
757
758// Z
759static inline void gen_op_eval_be(TCGv dst, TCGv src)
760{
761 gen_mov_reg_Z(dst, src);
762}
763
764// Z | (N ^ V)
765static inline void gen_op_eval_ble(TCGv dst, TCGv src)
766{
767 TCGv r_flag;
768
769 r_flag = tcg_temp_new(TCG_TYPE_TL);
770 gen_mov_reg_N(r_flag, src);
771 gen_mov_reg_V(dst, src);
772 tcg_gen_xor_tl(dst, dst, r_flag);
773 gen_mov_reg_Z(r_flag, src);
774 tcg_gen_or_tl(dst, dst, r_flag);
775}
776
777// N ^ V
778static inline void gen_op_eval_bl(TCGv dst, TCGv src)
779{
780 TCGv r_V;
781
782 r_V = tcg_temp_new(TCG_TYPE_TL);
783 gen_mov_reg_V(r_V, src);
784 gen_mov_reg_N(dst, src);
785 tcg_gen_xor_tl(dst, dst, r_V);
786}
787
788// C | Z
789static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
790{
791 TCGv r_Z;
792
793 r_Z = tcg_temp_new(TCG_TYPE_TL);
794 gen_mov_reg_Z(r_Z, src);
795 gen_mov_reg_C(dst, src);
796 tcg_gen_or_tl(dst, dst, r_Z);
797}
798
799// C
800static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
801{
802 gen_mov_reg_C(dst, src);
803}
804
805// V
806static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
807{
808 gen_mov_reg_V(dst, src);
809}
810
811// 0
812static inline void gen_op_eval_bn(TCGv dst)
813{
814 tcg_gen_movi_tl(dst, 0);
815}
816
817// N
818static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
819{
820 gen_mov_reg_N(dst, src);
821}
822
823// !Z
824static inline void gen_op_eval_bne(TCGv dst, TCGv src)
825{
826 gen_mov_reg_Z(dst, src);
827 tcg_gen_xori_tl(dst, dst, 0x1);
828}
829
830// !(Z | (N ^ V))
831static inline void gen_op_eval_bg(TCGv dst, TCGv src)
832{
833 TCGv r_flag;
834
835 r_flag = tcg_temp_new(TCG_TYPE_TL);
836 gen_mov_reg_N(r_flag, src);
837 gen_mov_reg_V(dst, src);
838 tcg_gen_xor_tl(dst, dst, r_flag);
839 gen_mov_reg_Z(r_flag, src);
840 tcg_gen_or_tl(dst, dst, r_flag);
841 tcg_gen_xori_tl(dst, dst, 0x1);
842}
843
844// !(N ^ V)
845static inline void gen_op_eval_bge(TCGv dst, TCGv src)
846{
847 TCGv r_V;
848
849 r_V = tcg_temp_new(TCG_TYPE_TL);
850 gen_mov_reg_V(r_V, src);
851 gen_mov_reg_N(dst, src);
852 tcg_gen_xor_tl(dst, dst, r_V);
853 tcg_gen_xori_tl(dst, dst, 0x1);
854}
855
856// !(C | Z)
857static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
858{
859 TCGv r_Z;
860
861 r_Z = tcg_temp_new(TCG_TYPE_TL);
862 gen_mov_reg_Z(r_Z, src);
863 gen_mov_reg_C(dst, src);
864 tcg_gen_or_tl(dst, dst, r_Z);
865 tcg_gen_xori_tl(dst, dst, 0x1);
866}
867
868// !C
869static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
870{
871 gen_mov_reg_C(dst, src);
872 tcg_gen_xori_tl(dst, dst, 0x1);
873}
874
875// !N
876static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
877{
878 gen_mov_reg_N(dst, src);
879 tcg_gen_xori_tl(dst, dst, 0x1);
880}
881
882// !V
883static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
884{
885 gen_mov_reg_V(dst, src);
886 tcg_gen_xori_tl(dst, dst, 0x1);
887}
888
889/*
890 FPSR bit field FCC1 | FCC0:
891 0 =
892 1 <
893 2 >
894 3 unordered
895*/
896static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
897 unsigned int fcc_offset)
898{
899 tcg_gen_shri_i32(reg, src, 10 + fcc_offset);
900 tcg_gen_andi_tl(reg, reg, 0x1);
901}
902
903static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
904 unsigned int fcc_offset)
905{
906 tcg_gen_shri_i32(reg, src, 11 + fcc_offset);
907 tcg_gen_andi_tl(reg, reg, 0x1);
908}
909
910// !0: FCC0 | FCC1
911static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
912 unsigned int fcc_offset)
913{
914 TCGv r_fcc1;
915
916 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
917 gen_mov_reg_FCC0(dst, src, fcc_offset);
918 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
919 tcg_gen_or_tl(dst, dst, r_fcc1);
920}
921
922// 1 or 2: FCC0 ^ FCC1
923static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
924 unsigned int fcc_offset)
925{
926 TCGv r_fcc1;
927
928 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
929 gen_mov_reg_FCC0(dst, src, fcc_offset);
930 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
931 tcg_gen_xor_tl(dst, dst, r_fcc1);
932}
933
934// 1 or 3: FCC0
935static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
936 unsigned int fcc_offset)
937{
938 gen_mov_reg_FCC0(dst, src, fcc_offset);
939}
940
941// 1: FCC0 & !FCC1
942static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
943 unsigned int fcc_offset)
944{
945 TCGv r_fcc1;
946
947 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
948 gen_mov_reg_FCC0(dst, src, fcc_offset);
949 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
950 tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
951 tcg_gen_and_tl(dst, dst, r_fcc1);
952}
953
954// 2 or 3: FCC1
955static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
956 unsigned int fcc_offset)
957{
958 gen_mov_reg_FCC1(dst, src, fcc_offset);
959}
960
961// 2: !FCC0 & FCC1
962static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
963 unsigned int fcc_offset)
964{
965 TCGv r_fcc1;
966
967 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
968 gen_mov_reg_FCC0(dst, src, fcc_offset);
969 tcg_gen_xori_tl(dst, dst, 0x1);
970 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
971 tcg_gen_and_tl(dst, dst, r_fcc1);
972}
973
974// 3: FCC0 & FCC1
975static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
976 unsigned int fcc_offset)
977{
978 TCGv r_fcc1;
979
980 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
981 gen_mov_reg_FCC0(dst, src, fcc_offset);
982 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
983 tcg_gen_and_tl(dst, dst, r_fcc1);
984}
985
986// 0: !(FCC0 | FCC1)
987static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
988 unsigned int fcc_offset)
989{
990 TCGv r_fcc1;
991
992 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
993 gen_mov_reg_FCC0(dst, src, fcc_offset);
994 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
995 tcg_gen_or_tl(dst, dst, r_fcc1);
996 tcg_gen_xori_tl(dst, dst, 0x1);
997}
998
999// 0 or 3: !(FCC0 ^ FCC1)
1000static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1001 unsigned int fcc_offset)
1002{
1003 TCGv r_fcc1;
1004
1005 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1006 gen_mov_reg_FCC0(dst, src, fcc_offset);
1007 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1008 tcg_gen_xor_tl(dst, dst, r_fcc1);
1009 tcg_gen_xori_tl(dst, dst, 0x1);
1010}
1011
1012// 0 or 2: !FCC0
1013static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1014 unsigned int fcc_offset)
1015{
1016 gen_mov_reg_FCC0(dst, src, fcc_offset);
1017 tcg_gen_xori_tl(dst, dst, 0x1);
1018}
1019
1020// !1: !(FCC0 & !FCC1)
1021static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1022 unsigned int fcc_offset)
1023{
1024 TCGv r_fcc1;
1025
1026 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1027 gen_mov_reg_FCC0(dst, src, fcc_offset);
1028 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1029 tcg_gen_xori_tl(r_fcc1, r_fcc1, 0x1);
1030 tcg_gen_and_tl(dst, dst, r_fcc1);
1031 tcg_gen_xori_tl(dst, dst, 0x1);
1032}
1033
1034// 0 or 1: !FCC1
1035static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1036 unsigned int fcc_offset)
1037{
1038 gen_mov_reg_FCC1(dst, src, fcc_offset);
1039 tcg_gen_xori_tl(dst, dst, 0x1);
1040}
1041
1042// !2: !(!FCC0 & FCC1)
1043static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1044 unsigned int fcc_offset)
1045{
1046 TCGv r_fcc1;
1047
1048 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1049 gen_mov_reg_FCC0(dst, src, fcc_offset);
1050 tcg_gen_xori_tl(dst, dst, 0x1);
1051 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1052 tcg_gen_and_tl(dst, dst, r_fcc1);
1053 tcg_gen_xori_tl(dst, dst, 0x1);
1054}
1055
1056// !3: !(FCC0 & FCC1)
1057static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1058 unsigned int fcc_offset)
1059{
1060 TCGv r_fcc1;
1061
1062 r_fcc1 = tcg_temp_new(TCG_TYPE_TL);
1063 gen_mov_reg_FCC0(dst, src, fcc_offset);
1064 gen_mov_reg_FCC1(r_fcc1, src, fcc_offset);
1065 tcg_gen_and_tl(dst, dst, r_fcc1);
1066 tcg_gen_xori_tl(dst, dst, 0x1);
1067}
1068
46525e1f 1069static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 1070 target_ulong pc2, TCGv r_cond)
83469015 1071{
19f329ad 1072 TCGv r_zero;
83469015
FB		 1073 int l1;
1074
1075 l1 = gen_new_label();
1ec6d2ea 1076 r_zero = tcg_const_tl(0);
83469015 1077
19f329ad 1078 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
83469015 1079
6e256c93 1080 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 1081
1082 gen_set_label(l1);
6e256c93 1083 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 1084}
1085
46525e1f 1086static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
19f329ad 1087 target_ulong pc2, TCGv r_cond)
83469015 1088{
19f329ad 1089 TCGv r_zero;
83469015
FB		 1090 int l1;
1091
1092 l1 = gen_new_label();
1ec6d2ea 1093 r_zero = tcg_const_tl(0);
83469015 1094
19f329ad 1095 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
83469015 1096
6e256c93 1097 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 1098
1099 gen_set_label(l1);
6e256c93 1100 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 1101}
1102
46525e1f
BS		 1103static inline void gen_branch(DisasContext *dc, target_ulong pc,
1104 target_ulong npc)
83469015 1105{
6e256c93 1106 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 1107}
1108
19f329ad
BS		 1109static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1110 TCGv r_cond)
83469015 1111{
19f329ad 1112 TCGv r_zero;
83469015
FB		 1113 int l1, l2;
1114
1115 l1 = gen_new_label();
1116 l2 = gen_new_label();
1ec6d2ea 1117 r_zero = tcg_const_tl(0);
19f329ad
BS		 1118
1119 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1);
83469015
FB		 1120
1121 gen_movl_npc_im(npc1);
1122 gen_op_jmp_label(l2);
1123
1124 gen_set_label(l1);
1125 gen_movl_npc_im(npc2);
1126 gen_set_label(l2);
1127}
1128
1129/* call this function before using T2 as it may have been set for a jump */
1130static inline void flush_T2(DisasContext * dc)
1131{
1132 if (dc->npc == JUMP_PC) {
19f329ad 1133 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
83469015
FB		 1134 dc->npc = DYNAMIC_PC;
1135 }
1136}
1137
72cbca10
FB		 1138static inline void save_npc(DisasContext * dc)
1139{
1140 if (dc->npc == JUMP_PC) {
19f329ad 1141 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
72cbca10
FB		 1142 dc->npc = DYNAMIC_PC;
1143 } else if (dc->npc != DYNAMIC_PC) {
3475187d 1144 gen_movl_npc_im(dc->npc);
72cbca10
FB		 1145 }
1146}
1147
1148static inline void save_state(DisasContext * dc)
1149{
3475187d 1150 gen_jmp_im(dc->pc);
72cbca10
FB		 1151 save_npc(dc);
1152}
1153
0bee699e
FB		 1154static inline void gen_mov_pc_npc(DisasContext * dc)
1155{
1156 if (dc->npc == JUMP_PC) {
19f329ad 1157 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
38bc628b
BS		 1158 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1159 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 1160 dc->pc = DYNAMIC_PC;
1161 } else if (dc->npc == DYNAMIC_PC) {
38bc628b
BS		 1162 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1163 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 1164 dc->pc = DYNAMIC_PC;
1165 } else {
1166 dc->pc = dc->npc;
1167 }
1168}
1169
38bc628b
BS		 1170static inline void gen_op_next_insn(void)
1171{
1172 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1173 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
1174 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
1175 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
1176}
1177
19f329ad
BS		 1178static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1179{
1180 TCGv r_src;
3475187d 1181
3475187d 1182#ifdef TARGET_SPARC64
19f329ad 1183 if (cc)
dc99a3f2 1184 r_src = cpu_xcc;
19f329ad 1185 else
dc99a3f2 1186 r_src = cpu_psr;
3475187d 1187#else
dc99a3f2 1188 r_src = cpu_psr;
3475187d 1189#endif
19f329ad
BS		 1190 switch (cond) {
1191 case 0x0:
1192 gen_op_eval_bn(r_dst);
1193 break;
1194 case 0x1:
1195 gen_op_eval_be(r_dst, r_src);
1196 break;
1197 case 0x2:
1198 gen_op_eval_ble(r_dst, r_src);
1199 break;
1200 case 0x3:
1201 gen_op_eval_bl(r_dst, r_src);
1202 break;
1203 case 0x4:
1204 gen_op_eval_bleu(r_dst, r_src);
1205 break;
1206 case 0x5:
1207 gen_op_eval_bcs(r_dst, r_src);
1208 break;
1209 case 0x6:
1210 gen_op_eval_bneg(r_dst, r_src);
1211 break;
1212 case 0x7:
1213 gen_op_eval_bvs(r_dst, r_src);
1214 break;
1215 case 0x8:
1216 gen_op_eval_ba(r_dst);
1217 break;
1218 case 0x9:
1219 gen_op_eval_bne(r_dst, r_src);
1220 break;
1221 case 0xa:
1222 gen_op_eval_bg(r_dst, r_src);
1223 break;
1224 case 0xb:
1225 gen_op_eval_bge(r_dst, r_src);
1226 break;
1227 case 0xc:
1228 gen_op_eval_bgu(r_dst, r_src);
1229 break;
1230 case 0xd:
1231 gen_op_eval_bcc(r_dst, r_src);
1232 break;
1233 case 0xe:
1234 gen_op_eval_bpos(r_dst, r_src);
1235 break;
1236 case 0xf:
1237 gen_op_eval_bvc(r_dst, r_src);
1238 break;
1239 }
1240}
7a3f1944 1241
19f329ad 1242static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
e8af50a3 1243{
19f329ad
BS		 1244 TCGv r_src;
1245 unsigned int offset;
1246
1247 r_src = tcg_temp_new(TCG_TYPE_TL);
1248 tcg_gen_ld_tl(r_src, cpu_env, offsetof(CPUSPARCState, fsr));
1249
1250 switch (cc) {
1251 default:
1252 case 0x0:
1253 offset = 0;
1254 break;
1255 case 0x1:
1256 offset = 32 - 10;
1257 break;
1258 case 0x2:
1259 offset = 34 - 10;
1260 break;
1261 case 0x3:
1262 offset = 36 - 10;
1263 break;
1264 }
1265
1266 switch (cond) {
1267 case 0x0:
1268 gen_op_eval_bn(r_dst);
1269 break;
1270 case 0x1:
1271 gen_op_eval_fbne(r_dst, r_src, offset);
1272 break;
1273 case 0x2:
1274 gen_op_eval_fblg(r_dst, r_src, offset);
1275 break;
1276 case 0x3:
1277 gen_op_eval_fbul(r_dst, r_src, offset);
1278 break;
1279 case 0x4:
1280 gen_op_eval_fbl(r_dst, r_src, offset);
1281 break;
1282 case 0x5:
1283 gen_op_eval_fbug(r_dst, r_src, offset);
1284 break;
1285 case 0x6:
1286 gen_op_eval_fbg(r_dst, r_src, offset);
1287 break;
1288 case 0x7:
1289 gen_op_eval_fbu(r_dst, r_src, offset);
1290 break;
1291 case 0x8:
1292 gen_op_eval_ba(r_dst);
1293 break;
1294 case 0x9:
1295 gen_op_eval_fbe(r_dst, r_src, offset);
1296 break;
1297 case 0xa:
1298 gen_op_eval_fbue(r_dst, r_src, offset);
1299 break;
1300 case 0xb:
1301 gen_op_eval_fbge(r_dst, r_src, offset);
1302 break;
1303 case 0xc:
1304 gen_op_eval_fbuge(r_dst, r_src, offset);
1305 break;
1306 case 0xd:
1307 gen_op_eval_fble(r_dst, r_src, offset);
1308 break;
1309 case 0xe:
1310 gen_op_eval_fbule(r_dst, r_src, offset);
1311 break;
1312 case 0xf:
1313 gen_op_eval_fbo(r_dst, r_src, offset);
1314 break;
1315 }
e8af50a3 1316}
00f219bf 1317
19f329ad 1318#ifdef TARGET_SPARC64
00f219bf
BS		 1319// Inverted logic
1320static const int gen_tcg_cond_reg[8] = {
1321 -1,
1322 TCG_COND_NE,
1323 TCG_COND_GT,
1324 TCG_COND_GE,
1325 -1,
1326 TCG_COND_EQ,
1327 TCG_COND_LE,
1328 TCG_COND_LT,
1329};
19f329ad
BS		 1330
1331static inline void gen_cond_reg(TCGv r_dst, int cond)
1332{
1333 TCGv r_zero;
1334 int l1;
1335
1336 l1 = gen_new_label();
1ec6d2ea 1337 r_zero = tcg_const_tl(0);
19f329ad
BS		 1338 tcg_gen_mov_tl(r_dst, r_zero);
1339 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1340 tcg_gen_movi_tl(r_dst, 1);
1341 gen_set_label(l1);
1342}
3475187d 1343#endif
cf495bcf 1344
0bee699e 1345/* XXX: potentially incorrect if dynamic npc */
3475187d 1346static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1347{
cf495bcf 1348 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1349 target_ulong target = dc->pc + offset;
5fafdf24 1350
cf495bcf 1351 if (cond == 0x0) {
0f8a249a
BS		 1352 /* unconditional not taken */
1353 if (a) {
1354 dc->pc = dc->npc + 4;
1355 dc->npc = dc->pc + 4;
1356 } else {
1357 dc->pc = dc->npc;
1358 dc->npc = dc->pc + 4;
1359 }
cf495bcf 1360 } else if (cond == 0x8) {
0f8a249a
BS		 1361 /* unconditional taken */
1362 if (a) {
1363 dc->pc = target;
1364 dc->npc = dc->pc + 4;
1365 } else {
1366 dc->pc = dc->npc;
1367 dc->npc = target;
1368 }
cf495bcf 1369 } else {
72cbca10 1370 flush_T2(dc);
19f329ad 1371 gen_cond(cpu_T[2], cc, cond);
0f8a249a 1372 if (a) {
19f329ad 1373 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
cf495bcf 1374 dc->is_br = 1;
0f8a249a 1375 } else {
cf495bcf 1376 dc->pc = dc->npc;
72cbca10
FB		 1377 dc->jump_pc[0] = target;
1378 dc->jump_pc[1] = dc->npc + 4;
1379 dc->npc = JUMP_PC;
0f8a249a 1380 }
cf495bcf 1381 }
7a3f1944
FB		 1382}
1383
0bee699e 1384/* XXX: potentially incorrect if dynamic npc */
3475187d 1385static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1386{
1387 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1388 target_ulong target = dc->pc + offset;
1389
e8af50a3 1390 if (cond == 0x0) {
0f8a249a
BS		 1391 /* unconditional not taken */
1392 if (a) {
1393 dc->pc = dc->npc + 4;
1394 dc->npc = dc->pc + 4;
1395 } else {
1396 dc->pc = dc->npc;
1397 dc->npc = dc->pc + 4;
1398 }
e8af50a3 1399 } else if (cond == 0x8) {
0f8a249a
BS		 1400 /* unconditional taken */
1401 if (a) {
1402 dc->pc = target;
1403 dc->npc = dc->pc + 4;
1404 } else {
1405 dc->pc = dc->npc;
1406 dc->npc = target;
1407 }
e8af50a3
FB		 1408 } else {
1409 flush_T2(dc);
19f329ad 1410 gen_fcond(cpu_T[2], cc, cond);
0f8a249a 1411 if (a) {
19f329ad 1412 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
e8af50a3 1413 dc->is_br = 1;
0f8a249a 1414 } else {
e8af50a3
FB		 1415 dc->pc = dc->npc;
1416 dc->jump_pc[0] = target;
1417 dc->jump_pc[1] = dc->npc + 4;
1418 dc->npc = JUMP_PC;
0f8a249a 1419 }
e8af50a3
FB		 1420 }
1421}
1422
3475187d
FB		 1423#ifdef TARGET_SPARC64
1424/* XXX: potentially incorrect if dynamic npc */
1425static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 1426{
3475187d
FB		 1427 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1428 target_ulong target = dc->pc + offset;
1429
1430 flush_T2(dc);
19f329ad 1431 gen_cond_reg(cpu_T[2], cond);
3475187d 1432 if (a) {
19f329ad 1433 gen_branch_a(dc, target, dc->npc, cpu_T[2]);
0f8a249a 1434 dc->is_br = 1;
3475187d 1435 } else {
0f8a249a
BS		 1436 dc->pc = dc->npc;
1437 dc->jump_pc[0] = target;
1438 dc->jump_pc[1] = dc->npc + 4;
1439 dc->npc = JUMP_PC;
3475187d 1440 }
7a3f1944
FB		 1441}
1442
3475187d 1443static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 1444 helper_fcmps,
1445 helper_fcmps_fcc1,
1446 helper_fcmps_fcc2,
1447 helper_fcmps_fcc3,
3475187d
FB		 1448};
1449
1450static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 1451 helper_fcmpd,
1452 helper_fcmpd_fcc1,
1453 helper_fcmpd_fcc2,
1454 helper_fcmpd_fcc3,
3475187d 1455};
417454b0 1456
1f587329
BS		 1457#if defined(CONFIG_USER_ONLY)
1458static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 1459 helper_fcmpq,
1460 helper_fcmpq_fcc1,
1461 helper_fcmpq_fcc2,
1462 helper_fcmpq_fcc3,
1f587329
BS		 1463};
1464#endif
1465
417454b0 1466static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 1467 helper_fcmpes,
1468 helper_fcmpes_fcc1,
1469 helper_fcmpes_fcc2,
1470 helper_fcmpes_fcc3,
417454b0
BS		 1471};
1472
1473static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 1474 helper_fcmped,
1475 helper_fcmped_fcc1,
1476 helper_fcmped_fcc2,
1477 helper_fcmped_fcc3,
417454b0
BS		 1478};
1479
1f587329
BS		 1480#if defined(CONFIG_USER_ONLY)
1481static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 1482 helper_fcmpeq,
1483 helper_fcmpeq_fcc1,
1484 helper_fcmpeq_fcc2,
1485 helper_fcmpeq_fcc3,
1f587329
BS		 1486};
1487#endif
7e8c2b6c
BS		 1488
1489static inline void gen_op_fcmps(int fccno)
1490{
1491 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1492}
1493
1494static inline void gen_op_fcmpd(int fccno)
1495{
1496 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1497}
1498
1499#if defined(CONFIG_USER_ONLY)
1500static inline void gen_op_fcmpq(int fccno)
1501{
1502 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1503}
1504#endif
1505
1506static inline void gen_op_fcmpes(int fccno)
1507{
1508 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1509}
1510
1511static inline void gen_op_fcmped(int fccno)
1512{
1513 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1514}
1515
1516#if defined(CONFIG_USER_ONLY)
1517static inline void gen_op_fcmpeq(int fccno)
1518{
1519 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1520}
1521#endif
1522
1523#else
1524
1525static inline void gen_op_fcmps(int fccno)
1526{
1527 tcg_gen_helper_0_0(helper_fcmps);
1528}
1529
1530static inline void gen_op_fcmpd(int fccno)
1531{
1532 tcg_gen_helper_0_0(helper_fcmpd);
1533}
1534
1535#if defined(CONFIG_USER_ONLY)
1536static inline void gen_op_fcmpq(int fccno)
1537{
1538 tcg_gen_helper_0_0(helper_fcmpq);
1539}
1540#endif
1541
1542static inline void gen_op_fcmpes(int fccno)
1543{
1544 tcg_gen_helper_0_0(helper_fcmpes);
1545}
1546
1547static inline void gen_op_fcmped(int fccno)
1548{
1549 tcg_gen_helper_0_0(helper_fcmped);
1550}
1551
1552#if defined(CONFIG_USER_ONLY)
1553static inline void gen_op_fcmpeq(int fccno)
1554{
1555 tcg_gen_helper_0_0(helper_fcmpeq);
1556}
1557#endif
1558
3475187d
FB		 1559#endif
1560
134d77a1
BS		 1561static inline void gen_op_fpexception_im(int fsr_flags)
1562{
1563 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1564 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~FSR_FTT_MASK);
1565 tcg_gen_ori_tl(cpu_tmp0, cpu_tmp0, fsr_flags);
1566 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1567 gen_op_exception(TT_FP_EXCP);
1568}
1569
a80dde08
FB		 1570static int gen_trap_ifnofpu(DisasContext * dc)
1571{
1572#if !defined(CONFIG_USER_ONLY)
1573 if (!dc->fpu_enabled) {
1574 save_state(dc);
1575 gen_op_exception(TT_NFPU_INSN);
1576 dc->is_br = 1;
1577 return 1;
1578 }
1579#endif
1580 return 0;
1581}
1582
7e8c2b6c
BS		 1583static inline void gen_op_clear_ieee_excp_and_FTT(void)
1584{
1585 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1586 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1587 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
1588}
1589
1590static inline void gen_clear_float_exceptions(void)
1591{
1592 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1593}
1594
1a2fb1c0
BS		 1595/* asi moves */
1596#ifdef TARGET_SPARC64
1597static inline void gen_ld_asi(int insn, int size, int sign)
1598{
1599 int asi, offset;
1600 TCGv r_size, r_sign;
1601
1602 r_size = tcg_temp_new(TCG_TYPE_I32);
1603 r_sign = tcg_temp_new(TCG_TYPE_I32);
1604 tcg_gen_movi_i32(r_size, size);
1605 tcg_gen_movi_i32(r_sign, sign);
1606 if (IS_IMM) {
1607 offset = GET_FIELD(insn, 25, 31);
1608 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1609 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1610 } else {
1611 asi = GET_FIELD(insn, 19, 26);
1612 tcg_gen_movi_i32(cpu_T[1], asi);
1613 }
1614 tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
1615 r_sign);
1616}
1617
1618static inline void gen_st_asi(int insn, int size)
1619{
1620 int asi, offset;
1621 TCGv r_asi, r_size;
1622
1623 r_asi = tcg_temp_new(TCG_TYPE_I32);
1624 r_size = tcg_temp_new(TCG_TYPE_I32);
1625 tcg_gen_movi_i32(r_size, size);
1626 if (IS_IMM) {
1627 offset = GET_FIELD(insn, 25, 31);
1628 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1629 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1630 } else {
1631 asi = GET_FIELD(insn, 19, 26);
1632 tcg_gen_movi_i32(r_asi, asi);
1633 }
1634 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
1635}
1636
1637static inline void gen_ldf_asi(int insn, int size, int rd)
1638{
1639 int asi, offset;
1640 TCGv r_asi, r_size, r_rd;
1641
1642 r_asi = tcg_temp_new(TCG_TYPE_I32);
1643 r_size = tcg_temp_new(TCG_TYPE_I32);
1644 r_rd = tcg_temp_new(TCG_TYPE_I32);
1645 tcg_gen_movi_i32(r_size, size);
1646 tcg_gen_movi_i32(r_rd, rd);
1647 if (IS_IMM) {
1648 offset = GET_FIELD(insn, 25, 31);
1649 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1650 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1651 } else {
1652 asi = GET_FIELD(insn, 19, 26);
1653 tcg_gen_movi_i32(r_asi, asi);
1654 }
1655 tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
1656}
1657
1658static inline void gen_stf_asi(int insn, int size, int rd)
1659{
1660 int asi, offset;
1661 TCGv r_asi, r_size, r_rd;
1662
1663 r_asi = tcg_temp_new(TCG_TYPE_I32);
1664 r_size = tcg_temp_new(TCG_TYPE_I32);
1665 r_rd = tcg_temp_new(TCG_TYPE_I32);
1666 tcg_gen_movi_i32(r_size, size);
1667 tcg_gen_movi_i32(r_rd, rd);
1668 if (IS_IMM) {
1669 offset = GET_FIELD(insn, 25, 31);
1670 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1671 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1672 } else {
1673 asi = GET_FIELD(insn, 19, 26);
1674 tcg_gen_movi_i32(r_asi, asi);
1675 }
1676 tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
1677}
1678
1679static inline void gen_swap_asi(int insn)
1680{
1681 int asi, offset;
1682 TCGv r_size, r_sign, r_temp;
1683
1684 r_size = tcg_temp_new(TCG_TYPE_I32);
1685 r_sign = tcg_temp_new(TCG_TYPE_I32);
1686 r_temp = tcg_temp_new(TCG_TYPE_I32);
1687 tcg_gen_movi_i32(r_size, 4);
1688 tcg_gen_movi_i32(r_sign, 0);
1689 if (IS_IMM) {
1690 offset = GET_FIELD(insn, 25, 31);
1691 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1692 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1693 } else {
1694 asi = GET_FIELD(insn, 19, 26);
1695 tcg_gen_movi_i32(cpu_T[1], asi);
1696 }
1697 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1698 r_sign);
1699 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1700 tcg_gen_mov_i32(cpu_T[1], r_temp);
1701}
1702
1703static inline void gen_ldda_asi(int insn)
1704{
1705 int asi, offset;
1706 TCGv r_size, r_sign, r_dword;
1707
1708 r_size = tcg_temp_new(TCG_TYPE_I32);
1709 r_sign = tcg_temp_new(TCG_TYPE_I32);
1710 r_dword = tcg_temp_new(TCG_TYPE_I64);
1711 tcg_gen_movi_i32(r_size, 8);
1712 tcg_gen_movi_i32(r_sign, 0);
1713 if (IS_IMM) {
1714 offset = GET_FIELD(insn, 25, 31);
1715 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1716 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
1717 } else {
1718 asi = GET_FIELD(insn, 19, 26);
1719 tcg_gen_movi_i32(cpu_T[1], asi);
1720 }
1721 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1722 r_sign);
1723 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1724 tcg_gen_shri_i64(r_dword, r_dword, 32);
1725 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1726}
1727
1728static inline void gen_cas_asi(int insn, int rd)
1729{
1730 int asi, offset;
1731 TCGv r_val1, r_asi;
1732
1733 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1734 r_asi = tcg_temp_new(TCG_TYPE_I32);
1735 gen_movl_reg_TN(rd, r_val1);
1736 if (IS_IMM) {
1737 offset = GET_FIELD(insn, 25, 31);
1738 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1739 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1740 } else {
1741 asi = GET_FIELD(insn, 19, 26);
1742 tcg_gen_movi_i32(r_asi, asi);
1743 }
1744 tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1745 r_asi);
1746}
1747
1748static inline void gen_casx_asi(int insn, int rd)
1749{
1750 int asi, offset;
1751 TCGv r_val1, r_asi;
1752
1753 r_val1 = tcg_temp_new(TCG_TYPE_I64);
1754 r_asi = tcg_temp_new(TCG_TYPE_I32);
1755 gen_movl_reg_TN(rd, r_val1);
1756 if (IS_IMM) {
1757 offset = GET_FIELD(insn, 25, 31);
1758 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1759 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1760 } else {
1761 asi = GET_FIELD(insn, 19, 26);
1762 tcg_gen_movi_i32(r_asi, asi);
1763 }
1764 tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1765 r_asi);
1766}
1767
1768#elif !defined(CONFIG_USER_ONLY)
1769
1770static inline void gen_ld_asi(int insn, int size, int sign)
1771{
1772 int asi;
1773 TCGv r_size, r_sign, r_dword;
1774
1775 r_size = tcg_temp_new(TCG_TYPE_I32);
1776 r_sign = tcg_temp_new(TCG_TYPE_I32);
1777 r_dword = tcg_temp_new(TCG_TYPE_I64);
1778 tcg_gen_movi_i32(r_size, size);
1779 tcg_gen_movi_i32(r_sign, sign);
1780 asi = GET_FIELD(insn, 19, 26);
1781 tcg_gen_movi_i32(cpu_T[1], asi);
1782 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1783 r_sign);
1784 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1785}
1786
1787static inline void gen_st_asi(int insn, int size)
1788{
1789 int asi;
1790 TCGv r_dword, r_asi, r_size;
1791
1792 r_dword = tcg_temp_new(TCG_TYPE_I64);
1793 tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1794 r_asi = tcg_temp_new(TCG_TYPE_I32);
1795 r_size = tcg_temp_new(TCG_TYPE_I32);
1796 asi = GET_FIELD(insn, 19, 26);
1797 tcg_gen_movi_i32(r_asi, asi);
1798 tcg_gen_movi_i32(r_size, size);
1799 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1800}
1801
1802static inline void gen_swap_asi(int insn)
1803{
1804 int asi;
1805 TCGv r_size, r_sign, r_temp;
1806
1807 r_size = tcg_temp_new(TCG_TYPE_I32);
1808 r_sign = tcg_temp_new(TCG_TYPE_I32);
1809 r_temp = tcg_temp_new(TCG_TYPE_I32);
1810 tcg_gen_movi_i32(r_size, 4);
1811 tcg_gen_movi_i32(r_sign, 0);
1812 asi = GET_FIELD(insn, 19, 26);
1813 tcg_gen_movi_i32(cpu_T[1], asi);
1814 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1815 r_sign);
1816 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1817 tcg_gen_mov_i32(cpu_T[1], r_temp);
1818}
1819
1820static inline void gen_ldda_asi(int insn)
1821{
1822 int asi;
1823 TCGv r_size, r_sign, r_dword;
1824
1825 r_size = tcg_temp_new(TCG_TYPE_I32);
1826 r_sign = tcg_temp_new(TCG_TYPE_I32);
1827 r_dword = tcg_temp_new(TCG_TYPE_I64);
1828 tcg_gen_movi_i32(r_size, 8);
1829 tcg_gen_movi_i32(r_sign, 0);
1830 asi = GET_FIELD(insn, 19, 26);
1831 tcg_gen_movi_i32(cpu_T[1], asi);
1832 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1833 r_sign);
1834 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1835 tcg_gen_shri_i64(r_dword, r_dword, 32);
1836 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1837}
1838#endif
1839
1840#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1841static inline void gen_ldstub_asi(int insn)
1842{
1843 int asi;
1844 TCGv r_dword, r_asi, r_size;
1845
1846 gen_ld_asi(insn, 1, 0);
1847
1848 r_dword = tcg_temp_new(TCG_TYPE_I64);
1849 r_asi = tcg_temp_new(TCG_TYPE_I32);
1850 r_size = tcg_temp_new(TCG_TYPE_I32);
1851 asi = GET_FIELD(insn, 19, 26);
1852 tcg_gen_movi_i32(r_dword, 0xff);
1853 tcg_gen_movi_i32(r_asi, asi);
1854 tcg_gen_movi_i32(r_size, 1);
1855 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1856}
1857#endif
1858
0bee699e 1859/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1860static void disas_sparc_insn(DisasContext * dc)
1861{
1862 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1863
0fa85d43 1864 insn = ldl_code(dc->pc);
cf495bcf 1865 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1866
cf495bcf
FB		 1867 rd = GET_FIELD(insn, 2, 6);
1868 switch (opc) {
0f8a249a
BS		 1869 case 0: /* branches/sethi */
1870 {
1871 unsigned int xop = GET_FIELD(insn, 7, 9);
1872 int32_t target;
1873 switch (xop) {
3475187d 1874#ifdef TARGET_SPARC64
0f8a249a
BS		 1875 case 0x1: /* V9 BPcc */
1876 {
1877 int cc;
1878
1879 target = GET_FIELD_SP(insn, 0, 18);
1880 target = sign_extend(target, 18);
1881 target <<= 2;
1882 cc = GET_FIELD_SP(insn, 20, 21);
1883 if (cc == 0)
1884 do_branch(dc, target, insn, 0);
1885 else if (cc == 2)
1886 do_branch(dc, target, insn, 1);
1887 else
1888 goto illegal_insn;
1889 goto jmp_insn;
1890 }
1891 case 0x3: /* V9 BPr */
1892 {
1893 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1894 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1895 target = sign_extend(target, 16);
1896 target <<= 2;
1897 rs1 = GET_FIELD(insn, 13, 17);
1898 gen_movl_reg_T0(rs1);
1899 do_branch_reg(dc, target, insn);
1900 goto jmp_insn;
1901 }
1902 case 0x5: /* V9 FBPcc */
1903 {
1904 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1905 if (gen_trap_ifnofpu(dc))
1906 goto jmp_insn;
0f8a249a
BS		 1907 target = GET_FIELD_SP(insn, 0, 18);
1908 target = sign_extend(target, 19);
1909 target <<= 2;
1910 do_fbranch(dc, target, insn, cc);
1911 goto jmp_insn;
1912 }
a4d17f19 1913#else
0f8a249a
BS		 1914 case 0x7: /* CBN+x */
1915 {
1916 goto ncp_insn;
1917 }
1918#endif
1919 case 0x2: /* BN+x */
1920 {
1921 target = GET_FIELD(insn, 10, 31);
1922 target = sign_extend(target, 22);
1923 target <<= 2;
1924 do_branch(dc, target, insn, 0);
1925 goto jmp_insn;
1926 }
1927 case 0x6: /* FBN+x */
1928 {
a80dde08
FB		 1929 if (gen_trap_ifnofpu(dc))
1930 goto jmp_insn;
0f8a249a
BS		 1931 target = GET_FIELD(insn, 10, 31);
1932 target = sign_extend(target, 22);
1933 target <<= 2;
1934 do_fbranch(dc, target, insn, 0);
1935 goto jmp_insn;
1936 }
1937 case 0x4: /* SETHI */
e80cfcfc
FB		 1938#define OPTIM
1939#if defined(OPTIM)
0f8a249a 1940 if (rd) { // nop
e80cfcfc 1941#endif
0f8a249a 1942 uint32_t value = GET_FIELD(insn, 10, 31);
1a2fb1c0 1943 tcg_gen_movi_tl(cpu_T[0], value << 10);
0f8a249a 1944 gen_movl_T0_reg(rd);
e80cfcfc 1945#if defined(OPTIM)
0f8a249a 1946 }
e80cfcfc 1947#endif
0f8a249a
BS		 1948 break;
1949 case 0x0: /* UNIMPL */
1950 default:
3475187d 1951 goto illegal_insn;
0f8a249a
BS		 1952 }
1953 break;
1954 }
1955 break;
cf495bcf 1956 case 1:
0f8a249a
BS		 1957 /*CALL*/ {
1958 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1959
1a2fb1c0 1960 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1961 gen_movl_T0_reg(15);
1962 target += dc->pc;
0bee699e 1963 gen_mov_pc_npc(dc);
0f8a249a
BS		 1964 dc->npc = target;
1965 }
1966 goto jmp_insn;
1967 case 2: /* FPU & Logical Operations */
1968 {
1969 unsigned int xop = GET_FIELD(insn, 7, 12);
1970 if (xop == 0x3a) { /* generate trap */
cf495bcf 1971 int cond;
3475187d 1972
cf495bcf
FB		 1973 rs1 = GET_FIELD(insn, 13, 17);
1974 gen_movl_reg_T0(rs1);
0f8a249a
BS		 1975 if (IS_IMM) {
1976 rs2 = GET_FIELD(insn, 25, 31);
1a2fb1c0 1977 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
cf495bcf
FB		 1978 } else {
1979 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 1980#if defined(OPTIM)
0f8a249a 1981 if (rs2 != 0) {
e80cfcfc 1982#endif
0f8a249a
BS		 1983 gen_movl_reg_T1(rs2);
1984 gen_op_add_T1_T0();
e80cfcfc 1985#if defined(OPTIM)
0f8a249a 1986 }
e80cfcfc 1987#endif
cf495bcf 1988 }
cf495bcf
FB		 1989 cond = GET_FIELD(insn, 3, 6);
1990 if (cond == 0x8) {
a80dde08 1991 save_state(dc);
1a2fb1c0 1992 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
af7bf89b 1993 } else if (cond != 0) {
3475187d 1994#ifdef TARGET_SPARC64
0f8a249a
BS		 1995 /* V9 icc/xcc */
1996 int cc = GET_FIELD_SP(insn, 11, 12);
1997 flush_T2(dc);
a80dde08 1998 save_state(dc);
0f8a249a 1999 if (cc == 0)
19f329ad 2000 gen_cond(cpu_T[2], 0, cond);
0f8a249a 2001 else if (cc == 2)
19f329ad 2002 gen_cond(cpu_T[2], 1, cond);
0f8a249a
BS		 2003 else
2004 goto illegal_insn;
3475187d 2005#else
0f8a249a 2006 flush_T2(dc);
a80dde08 2007 save_state(dc);
19f329ad 2008 gen_cond(cpu_T[2], 0, cond);
3475187d 2009#endif
1a2fb1c0 2010 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]);
cf495bcf 2011 }
a80dde08 2012 gen_op_next_insn();
57fec1fe 2013 tcg_gen_exit_tb(0);
a80dde08
FB		 2014 dc->is_br = 1;
2015 goto jmp_insn;
cf495bcf
FB		 2016 } else if (xop == 0x28) {
2017 rs1 = GET_FIELD(insn, 13, 17);
2018 switch(rs1) {
2019 case 0: /* rdy */
65fe7b09
BS		 2020#ifndef TARGET_SPARC64
2021 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2022 manual, rdy on the microSPARC
2023 II */
2024 case 0x0f: /* stbar in the SPARCv8 manual,
2025 rdy on the microSPARC II */
2026 case 0x10 ... 0x1f: /* implementation-dependent in the
2027 SPARCv8 manual, rdy on the
2028 microSPARC II */
2029#endif
2030 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 2031 gen_movl_T0_reg(rd);
2032 break;
3475187d 2033#ifdef TARGET_SPARC64
0f8a249a 2034 case 0x2: /* V9 rdccr */
3475187d
FB		 2035 gen_op_rdccr();
2036 gen_movl_T0_reg(rd);
2037 break;
0f8a249a
BS		 2038 case 0x3: /* V9 rdasi */
2039 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
3475187d
FB		 2040 gen_movl_T0_reg(rd);
2041 break;
0f8a249a 2042 case 0x4: /* V9 rdtick */
ccd4a219
BS		 2043 {
2044 TCGv r_tickptr;
2045
2046 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2047 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2048 offsetof(CPUState, tick));
2049 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2050 r_tickptr);
2051 gen_movl_T0_reg(rd);
2052 }
3475187d 2053 break;
0f8a249a 2054 case 0x5: /* V9 rdpc */
1a2fb1c0 2055 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 2056 gen_movl_T0_reg(rd);
2057 break;
2058 case 0x6: /* V9 rdfprs */
2059 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
3475187d
FB		 2060 gen_movl_T0_reg(rd);
2061 break;
65fe7b09
BS		 2062 case 0xf: /* V9 membar */
2063 break; /* no effect */
0f8a249a 2064 case 0x13: /* Graphics Status */
725cb90b
FB		 2065 if (gen_trap_ifnofpu(dc))
2066 goto jmp_insn;
0f8a249a 2067 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
725cb90b
FB		 2068 gen_movl_T0_reg(rd);
2069 break;
0f8a249a
BS		 2070 case 0x17: /* Tick compare */
2071 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
83469015
FB		 2072 gen_movl_T0_reg(rd);
2073 break;
0f8a249a 2074 case 0x18: /* System tick */
ccd4a219
BS		 2075 {
2076 TCGv r_tickptr;
2077
2078 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2079 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2080 offsetof(CPUState, stick));
2081 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2082 r_tickptr);
2083 gen_movl_T0_reg(rd);
2084 }
83469015 2085 break;
0f8a249a
BS		 2086 case 0x19: /* System tick compare */
2087 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
83469015
FB		 2088 gen_movl_T0_reg(rd);
2089 break;
0f8a249a
BS		 2090 case 0x10: /* Performance Control */
2091 case 0x11: /* Performance Instrumentation Counter */
2092 case 0x12: /* Dispatch Control */
2093 case 0x14: /* Softint set, WO */
2094 case 0x15: /* Softint clear, WO */
2095 case 0x16: /* Softint write */
3475187d
FB		 2096#endif
2097 default:
cf495bcf
FB		 2098 goto illegal_insn;
2099 }
e8af50a3 2100#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2101 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2102#ifndef TARGET_SPARC64
0f8a249a
BS		 2103 if (!supervisor(dc))
2104 goto priv_insn;
1a2fb1c0 2105 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
e9ebed4d
BS		 2106#else
2107 if (!hypervisor(dc))
2108 goto priv_insn;
2109 rs1 = GET_FIELD(insn, 13, 17);
2110 switch (rs1) {
2111 case 0: // hpstate
2112 // gen_op_rdhpstate();
2113 break;
2114 case 1: // htstate
2115 // gen_op_rdhtstate();
2116 break;
2117 case 3: // hintp
2118 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2119 break;
2120 case 5: // htba
2121 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2122 break;
2123 case 6: // hver
2124 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2125 break;
2126 case 31: // hstick_cmpr
2127 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2128 break;
2129 default:
2130 goto illegal_insn;
2131 }
2132#endif
e8af50a3
FB		 2133 gen_movl_T0_reg(rd);
2134 break;
3475187d 2135 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 2136 if (!supervisor(dc))
2137 goto priv_insn;
3475187d
FB		 2138#ifdef TARGET_SPARC64
2139 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2140 switch (rs1) {
2141 case 0: // tpc
375ee38b
BS		 2142 {
2143 TCGv r_tsptr;
2144
2145 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2146 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2147 offsetof(CPUState, tsptr));
2148 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2149 offsetof(trap_state, tpc));
2150 }
0f8a249a
BS		 2151 break;
2152 case 1: // tnpc
375ee38b
BS		 2153 {
2154 TCGv r_tsptr;
2155
2156 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2157 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2158 offsetof(CPUState, tsptr));
2159 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2160 offsetof(trap_state, tnpc));
2161 }
0f8a249a
BS		 2162 break;
2163 case 2: // tstate
375ee38b
BS		 2164 {
2165 TCGv r_tsptr;
2166
2167 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2168 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2169 offsetof(CPUState, tsptr));
2170 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
2171 offsetof(trap_state, tstate));
2172 }
0f8a249a
BS		 2173 break;
2174 case 3: // tt
375ee38b
BS		 2175 {
2176 TCGv r_tsptr;
2177
2178 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2179 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2180 offsetof(CPUState, tsptr));
2181 tcg_gen_ld_i32(cpu_T[0], r_tsptr,
2182 offsetof(trap_state, tt));
2183 }
0f8a249a
BS		 2184 break;
2185 case 4: // tick
ccd4a219
BS		 2186 {
2187 TCGv r_tickptr;
2188
2189 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2190 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2191 offsetof(CPUState, tick));
2192 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2193 r_tickptr);
2194 gen_movl_T0_reg(rd);
2195 }
0f8a249a
BS		 2196 break;
2197 case 5: // tba
2198 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2199 break;
2200 case 6: // pstate
1a2fb1c0 2201 gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2202 break;
2203 case 7: // tl
2204 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2205 break;
2206 case 8: // pil
2207 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2208 break;
2209 case 9: // cwp
2210 gen_op_rdcwp();
2211 break;
2212 case 10: // cansave
2213 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2214 break;
2215 case 11: // canrestore
2216 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2217 break;
2218 case 12: // cleanwin
2219 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2220 break;
2221 case 13: // otherwin
2222 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2223 break;
2224 case 14: // wstate
2225 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2226 break;
e9ebed4d
BS		 2227 case 16: // UA2005 gl
2228 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2229 break;
2230 case 26: // UA2005 strand status
2231 if (!hypervisor(dc))
2232 goto priv_insn;
2233 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2234 break;
0f8a249a
BS		 2235 case 31: // ver
2236 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2237 break;
2238 case 15: // fq
2239 default:
2240 goto illegal_insn;
2241 }
3475187d 2242#else
0f8a249a 2243 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
3475187d 2244#endif
e8af50a3
FB		 2245 gen_movl_T0_reg(rd);
2246 break;
3475187d
FB		 2247 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2248#ifdef TARGET_SPARC64
0f8a249a 2249 gen_op_flushw();
3475187d 2250#else
0f8a249a
BS		 2251 if (!supervisor(dc))
2252 goto priv_insn;
2253 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 2254 gen_movl_T0_reg(rd);
3475187d 2255#endif
e8af50a3
FB		 2256 break;
2257#endif
0f8a249a 2258 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 2259 if (gen_trap_ifnofpu(dc))
2260 goto jmp_insn;
0f8a249a 2261 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2262 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2263 rs2 = GET_FIELD(insn, 27, 31);
2264 xop = GET_FIELD(insn, 18, 26);
2265 switch (xop) {
2266 case 0x1: /* fmovs */
2267 gen_op_load_fpr_FT0(rs2);
2268 gen_op_store_FT0_fpr(rd);
2269 break;
2270 case 0x5: /* fnegs */
2271 gen_op_load_fpr_FT1(rs2);
2272 gen_op_fnegs();
2273 gen_op_store_FT0_fpr(rd);
2274 break;
2275 case 0x9: /* fabss */
2276 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2277 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 2278 gen_op_store_FT0_fpr(rd);
2279 break;
2280 case 0x29: /* fsqrts */
2281 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 2282 gen_clear_float_exceptions();
2283 tcg_gen_helper_0_0(helper_fsqrts);
2284 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2285 gen_op_store_FT0_fpr(rd);
2286 break;
2287 case 0x2a: /* fsqrtd */
2288 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 2289 gen_clear_float_exceptions();
2290 tcg_gen_helper_0_0(helper_fsqrtd);
2291 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2292 gen_op_store_DT0_fpr(DFPREG(rd));
2293 break;
2294 case 0x2b: /* fsqrtq */
1f587329
BS		 2295#if defined(CONFIG_USER_ONLY)
2296 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 2297 gen_clear_float_exceptions();
2298 tcg_gen_helper_0_0(helper_fsqrtq);
2299 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2300 gen_op_store_QT0_fpr(QFPREG(rd));
2301 break;
2302#else
0f8a249a 2303 goto nfpu_insn;
1f587329 2304#endif
0f8a249a
BS		 2305 case 0x41:
2306 gen_op_load_fpr_FT0(rs1);
2307 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2308 gen_clear_float_exceptions();
0f8a249a 2309 gen_op_fadds();
7e8c2b6c 2310 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2311 gen_op_store_FT0_fpr(rd);
2312 break;
2313 case 0x42:
2314 gen_op_load_fpr_DT0(DFPREG(rs1));
2315 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2316 gen_clear_float_exceptions();
0f8a249a 2317 gen_op_faddd();
7e8c2b6c 2318 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2319 gen_op_store_DT0_fpr(DFPREG(rd));
2320 break;
2321 case 0x43: /* faddq */
1f587329
BS		 2322#if defined(CONFIG_USER_ONLY)
2323 gen_op_load_fpr_QT0(QFPREG(rs1));
2324 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2325 gen_clear_float_exceptions();
1f587329 2326 gen_op_faddq();
7e8c2b6c 2327 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2328 gen_op_store_QT0_fpr(QFPREG(rd));
2329 break;
2330#else
0f8a249a 2331 goto nfpu_insn;
1f587329 2332#endif
0f8a249a
BS		 2333 case 0x45:
2334 gen_op_load_fpr_FT0(rs1);
2335 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2336 gen_clear_float_exceptions();
0f8a249a 2337 gen_op_fsubs();
7e8c2b6c 2338 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2339 gen_op_store_FT0_fpr(rd);
2340 break;
2341 case 0x46:
2342 gen_op_load_fpr_DT0(DFPREG(rs1));
2343 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2344 gen_clear_float_exceptions();
0f8a249a 2345 gen_op_fsubd();
7e8c2b6c 2346 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2347 gen_op_store_DT0_fpr(DFPREG(rd));
2348 break;
2349 case 0x47: /* fsubq */
1f587329
BS		 2350#if defined(CONFIG_USER_ONLY)
2351 gen_op_load_fpr_QT0(QFPREG(rs1));
2352 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2353 gen_clear_float_exceptions();
1f587329 2354 gen_op_fsubq();
7e8c2b6c 2355 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2356 gen_op_store_QT0_fpr(QFPREG(rd));
2357 break;
2358#else
0f8a249a 2359 goto nfpu_insn;
1f587329 2360#endif
0f8a249a
BS		 2361 case 0x49:
2362 gen_op_load_fpr_FT0(rs1);
2363 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2364 gen_clear_float_exceptions();
0f8a249a 2365 gen_op_fmuls();
7e8c2b6c 2366 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2367 gen_op_store_FT0_fpr(rd);
2368 break;
2369 case 0x4a:
2370 gen_op_load_fpr_DT0(DFPREG(rs1));
2371 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2372 gen_clear_float_exceptions();
0f8a249a 2373 gen_op_fmuld();
7e8c2b6c 2374 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 2375 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2376 break;
2377 case 0x4b: /* fmulq */
1f587329
BS		 2378#if defined(CONFIG_USER_ONLY)
2379 gen_op_load_fpr_QT0(QFPREG(rs1));
2380 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2381 gen_clear_float_exceptions();
1f587329 2382 gen_op_fmulq();
7e8c2b6c 2383 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2384 gen_op_store_QT0_fpr(QFPREG(rd));
2385 break;
2386#else
0f8a249a 2387 goto nfpu_insn;
1f587329 2388#endif
0f8a249a
BS		 2389 case 0x4d:
2390 gen_op_load_fpr_FT0(rs1);
2391 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2392 gen_clear_float_exceptions();
0f8a249a 2393 gen_op_fdivs();
7e8c2b6c 2394 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2395 gen_op_store_FT0_fpr(rd);
2396 break;
2397 case 0x4e:
2398 gen_op_load_fpr_DT0(DFPREG(rs1));
2399 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2400 gen_clear_float_exceptions();
0f8a249a 2401 gen_op_fdivd();
7e8c2b6c 2402 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2403 gen_op_store_DT0_fpr(DFPREG(rd));
2404 break;
2405 case 0x4f: /* fdivq */
1f587329
BS		 2406#if defined(CONFIG_USER_ONLY)
2407 gen_op_load_fpr_QT0(QFPREG(rs1));
2408 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2409 gen_clear_float_exceptions();
1f587329 2410 gen_op_fdivq();
7e8c2b6c 2411 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2412 gen_op_store_QT0_fpr(QFPREG(rd));
2413 break;
2414#else
0f8a249a 2415 goto nfpu_insn;
1f587329 2416#endif
0f8a249a
BS		 2417 case 0x69:
2418 gen_op_load_fpr_FT0(rs1);
2419 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2420 gen_clear_float_exceptions();
0f8a249a 2421 gen_op_fsmuld();
7e8c2b6c 2422 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2423 gen_op_store_DT0_fpr(DFPREG(rd));
2424 break;
2425 case 0x6e: /* fdmulq */
1f587329
BS		 2426#if defined(CONFIG_USER_ONLY)
2427 gen_op_load_fpr_DT0(DFPREG(rs1));
2428 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2429 gen_clear_float_exceptions();
1f587329 2430 gen_op_fdmulq();
7e8c2b6c 2431 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2432 gen_op_store_QT0_fpr(QFPREG(rd));
2433 break;
2434#else
0f8a249a 2435 goto nfpu_insn;
1f587329 2436#endif
0f8a249a
BS		 2437 case 0xc4:
2438 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2439 gen_clear_float_exceptions();
0f8a249a 2440 gen_op_fitos();
7e8c2b6c 2441 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2442 gen_op_store_FT0_fpr(rd);
2443 break;
2444 case 0xc6:
2445 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2446 gen_clear_float_exceptions();
0f8a249a 2447 gen_op_fdtos();
7e8c2b6c 2448 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2449 gen_op_store_FT0_fpr(rd);
2450 break;
2451 case 0xc7: /* fqtos */
1f587329
BS		 2452#if defined(CONFIG_USER_ONLY)
2453 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2454 gen_clear_float_exceptions();
1f587329 2455 gen_op_fqtos();
7e8c2b6c 2456 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2457 gen_op_store_FT0_fpr(rd);
2458 break;
2459#else
0f8a249a 2460 goto nfpu_insn;
1f587329 2461#endif
0f8a249a
BS		 2462 case 0xc8:
2463 gen_op_load_fpr_FT1(rs2);
2464 gen_op_fitod();
2465 gen_op_store_DT0_fpr(DFPREG(rd));
2466 break;
2467 case 0xc9:
2468 gen_op_load_fpr_FT1(rs2);
2469 gen_op_fstod();
2470 gen_op_store_DT0_fpr(DFPREG(rd));
2471 break;
2472 case 0xcb: /* fqtod */
1f587329
BS		 2473#if defined(CONFIG_USER_ONLY)
2474 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2475 gen_clear_float_exceptions();
1f587329 2476 gen_op_fqtod();
7e8c2b6c 2477 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2478 gen_op_store_DT0_fpr(DFPREG(rd));
2479 break;
2480#else
0f8a249a 2481 goto nfpu_insn;
1f587329 2482#endif
0f8a249a 2483 case 0xcc: /* fitoq */
1f587329
BS		 2484#if defined(CONFIG_USER_ONLY)
2485 gen_op_load_fpr_FT1(rs2);
2486 gen_op_fitoq();
2487 gen_op_store_QT0_fpr(QFPREG(rd));
2488 break;
2489#else
0f8a249a 2490 goto nfpu_insn;
1f587329 2491#endif
0f8a249a 2492 case 0xcd: /* fstoq */
1f587329
BS		 2493#if defined(CONFIG_USER_ONLY)
2494 gen_op_load_fpr_FT1(rs2);
2495 gen_op_fstoq();
2496 gen_op_store_QT0_fpr(QFPREG(rd));
2497 break;
2498#else
0f8a249a 2499 goto nfpu_insn;
1f587329 2500#endif
0f8a249a 2501 case 0xce: /* fdtoq */
1f587329
BS		 2502#if defined(CONFIG_USER_ONLY)
2503 gen_op_load_fpr_DT1(DFPREG(rs2));
2504 gen_op_fdtoq();
2505 gen_op_store_QT0_fpr(QFPREG(rd));
2506 break;
2507#else
0f8a249a 2508 goto nfpu_insn;
1f587329 2509#endif
0f8a249a
BS		 2510 case 0xd1:
2511 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2512 gen_clear_float_exceptions();
0f8a249a 2513 gen_op_fstoi();
7e8c2b6c 2514 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2515 gen_op_store_FT0_fpr(rd);
2516 break;
2517 case 0xd2:
2382dc6b 2518 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2519 gen_clear_float_exceptions();
0f8a249a 2520 gen_op_fdtoi();
7e8c2b6c 2521 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2522 gen_op_store_FT0_fpr(rd);
2523 break;
2524 case 0xd3: /* fqtoi */
1f587329
BS		 2525#if defined(CONFIG_USER_ONLY)
2526 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2527 gen_clear_float_exceptions();
1f587329 2528 gen_op_fqtoi();
7e8c2b6c 2529 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2530 gen_op_store_FT0_fpr(rd);
2531 break;
2532#else
0f8a249a 2533 goto nfpu_insn;
1f587329 2534#endif
3475187d 2535#ifdef TARGET_SPARC64
0f8a249a
BS		 2536 case 0x2: /* V9 fmovd */
2537 gen_op_load_fpr_DT0(DFPREG(rs2));
2538 gen_op_store_DT0_fpr(DFPREG(rd));
2539 break;
1f587329
BS		 2540 case 0x3: /* V9 fmovq */
2541#if defined(CONFIG_USER_ONLY)
2542 gen_op_load_fpr_QT0(QFPREG(rs2));
2543 gen_op_store_QT0_fpr(QFPREG(rd));
2544 break;
2545#else
2546 goto nfpu_insn;
2547#endif
0f8a249a
BS		 2548 case 0x6: /* V9 fnegd */
2549 gen_op_load_fpr_DT1(DFPREG(rs2));
2550 gen_op_fnegd();
2551 gen_op_store_DT0_fpr(DFPREG(rd));
2552 break;
1f587329
BS		 2553 case 0x7: /* V9 fnegq */
2554#if defined(CONFIG_USER_ONLY)
2555 gen_op_load_fpr_QT1(QFPREG(rs2));
2556 gen_op_fnegq();
2557 gen_op_store_QT0_fpr(QFPREG(rd));
2558 break;
2559#else
2560 goto nfpu_insn;
2561#endif
0f8a249a
BS		 2562 case 0xa: /* V9 fabsd */
2563 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2564 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 2565 gen_op_store_DT0_fpr(DFPREG(rd));
2566 break;
1f587329
BS		 2567 case 0xb: /* V9 fabsq */
2568#if defined(CONFIG_USER_ONLY)
2569 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2570 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 2571 gen_op_store_QT0_fpr(QFPREG(rd));
2572 break;
2573#else
2574 goto nfpu_insn;
2575#endif
0f8a249a
BS		 2576 case 0x81: /* V9 fstox */
2577 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2578 gen_clear_float_exceptions();
0f8a249a 2579 gen_op_fstox();
7e8c2b6c 2580 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2581 gen_op_store_DT0_fpr(DFPREG(rd));
2582 break;
2583 case 0x82: /* V9 fdtox */
2584 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2585 gen_clear_float_exceptions();
0f8a249a 2586 gen_op_fdtox();
7e8c2b6c 2587 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2588 gen_op_store_DT0_fpr(DFPREG(rd));
2589 break;
1f587329
BS		 2590 case 0x83: /* V9 fqtox */
2591#if defined(CONFIG_USER_ONLY)
2592 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2593 gen_clear_float_exceptions();
1f587329 2594 gen_op_fqtox();
7e8c2b6c 2595 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2596 gen_op_store_DT0_fpr(DFPREG(rd));
2597 break;
2598#else
2599 goto nfpu_insn;
2600#endif
0f8a249a
BS		 2601 case 0x84: /* V9 fxtos */
2602 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2603 gen_clear_float_exceptions();
0f8a249a 2604 gen_op_fxtos();
7e8c2b6c 2605 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2606 gen_op_store_FT0_fpr(rd);
2607 break;
2608 case 0x88: /* V9 fxtod */
2609 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2610 gen_clear_float_exceptions();
0f8a249a 2611 gen_op_fxtod();
7e8c2b6c 2612 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 2613 gen_op_store_DT0_fpr(DFPREG(rd));
2614 break;
0f8a249a 2615 case 0x8c: /* V9 fxtoq */
1f587329
BS		 2616#if defined(CONFIG_USER_ONLY)
2617 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2618 gen_clear_float_exceptions();
1f587329 2619 gen_op_fxtoq();
7e8c2b6c 2620 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 2621 gen_op_store_QT0_fpr(QFPREG(rd));
2622 break;
2623#else
0f8a249a 2624 goto nfpu_insn;
1f587329 2625#endif
0f8a249a
BS		 2626#endif
2627 default:
2628 goto illegal_insn;
2629 }
2630 } else if (xop == 0x35) { /* FPU Operations */
3475187d 2631#ifdef TARGET_SPARC64
0f8a249a 2632 int cond;
3475187d 2633#endif
a80dde08
FB		 2634 if (gen_trap_ifnofpu(dc))
2635 goto jmp_insn;
0f8a249a 2636 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 2637 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2638 rs2 = GET_FIELD(insn, 27, 31);
2639 xop = GET_FIELD(insn, 18, 26);
3475187d 2640#ifdef TARGET_SPARC64
0f8a249a 2641 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 2642 TCGv r_zero;
2643 int l1;
2644
2645 l1 = gen_new_label();
1ec6d2ea 2646 r_zero = tcg_const_tl(0);
0f8a249a 2647 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 2648 rs1 = GET_FIELD(insn, 13, 17);
2649 gen_movl_reg_T0(rs1);
dcf24905 2650 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
19f329ad 2651 gen_op_load_fpr_FT0(rs2);
0f8a249a 2652 gen_op_store_FT0_fpr(rd);
dcf24905 2653 gen_set_label(l1);
0f8a249a
BS		 2654 break;
2655 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 2656 TCGv r_zero;
2657 int l1;
2658
2659 l1 = gen_new_label();
1ec6d2ea 2660 r_zero = tcg_const_tl(0);
0f8a249a 2661 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 2662 rs1 = GET_FIELD(insn, 13, 17);
2663 gen_movl_reg_T0(rs1);
dcf24905 2664 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
19f329ad 2665 gen_op_load_fpr_DT0(DFPREG(rs2));
2382dc6b 2666 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 2667 gen_set_label(l1);
0f8a249a
BS		 2668 break;
2669 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329 2670#if defined(CONFIG_USER_ONLY)
dcf24905
BS		 2671 TCGv r_zero;
2672 int l1;
2673
2674 l1 = gen_new_label();
1ec6d2ea 2675 r_zero = tcg_const_tl(0);
1f587329 2676 cond = GET_FIELD_SP(insn, 14, 17);
1f587329
BS		 2677 rs1 = GET_FIELD(insn, 13, 17);
2678 gen_movl_reg_T0(rs1);
dcf24905 2679 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
19f329ad 2680 gen_op_load_fpr_QT0(QFPREG(rs2));
1f587329 2681 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 2682 gen_set_label(l1);
1f587329
BS		 2683 break;
2684#else
0f8a249a 2685 goto nfpu_insn;
1f587329 2686#endif
0f8a249a
BS		 2687 }
2688#endif
2689 switch (xop) {
3475187d 2690#ifdef TARGET_SPARC64
19f329ad
BS		 2691#define FMOVCC(size_FDQ, fcc) \
2692 { \
2693 TCGv r_zero, r_cond; \
2694 int l1; \
2695 \
2696 l1 = gen_new_label(); \
1ec6d2ea 2697 r_zero = tcg_const_tl(0); \
19f329ad 2698 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2699 cond = GET_FIELD_SP(insn, 14, 17); \
2700 gen_fcond(r_cond, fcc, cond); \
2701 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2702 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2703 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2704 gen_set_label(l1); \
2705 }
0f8a249a 2706 case 0x001: /* V9 fmovscc %fcc0 */
19f329ad 2707 FMOVCC(F, 0);
0f8a249a
BS		 2708 break;
2709 case 0x002: /* V9 fmovdcc %fcc0 */
19f329ad 2710 FMOVCC(D, 0);
0f8a249a
BS		 2711 break;
2712 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329 2713#if defined(CONFIG_USER_ONLY)
19f329ad 2714 FMOVCC(Q, 0);
1f587329
BS		 2715 break;
2716#else
0f8a249a 2717 goto nfpu_insn;
1f587329 2718#endif
0f8a249a 2719 case 0x041: /* V9 fmovscc %fcc1 */
19f329ad 2720 FMOVCC(F, 1);
0f8a249a
BS		 2721 break;
2722 case 0x042: /* V9 fmovdcc %fcc1 */
19f329ad 2723 FMOVCC(D, 1);
0f8a249a
BS		 2724 break;
2725 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329 2726#if defined(CONFIG_USER_ONLY)
19f329ad 2727 FMOVCC(Q, 1);
1f587329
BS		 2728 break;
2729#else
0f8a249a 2730 goto nfpu_insn;
1f587329 2731#endif
0f8a249a 2732 case 0x081: /* V9 fmovscc %fcc2 */
19f329ad 2733 FMOVCC(F, 2);
0f8a249a
BS		 2734 break;
2735 case 0x082: /* V9 fmovdcc %fcc2 */
19f329ad 2736 FMOVCC(D, 2);
0f8a249a
BS		 2737 break;
2738 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329 2739#if defined(CONFIG_USER_ONLY)
19f329ad 2740 FMOVCC(Q, 2);
1f587329
BS		 2741 break;
2742#else
0f8a249a 2743 goto nfpu_insn;
1f587329 2744#endif
0f8a249a 2745 case 0x0c1: /* V9 fmovscc %fcc3 */
19f329ad 2746 FMOVCC(F, 3);
0f8a249a
BS		 2747 break;
2748 case 0x0c2: /* V9 fmovdcc %fcc3 */
19f329ad 2749 FMOVCC(D, 3);
0f8a249a
BS		 2750 break;
2751 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329 2752#if defined(CONFIG_USER_ONLY)
19f329ad 2753 FMOVCC(Q, 3);
1f587329
BS		 2754 break;
2755#else
0f8a249a 2756 goto nfpu_insn;
1f587329 2757#endif
19f329ad
BS		 2758#undef FMOVCC
2759#define FMOVCC(size_FDQ, icc) \
2760 { \
2761 TCGv r_zero, r_cond; \
2762 int l1; \
2763 \
2764 l1 = gen_new_label(); \
1ec6d2ea 2765 r_zero = tcg_const_tl(0); \
19f329ad 2766 r_cond = tcg_temp_new(TCG_TYPE_TL); \
19f329ad
BS		 2767 cond = GET_FIELD_SP(insn, 14, 17); \
2768 gen_cond(r_cond, icc, cond); \
2769 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, r_zero, l1); \
2770 glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2771 glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2772 gen_set_label(l1); \
2773 }
2774
0f8a249a 2775 case 0x101: /* V9 fmovscc %icc */
19f329ad 2776 FMOVCC(F, 0);
0f8a249a
BS		 2777 break;
2778 case 0x102: /* V9 fmovdcc %icc */
19f329ad 2779 FMOVCC(D, 0);
0f8a249a 2780 case 0x103: /* V9 fmovqcc %icc */
1f587329 2781#if defined(CONFIG_USER_ONLY)
19f329ad 2782 FMOVCC(D, 0);
1f587329
BS		 2783 break;
2784#else
0f8a249a 2785 goto nfpu_insn;
1f587329 2786#endif
0f8a249a 2787 case 0x181: /* V9 fmovscc %xcc */
19f329ad 2788 FMOVCC(F, 1);
0f8a249a
BS		 2789 break;
2790 case 0x182: /* V9 fmovdcc %xcc */
19f329ad 2791 FMOVCC(D, 1);
0f8a249a
BS		 2792 break;
2793 case 0x183: /* V9 fmovqcc %xcc */
1f587329 2794#if defined(CONFIG_USER_ONLY)
19f329ad 2795 FMOVCC(Q, 1);
1f587329
BS		 2796 break;
2797#else
0f8a249a
BS		 2798 goto nfpu_insn;
2799#endif
19f329ad 2800#undef FMOVCC
1f587329
BS		 2801#endif
2802 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2803 gen_op_load_fpr_FT0(rs1);
2804 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2805 gen_op_fcmps(rd & 3);
0f8a249a 2806 break;
1f587329 2807 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2808 gen_op_load_fpr_DT0(DFPREG(rs1));
2809 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2810 gen_op_fcmpd(rd & 3);
0f8a249a 2811 break;
1f587329
BS		 2812 case 0x53: /* fcmpq, V9 %fcc */
2813#if defined(CONFIG_USER_ONLY)
2814 gen_op_load_fpr_QT0(QFPREG(rs1));
2815 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2816 gen_op_fcmpq(rd & 3);
1f587329
BS		 2817 break;
2818#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 2819 goto nfpu_insn;
1f587329 2820#endif
0f8a249a
BS		 2821 case 0x55: /* fcmpes, V9 %fcc */
2822 gen_op_load_fpr_FT0(rs1);
2823 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2824 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2825 break;
2826 case 0x56: /* fcmped, V9 %fcc */
2827 gen_op_load_fpr_DT0(DFPREG(rs1));
2828 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2829 gen_op_fcmped(rd & 3);
0f8a249a 2830 break;
1f587329
BS		 2831 case 0x57: /* fcmpeq, V9 %fcc */
2832#if defined(CONFIG_USER_ONLY)
2833 gen_op_load_fpr_QT0(QFPREG(rs1));
2834 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2835 gen_op_fcmpeq(rd & 3);
1f587329
BS		 2836 break;
2837#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 2838 goto nfpu_insn;
1f587329 2839#endif
0f8a249a
BS		 2840 default:
2841 goto illegal_insn;
2842 }
e80cfcfc 2843#if defined(OPTIM)
0f8a249a
BS		 2844 } else if (xop == 0x2) {
2845 // clr/mov shortcut
e80cfcfc
FB		 2846
2847 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2848 if (rs1 == 0) {
1a2fb1c0 2849 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 2850 if (IS_IMM) { /* immediate */
2851 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2852 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
0f8a249a
BS		 2853 } else { /* register */
2854 rs2 = GET_FIELD(insn, 27, 31);
1a2fb1c0 2855 gen_movl_reg_T0(rs2);
0f8a249a 2856 }
0f8a249a
BS		 2857 } else {
2858 gen_movl_reg_T0(rs1);
2859 if (IS_IMM) { /* immediate */
0f8a249a 2860 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2861 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 2862 } else { /* register */
2863 // or x, %g0, y -> mov T1, x; mov y, T1
2864 rs2 = GET_FIELD(insn, 27, 31);
2865 if (rs2 != 0) {
2866 gen_movl_reg_T1(rs2);
2867 gen_op_or_T1_T0();
2868 }
2869 }
0f8a249a 2870 }
1a2fb1c0 2871 gen_movl_T0_reg(rd);
83469015
FB		 2872#endif
2873#ifdef TARGET_SPARC64
0f8a249a 2874 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015 2875 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2876 gen_movl_reg_T0(rs1);
2877 if (IS_IMM) { /* immediate */
83469015 2878 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2879 if (insn & (1 << 12)) {
2880 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2881 } else {
2882 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2883 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2884 }
0f8a249a 2885 } else { /* register */
83469015
FB		 2886 rs2 = GET_FIELD(insn, 27, 31);
2887 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2888 if (insn & (1 << 12)) {
2889 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2890 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2891 } else {
2892 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2893 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2894 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2895 }
83469015 2896 }
0f8a249a
BS		 2897 gen_movl_T0_reg(rd);
2898 } else if (xop == 0x26) { /* srl, V9 srlx */
83469015 2899 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2900 gen_movl_reg_T0(rs1);
2901 if (IS_IMM) { /* immediate */
83469015 2902 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2903 if (insn & (1 << 12)) {
2904 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2905 } else {
2906 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2907 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2908 }
0f8a249a 2909 } else { /* register */
83469015
FB		 2910 rs2 = GET_FIELD(insn, 27, 31);
2911 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2912 if (insn & (1 << 12)) {
2913 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2914 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2915 } else {
2916 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2917 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2918 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2919 }
83469015 2920 }
0f8a249a
BS		 2921 gen_movl_T0_reg(rd);
2922 } else if (xop == 0x27) { /* sra, V9 srax */
83469015 2923 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2924 gen_movl_reg_T0(rs1);
2925 if (IS_IMM) { /* immediate */
83469015 2926 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2927 if (insn & (1 << 12)) {
2928 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2929 } else {
2930 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2931 tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2932 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2933 }
0f8a249a 2934 } else { /* register */
83469015
FB		 2935 rs2 = GET_FIELD(insn, 27, 31);
2936 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2937 if (insn & (1 << 12)) {
2938 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2939 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2940 } else {
2941 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2942 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2943 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2944 }
83469015 2945 }
0f8a249a 2946 gen_movl_T0_reg(rd);
e80cfcfc 2947#endif
fcc72045 2948 } else if (xop < 0x36) {
e80cfcfc 2949 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2950 gen_movl_reg_T0(rs1);
2951 if (IS_IMM) { /* immediate */
cf495bcf 2952 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 2953 gen_movl_simm_T1(rs2);
0f8a249a 2954 } else { /* register */
cf495bcf
FB		 2955 rs2 = GET_FIELD(insn, 27, 31);
2956 gen_movl_reg_T1(rs2);
2957 }
2958 if (xop < 0x20) {
2959 switch (xop & ~0x10) {
2960 case 0x0:
2961 if (xop & 0x10)
2962 gen_op_add_T1_T0_cc();
2963 else
2964 gen_op_add_T1_T0();
2965 break;
2966 case 0x1:
1a2fb1c0 2967 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2968 if (xop & 0x10)
2969 gen_op_logic_T0_cc();
2970 break;
2971 case 0x2:
1a2fb1c0 2972 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
0f8a249a
BS		 2973 if (xop & 0x10)
2974 gen_op_logic_T0_cc();
2975 break;
cf495bcf 2976 case 0x3:
1a2fb1c0 2977 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2978 if (xop & 0x10)
2979 gen_op_logic_T0_cc();
2980 break;
2981 case 0x4:
2982 if (xop & 0x10)
2983 gen_op_sub_T1_T0_cc();
2984 else
1a2fb1c0 2985 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2986 break;
2987 case 0x5:
56ec06bb
BS		 2988 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2989 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2990 if (xop & 0x10)
2991 gen_op_logic_T0_cc();
2992 break;
2993 case 0x6:
56ec06bb
BS		 2994 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
2995 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2996 if (xop & 0x10)
2997 gen_op_logic_T0_cc();
2998 break;
2999 case 0x7:
56ec06bb
BS		 3000 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3001 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3002 if (xop & 0x10)
3003 gen_op_logic_T0_cc();
3004 break;
3005 case 0x8:
cf495bcf 3006 if (xop & 0x10)
af7bf89b 3007 gen_op_addx_T1_T0_cc();
38bc628b 3008 else {
dc99a3f2 3009 gen_mov_reg_C(cpu_tmp0, cpu_psr);
38bc628b
BS		 3010 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3011 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3012 }
cf495bcf 3013 break;
ded3ab80 3014#ifdef TARGET_SPARC64
0f8a249a 3015 case 0x9: /* V9 mulx */
1a2fb1c0 3016 tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
ded3ab80
PB		 3017 break;
3018#endif
cf495bcf
FB		 3019 case 0xa:
3020 gen_op_umul_T1_T0();
3021 if (xop & 0x10)
3022 gen_op_logic_T0_cc();
3023 break;
3024 case 0xb:
3025 gen_op_smul_T1_T0();
3026 if (xop & 0x10)
3027 gen_op_logic_T0_cc();
3028 break;
3029 case 0xc:
cf495bcf 3030 if (xop & 0x10)
af7bf89b 3031 gen_op_subx_T1_T0_cc();
38bc628b 3032 else {
dc99a3f2 3033 gen_mov_reg_C(cpu_tmp0, cpu_psr);
38bc628b
BS		 3034 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
3035 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3036 }
cf495bcf 3037 break;
ded3ab80 3038#ifdef TARGET_SPARC64
0f8a249a 3039 case 0xd: /* V9 udivx */
ded3ab80
PB		 3040 gen_op_udivx_T1_T0();
3041 break;
3042#endif
cf495bcf
FB		 3043 case 0xe:
3044 gen_op_udiv_T1_T0();
3045 if (xop & 0x10)
3046 gen_op_div_cc();
3047 break;
3048 case 0xf:
3049 gen_op_sdiv_T1_T0();
3050 if (xop & 0x10)
3051 gen_op_div_cc();
3052 break;
3053 default:
3054 goto illegal_insn;
3055 }
0f8a249a 3056 gen_movl_T0_reg(rd);
cf495bcf
FB		 3057 } else {
3058 switch (xop) {
0f8a249a
BS		 3059 case 0x20: /* taddcc */
3060 gen_op_tadd_T1_T0_cc();
3061 gen_movl_T0_reg(rd);
3062 break;
3063 case 0x21: /* tsubcc */
3064 gen_op_tsub_T1_T0_cc();
3065 gen_movl_T0_reg(rd);
3066 break;
3067 case 0x22: /* taddcctv */
90251fb9 3068 save_state(dc);
0f8a249a
BS		 3069 gen_op_tadd_T1_T0_ccTV();
3070 gen_movl_T0_reg(rd);
3071 break;
3072 case 0x23: /* tsubcctv */
90251fb9 3073 save_state(dc);
0f8a249a
BS		 3074 gen_op_tsub_T1_T0_ccTV();
3075 gen_movl_T0_reg(rd);
3076 break;
cf495bcf
FB		 3077 case 0x24: /* mulscc */
3078 gen_op_mulscc_T1_T0();
3079 gen_movl_T0_reg(rd);
3080 break;
83469015 3081#ifndef TARGET_SPARC64
0f8a249a 3082 case 0x25: /* sll */
1a2fb1c0
BS		 3083 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3084 tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3085 gen_movl_T0_reg(rd);
3086 break;
83469015 3087 case 0x26: /* srl */
1a2fb1c0
BS		 3088 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3089 tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3090 gen_movl_T0_reg(rd);
3091 break;
83469015 3092 case 0x27: /* sra */
1a2fb1c0
BS		 3093 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
3094 tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 3095 gen_movl_T0_reg(rd);
3096 break;
83469015 3097#endif
cf495bcf
FB		 3098 case 0x30:
3099 {
cf495bcf 3100 switch(rd) {
3475187d 3101 case 0: /* wry */
0f8a249a
BS		 3102 gen_op_xor_T1_T0();
3103 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 3104 break;
65fe7b09
BS		 3105#ifndef TARGET_SPARC64
3106 case 0x01 ... 0x0f: /* undefined in the
3107 SPARCv8 manual, nop
3108 on the microSPARC
3109 II */
3110 case 0x10 ... 0x1f: /* implementation-dependent
3111 in the SPARCv8
3112 manual, nop on the
3113 microSPARC II */
3114 break;
3115#else
0f8a249a 3116 case 0x2: /* V9 wrccr */
ee0b03fd 3117 gen_op_xor_T1_T0();
3475187d 3118 gen_op_wrccr();
0f8a249a
BS		 3119 break;
3120 case 0x3: /* V9 wrasi */
ee0b03fd 3121 gen_op_xor_T1_T0();
0f8a249a
BS		 3122 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3123 break;
3124 case 0x6: /* V9 wrfprs */
3125 gen_op_xor_T1_T0();
3126 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 3127 save_state(dc);
3128 gen_op_next_insn();
57fec1fe 3129 tcg_gen_exit_tb(0);
3299908c 3130 dc->is_br = 1;
0f8a249a
BS		 3131 break;
3132 case 0xf: /* V9 sir, nop if user */
3475187d 3133#if !defined(CONFIG_USER_ONLY)
0f8a249a 3134 if (supervisor(dc))
1a2fb1c0 3135 ; // XXX
3475187d 3136#endif
0f8a249a
BS		 3137 break;
3138 case 0x13: /* Graphics Status */
725cb90b
FB		 3139 if (gen_trap_ifnofpu(dc))
3140 goto jmp_insn;
ee0b03fd 3141 gen_op_xor_T1_T0();
0f8a249a
BS		 3142 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3143 break;
3144 case 0x17: /* Tick compare */
83469015 3145#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3146 if (!supervisor(dc))
3147 goto illegal_insn;
83469015 3148#endif
ccd4a219
BS		 3149 {
3150 TCGv r_tickptr;
3151
3152 gen_op_xor_T1_T0();
3153 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3154 tick_cmpr));
3155 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3156 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3157 offsetof(CPUState, tick));
3158 tcg_gen_helper_0_2(helper_tick_set_limit,
3159 r_tickptr, cpu_T[0]);
3160 }
0f8a249a
BS		 3161 break;
3162 case 0x18: /* System tick */
83469015 3163#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3164 if (!supervisor(dc))
3165 goto illegal_insn;
83469015 3166#endif
ccd4a219
BS		 3167 {
3168 TCGv r_tickptr;
3169
3170 gen_op_xor_T1_T0();
3171 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3172 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3173 offsetof(CPUState, stick));
3174 tcg_gen_helper_0_2(helper_tick_set_count,
3175 r_tickptr, cpu_T[0]);
3176 }
0f8a249a
BS		 3177 break;
3178 case 0x19: /* System tick compare */
83469015 3179#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3180 if (!supervisor(dc))
3181 goto illegal_insn;
3475187d 3182#endif
ccd4a219
BS		 3183 {
3184 TCGv r_tickptr;
3185
3186 gen_op_xor_T1_T0();
3187 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3188 stick_cmpr));
3189 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3190 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3191 offsetof(CPUState, stick));
3192 tcg_gen_helper_0_2(helper_tick_set_limit,
3193 r_tickptr, cpu_T[0]);
3194 }
0f8a249a 3195 break;
83469015 3196
0f8a249a
BS		 3197 case 0x10: /* Performance Control */
3198 case 0x11: /* Performance Instrumentation Counter */
3199 case 0x12: /* Dispatch Control */
3200 case 0x14: /* Softint set */
3201 case 0x15: /* Softint clear */
3202 case 0x16: /* Softint write */
83469015 3203#endif
3475187d 3204 default:
cf495bcf
FB		 3205 goto illegal_insn;
3206 }
3207 }
3208 break;
e8af50a3 3209#if !defined(CONFIG_USER_ONLY)
af7bf89b 3210 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3211 {
0f8a249a
BS		 3212 if (!supervisor(dc))
3213 goto priv_insn;
3475187d 3214#ifdef TARGET_SPARC64
0f8a249a
BS		 3215 switch (rd) {
3216 case 0:
3217 gen_op_saved();
3218 break;
3219 case 1:
3220 gen_op_restored();
3221 break;
e9ebed4d
BS		 3222 case 2: /* UA2005 allclean */
3223 case 3: /* UA2005 otherw */
3224 case 4: /* UA2005 normalw */
3225 case 5: /* UA2005 invalw */
3226 // XXX
0f8a249a 3227 default:
3475187d
FB		 3228 goto illegal_insn;
3229 }
3230#else
e8af50a3 3231 gen_op_xor_T1_T0();
1a2fb1c0 3232 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
9e61bde5
FB		 3233 save_state(dc);
3234 gen_op_next_insn();
57fec1fe 3235 tcg_gen_exit_tb(0);
0f8a249a 3236 dc->is_br = 1;
3475187d 3237#endif
e8af50a3
FB		 3238 }
3239 break;
af7bf89b 3240 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3241 {
0f8a249a
BS		 3242 if (!supervisor(dc))
3243 goto priv_insn;
e8af50a3 3244 gen_op_xor_T1_T0();
3475187d 3245#ifdef TARGET_SPARC64
0f8a249a
BS		 3246 switch (rd) {
3247 case 0: // tpc
375ee38b
BS		 3248 {
3249 TCGv r_tsptr;
3250
3251 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3252 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3253 offsetof(CPUState, tsptr));
3254 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3255 offsetof(trap_state, tpc));
3256 }
0f8a249a
BS		 3257 break;
3258 case 1: // tnpc
375ee38b
BS		 3259 {
3260 TCGv r_tsptr;
3261
3262 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3263 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3264 offsetof(CPUState, tsptr));
3265 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3266 offsetof(trap_state, tnpc));
3267 }
0f8a249a
BS		 3268 break;
3269 case 2: // tstate
375ee38b
BS		 3270 {
3271 TCGv r_tsptr;
3272
3273 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3274 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3275 offsetof(CPUState, tsptr));
3276 tcg_gen_st_tl(cpu_T[0], r_tsptr,
3277 offsetof(trap_state, tstate));
3278 }
0f8a249a
BS		 3279 break;
3280 case 3: // tt
375ee38b
BS		 3281 {
3282 TCGv r_tsptr;
3283
3284 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3285 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3286 offsetof(CPUState, tsptr));
3287 tcg_gen_st_i32(cpu_T[0], r_tsptr,
3288 offsetof(trap_state, tt));
3289 }
0f8a249a
BS		 3290 break;
3291 case 4: // tick
ccd4a219
BS		 3292 {
3293 TCGv r_tickptr;
3294
3295 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3296 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3297 offsetof(CPUState, tick));
3298 tcg_gen_helper_0_2(helper_tick_set_count,
3299 r_tickptr, cpu_T[0]);
3300 }
0f8a249a
BS		 3301 break;
3302 case 5: // tba
3303 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3304 break;
3305 case 6: // pstate
ded3ab80 3306 save_state(dc);
1a2fb1c0 3307 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
ded3ab80 3308 gen_op_next_insn();
57fec1fe 3309 tcg_gen_exit_tb(0);
ded3ab80 3310 dc->is_br = 1;
0f8a249a
BS		 3311 break;
3312 case 7: // tl
3313 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3314 break;
3315 case 8: // pil
3316 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3317 break;
3318 case 9: // cwp
3319 gen_op_wrcwp();
3320 break;
3321 case 10: // cansave
3322 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3323 break;
3324 case 11: // canrestore
3325 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3326 break;
3327 case 12: // cleanwin
3328 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3329 break;
3330 case 13: // otherwin
3331 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3332 break;
3333 case 14: // wstate
3334 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3335 break;
e9ebed4d
BS		 3336 case 16: // UA2005 gl
3337 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3338 break;
3339 case 26: // UA2005 strand status
3340 if (!hypervisor(dc))
3341 goto priv_insn;
3342 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3343 break;
0f8a249a
BS		 3344 default:
3345 goto illegal_insn;
3346 }
3475187d 3347#else
1a2fb1c0
BS		 3348 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3349 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3475187d 3350#endif
e8af50a3
FB		 3351 }
3352 break;
e9ebed4d 3353 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3354 {
e9ebed4d 3355#ifndef TARGET_SPARC64
0f8a249a
BS		 3356 if (!supervisor(dc))
3357 goto priv_insn;
e8af50a3 3358 gen_op_xor_T1_T0();
e9ebed4d
BS		 3359 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3360#else
3361 if (!hypervisor(dc))
3362 goto priv_insn;
3363 gen_op_xor_T1_T0();
3364 switch (rd) {
3365 case 0: // hpstate
3366 // XXX gen_op_wrhpstate();
3367 save_state(dc);
3368 gen_op_next_insn();
57fec1fe 3369 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3370 dc->is_br = 1;
3371 break;
3372 case 1: // htstate
3373 // XXX gen_op_wrhtstate();
3374 break;
3375 case 3: // hintp
3376 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3377 break;
3378 case 5: // htba
3379 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3380 break;
3381 case 31: // hstick_cmpr
ccd4a219
BS		 3382 {
3383 TCGv r_tickptr;
3384
3385 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
3386 hstick_cmpr));
3387 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3388 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3389 offsetof(CPUState, hstick));
3390 tcg_gen_helper_0_2(helper_tick_set_limit,
3391 r_tickptr, cpu_T[0]);
3392 }
e9ebed4d
BS		 3393 break;
3394 case 6: // hver readonly
3395 default:
3396 goto illegal_insn;
3397 }
3398#endif
e8af50a3
FB		 3399 }
3400 break;
3401#endif
3475187d 3402#ifdef TARGET_SPARC64
0f8a249a
BS		 3403 case 0x2c: /* V9 movcc */
3404 {
3405 int cc = GET_FIELD_SP(insn, 11, 12);
3406 int cond = GET_FIELD_SP(insn, 14, 17);
00f219bf
BS		 3407 TCGv r_zero;
3408 int l1;
3409
0f8a249a
BS		 3410 flush_T2(dc);
3411 if (insn & (1 << 18)) {
3412 if (cc == 0)
19f329ad 3413 gen_cond(cpu_T[2], 0, cond);
0f8a249a 3414 else if (cc == 2)
19f329ad 3415 gen_cond(cpu_T[2], 1, cond);
0f8a249a
BS		 3416 else
3417 goto illegal_insn;
3418 } else {
19f329ad 3419 gen_fcond(cpu_T[2], cc, cond);
0f8a249a 3420 }
00f219bf
BS		 3421
3422 l1 = gen_new_label();
3423
1ec6d2ea 3424 r_zero = tcg_const_tl(0);
00f219bf
BS		 3425 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1);
3426 if (IS_IMM) { /* immediate */
3427 rs2 = GET_FIELD_SPs(insn, 0, 10);
3428 gen_movl_simm_T1(rs2);
3429 } else {
3430 rs2 = GET_FIELD_SP(insn, 0, 4);
3431 gen_movl_reg_T1(rs2);
3432 }
3433 gen_movl_T1_reg(rd);
3434 gen_set_label(l1);
0f8a249a
BS		 3435 break;
3436 }
3437 case 0x2d: /* V9 sdivx */
3475187d 3438 gen_op_sdivx_T1_T0();
0f8a249a
BS		 3439 gen_movl_T0_reg(rd);
3440 break;
3441 case 0x2e: /* V9 popc */
3442 {
3443 if (IS_IMM) { /* immediate */
3444 rs2 = GET_FIELD_SPs(insn, 0, 12);
3445 gen_movl_simm_T1(rs2);
3446 // XXX optimize: popc(constant)
3447 }
3448 else {
3449 rs2 = GET_FIELD_SP(insn, 0, 4);
3450 gen_movl_reg_T1(rs2);
3451 }
1a2fb1c0
BS		 3452 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3453 cpu_T[1]);
0f8a249a
BS		 3454 gen_movl_T0_reg(rd);
3455 }
3456 case 0x2f: /* V9 movr */
3457 {
3458 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 3459 TCGv r_zero;
3460 int l1;
3461
0f8a249a 3462 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3463 gen_movl_reg_T0(rs1);
00f219bf
BS		 3464
3465 l1 = gen_new_label();
3466
1ec6d2ea 3467 r_zero = tcg_const_tl(0);
00f219bf 3468 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
0f8a249a
BS		 3469 if (IS_IMM) { /* immediate */
3470 rs2 = GET_FIELD_SPs(insn, 0, 9);
3471 gen_movl_simm_T1(rs2);
00f219bf 3472 } else {
0f8a249a
BS		 3473 rs2 = GET_FIELD_SP(insn, 0, 4);
3474 gen_movl_reg_T1(rs2);
3475 }
00f219bf
BS		 3476 gen_movl_T1_reg(rd);
3477 gen_set_label(l1);
0f8a249a
BS		 3478 break;
3479 }
3480#endif
3481 default:
3482 goto illegal_insn;
3483 }
3484 }
3299908c
BS		 3485 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3486#ifdef TARGET_SPARC64
3487 int opf = GET_FIELD_SP(insn, 5, 13);
3488 rs1 = GET_FIELD(insn, 13, 17);
3489 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 3490 if (gen_trap_ifnofpu(dc))
3491 goto jmp_insn;
3299908c
BS		 3492
3493 switch (opf) {
e9ebed4d
BS		 3494 case 0x000: /* VIS I edge8cc */
3495 case 0x001: /* VIS II edge8n */
3496 case 0x002: /* VIS I edge8lcc */
3497 case 0x003: /* VIS II edge8ln */
3498 case 0x004: /* VIS I edge16cc */
3499 case 0x005: /* VIS II edge16n */
3500 case 0x006: /* VIS I edge16lcc */
3501 case 0x007: /* VIS II edge16ln */
3502 case 0x008: /* VIS I edge32cc */
3503 case 0x009: /* VIS II edge32n */
3504 case 0x00a: /* VIS I edge32lcc */
3505 case 0x00b: /* VIS II edge32ln */
3506 // XXX
3507 goto illegal_insn;
3508 case 0x010: /* VIS I array8 */
3509 gen_movl_reg_T0(rs1);
3510 gen_movl_reg_T1(rs2);
3511 gen_op_array8();
3512 gen_movl_T0_reg(rd);
3513 break;
3514 case 0x012: /* VIS I array16 */
3515 gen_movl_reg_T0(rs1);
3516 gen_movl_reg_T1(rs2);
3517 gen_op_array16();
3518 gen_movl_T0_reg(rd);
3519 break;
3520 case 0x014: /* VIS I array32 */
3521 gen_movl_reg_T0(rs1);
3522 gen_movl_reg_T1(rs2);
3523 gen_op_array32();
3524 gen_movl_T0_reg(rd);
3525 break;
3299908c 3526 case 0x018: /* VIS I alignaddr */
3299908c
BS		 3527 gen_movl_reg_T0(rs1);
3528 gen_movl_reg_T1(rs2);
3529 gen_op_alignaddr();
3530 gen_movl_T0_reg(rd);
3531 break;
e9ebed4d 3532 case 0x019: /* VIS II bmask */
3299908c 3533 case 0x01a: /* VIS I alignaddrl */
3299908c 3534 // XXX
e9ebed4d
BS		 3535 goto illegal_insn;
3536 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 3537 gen_op_load_fpr_DT0(DFPREG(rs1));
3538 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3539 gen_op_fcmple16();
2382dc6b 3540 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3541 break;
3542 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 3543 gen_op_load_fpr_DT0(DFPREG(rs1));
3544 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3545 gen_op_fcmpne16();
2382dc6b 3546 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3547 break;
e9ebed4d 3548 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 3549 gen_op_load_fpr_DT0(DFPREG(rs1));
3550 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3551 gen_op_fcmple32();
2382dc6b 3552 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3553 break;
3554 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 3555 gen_op_load_fpr_DT0(DFPREG(rs1));
3556 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3557 gen_op_fcmpne32();
2382dc6b 3558 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3559 break;
3560 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 3561 gen_op_load_fpr_DT0(DFPREG(rs1));
3562 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3563 gen_op_fcmpgt16();
2382dc6b 3564 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3565 break;
3566 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 3567 gen_op_load_fpr_DT0(DFPREG(rs1));
3568 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3569 gen_op_fcmpeq16();
2382dc6b 3570 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3571 break;
3572 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 3573 gen_op_load_fpr_DT0(DFPREG(rs1));
3574 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3575 gen_op_fcmpgt32();
2382dc6b 3576 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3577 break;
3578 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 3579 gen_op_load_fpr_DT0(DFPREG(rs1));
3580 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3581 gen_op_fcmpeq32();
2382dc6b 3582 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3583 break;
3584 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 3585 gen_op_load_fpr_DT0(DFPREG(rs1));
3586 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3587 gen_op_fmul8x16();
2382dc6b 3588 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3589 break;
3590 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 3591 gen_op_load_fpr_DT0(DFPREG(rs1));
3592 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3593 gen_op_fmul8x16au();
2382dc6b 3594 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3595 break;
3596 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 3597 gen_op_load_fpr_DT0(DFPREG(rs1));
3598 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3599 gen_op_fmul8x16al();
2382dc6b 3600 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3601 break;
3602 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 3603 gen_op_load_fpr_DT0(DFPREG(rs1));
3604 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3605 gen_op_fmul8sux16();
2382dc6b 3606 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3607 break;
3608 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 3609 gen_op_load_fpr_DT0(DFPREG(rs1));
3610 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3611 gen_op_fmul8ulx16();
2382dc6b 3612 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3613 break;
3614 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 3615 gen_op_load_fpr_DT0(DFPREG(rs1));
3616 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3617 gen_op_fmuld8sux16();
2382dc6b 3618 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3619 break;
3620 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 3621 gen_op_load_fpr_DT0(DFPREG(rs1));
3622 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3623 gen_op_fmuld8ulx16();
2382dc6b 3624 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3625 break;
3626 case 0x03a: /* VIS I fpack32 */
3627 case 0x03b: /* VIS I fpack16 */
3628 case 0x03d: /* VIS I fpackfix */
3629 case 0x03e: /* VIS I pdist */
3630 // XXX
3631 goto illegal_insn;
3299908c 3632 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 3633 gen_op_load_fpr_DT0(DFPREG(rs1));
3634 gen_op_load_fpr_DT1(DFPREG(rs2));
3299908c 3635 gen_op_faligndata();
2382dc6b 3636 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 3637 break;
e9ebed4d 3638 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 3639 gen_op_load_fpr_DT0(DFPREG(rs1));
3640 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3641 gen_op_fpmerge();
2382dc6b 3642 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3643 break;
3644 case 0x04c: /* VIS II bshuffle */
3645 // XXX
3646 goto illegal_insn;
3647 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 3648 gen_op_load_fpr_DT0(DFPREG(rs1));
3649 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3650 gen_op_fexpand();
2382dc6b 3651 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3652 break;
3653 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 3654 gen_op_load_fpr_DT0(DFPREG(rs1));
3655 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3656 gen_op_fpadd16();
2382dc6b 3657 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3658 break;
3659 case 0x051: /* VIS I fpadd16s */
3660 gen_op_load_fpr_FT0(rs1);
3661 gen_op_load_fpr_FT1(rs2);
3662 gen_op_fpadd16s();
3663 gen_op_store_FT0_fpr(rd);
3664 break;
3665 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 3666 gen_op_load_fpr_DT0(DFPREG(rs1));
3667 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3668 gen_op_fpadd32();
2382dc6b 3669 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3670 break;
3671 case 0x053: /* VIS I fpadd32s */
3672 gen_op_load_fpr_FT0(rs1);
3673 gen_op_load_fpr_FT1(rs2);
3674 gen_op_fpadd32s();
3675 gen_op_store_FT0_fpr(rd);
3676 break;
3677 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 3678 gen_op_load_fpr_DT0(DFPREG(rs1));
3679 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3680 gen_op_fpsub16();
2382dc6b 3681 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3682 break;
3683 case 0x055: /* VIS I fpsub16s */
3684 gen_op_load_fpr_FT0(rs1);
3685 gen_op_load_fpr_FT1(rs2);
3686 gen_op_fpsub16s();
3687 gen_op_store_FT0_fpr(rd);
3688 break;
3689 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 3690 gen_op_load_fpr_DT0(DFPREG(rs1));
3691 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3692 gen_op_fpadd32();
2382dc6b 3693 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3694 break;
3695 case 0x057: /* VIS I fpsub32s */
3696 gen_op_load_fpr_FT0(rs1);
3697 gen_op_load_fpr_FT1(rs2);
3698 gen_op_fpsub32s();
3699 gen_op_store_FT0_fpr(rd);
3700 break;
3299908c 3701 case 0x060: /* VIS I fzero */
3299908c 3702 gen_op_movl_DT0_0();
2382dc6b 3703 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3704 break;
3705 case 0x061: /* VIS I fzeros */
3299908c
BS		 3706 gen_op_movl_FT0_0();
3707 gen_op_store_FT0_fpr(rd);
3708 break;
e9ebed4d 3709 case 0x062: /* VIS I fnor */
2382dc6b
BS		 3710 gen_op_load_fpr_DT0(DFPREG(rs1));
3711 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3712 gen_op_fnor();
2382dc6b 3713 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3714 break;
3715 case 0x063: /* VIS I fnors */
3716 gen_op_load_fpr_FT0(rs1);
3717 gen_op_load_fpr_FT1(rs2);
3718 gen_op_fnors();
3719 gen_op_store_FT0_fpr(rd);
3720 break;
3721 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 3722 gen_op_load_fpr_DT1(DFPREG(rs1));
3723 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3724 gen_op_fandnot();
2382dc6b 3725 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3726 break;
3727 case 0x065: /* VIS I fandnot2s */
3728 gen_op_load_fpr_FT1(rs1);
3729 gen_op_load_fpr_FT0(rs2);
3730 gen_op_fandnots();
3731 gen_op_store_FT0_fpr(rd);
3732 break;
3733 case 0x066: /* VIS I fnot2 */
2382dc6b 3734 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3735 gen_op_fnot();
2382dc6b 3736 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3737 break;
3738 case 0x067: /* VIS I fnot2s */
3739 gen_op_load_fpr_FT1(rs2);
3740 gen_op_fnot();
3741 gen_op_store_FT0_fpr(rd);
3742 break;
3743 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 3744 gen_op_load_fpr_DT0(DFPREG(rs1));
3745 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3746 gen_op_fandnot();
2382dc6b 3747 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3748 break;
3749 case 0x069: /* VIS I fandnot1s */
3750 gen_op_load_fpr_FT0(rs1);
3751 gen_op_load_fpr_FT1(rs2);
3752 gen_op_fandnots();
3753 gen_op_store_FT0_fpr(rd);
3754 break;
3755 case 0x06a: /* VIS I fnot1 */
2382dc6b 3756 gen_op_load_fpr_DT1(DFPREG(rs1));
e9ebed4d 3757 gen_op_fnot();
2382dc6b 3758 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3759 break;
3760 case 0x06b: /* VIS I fnot1s */
3761 gen_op_load_fpr_FT1(rs1);
3762 gen_op_fnot();
3763 gen_op_store_FT0_fpr(rd);
3764 break;
3765 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 3766 gen_op_load_fpr_DT0(DFPREG(rs1));
3767 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3768 gen_op_fxor();
2382dc6b 3769 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3770 break;
3771 case 0x06d: /* VIS I fxors */
3772 gen_op_load_fpr_FT0(rs1);
3773 gen_op_load_fpr_FT1(rs2);
3774 gen_op_fxors();
3775 gen_op_store_FT0_fpr(rd);
3776 break;
3777 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 3778 gen_op_load_fpr_DT0(DFPREG(rs1));
3779 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3780 gen_op_fnand();
2382dc6b 3781 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3782 break;
3783 case 0x06f: /* VIS I fnands */
3784 gen_op_load_fpr_FT0(rs1);
3785 gen_op_load_fpr_FT1(rs2);
3786 gen_op_fnands();
3787 gen_op_store_FT0_fpr(rd);
3788 break;
3789 case 0x070: /* VIS I fand */
2382dc6b
BS		 3790 gen_op_load_fpr_DT0(DFPREG(rs1));
3791 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3792 gen_op_fand();
2382dc6b 3793 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3794 break;
3795 case 0x071: /* VIS I fands */
3796 gen_op_load_fpr_FT0(rs1);
3797 gen_op_load_fpr_FT1(rs2);
3798 gen_op_fands();
3799 gen_op_store_FT0_fpr(rd);
3800 break;
3801 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 3802 gen_op_load_fpr_DT0(DFPREG(rs1));
3803 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3804 gen_op_fxnor();
2382dc6b 3805 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3806 break;
3807 case 0x073: /* VIS I fxnors */
3808 gen_op_load_fpr_FT0(rs1);
3809 gen_op_load_fpr_FT1(rs2);
3810 gen_op_fxnors();
3811 gen_op_store_FT0_fpr(rd);
3812 break;
3299908c 3813 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 3814 gen_op_load_fpr_DT0(DFPREG(rs1));
3815 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3816 break;
3817 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 3818 gen_op_load_fpr_FT0(rs1);
3819 gen_op_store_FT0_fpr(rd);
3820 break;
e9ebed4d 3821 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 3822 gen_op_load_fpr_DT1(DFPREG(rs1));
3823 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3824 gen_op_fornot();
2382dc6b 3825 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3826 break;
3827 case 0x077: /* VIS I fornot2s */
3828 gen_op_load_fpr_FT1(rs1);
3829 gen_op_load_fpr_FT0(rs2);
3830 gen_op_fornots();
3831 gen_op_store_FT0_fpr(rd);
3832 break;
3299908c 3833 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 3834 gen_op_load_fpr_DT0(DFPREG(rs2));
3835 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3836 break;
3837 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 3838 gen_op_load_fpr_FT0(rs2);
3839 gen_op_store_FT0_fpr(rd);
3840 break;
e9ebed4d 3841 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 3842 gen_op_load_fpr_DT0(DFPREG(rs1));
3843 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3844 gen_op_fornot();
2382dc6b 3845 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3846 break;
3847 case 0x07b: /* VIS I fornot1s */
3848 gen_op_load_fpr_FT0(rs1);
3849 gen_op_load_fpr_FT1(rs2);
3850 gen_op_fornots();
3851 gen_op_store_FT0_fpr(rd);
3852 break;
3853 case 0x07c: /* VIS I for */
2382dc6b
BS		 3854 gen_op_load_fpr_DT0(DFPREG(rs1));
3855 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3856 gen_op_for();
2382dc6b 3857 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3858 break;
3859 case 0x07d: /* VIS I fors */
3860 gen_op_load_fpr_FT0(rs1);
3861 gen_op_load_fpr_FT1(rs2);
3862 gen_op_fors();
3863 gen_op_store_FT0_fpr(rd);
3864 break;
3299908c 3865 case 0x07e: /* VIS I fone */
3299908c 3866 gen_op_movl_DT0_1();
2382dc6b 3867 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3868 break;
3869 case 0x07f: /* VIS I fones */
3299908c
BS		 3870 gen_op_movl_FT0_1();
3871 gen_op_store_FT0_fpr(rd);
3872 break;
e9ebed4d
BS		 3873 case 0x080: /* VIS I shutdown */
3874 case 0x081: /* VIS II siam */
3875 // XXX
3876 goto illegal_insn;
3299908c
BS		 3877 default:
3878 goto illegal_insn;
3879 }
3880#else
0f8a249a 3881 goto ncp_insn;
3299908c
BS		 3882#endif
3883 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 3884#ifdef TARGET_SPARC64
0f8a249a 3885 goto illegal_insn;
fcc72045 3886#else
0f8a249a 3887 goto ncp_insn;
fcc72045 3888#endif
3475187d 3889#ifdef TARGET_SPARC64
0f8a249a 3890 } else if (xop == 0x39) { /* V9 return */
3475187d 3891 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 3892 save_state(dc);
0f8a249a
BS		 3893 gen_movl_reg_T0(rs1);
3894 if (IS_IMM) { /* immediate */
3895 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3896 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3897 } else { /* register */
3475187d
FB		 3898 rs2 = GET_FIELD(insn, 27, 31);
3899#if defined(OPTIM)
0f8a249a 3900 if (rs2) {
3475187d 3901#endif
0f8a249a
BS		 3902 gen_movl_reg_T1(rs2);
3903 gen_op_add_T1_T0();
3475187d 3904#if defined(OPTIM)
0f8a249a 3905 }
3475187d
FB		 3906#endif
3907 }
0f8a249a
BS		 3908 gen_op_restore();
3909 gen_mov_pc_npc(dc);
6ea4a6c8 3910 gen_op_check_align_T0_3();
1a2fb1c0 3911 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3912 dc->npc = DYNAMIC_PC;
3913 goto jmp_insn;
3475187d 3914#endif
0f8a249a 3915 } else {
e80cfcfc 3916 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3917 gen_movl_reg_T0(rs1);
3918 if (IS_IMM) { /* immediate */
3919 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3920 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3921 } else { /* register */
e80cfcfc
FB		 3922 rs2 = GET_FIELD(insn, 27, 31);
3923#if defined(OPTIM)
0f8a249a 3924 if (rs2) {
e80cfcfc 3925#endif
0f8a249a
BS		 3926 gen_movl_reg_T1(rs2);
3927 gen_op_add_T1_T0();
e80cfcfc 3928#if defined(OPTIM)
0f8a249a 3929 }
e8af50a3 3930#endif
cf495bcf 3931 }
0f8a249a
BS		 3932 switch (xop) {
3933 case 0x38: /* jmpl */
3934 {
3935 if (rd != 0) {
1a2fb1c0 3936 tcg_gen_movi_tl(cpu_T[1], dc->pc);
0f8a249a
BS		 3937 gen_movl_T1_reg(rd);
3938 }
0bee699e 3939 gen_mov_pc_npc(dc);
6ea4a6c8 3940 gen_op_check_align_T0_3();
1a2fb1c0 3941 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3942 dc->npc = DYNAMIC_PC;
3943 }
3944 goto jmp_insn;
3475187d 3945#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3946 case 0x39: /* rett, V9 return */
3947 {
3948 if (!supervisor(dc))
3949 goto priv_insn;
0bee699e 3950 gen_mov_pc_npc(dc);
6ea4a6c8 3951 gen_op_check_align_T0_3();
1a2fb1c0 3952 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a 3953 dc->npc = DYNAMIC_PC;
1a2fb1c0 3954 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3955 }
3956 goto jmp_insn;
3957#endif
3958 case 0x3b: /* flush */
1a2fb1c0 3959 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
0f8a249a
BS		 3960 break;
3961 case 0x3c: /* save */
3962 save_state(dc);
3963 gen_op_save();
3964 gen_movl_T0_reg(rd);
3965 break;
3966 case 0x3d: /* restore */
3967 save_state(dc);
3968 gen_op_restore();
3969 gen_movl_T0_reg(rd);
3970 break;
3475187d 3971#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3972 case 0x3e: /* V9 done/retry */
3973 {
3974 switch (rd) {
3975 case 0:
3976 if (!supervisor(dc))
3977 goto priv_insn;
3978 dc->npc = DYNAMIC_PC;
3979 dc->pc = DYNAMIC_PC;
1a2fb1c0 3980 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3981 goto jmp_insn;
3982 case 1:
3983 if (!supervisor(dc))
3984 goto priv_insn;
3985 dc->npc = DYNAMIC_PC;
3986 dc->pc = DYNAMIC_PC;
1a2fb1c0 3987 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3988 goto jmp_insn;
3989 default:
3990 goto illegal_insn;
3991 }
3992 }
3993 break;
3994#endif
3995 default:
3996 goto illegal_insn;
3997 }
cf495bcf 3998 }
0f8a249a
BS		 3999 break;
4000 }
4001 break;
4002 case 3: /* load/store instructions */
4003 {
4004 unsigned int xop = GET_FIELD(insn, 7, 12);
4005 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 4006 save_state(dc);
0f8a249a 4007 gen_movl_reg_T0(rs1);
81ad8ba2
BS		 4008 if (xop == 0x3c || xop == 0x3e)
4009 {
4010 rs2 = GET_FIELD(insn, 27, 31);
4011 gen_movl_reg_T1(rs2);
4012 }
4013 else if (IS_IMM) { /* immediate */
0f8a249a 4014 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 4015 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 4016 } else { /* register */
4017 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 4018#if defined(OPTIM)
0f8a249a 4019 if (rs2 != 0) {
e80cfcfc 4020#endif
0f8a249a
BS		 4021 gen_movl_reg_T1(rs2);
4022 gen_op_add_T1_T0();
e80cfcfc 4023#if defined(OPTIM)
0f8a249a 4024 }
e80cfcfc 4025#endif
0f8a249a 4026 }
2f2ecb83
BS		 4027 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4028 (xop > 0x17 && xop <= 0x1d ) ||
4029 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 4030 switch (xop) {
1a2fb1c0 4031 case 0x0: /* load unsigned word */
6ea4a6c8 4032 gen_op_check_align_T0_3();
1a2fb1c0
BS		 4033 ABI32_MASK(cpu_T[0]);
4034 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4035 break;
4036 case 0x1: /* load unsigned byte */
1a2fb1c0
BS		 4037 ABI32_MASK(cpu_T[0]);
4038 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4039 break;
4040 case 0x2: /* load unsigned halfword */
6ea4a6c8 4041 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4042 ABI32_MASK(cpu_T[0]);
4043 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4044 break;
4045 case 0x3: /* load double word */
0f8a249a 4046 if (rd & 1)
d4218d99 4047 goto illegal_insn;
1a2fb1c0
BS		 4048 else {
4049 TCGv r_dword;
4050
4051 r_dword = tcg_temp_new(TCG_TYPE_I64);
4052 gen_op_check_align_T0_7();
4053 ABI32_MASK(cpu_T[0]);
4054 tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
4055 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
4056 gen_movl_T0_reg(rd + 1);
4057 tcg_gen_shri_i64(r_dword, r_dword, 32);
4058 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
4059 }
0f8a249a
BS		 4060 break;
4061 case 0x9: /* load signed byte */
1a2fb1c0
BS		 4062 ABI32_MASK(cpu_T[0]);
4063 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4064 break;
4065 case 0xa: /* load signed halfword */
6ea4a6c8 4066 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4067 ABI32_MASK(cpu_T[0]);
4068 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4069 break;
4070 case 0xd: /* ldstub -- XXX: should be atomically */
1a2fb1c0
BS		 4071 tcg_gen_movi_i32(cpu_tmp0, 0xff);
4072 ABI32_MASK(cpu_T[0]);
4073 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4074 tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4075 break;
4076 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8 4077 gen_op_check_align_T0_3();
0f8a249a 4078 gen_movl_reg_T1(rd);
1a2fb1c0
BS		 4079 ABI32_MASK(cpu_T[0]);
4080 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
4081 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4082 tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
0f8a249a 4083 break;
3475187d 4084#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4085 case 0x10: /* load word alternate */
3475187d 4086#ifndef TARGET_SPARC64
0f8a249a
BS		 4087 if (IS_IMM)
4088 goto illegal_insn;
4089 if (!supervisor(dc))
4090 goto priv_insn;
6ea4a6c8 4091#endif
8f577d3d 4092 gen_op_check_align_T0_3();
81ad8ba2 4093 gen_ld_asi(insn, 4, 0);
0f8a249a
BS		 4094 break;
4095 case 0x11: /* load unsigned byte alternate */
3475187d 4096#ifndef TARGET_SPARC64
0f8a249a
BS		 4097 if (IS_IMM)
4098 goto illegal_insn;
4099 if (!supervisor(dc))
4100 goto priv_insn;
4101#endif
81ad8ba2 4102 gen_ld_asi(insn, 1, 0);
0f8a249a
BS		 4103 break;
4104 case 0x12: /* load unsigned halfword alternate */
3475187d 4105#ifndef TARGET_SPARC64
0f8a249a
BS		 4106 if (IS_IMM)
4107 goto illegal_insn;
4108 if (!supervisor(dc))
4109 goto priv_insn;
3475187d 4110#endif
8f577d3d 4111 gen_op_check_align_T0_1();
81ad8ba2 4112 gen_ld_asi(insn, 2, 0);
0f8a249a
BS		 4113 break;
4114 case 0x13: /* load double word alternate */
3475187d 4115#ifndef TARGET_SPARC64
0f8a249a
BS		 4116 if (IS_IMM)
4117 goto illegal_insn;
4118 if (!supervisor(dc))
4119 goto priv_insn;
3475187d 4120#endif
0f8a249a 4121 if (rd & 1)
d4218d99 4122 goto illegal_insn;
6ea4a6c8 4123 gen_op_check_align_T0_7();
81ad8ba2 4124 gen_ldda_asi(insn);
0f8a249a
BS		 4125 gen_movl_T0_reg(rd + 1);
4126 break;
4127 case 0x19: /* load signed byte alternate */
3475187d 4128#ifndef TARGET_SPARC64
0f8a249a
BS		 4129 if (IS_IMM)
4130 goto illegal_insn;
4131 if (!supervisor(dc))
4132 goto priv_insn;
4133#endif
81ad8ba2 4134 gen_ld_asi(insn, 1, 1);
0f8a249a
BS		 4135 break;
4136 case 0x1a: /* load signed halfword alternate */
3475187d 4137#ifndef TARGET_SPARC64
0f8a249a
BS		 4138 if (IS_IMM)
4139 goto illegal_insn;
4140 if (!supervisor(dc))
4141 goto priv_insn;
3475187d 4142#endif
8f577d3d 4143 gen_op_check_align_T0_1();
81ad8ba2 4144 gen_ld_asi(insn, 2, 1);
0f8a249a
BS		 4145 break;
4146 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4147#ifndef TARGET_SPARC64
0f8a249a
BS		 4148 if (IS_IMM)
4149 goto illegal_insn;
4150 if (!supervisor(dc))
4151 goto priv_insn;
4152#endif
81ad8ba2 4153 gen_ldstub_asi(insn);
0f8a249a
BS		 4154 break;
4155 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 4156#ifndef TARGET_SPARC64
0f8a249a
BS		 4157 if (IS_IMM)
4158 goto illegal_insn;
4159 if (!supervisor(dc))
4160 goto priv_insn;
6ea4a6c8 4161#endif
8f577d3d 4162 gen_op_check_align_T0_3();
81ad8ba2
BS		 4163 gen_movl_reg_T1(rd);
4164 gen_swap_asi(insn);
0f8a249a 4165 break;
3475187d
FB		 4166
4167#ifndef TARGET_SPARC64
0f8a249a
BS		 4168 case 0x30: /* ldc */
4169 case 0x31: /* ldcsr */
4170 case 0x33: /* lddc */
4171 goto ncp_insn;
3475187d
FB		 4172#endif
4173#endif
4174#ifdef TARGET_SPARC64
0f8a249a 4175 case 0x08: /* V9 ldsw */
6ea4a6c8 4176 gen_op_check_align_T0_3();
1a2fb1c0
BS		 4177 ABI32_MASK(cpu_T[0]);
4178 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4179 break;
4180 case 0x0b: /* V9 ldx */
6ea4a6c8 4181 gen_op_check_align_T0_7();
1a2fb1c0
BS		 4182 ABI32_MASK(cpu_T[0]);
4183 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4184 break;
4185 case 0x18: /* V9 ldswa */
6ea4a6c8 4186 gen_op_check_align_T0_3();
81ad8ba2 4187 gen_ld_asi(insn, 4, 1);
0f8a249a
BS		 4188 break;
4189 case 0x1b: /* V9 ldxa */
6ea4a6c8 4190 gen_op_check_align_T0_7();
81ad8ba2 4191 gen_ld_asi(insn, 8, 0);
0f8a249a
BS		 4192 break;
4193 case 0x2d: /* V9 prefetch, no effect */
4194 goto skip_move;
4195 case 0x30: /* V9 ldfa */
6ea4a6c8 4196 gen_op_check_align_T0_3();
2382dc6b 4197 gen_ldf_asi(insn, 4, rd);
81ad8ba2 4198 goto skip_move;
0f8a249a 4199 case 0x33: /* V9 lddfa */
3391c818 4200 gen_op_check_align_T0_3();
2382dc6b 4201 gen_ldf_asi(insn, 8, DFPREG(rd));
81ad8ba2 4202 goto skip_move;
0f8a249a
BS		 4203 case 0x3d: /* V9 prefetcha, no effect */
4204 goto skip_move;
4205 case 0x32: /* V9 ldqfa */
1f587329
BS		 4206#if defined(CONFIG_USER_ONLY)
4207 gen_op_check_align_T0_3();
2382dc6b 4208 gen_ldf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 4209 goto skip_move;
4210#else
0f8a249a 4211 goto nfpu_insn;
1f587329 4212#endif
0f8a249a
BS		 4213#endif
4214 default:
4215 goto illegal_insn;
4216 }
4217 gen_movl_T1_reg(rd);
3475187d 4218#ifdef TARGET_SPARC64
0f8a249a 4219 skip_move: ;
3475187d 4220#endif
0f8a249a 4221 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 4222 if (gen_trap_ifnofpu(dc))
4223 goto jmp_insn;
0f8a249a
BS		 4224 switch (xop) {
4225 case 0x20: /* load fpreg */
6ea4a6c8 4226 gen_op_check_align_T0_3();
0f8a249a
BS		 4227 gen_op_ldst(ldf);
4228 gen_op_store_FT0_fpr(rd);
4229 break;
4230 case 0x21: /* load fsr */
6ea4a6c8 4231 gen_op_check_align_T0_3();
0f8a249a
BS		 4232 gen_op_ldst(ldf);
4233 gen_op_ldfsr();
7e8c2b6c 4234 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 4235 break;
4236 case 0x22: /* load quad fpreg */
1f587329
BS		 4237#if defined(CONFIG_USER_ONLY)
4238 gen_op_check_align_T0_7();
4239 gen_op_ldst(ldqf);
4240 gen_op_store_QT0_fpr(QFPREG(rd));
4241 break;
4242#else
0f8a249a 4243 goto nfpu_insn;
1f587329 4244#endif
0f8a249a 4245 case 0x23: /* load double fpreg */
6ea4a6c8 4246 gen_op_check_align_T0_7();
0f8a249a
BS		 4247 gen_op_ldst(lddf);
4248 gen_op_store_DT0_fpr(DFPREG(rd));
4249 break;
4250 default:
4251 goto illegal_insn;
4252 }
4253 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4254 xop == 0xe || xop == 0x1e) {
4255 gen_movl_reg_T1(rd);
4256 switch (xop) {
1a2fb1c0 4257 case 0x4: /* store word */
6ea4a6c8 4258 gen_op_check_align_T0_3();
1a2fb1c0
BS		 4259 ABI32_MASK(cpu_T[0]);
4260 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4261 break;
1a2fb1c0
BS		 4262 case 0x5: /* store byte */
4263 ABI32_MASK(cpu_T[0]);
4264 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4265 break;
1a2fb1c0 4266 case 0x6: /* store halfword */
6ea4a6c8 4267 gen_op_check_align_T0_1();
1a2fb1c0
BS		 4268 ABI32_MASK(cpu_T[0]);
4269 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 4270 break;
1a2fb1c0 4271 case 0x7: /* store double word */
0f8a249a 4272 if (rd & 1)
d4218d99 4273 goto illegal_insn;
b25deda7 4274#ifndef __i386__
1a2fb1c0
BS		 4275 else {
4276 TCGv r_dword, r_low;
4277
4278 gen_op_check_align_T0_7();
4279 r_dword = tcg_temp_new(TCG_TYPE_I64);
4280 r_low = tcg_temp_new(TCG_TYPE_I32);
4281 gen_movl_reg_TN(rd + 1, r_low);
4282 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4283 r_low);
4284 tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
4285 }
b25deda7
BS		 4286#else /* __i386__ */
4287 gen_op_check_align_T0_7();
4288 flush_T2(dc);
4289 gen_movl_reg_T2(rd + 1);
4290 gen_op_ldst(std);
4291#endif /* __i386__ */
0f8a249a 4292 break;
3475187d 4293#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 4294 case 0x14: /* store word alternate */
3475187d 4295#ifndef TARGET_SPARC64
0f8a249a
BS		 4296 if (IS_IMM)
4297 goto illegal_insn;
4298 if (!supervisor(dc))
4299 goto priv_insn;
6ea4a6c8 4300#endif
6ea4a6c8 4301 gen_op_check_align_T0_3();
81ad8ba2 4302 gen_st_asi(insn, 4);
d39c0b99 4303 break;
1a2fb1c0 4304 case 0x15: /* store byte alternate */
3475187d 4305#ifndef TARGET_SPARC64
0f8a249a
BS		 4306 if (IS_IMM)
4307 goto illegal_insn;
4308 if (!supervisor(dc))
4309 goto priv_insn;
3475187d 4310#endif
81ad8ba2 4311 gen_st_asi(insn, 1);
d39c0b99 4312 break;
1a2fb1c0 4313 case 0x16: /* store halfword alternate */
3475187d 4314#ifndef TARGET_SPARC64
0f8a249a
BS		 4315 if (IS_IMM)
4316 goto illegal_insn;
4317 if (!supervisor(dc))
4318 goto priv_insn;
6ea4a6c8 4319#endif
6ea4a6c8 4320 gen_op_check_align_T0_1();
81ad8ba2 4321 gen_st_asi(insn, 2);
d39c0b99 4322 break;
1a2fb1c0 4323 case 0x17: /* store double word alternate */
3475187d 4324#ifndef TARGET_SPARC64
0f8a249a
BS		 4325 if (IS_IMM)
4326 goto illegal_insn;
4327 if (!supervisor(dc))
4328 goto priv_insn;
3475187d 4329#endif
0f8a249a 4330 if (rd & 1)
d4218d99 4331 goto illegal_insn;
1a2fb1c0
BS		 4332 else {
4333 int asi;
4334 TCGv r_dword, r_temp, r_size;
4335
4336 gen_op_check_align_T0_7();
4337 r_dword = tcg_temp_new(TCG_TYPE_I64);
4338 r_temp = tcg_temp_new(TCG_TYPE_I32);
4339 r_size = tcg_temp_new(TCG_TYPE_I32);
4340 gen_movl_reg_TN(rd + 1, r_temp);
4341 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
4342 r_temp);
4343#ifdef TARGET_SPARC64
4344 if (IS_IMM) {
4345 int offset;
4346
4347 offset = GET_FIELD(insn, 25, 31);
4348 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
4349 tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
4350 } else {
4351#endif
4352 asi = GET_FIELD(insn, 19, 26);
4353 tcg_gen_movi_i32(r_temp, asi);
4354#ifdef TARGET_SPARC64
4355 }
4356#endif
4357 tcg_gen_movi_i32(r_size, 8);
4358 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
4359 }
d39c0b99 4360 break;
e80cfcfc 4361#endif
3475187d 4362#ifdef TARGET_SPARC64
0f8a249a 4363 case 0x0e: /* V9 stx */
6ea4a6c8 4364 gen_op_check_align_T0_7();
1a2fb1c0
BS		 4365 ABI32_MASK(cpu_T[0]);
4366 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 4367 break;
4368 case 0x1e: /* V9 stxa */
6ea4a6c8 4369 gen_op_check_align_T0_7();
81ad8ba2 4370 gen_st_asi(insn, 8);
0f8a249a 4371 break;
3475187d 4372#endif
0f8a249a
BS		 4373 default:
4374 goto illegal_insn;
4375 }
4376 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 4377 if (gen_trap_ifnofpu(dc))
4378 goto jmp_insn;
0f8a249a
BS		 4379 switch (xop) {
4380 case 0x24:
6ea4a6c8 4381 gen_op_check_align_T0_3();
e8af50a3 4382 gen_op_load_fpr_FT0(rd);
0f8a249a
BS		 4383 gen_op_ldst(stf);
4384 break;
4385 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 4386#ifdef CONFIG_USER_ONLY
4387 gen_op_check_align_T0_3();
4388#endif
0f8a249a
BS		 4389 gen_op_stfsr();
4390 gen_op_ldst(stf);
4391 break;
1f587329
BS		 4392 case 0x26:
4393#ifdef TARGET_SPARC64
4394#if defined(CONFIG_USER_ONLY)
4395 /* V9 stqf, store quad fpreg */
4396 gen_op_check_align_T0_7();
4397 gen_op_load_fpr_QT0(QFPREG(rd));
4398 gen_op_ldst(stqf);
4399 break;
4400#else
4401 goto nfpu_insn;
4402#endif
4403#else /* !TARGET_SPARC64 */
4404 /* stdfq, store floating point queue */
4405#if defined(CONFIG_USER_ONLY)
4406 goto illegal_insn;
4407#else
0f8a249a
BS		 4408 if (!supervisor(dc))
4409 goto priv_insn;
4410 if (gen_trap_ifnofpu(dc))
4411 goto jmp_insn;
4412 goto nfq_insn;
1f587329 4413#endif
0f8a249a
BS		 4414#endif
4415 case 0x27:
6ea4a6c8 4416 gen_op_check_align_T0_7();
3475187d 4417 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 4418 gen_op_ldst(stdf);
4419 break;
4420 default:
4421 goto illegal_insn;
4422 }
4423 } else if (xop > 0x33 && xop < 0x3f) {
4424 switch (xop) {
a4d17f19 4425#ifdef TARGET_SPARC64
0f8a249a 4426 case 0x34: /* V9 stfa */
6ea4a6c8 4427 gen_op_check_align_T0_3();
3391c818 4428 gen_op_load_fpr_FT0(rd);
2382dc6b 4429 gen_stf_asi(insn, 4, rd);
0f8a249a 4430 break;
1f587329
BS		 4431 case 0x36: /* V9 stqfa */
4432#if defined(CONFIG_USER_ONLY)
4433 gen_op_check_align_T0_7();
4434 gen_op_load_fpr_QT0(QFPREG(rd));
2382dc6b 4435 gen_stf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 4436 break;
4437#else
4438 goto nfpu_insn;
4439#endif
0f8a249a 4440 case 0x37: /* V9 stdfa */
3391c818
BS		 4441 gen_op_check_align_T0_3();
4442 gen_op_load_fpr_DT0(DFPREG(rd));
2382dc6b 4443 gen_stf_asi(insn, 8, DFPREG(rd));
0f8a249a
BS		 4444 break;
4445 case 0x3c: /* V9 casa */
6ea4a6c8 4446 gen_op_check_align_T0_3();
1a2fb1c0 4447 gen_cas_asi(insn, rd);
81ad8ba2 4448 gen_movl_T1_reg(rd);
0f8a249a
BS		 4449 break;
4450 case 0x3e: /* V9 casxa */
6ea4a6c8 4451 gen_op_check_align_T0_7();
1a2fb1c0 4452 gen_casx_asi(insn, rd);
81ad8ba2 4453 gen_movl_T1_reg(rd);
0f8a249a 4454 break;
a4d17f19 4455#else
0f8a249a
BS		 4456 case 0x34: /* stc */
4457 case 0x35: /* stcsr */
4458 case 0x36: /* stdcq */
4459 case 0x37: /* stdc */
4460 goto ncp_insn;
4461#endif
4462 default:
4463 goto illegal_insn;
4464 }
e8af50a3 4465 }
0f8a249a
BS		 4466 else
4467 goto illegal_insn;
4468 }
4469 break;
cf495bcf
FB		 4470 }
4471 /* default case for non jump instructions */
72cbca10 4472 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 4473 dc->pc = DYNAMIC_PC;
4474 gen_op_next_insn();
72cbca10
FB		 4475 } else if (dc->npc == JUMP_PC) {
4476 /* we can do a static jump */
19f329ad 4477 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
72cbca10
FB		 4478 dc->is_br = 1;
4479 } else {
0f8a249a
BS		 4480 dc->pc = dc->npc;
4481 dc->npc = dc->npc + 4;
cf495bcf 4482 }
e80cfcfc 4483 jmp_insn:
cf495bcf
FB		 4484 return;
4485 illegal_insn:
72cbca10 4486 save_state(dc);
cf495bcf
FB		 4487 gen_op_exception(TT_ILL_INSN);
4488 dc->is_br = 1;
e8af50a3 4489 return;
e80cfcfc 4490#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 4491 priv_insn:
4492 save_state(dc);
4493 gen_op_exception(TT_PRIV_INSN);
4494 dc->is_br = 1;
e80cfcfc 4495 return;
e80cfcfc
FB		 4496 nfpu_insn:
4497 save_state(dc);
4498 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4499 dc->is_br = 1;
fcc72045 4500 return;
1f587329 4501#ifndef TARGET_SPARC64
9143e598
BS		 4502 nfq_insn:
4503 save_state(dc);
4504 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4505 dc->is_br = 1;
4506 return;
4507#endif
1f587329 4508#endif
fcc72045
BS		 4509#ifndef TARGET_SPARC64
4510 ncp_insn:
4511 save_state(dc);
4512 gen_op_exception(TT_NCP_INSN);
4513 dc->is_br = 1;
4514 return;
4515#endif
7a3f1944
FB		 4516}
4517
1a2fb1c0
BS		 4518static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4519{
4520}
4521
cf495bcf 4522static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 4523 int spc, CPUSPARCState *env)
7a3f1944 4524{
72cbca10 4525 target_ulong pc_start, last_pc;
cf495bcf
FB		 4526 uint16_t *gen_opc_end;
4527 DisasContext dc1, *dc = &dc1;
e8af50a3 4528 int j, lj = -1;
cf495bcf
FB		 4529
4530 memset(dc, 0, sizeof(DisasContext));
cf495bcf 4531 dc->tb = tb;
72cbca10 4532 pc_start = tb->pc;
cf495bcf 4533 dc->pc = pc_start;
e80cfcfc 4534 last_pc = dc->pc;
72cbca10 4535 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 4536 dc->mem_idx = cpu_mmu_index(env);
4537 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 4538 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 4539
1a2fb1c0 4540 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
1a2fb1c0 4541
cf495bcf 4542 do {
e8af50a3
FB		 4543 if (env->nb_breakpoints > 0) {
4544 for(j = 0; j < env->nb_breakpoints; j++) {
4545 if (env->breakpoints[j] == dc->pc) {
0f8a249a
BS		 4546 if (dc->pc != pc_start)
4547 save_state(dc);
1a2fb1c0 4548 tcg_gen_helper_0_0(helper_debug);
57fec1fe 4549 tcg_gen_exit_tb(0);
0f8a249a 4550 dc->is_br = 1;
e80cfcfc 4551 goto exit_gen_loop;
e8af50a3
FB		 4552 }
4553 }
4554 }
4555 if (spc) {
4556 if (loglevel > 0)
4557 fprintf(logfile, "Search PC...\n");
4558 j = gen_opc_ptr - gen_opc_buf;
4559 if (lj < j) {
4560 lj++;
4561 while (lj < j)
4562 gen_opc_instr_start[lj++] = 0;
4563 gen_opc_pc[lj] = dc->pc;
4564 gen_opc_npc[lj] = dc->npc;
4565 gen_opc_instr_start[lj] = 1;
4566 }
4567 }
0f8a249a
BS		 4568 last_pc = dc->pc;
4569 disas_sparc_insn(dc);
4570
4571 if (dc->is_br)
4572 break;
4573 /* if the next PC is different, we abort now */
4574 if (dc->pc != (last_pc + 4))
4575 break;
d39c0b99
FB		 4576 /* if we reach a page boundary, we stop generation so that the
4577 PC of a TT_TFAULT exception is always in the right page */
4578 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4579 break;
e80cfcfc
FB		 4580 /* if single step mode, we generate only one instruction and
4581 generate an exception */
4582 if (env->singlestep_enabled) {
3475187d 4583 gen_jmp_im(dc->pc);
57fec1fe 4584 tcg_gen_exit_tb(0);
e80cfcfc
FB		 4585 break;
4586 }
cf495bcf 4587 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 4588 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 4589
4590 exit_gen_loop:
72cbca10 4591 if (!dc->is_br) {
5fafdf24 4592 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 4593 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4594 /* static PC and NPC: we can use direct chaining */
46525e1f 4595 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 4596 } else {
4597 if (dc->pc != DYNAMIC_PC)
3475187d 4598 gen_jmp_im(dc->pc);
72cbca10 4599 save_npc(dc);
57fec1fe 4600 tcg_gen_exit_tb(0);
72cbca10
FB		 4601 }
4602 }
cf495bcf 4603 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 4604 if (spc) {
4605 j = gen_opc_ptr - gen_opc_buf;
4606 lj++;
4607 while (lj <= j)
4608 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 4609#if 0
4610 if (loglevel > 0) {
4611 page_dump(logfile);
4612 }
4613#endif
c3278b7b
FB		 4614 gen_opc_jump_pc[0] = dc->jump_pc[0];
4615 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 4616 } else {
e80cfcfc 4617 tb->size = last_pc + 4 - pc_start;
e8af50a3 4618 }
7a3f1944 4619#ifdef DEBUG_DISAS
e19e89a5 4620 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 4621 fprintf(logfile, "--------------\n");
4622 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4623 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4624 fprintf(logfile, "\n");
cf495bcf 4625 }
7a3f1944 4626#endif
cf495bcf 4627 return 0;
7a3f1944
FB		 4628}
4629
cf495bcf 4630int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4631{
e8af50a3 4632 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 4633}
4634
cf495bcf 4635int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 4636{
e8af50a3 4637 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 4638}
4639
e80cfcfc
FB		 4640void cpu_reset(CPUSPARCState *env)
4641{
bb05683b 4642 tlb_flush(env, 1);
cf495bcf
FB		 4643 env->cwp = 0;
4644 env->wim = 1;
4645 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 4646#if defined(CONFIG_USER_ONLY)
cf495bcf 4647 env->user_mode_only = 1;
5ef54116 4648#ifdef TARGET_SPARC64
6ef905f6
BS		 4649 env->cleanwin = NWINDOWS - 2;
4650 env->cansave = NWINDOWS - 2;
4651 env->pstate = PS_RMO | PS_PEF | PS_IE;
4652 env->asi = 0x82; // Primary no-fault
5ef54116 4653#endif
e8af50a3 4654#else
32af58f9 4655 env->psret = 0;
e8af50a3 4656 env->psrs = 1;
0bee699e 4657 env->psrps = 1;
3475187d 4658#ifdef TARGET_SPARC64
83469015 4659 env->pstate = PS_PRIV;
6f27aba6 4660 env->hpstate = HS_PRIV;
83469015 4661 env->pc = 0x1fff0000000ULL;
375ee38b 4662 env->tsptr = &env->ts[env->tl];
3475187d 4663#else
40ce0a9a 4664 env->pc = 0;
32af58f9 4665 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
6d5f237a 4666 env->mmuregs[0] |= env->mmu_bm;
3475187d 4667#endif
83469015 4668 env->npc = env->pc + 4;
e8af50a3 4669#endif
e80cfcfc
FB		 4670}
4671
aaed909a 4672CPUSPARCState *cpu_sparc_init(const char *cpu_model)
e80cfcfc
FB		 4673{
4674 CPUSPARCState *env;
aaed909a 4675 const sparc_def_t *def;
1a2fb1c0 4676 static int inited;
f5069b26
BS		 4677 unsigned int i;
4678 static const char * const gregnames[8] = {
4679 NULL, // g0 not used
4680 "g1",
4681 "g2",
4682 "g3",
4683 "g4",
4684 "g5",
4685 "g6",
4686 "g7",
4687 };
aaed909a
FB		 4688
4689 def = cpu_sparc_find_by_name(cpu_model);
4690 if (!def)
4691 return NULL;
e80cfcfc 4692
c68ea704
FB		 4693 env = qemu_mallocz(sizeof(CPUSPARCState));
4694 if (!env)
0f8a249a 4695 return NULL;
c68ea704 4696 cpu_exec_init(env);
01ba9816 4697 env->cpu_model_str = cpu_model;
aaed909a
FB		 4698 env->version = def->iu_version;
4699 env->fsr = def->fpu_version;
4700#if !defined(TARGET_SPARC64)
4701 env->mmu_bm = def->mmu_bm;
3deaeab7
BS		 4702 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4703 env->mmu_cxr_mask = def->mmu_cxr_mask;
4704 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4705 env->mmu_trcr_mask = def->mmu_trcr_mask;
aaed909a
FB		 4706 env->mmuregs[0] |= def->mmu_version;
4707 cpu_sparc_set_id(env, 0);
4708#endif
1a2fb1c0
BS		 4709
4710 /* init various static tables */
4711 if (!inited) {
4712 inited = 1;
4713
4714 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4715 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
db4a4ea4
BS		 4716 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4717 offsetof(CPUState, regwptr),
4718 "regwptr");
1a2fb1c0
BS		 4719 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4720#ifdef TARGET_SPARC64
4721 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4722 TCG_AREG0, offsetof(CPUState, t0), "T0");
4723 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4724 TCG_AREG0, offsetof(CPUState, t1), "T1");
4725 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4726 TCG_AREG0, offsetof(CPUState, t2), "T2");
dc99a3f2
BS		 4727 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4728 TCG_AREG0, offsetof(CPUState, xcc),
4729 "xcc");
1a2fb1c0
BS		 4730#else
4731 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4732 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4733 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4734#endif
dc99a3f2
BS		 4735 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4736 TCG_AREG0, offsetof(CPUState, cc_src),
4737 "cc_src");
4738 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4739 TCG_AREG0, offsetof(CPUState, cc_dst),
4740 "cc_dst");
4741 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4742 TCG_AREG0, offsetof(CPUState, psr),
4743 "psr");
f5069b26
BS		 4744 for (i = 1; i < 8; i++)
4745 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4746 offsetof(CPUState, gregs[i]),
4747 gregnames[i]);
1a2fb1c0
BS		 4748 }
4749
aaed909a
FB		 4750 cpu_reset(env);
4751
4752 return env;
4753}
4754
4755void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4756{
4757#if !defined(TARGET_SPARC64)
4758 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4759#endif
7a3f1944
FB		 4760}
4761
62724a37
BS		 4762static const sparc_def_t sparc_defs[] = {
4763#ifdef TARGET_SPARC64
7d77bf20
BS		 4764 {
4765 .name = "Fujitsu Sparc64",
4766 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4767 | (MAXTL << 8) | (NWINDOWS - 1)),
4768 .fpu_version = 0x00000000,
4769 .mmu_version = 0,
4770 },
4771 {
4772 .name = "Fujitsu Sparc64 III",
4773 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4774 | (MAXTL << 8) | (NWINDOWS - 1)),
4775 .fpu_version = 0x00000000,
4776 .mmu_version = 0,
4777 },
4778 {
4779 .name = "Fujitsu Sparc64 IV",
4780 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4781 | (MAXTL << 8) | (NWINDOWS - 1)),
4782 .fpu_version = 0x00000000,
4783 .mmu_version = 0,
4784 },
4785 {
4786 .name = "Fujitsu Sparc64 V",
4787 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4788 | (MAXTL << 8) | (NWINDOWS - 1)),
4789 .fpu_version = 0x00000000,
4790 .mmu_version = 0,
4791 },
4792 {
4793 .name = "TI UltraSparc I",
4794 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4795 | (MAXTL << 8) | (NWINDOWS - 1)),
4796 .fpu_version = 0x00000000,
4797 .mmu_version = 0,
4798 },
62724a37
BS		 4799 {
4800 .name = "TI UltraSparc II",
7d77bf20
BS		 4801 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4802 | (MAXTL << 8) | (NWINDOWS - 1)),
4803 .fpu_version = 0x00000000,
4804 .mmu_version = 0,
4805 },
4806 {
4807 .name = "TI UltraSparc IIi",
4808 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4809 | (MAXTL << 8) | (NWINDOWS - 1)),
4810 .fpu_version = 0x00000000,
4811 .mmu_version = 0,
4812 },
4813 {
4814 .name = "TI UltraSparc IIe",
4815 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4816 | (MAXTL << 8) | (NWINDOWS - 1)),
4817 .fpu_version = 0x00000000,
4818 .mmu_version = 0,
4819 },
4820 {
4821 .name = "Sun UltraSparc III",
4822 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4823 | (MAXTL << 8) | (NWINDOWS - 1)),
4824 .fpu_version = 0x00000000,
4825 .mmu_version = 0,
4826 },
4827 {
4828 .name = "Sun UltraSparc III Cu",
4829 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4830 | (MAXTL << 8) | (NWINDOWS - 1)),
4831 .fpu_version = 0x00000000,
4832 .mmu_version = 0,
4833 },
4834 {
4835 .name = "Sun UltraSparc IIIi",
4836 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4837 | (MAXTL << 8) | (NWINDOWS - 1)),
4838 .fpu_version = 0x00000000,
4839 .mmu_version = 0,
4840 },
4841 {
4842 .name = "Sun UltraSparc IV",
4843 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4844 | (MAXTL << 8) | (NWINDOWS - 1)),
4845 .fpu_version = 0x00000000,
4846 .mmu_version = 0,
4847 },
4848 {
4849 .name = "Sun UltraSparc IV+",
4850 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4851 | (MAXTL << 8) | (NWINDOWS - 1)),
4852 .fpu_version = 0x00000000,
4853 .mmu_version = 0,
4854 },
4855 {
4856 .name = "Sun UltraSparc IIIi+",
4857 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4858 | (MAXTL << 8) | (NWINDOWS - 1)),
4859 .fpu_version = 0x00000000,
4860 .mmu_version = 0,
4861 },
4862 {
4863 .name = "NEC UltraSparc I",
4864 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
62724a37
BS		 4865 | (MAXTL << 8) | (NWINDOWS - 1)),
4866 .fpu_version = 0x00000000,
4867 .mmu_version = 0,
4868 },
4869#else
406f82e8
BS		 4870 {
4871 .name = "Fujitsu MB86900",
4872 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4873 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4874 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4875 .mmu_bm = 0x00004000,
3deaeab7
BS		 4876 .mmu_ctpr_mask = 0x007ffff0,
4877 .mmu_cxr_mask = 0x0000003f,
4878 .mmu_sfsr_mask = 0xffffffff,
4879 .mmu_trcr_mask = 0xffffffff,
406f82e8 4880 },
62724a37
BS		 4881 {
4882 .name = "Fujitsu MB86904",
4883 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4884 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4885 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
6d5f237a 4886 .mmu_bm = 0x00004000,
3deaeab7
BS		 4887 .mmu_ctpr_mask = 0x00ffffc0,
4888 .mmu_cxr_mask = 0x000000ff,
4889 .mmu_sfsr_mask = 0x00016fff,
4890 .mmu_trcr_mask = 0x00ffffff,
62724a37 4891 },
e0353fe2 4892 {
5ef62c5c
BS		 4893 .name = "Fujitsu MB86907",
4894 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4895 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4896 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
6d5f237a 4897 .mmu_bm = 0x00004000,
3deaeab7
BS		 4898 .mmu_ctpr_mask = 0xffffffc0,
4899 .mmu_cxr_mask = 0x000000ff,
4900 .mmu_sfsr_mask = 0x00016fff,
4901 .mmu_trcr_mask = 0xffffffff,
5ef62c5c 4902 },
406f82e8
BS		 4903 {
4904 .name = "LSI L64811",
4905 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4906 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4907 .mmu_version = 0x10 << 24,
4908 .mmu_bm = 0x00004000,
3deaeab7
BS		 4909 .mmu_ctpr_mask = 0x007ffff0,
4910 .mmu_cxr_mask = 0x0000003f,
4911 .mmu_sfsr_mask = 0xffffffff,
4912 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4913 },
4914 {
4915 .name = "Cypress CY7C601",
4916 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4917 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4918 .mmu_version = 0x10 << 24,
4919 .mmu_bm = 0x00004000,
3deaeab7
BS		 4920 .mmu_ctpr_mask = 0x007ffff0,
4921 .mmu_cxr_mask = 0x0000003f,
4922 .mmu_sfsr_mask = 0xffffffff,
4923 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4924 },
4925 {
4926 .name = "Cypress CY7C611",
4927 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4928 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4929 .mmu_version = 0x10 << 24,
4930 .mmu_bm = 0x00004000,
3deaeab7
BS		 4931 .mmu_ctpr_mask = 0x007ffff0,
4932 .mmu_cxr_mask = 0x0000003f,
4933 .mmu_sfsr_mask = 0xffffffff,
4934 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4935 },
4936 {
4937 .name = "TI SuperSparc II",
4938 .iu_version = 0x40000000,
4939 .fpu_version = 0 << 17,
4940 .mmu_version = 0x04000000,
4941 .mmu_bm = 0x00002000,
3deaeab7
BS		 4942 .mmu_ctpr_mask = 0xffffffc0,
4943 .mmu_cxr_mask = 0x0000ffff,
4944 .mmu_sfsr_mask = 0xffffffff,
4945 .mmu_trcr_mask = 0xffffffff,
406f82e8 4946 },
5ef62c5c
BS		 4947 {
4948 .name = "TI MicroSparc I",
4949 .iu_version = 0x41000000,
4950 .fpu_version = 4 << 17,
4951 .mmu_version = 0x41000000,
6d5f237a 4952 .mmu_bm = 0x00004000,
3deaeab7
BS		 4953 .mmu_ctpr_mask = 0x007ffff0,
4954 .mmu_cxr_mask = 0x0000003f,
4955 .mmu_sfsr_mask = 0x00016fff,
4956 .mmu_trcr_mask = 0x0000003f,
5ef62c5c
BS		 4957 },
4958 {
406f82e8
BS		 4959 .name = "TI MicroSparc II",
4960 .iu_version = 0x42000000,
4961 .fpu_version = 4 << 17,
4962 .mmu_version = 0x02000000,
4963 .mmu_bm = 0x00004000,
3deaeab7
BS		 4964 .mmu_ctpr_mask = 0x00ffffc0,
4965 .mmu_cxr_mask = 0x000000ff,
a3ffaf30 4966 .mmu_sfsr_mask = 0x00016fff,
3deaeab7 4967 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4968 },
4969 {
4970 .name = "TI MicroSparc IIep",
4971 .iu_version = 0x42000000,
4972 .fpu_version = 4 << 17,
4973 .mmu_version = 0x04000000,
4974 .mmu_bm = 0x00004000,
3deaeab7
BS		 4975 .mmu_ctpr_mask = 0x00ffffc0,
4976 .mmu_cxr_mask = 0x000000ff,
4977 .mmu_sfsr_mask = 0x00016bff,
4978 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4979 },
4980 {
4981 .name = "TI SuperSparc 51",
4982 .iu_version = 0x43000000,
5ef62c5c
BS		 4983 .fpu_version = 0 << 17,
4984 .mmu_version = 0x04000000,
6d5f237a 4985 .mmu_bm = 0x00002000,
3deaeab7
BS		 4986 .mmu_ctpr_mask = 0xffffffc0,
4987 .mmu_cxr_mask = 0x0000ffff,
4988 .mmu_sfsr_mask = 0xffffffff,
4989 .mmu_trcr_mask = 0xffffffff,
5ef62c5c
BS		 4990 },
4991 {
406f82e8
BS		 4992 .name = "TI SuperSparc 61",
4993 .iu_version = 0x44000000,
4994 .fpu_version = 0 << 17,
4995 .mmu_version = 0x04000000,
4996 .mmu_bm = 0x00002000,
3deaeab7
BS		 4997 .mmu_ctpr_mask = 0xffffffc0,
4998 .mmu_cxr_mask = 0x0000ffff,
4999 .mmu_sfsr_mask = 0xffffffff,
5000 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5001 },
5002 {
5003 .name = "Ross RT625",
5ef62c5c
BS		 5004 .iu_version = 0x1e000000,
5005 .fpu_version = 1 << 17,
406f82e8
BS		 5006 .mmu_version = 0x1e000000,
5007 .mmu_bm = 0x00004000,
3deaeab7
BS		 5008 .mmu_ctpr_mask = 0x007ffff0,
5009 .mmu_cxr_mask = 0x0000003f,
5010 .mmu_sfsr_mask = 0xffffffff,
5011 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5012 },
5013 {
5014 .name = "Ross RT620",
5015 .iu_version = 0x1f000000,
5016 .fpu_version = 1 << 17,
5017 .mmu_version = 0x1f000000,
5018 .mmu_bm = 0x00004000,
3deaeab7
BS		 5019 .mmu_ctpr_mask = 0x007ffff0,
5020 .mmu_cxr_mask = 0x0000003f,
5021 .mmu_sfsr_mask = 0xffffffff,
5022 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5023 },
5024 {
5025 .name = "BIT B5010",
5026 .iu_version = 0x20000000,
5027 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
5028 .mmu_version = 0x20000000,
5029 .mmu_bm = 0x00004000,
3deaeab7
BS		 5030 .mmu_ctpr_mask = 0x007ffff0,
5031 .mmu_cxr_mask = 0x0000003f,
5032 .mmu_sfsr_mask = 0xffffffff,
5033 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5034 },
5035 {
5036 .name = "Matsushita MN10501",
5037 .iu_version = 0x50000000,
5038 .fpu_version = 0 << 17,
5039 .mmu_version = 0x50000000,
5040 .mmu_bm = 0x00004000,
3deaeab7
BS		 5041 .mmu_ctpr_mask = 0x007ffff0,
5042 .mmu_cxr_mask = 0x0000003f,
5043 .mmu_sfsr_mask = 0xffffffff,
5044 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5045 },
5046 {
5047 .name = "Weitek W8601",
5048 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
5049 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
5050 .mmu_version = 0x10 << 24,
5051 .mmu_bm = 0x00004000,
3deaeab7
BS		 5052 .mmu_ctpr_mask = 0x007ffff0,
5053 .mmu_cxr_mask = 0x0000003f,
5054 .mmu_sfsr_mask = 0xffffffff,
5055 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5056 },
5057 {
5058 .name = "LEON2",
5059 .iu_version = 0xf2000000,
5060 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5061 .mmu_version = 0xf2000000,
5062 .mmu_bm = 0x00004000,
3deaeab7
BS		 5063 .mmu_ctpr_mask = 0x007ffff0,
5064 .mmu_cxr_mask = 0x0000003f,
5065 .mmu_sfsr_mask = 0xffffffff,
5066 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 5067 },
5068 {
5069 .name = "LEON3",
5070 .iu_version = 0xf3000000,
5071 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
5072 .mmu_version = 0xf3000000,
6d5f237a 5073 .mmu_bm = 0x00004000,
3deaeab7
BS		 5074 .mmu_ctpr_mask = 0x007ffff0,
5075 .mmu_cxr_mask = 0x0000003f,
5076 .mmu_sfsr_mask = 0xffffffff,
5077 .mmu_trcr_mask = 0xffffffff,
e0353fe2 5078 },
62724a37
BS		 5079#endif
5080};
5081
aaed909a 5082static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
62724a37 5083{
62724a37
BS		 5084 unsigned int i;
5085
62724a37
BS		 5086 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5087 if (strcasecmp(name, sparc_defs[i].name) == 0) {
aaed909a 5088 return &sparc_defs[i];
62724a37
BS		 5089 }
5090 }
aaed909a 5091 return NULL;
62724a37
BS		 5092}
5093
5094void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5095{
5096 unsigned int i;
5097
5098 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
5099 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
5100 sparc_defs[i].name,
5101 sparc_defs[i].iu_version,
5102 sparc_defs[i].fpu_version,
5103 sparc_defs[i].mmu_version);
5104 }
5105}
5106
7a3f1944
FB		 5107#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
5108
5fafdf24 5109void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 5110 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5111 int flags)
7a3f1944 5112{
cf495bcf
FB		 5113 int i, x;
5114
af7bf89b 5115 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 5116 cpu_fprintf(f, "General Registers:\n");
cf495bcf 5117 for (i = 0; i < 4; i++)
0f8a249a 5118 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 5119 cpu_fprintf(f, "\n");
cf495bcf 5120 for (; i < 8; i++)
0f8a249a 5121 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 5122 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf 5123 for (x = 0; x < 3; x++) {
0f8a249a
BS		 5124 for (i = 0; i < 4; i++)
5125 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5126 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
5127 env->regwptr[i + x * 8]);
5128 cpu_fprintf(f, "\n");
5129 for (; i < 8; i++)
5130 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
5131 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
5132 env->regwptr[i + x * 8]);
5133 cpu_fprintf(f, "\n");
cf495bcf 5134 }
7fe48483 5135 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 5136 for (i = 0; i < 32; i++) {
5137 if ((i & 3) == 0)
7fe48483
FB		 5138 cpu_fprintf(f, "%%f%02d:", i);
5139 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 5140 if ((i & 3) == 3)
7fe48483 5141 cpu_fprintf(f, "\n");
e8af50a3 5142 }
ded3ab80 5143#ifdef TARGET_SPARC64
3299908c 5144 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
0f8a249a 5145 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80 5146 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
0f8a249a
BS		 5147 env->cansave, env->canrestore, env->otherwin, env->wstate,
5148 env->cleanwin, NWINDOWS - 1 - env->cwp);
ded3ab80 5149#else
7fe48483 5150 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
0f8a249a
BS		 5151 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
5152 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5153 env->psrs?'S':'-', env->psrps?'P':'-',
5154 env->psret?'E':'-', env->wim);
ded3ab80 5155#endif
3475187d 5156 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 5157}
edfcbd99 5158
e80cfcfc 5159#if defined(CONFIG_USER_ONLY)
9b3c35e0 5160target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 5161{
5162 return addr;
5163}
658138bc 5164
e80cfcfc 5165#else
af7bf89b
FB		 5166extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
5167 int *access_index, target_ulong address, int rw,
6ebbf390 5168 int mmu_idx);
0fa85d43 5169
9b3c35e0 5170target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 5171{
af7bf89b 5172 target_phys_addr_t phys_addr;
e80cfcfc
FB		 5173 int prot, access_index;
5174
9e31b9e2
BS		 5175 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
5176 MMU_KERNEL_IDX) != 0)
5177 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
5178 0, MMU_KERNEL_IDX) != 0)
6b1575b7 5179 return -1;
6c36d3fa
BS		 5180 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
5181 return -1;
e80cfcfc
FB		 5182 return phys_addr;
5183}
5184#endif
5185
658138bc
FB		 5186void helper_flush(target_ulong addr)
5187{
5188 addr &= ~7;
5189 tb_invalidate_page_range(addr, addr + 8);
5190}
Empty description
This page took 0.935363 seconds and 4 git commands to generate.