]> Git Repo - qemu.git/blame - target-sparc/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
do not depend on thunk.h - more log items
[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
bd497938 5 Copyright (C) 2003 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
bd497938 25 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 26 FPU-Instructions
7a3f1944 27 Privileged instructions
bd497938 28 Coprocessor-Instructions
7a3f1944
FB		 29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
72cbca10
FB		 45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
72cbca10
FB		 50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf
FB		 53 int is_br;
54 struct TranslationBlock *tb;
7a3f1944
FB		 55} DisasContext;
56
57static uint16_t *gen_opc_ptr;
58static uint32_t *gen_opparam_ptr;
59extern FILE *logfile;
60extern int loglevel;
61
62enum {
63#define DEF(s,n,copy_size) INDEX_op_ ## s,
64#include "opc.h"
65#undef DEF
cf495bcf 66 NB_OPS
7a3f1944
FB		 67};
68
69#include "gen-op.h"
70
71#define GET_FIELD(X, FROM, TO) \
72 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
73
74#define IS_IMM (insn & (1<<13))
75
cf495bcf 76static void disas_sparc_insn(DisasContext * dc);
7a3f1944 77
7a3f1944 78static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 79 {
80 gen_op_movl_g0_T0,
81 gen_op_movl_g1_T0,
82 gen_op_movl_g2_T0,
83 gen_op_movl_g3_T0,
84 gen_op_movl_g4_T0,
85 gen_op_movl_g5_T0,
86 gen_op_movl_g6_T0,
87 gen_op_movl_g7_T0,
88 gen_op_movl_o0_T0,
89 gen_op_movl_o1_T0,
90 gen_op_movl_o2_T0,
91 gen_op_movl_o3_T0,
92 gen_op_movl_o4_T0,
93 gen_op_movl_o5_T0,
94 gen_op_movl_o6_T0,
95 gen_op_movl_o7_T0,
96 gen_op_movl_l0_T0,
97 gen_op_movl_l1_T0,
98 gen_op_movl_l2_T0,
99 gen_op_movl_l3_T0,
100 gen_op_movl_l4_T0,
101 gen_op_movl_l5_T0,
102 gen_op_movl_l6_T0,
103 gen_op_movl_l7_T0,
104 gen_op_movl_i0_T0,
105 gen_op_movl_i1_T0,
106 gen_op_movl_i2_T0,
107 gen_op_movl_i3_T0,
108 gen_op_movl_i4_T0,
109 gen_op_movl_i5_T0,
110 gen_op_movl_i6_T0,
111 gen_op_movl_i7_T0,
112 },
113 {
114 gen_op_movl_g0_T1,
115 gen_op_movl_g1_T1,
116 gen_op_movl_g2_T1,
117 gen_op_movl_g3_T1,
118 gen_op_movl_g4_T1,
119 gen_op_movl_g5_T1,
120 gen_op_movl_g6_T1,
121 gen_op_movl_g7_T1,
122 gen_op_movl_o0_T1,
123 gen_op_movl_o1_T1,
124 gen_op_movl_o2_T1,
125 gen_op_movl_o3_T1,
126 gen_op_movl_o4_T1,
127 gen_op_movl_o5_T1,
128 gen_op_movl_o6_T1,
129 gen_op_movl_o7_T1,
130 gen_op_movl_l0_T1,
131 gen_op_movl_l1_T1,
132 gen_op_movl_l2_T1,
133 gen_op_movl_l3_T1,
134 gen_op_movl_l4_T1,
135 gen_op_movl_l5_T1,
136 gen_op_movl_l6_T1,
137 gen_op_movl_l7_T1,
138 gen_op_movl_i0_T1,
139 gen_op_movl_i1_T1,
140 gen_op_movl_i2_T1,
141 gen_op_movl_i3_T1,
142 gen_op_movl_i4_T1,
143 gen_op_movl_i5_T1,
144 gen_op_movl_i6_T1,
145 gen_op_movl_i7_T1,
146 }
7a3f1944
FB		 147};
148
149static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 150 {
151 gen_op_movl_T0_g0,
152 gen_op_movl_T0_g1,
153 gen_op_movl_T0_g2,
154 gen_op_movl_T0_g3,
155 gen_op_movl_T0_g4,
156 gen_op_movl_T0_g5,
157 gen_op_movl_T0_g6,
158 gen_op_movl_T0_g7,
159 gen_op_movl_T0_o0,
160 gen_op_movl_T0_o1,
161 gen_op_movl_T0_o2,
162 gen_op_movl_T0_o3,
163 gen_op_movl_T0_o4,
164 gen_op_movl_T0_o5,
165 gen_op_movl_T0_o6,
166 gen_op_movl_T0_o7,
167 gen_op_movl_T0_l0,
168 gen_op_movl_T0_l1,
169 gen_op_movl_T0_l2,
170 gen_op_movl_T0_l3,
171 gen_op_movl_T0_l4,
172 gen_op_movl_T0_l5,
173 gen_op_movl_T0_l6,
174 gen_op_movl_T0_l7,
175 gen_op_movl_T0_i0,
176 gen_op_movl_T0_i1,
177 gen_op_movl_T0_i2,
178 gen_op_movl_T0_i3,
179 gen_op_movl_T0_i4,
180 gen_op_movl_T0_i5,
181 gen_op_movl_T0_i6,
182 gen_op_movl_T0_i7,
183 },
184 {
185 gen_op_movl_T1_g0,
186 gen_op_movl_T1_g1,
187 gen_op_movl_T1_g2,
188 gen_op_movl_T1_g3,
189 gen_op_movl_T1_g4,
190 gen_op_movl_T1_g5,
191 gen_op_movl_T1_g6,
192 gen_op_movl_T1_g7,
193 gen_op_movl_T1_o0,
194 gen_op_movl_T1_o1,
195 gen_op_movl_T1_o2,
196 gen_op_movl_T1_o3,
197 gen_op_movl_T1_o4,
198 gen_op_movl_T1_o5,
199 gen_op_movl_T1_o6,
200 gen_op_movl_T1_o7,
201 gen_op_movl_T1_l0,
202 gen_op_movl_T1_l1,
203 gen_op_movl_T1_l2,
204 gen_op_movl_T1_l3,
205 gen_op_movl_T1_l4,
206 gen_op_movl_T1_l5,
207 gen_op_movl_T1_l6,
208 gen_op_movl_T1_l7,
209 gen_op_movl_T1_i0,
210 gen_op_movl_T1_i1,
211 gen_op_movl_T1_i2,
212 gen_op_movl_T1_i3,
213 gen_op_movl_T1_i4,
214 gen_op_movl_T1_i5,
215 gen_op_movl_T1_i6,
216 gen_op_movl_T1_i7,
217 },
218 {
219 gen_op_movl_T2_g0,
220 gen_op_movl_T2_g1,
221 gen_op_movl_T2_g2,
222 gen_op_movl_T2_g3,
223 gen_op_movl_T2_g4,
224 gen_op_movl_T2_g5,
225 gen_op_movl_T2_g6,
226 gen_op_movl_T2_g7,
227 gen_op_movl_T2_o0,
228 gen_op_movl_T2_o1,
229 gen_op_movl_T2_o2,
230 gen_op_movl_T2_o3,
231 gen_op_movl_T2_o4,
232 gen_op_movl_T2_o5,
233 gen_op_movl_T2_o6,
234 gen_op_movl_T2_o7,
235 gen_op_movl_T2_l0,
236 gen_op_movl_T2_l1,
237 gen_op_movl_T2_l2,
238 gen_op_movl_T2_l3,
239 gen_op_movl_T2_l4,
240 gen_op_movl_T2_l5,
241 gen_op_movl_T2_l6,
242 gen_op_movl_T2_l7,
243 gen_op_movl_T2_i0,
244 gen_op_movl_T2_i1,
245 gen_op_movl_T2_i2,
246 gen_op_movl_T2_i3,
247 gen_op_movl_T2_i4,
248 gen_op_movl_T2_i5,
249 gen_op_movl_T2_i6,
250 gen_op_movl_T2_i7,
251 }
7a3f1944
FB		 252};
253
254static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 255 gen_op_movl_T0_im,
256 gen_op_movl_T1_im,
257 gen_op_movl_T2_im
7a3f1944
FB		 258};
259
cf495bcf 260static inline void gen_movl_imm_TN(int reg, int imm)
7a3f1944 261{
cf495bcf 262 gen_op_movl_TN_im[reg] (imm);
7a3f1944
FB		 263}
264
cf495bcf 265static inline void gen_movl_imm_T1(int val)
7a3f1944 266{
cf495bcf 267 gen_movl_imm_TN(1, val);
7a3f1944
FB		 268}
269
cf495bcf 270static inline void gen_movl_imm_T0(int val)
7a3f1944 271{
cf495bcf 272 gen_movl_imm_TN(0, val);
7a3f1944
FB		 273}
274
cf495bcf 275static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 276{
cf495bcf
FB		 277 if (reg)
278 gen_op_movl_reg_TN[t][reg] ();
279 else
280 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 281}
282
cf495bcf 283static inline void gen_movl_reg_T0(int reg)
7a3f1944 284{
cf495bcf 285 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 286}
287
cf495bcf 288static inline void gen_movl_reg_T1(int reg)
7a3f1944 289{
cf495bcf 290 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 291}
292
cf495bcf 293static inline void gen_movl_reg_T2(int reg)
7a3f1944 294{
cf495bcf 295 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 296}
297
cf495bcf 298static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 299{
cf495bcf
FB		 300 if (reg)
301 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 302}
303
cf495bcf 304static inline void gen_movl_T0_reg(int reg)
7a3f1944 305{
cf495bcf 306 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 307}
308
cf495bcf 309static inline void gen_movl_T1_reg(int reg)
7a3f1944 310{
cf495bcf 311 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 312}
313
72cbca10
FB		 314/* call this function before using T2 as it may have been set for a jump */
315static inline void flush_T2(DisasContext * dc)
316{
317 if (dc->npc == JUMP_PC) {
318 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
319 dc->npc = DYNAMIC_PC;
320 }
321}
322
323static inline void save_npc(DisasContext * dc)
324{
325 if (dc->npc == JUMP_PC) {
326 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
327 dc->npc = DYNAMIC_PC;
328 } else if (dc->npc != DYNAMIC_PC) {
329 gen_op_movl_npc_im(dc->npc);
330 }
331}
332
333static inline void save_state(DisasContext * dc)
334{
335 gen_op_jmp_im((uint32_t)dc->pc);
336 save_npc(dc);
337}
338
cf495bcf 339static void gen_cond(int cond)
7a3f1944 340{
7a3f1944 341 switch (cond) {
cf495bcf
FB		 342 case 0x0:
343 gen_op_movl_T2_0();
344 break;
345 case 0x1:
346 gen_op_eval_be();
347 break;
348 case 0x2:
349 gen_op_eval_ble();
350 break;
351 case 0x3:
352 gen_op_eval_bl();
353 break;
354 case 0x4:
355 gen_op_eval_bleu();
356 break;
357 case 0x5:
358 gen_op_eval_bcs();
359 break;
360 case 0x6:
361 gen_op_eval_bneg();
362 break;
363 case 0x7:
364 gen_op_eval_bvs();
365 break;
366 case 0x8:
367 gen_op_movl_T2_1();
368 break;
369 case 0x9:
370 gen_op_eval_bne();
371 break;
372 case 0xa:
373 gen_op_eval_bg();
374 break;
375 case 0xb:
376 gen_op_eval_bge();
377 break;
378 case 0xc:
379 gen_op_eval_bgu();
380 break;
381 case 0xd:
382 gen_op_eval_bcc();
383 break;
384 case 0xe:
385 gen_op_eval_bpos();
386 break;
387 default:
388 case 0xf:
389 gen_op_eval_bvc();
390 break;
7a3f1944 391 }
7a3f1944
FB		 392}
393
cf495bcf
FB		 394
395static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn)
7a3f1944 396{
cf495bcf
FB		 397 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
398 target += (uint32_t) dc->pc;
399 if (cond == 0x0) {
400 /* unconditional not taken */
401 if (a) {
402 dc->pc = dc->npc + 4;
403 dc->npc = dc->pc + 4;
404 } else {
405 dc->pc = dc->npc;
406 dc->npc = dc->pc + 4;
407 }
408 } else if (cond == 0x8) {
409 /* unconditional taken */
410 if (a) {
72cbca10 411 dc->pc = target;
cf495bcf
FB		 412 dc->npc = dc->pc + 4;
413 } else {
414 dc->pc = dc->npc;
72cbca10 415 dc->npc = target;
cf495bcf
FB		 416 }
417 } else {
72cbca10 418 flush_T2(dc);
cf495bcf
FB		 419 gen_cond(cond);
420 if (a) {
72cbca10 421 gen_op_branch_a((long)dc->tb, target, dc->npc);
cf495bcf 422 dc->is_br = 1;
cf495bcf
FB		 423 } else {
424 dc->pc = dc->npc;
72cbca10
FB		 425 dc->jump_pc[0] = target;
426 dc->jump_pc[1] = dc->npc + 4;
427 dc->npc = JUMP_PC;
cf495bcf
FB		 428 }
429 }
7a3f1944
FB		 430}
431
cf495bcf 432#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
7a3f1944 433
cf495bcf 434static int sign_extend(int x, int len)
7a3f1944 435{
cf495bcf
FB		 436 len = 32 - len;
437 return (x << len) >> len;
7a3f1944
FB		 438}
439
cf495bcf
FB		 440static void disas_sparc_insn(DisasContext * dc)
441{
442 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 443
72cbca10 444 insn = ldl_code((uint8_t *)dc->pc);
cf495bcf 445 opc = GET_FIELD(insn, 0, 1);
7a3f1944 446
cf495bcf
FB		 447 rd = GET_FIELD(insn, 2, 6);
448 switch (opc) {
449 case 0: /* branches/sethi */
450 {
451 unsigned int xop = GET_FIELD(insn, 7, 9);
452 int target;
453 target = GET_FIELD(insn, 10, 31);
454 switch (xop) {
455 case 0x0:
456 case 0x1: /* UNIMPL */
457 goto illegal_insn;
458 case 0x2: /* BN+x */
7a3f1944 459 {
cf495bcf
FB		 460 target <<= 2;
461 target = sign_extend(target, 22);
462 do_branch(dc, target, insn);
463 goto jmp_insn;
7a3f1944 464 }
cf495bcf
FB		 465 case 0x3: /* FBN+x */
466 break;
467 case 0x4: /* SETHI */
468 gen_movl_imm_T0(target << 10);
469 gen_movl_T0_reg(rd);
470 break;
471 case 0x5: /*CBN+x */
472 break;
473 }
474 break;
475 }
476 case 1:
477 /*CALL*/ {
478 unsigned int target = GET_FIELDs(insn, 2, 31) << 2;
479
480 gen_op_movl_T0_im((long) (dc->pc));
481 gen_movl_T0_reg(15);
72cbca10 482 target = dc->pc + target;
cf495bcf 483 dc->pc = dc->npc;
72cbca10 484 dc->npc = target;
cf495bcf
FB		 485 }
486 goto jmp_insn;
487 case 2: /* FPU & Logical Operations */
488 {
489 unsigned int xop = GET_FIELD(insn, 7, 12);
490 if (xop == 0x3a) { /* generate trap */
491 int cond;
492 rs1 = GET_FIELD(insn, 13, 17);
493 gen_movl_reg_T0(rs1);
494 if (IS_IMM) {
495 gen_movl_imm_T1(GET_FIELD(insn, 25, 31));
496 } else {
497 rs2 = GET_FIELD(insn, 27, 31);
498 gen_movl_reg_T1(rs2);
499 }
500 gen_op_add_T1_T0();
501 save_state(dc);
502 cond = GET_FIELD(insn, 3, 6);
503 if (cond == 0x8) {
504 gen_op_trap_T0();
505 dc->is_br = 1;
506 goto jmp_insn;
507 } else {
508 gen_op_trapcc_T0();
509 }
510 } else if (xop == 0x28) {
511 rs1 = GET_FIELD(insn, 13, 17);
512 switch(rs1) {
513 case 0: /* rdy */
514 gen_op_rdy();
515 gen_movl_T0_reg(rd);
516 break;
517 default:
518 goto illegal_insn;
519 }
520 } else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */
521 goto illegal_insn;
522 } else {
523 rs1 = GET_FIELD(insn, 13, 17);
524 gen_movl_reg_T0(rs1);
525 if (IS_IMM) { /* immediate */
526 rs2 = GET_FIELDs(insn, 19, 31);
527 gen_movl_imm_T1(rs2);
528 } else { /* register */
529 rs2 = GET_FIELD(insn, 27, 31);
530 gen_movl_reg_T1(rs2);
531 }
532 if (xop < 0x20) {
533 switch (xop & ~0x10) {
534 case 0x0:
535 if (xop & 0x10)
536 gen_op_add_T1_T0_cc();
537 else
538 gen_op_add_T1_T0();
539 break;
540 case 0x1:
541 gen_op_and_T1_T0();
542 if (xop & 0x10)
543 gen_op_logic_T0_cc();
544 break;
545 case 0x2:
546 gen_op_or_T1_T0();
547 if (xop & 0x10)
548 gen_op_logic_T0_cc();
549 break;
550 case 0x3:
551 gen_op_xor_T1_T0();
552 if (xop & 0x10)
553 gen_op_logic_T0_cc();
554 break;
555 case 0x4:
556 if (xop & 0x10)
557 gen_op_sub_T1_T0_cc();
558 else
559 gen_op_sub_T1_T0();
560 break;
561 case 0x5:
562 gen_op_andn_T1_T0();
563 if (xop & 0x10)
564 gen_op_logic_T0_cc();
565 break;
566 case 0x6:
567 gen_op_orn_T1_T0();
568 if (xop & 0x10)
569 gen_op_logic_T0_cc();
570 break;
571 case 0x7:
572 gen_op_xnor_T1_T0();
573 if (xop & 0x10)
574 gen_op_logic_T0_cc();
575 break;
576 case 0x8:
577 gen_op_addx_T1_T0();
578 if (xop & 0x10)
579 gen_op_set_flags();
580 break;
581 case 0xa:
582 gen_op_umul_T1_T0();
583 if (xop & 0x10)
584 gen_op_logic_T0_cc();
585 break;
586 case 0xb:
587 gen_op_smul_T1_T0();
588 if (xop & 0x10)
589 gen_op_logic_T0_cc();
590 break;
591 case 0xc:
592 gen_op_subx_T1_T0();
593 if (xop & 0x10)
594 gen_op_set_flags();
595 break;
596 case 0xe:
597 gen_op_udiv_T1_T0();
598 if (xop & 0x10)
599 gen_op_div_cc();
600 break;
601 case 0xf:
602 gen_op_sdiv_T1_T0();
603 if (xop & 0x10)
604 gen_op_div_cc();
605 break;
606 default:
607 goto illegal_insn;
608 }
609 gen_movl_T0_reg(rd);
610 } else {
611 switch (xop) {
612 case 0x24: /* mulscc */
613 gen_op_mulscc_T1_T0();
614 gen_movl_T0_reg(rd);
615 break;
616 case 0x25: /* SLL */
617 gen_op_sll();
618 gen_movl_T0_reg(rd);
619 break;
620 case 0x26:
621 gen_op_srl();
622 gen_movl_T0_reg(rd);
623 break;
624 case 0x27:
625 gen_op_sra();
626 gen_movl_T0_reg(rd);
627 break;
628 case 0x30:
629 {
630 gen_op_xor_T1_T0();
631 switch(rd) {
632 case 0:
633 gen_op_wry();
634 break;
635 default:
636 goto illegal_insn;
637 }
638 }
639 break;
640 case 0x38: /* jmpl */
641 {
642 gen_op_add_T1_T0();
643 gen_op_movl_npc_T0();
644 if (rd != 0) {
645 gen_op_movl_T0_im((long) (dc->pc));
646 gen_movl_T0_reg(rd);
647 }
648 dc->pc = dc->npc;
72cbca10 649 dc->npc = DYNAMIC_PC;
cf495bcf
FB		 650 }
651 goto jmp_insn;
652 case 0x3b: /* flush */
653 /* nothing to do */
654 break;
655 case 0x3c: /* save */
656 save_state(dc);
657 gen_op_add_T1_T0();
658 gen_op_save();
659 gen_movl_T0_reg(rd);
660 break;
661 case 0x3d: /* restore */
662 save_state(dc);
663 gen_op_add_T1_T0();
664 gen_op_restore();
665 gen_movl_T0_reg(rd);
666 break;
667 default:
668 goto illegal_insn;
669 }
670 }
671 }
672 break;
673 }
674 case 3: /* load/store instructions */
675 {
676 unsigned int xop = GET_FIELD(insn, 7, 12);
677 rs1 = GET_FIELD(insn, 13, 17);
678 gen_movl_reg_T0(rs1);
679 if (IS_IMM) { /* immediate */
680 rs2 = GET_FIELDs(insn, 19, 31);
681 gen_movl_imm_T1(rs2);
682 } else { /* register */
683 rs2 = GET_FIELD(insn, 27, 31);
684 gen_movl_reg_T1(rs2);
685 }
686 gen_op_add_T1_T0();
687 if (xop < 4 || xop > 7) {
688 switch (xop) {
689 case 0x0: /* load word */
690 gen_op_ld();
691 break;
692 case 0x1: /* load unsigned byte */
693 gen_op_ldub();
694 break;
695 case 0x2: /* load unsigned halfword */
696 gen_op_lduh();
697 break;
698 case 0x3: /* load double word */
699 gen_op_ldd();
700 gen_movl_T0_reg(rd + 1);
701 break;
702 case 0x9: /* load signed byte */
703 gen_op_ldsb();
704 break;
705 case 0xa: /* load signed halfword */
706 gen_op_ldsh();
707 break;
708 case 0xd: /* ldstub -- XXX: should be atomically */
709 gen_op_ldstub();
710 break;
711 case 0x0f: /* swap register with memory. Also atomically */
712 gen_op_swap();
713 break;
7a3f1944 714 }
cf495bcf
FB		 715 gen_movl_T1_reg(rd);
716 } else if (xop < 8) {
717 gen_movl_reg_T1(rd);
718 switch (xop) {
719 case 0x4:
720 gen_op_st();
721 break;
722 case 0x5:
723 gen_op_stb();
724 break;
725 case 0x6:
726 gen_op_sth();
727 break;
728 case 0x7:
72cbca10 729 flush_T2(dc);
cf495bcf
FB		 730 gen_movl_reg_T2(rd + 1);
731 gen_op_std();
732 break;
7a3f1944 733 }
cf495bcf 734 }
7a3f1944 735 }
cf495bcf
FB		 736 }
737 /* default case for non jump instructions */
72cbca10
FB		 738 if (dc->npc == DYNAMIC_PC) {
739 dc->pc = DYNAMIC_PC;
740 gen_op_next_insn();
741 } else if (dc->npc == JUMP_PC) {
742 /* we can do a static jump */
743 gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
744 dc->is_br = 1;
745 } else {
cf495bcf
FB		 746 dc->pc = dc->npc;
747 dc->npc = dc->npc + 4;
cf495bcf
FB		 748 }
749 jmp_insn:;
750 return;
751 illegal_insn:
72cbca10 752 save_state(dc);
cf495bcf
FB		 753 gen_op_exception(TT_ILL_INSN);
754 dc->is_br = 1;
7a3f1944
FB		 755}
756
cf495bcf
FB		 757static inline int gen_intermediate_code_internal(TranslationBlock * tb,
758 int spc)
7a3f1944 759{
72cbca10 760 target_ulong pc_start, last_pc;
cf495bcf
FB		 761 uint16_t *gen_opc_end;
762 DisasContext dc1, *dc = &dc1;
763
764 memset(dc, 0, sizeof(DisasContext));
765 if (spc) {
766 printf("SearchPC not yet supported\n");
767 exit(0);
768 }
769 dc->tb = tb;
72cbca10 770 pc_start = tb->pc;
cf495bcf 771 dc->pc = pc_start;
72cbca10 772 dc->npc = (target_ulong) tb->cs_base;
cf495bcf
FB		 773
774 gen_opc_ptr = gen_opc_buf;
775 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
776 gen_opparam_ptr = gen_opparam_buf;
777
778 do {
779 last_pc = dc->pc;
780 disas_sparc_insn(dc);
781 if (dc->is_br)
782 break;
783 /* if the next PC is different, we abort now */
784 if (dc->pc != (last_pc + 4))
785 break;
786 } while ((gen_opc_ptr < gen_opc_end) &&
787 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
72cbca10
FB		 788 if (!dc->is_br) {
789 if (dc->pc != DYNAMIC_PC &&
790 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
791 /* static PC and NPC: we can use direct chaining */
792 gen_op_branch((long)tb, dc->pc, dc->npc);
793 } else {
794 if (dc->pc != DYNAMIC_PC)
795 gen_op_jmp_im(dc->pc);
796 save_npc(dc);
797 gen_op_movl_T0_0();
798 gen_op_exit_tb();
799 }
800 }
cf495bcf 801 *gen_opc_ptr = INDEX_op_end;
7a3f1944 802#ifdef DEBUG_DISAS
cf495bcf
FB		 803 if (loglevel) {
804 fprintf(logfile, "--------------\n");
72cbca10
FB		 805 fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
806 disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0);
cf495bcf
FB		 807 fprintf(logfile, "\n");
808 fprintf(logfile, "OP:\n");
809 dump_ops(gen_opc_buf, gen_opparam_buf);
810 fprintf(logfile, "\n");
811 }
7a3f1944
FB		 812#endif
813
cf495bcf 814 return 0;
7a3f1944
FB		 815}
816
cf495bcf 817int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 818{
cf495bcf 819 return gen_intermediate_code_internal(tb, 0);
7a3f1944
FB		 820}
821
cf495bcf 822int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 823{
cf495bcf 824 return gen_intermediate_code_internal(tb, 1);
7a3f1944
FB		 825}
826
cf495bcf 827CPUSPARCState *cpu_sparc_init(void)
7a3f1944 828{
cf495bcf
FB		 829 CPUSPARCState *env;
830
831 cpu_exec_init();
832
833 if (!(env = malloc(sizeof(CPUSPARCState))))
834 return (NULL);
835 memset(env, 0, sizeof(*env));
836 env->cwp = 0;
837 env->wim = 1;
838 env->regwptr = env->regbase + (env->cwp * 16);
839 env->user_mode_only = 1;
840 return (env);
7a3f1944
FB		 841}
842
843#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
844
cf495bcf 845void cpu_sparc_dump_state(CPUSPARCState * env, FILE * f, int flags)
7a3f1944 846{
cf495bcf
FB		 847 int i, x;
848
849 fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc);
850 fprintf(f, "General Registers:\n");
851 for (i = 0; i < 4; i++)
852 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
853 fprintf(f, "\n");
854 for (; i < 8; i++)
855 fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
856 fprintf(f, "\nCurrent Register Window:\n");
857 for (x = 0; x < 3; x++) {
858 for (i = 0; i < 4; i++)
859 fprintf(f, "%%%c%d: 0x%08x\t",
860 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
861 env->regwptr[i + x * 8]);
862 fprintf(f, "\n");
863 for (; i < 8; i++)
864 fprintf(f, "%%%c%d: 0x%08x\t",
865 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
866 env->regwptr[i + x * 8]);
867 fprintf(f, "\n");
868 }
869 fprintf(f, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env->psr | env->cwp,
870 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
871 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
872 env->wim);
7a3f1944 873}
edfcbd99
FB		 874
875target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
876{
877 return addr;
878}
Empty description
This page took 0.127701 seconds and 4 git commands to generate.