[qemu.git] / hw / ioapic.c

/*
 *  ioapic.c IOAPIC emulation logic
 *
 *  Copyright (c) 2004-2005 Fabrice Bellard
 *
 *  Split the ioapic logic from apic.c
 *  Xiantao Zhang <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw.h"
#include "pc.h"
#include "apic.h"
#include "qemu-timer.h"
#include "host-utils.h"
#include "sysbus.h"

//#define DEBUG_IOAPIC

#ifdef DEBUG_IOAPIC
#define DPRINTF(fmt, ...)                                       \
    do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

#define IOAPIC_LVT_MASKED 		(1<<16)

#define IOAPIC_TRIGGER_EDGE		0
#define IOAPIC_TRIGGER_LEVEL		1

/*io{apic,sapic} delivery mode*/
#define IOAPIC_DM_FIXED			0x0
#define IOAPIC_DM_LOWEST_PRIORITY	0x1
#define IOAPIC_DM_PMI			0x2
#define IOAPIC_DM_NMI			0x4
#define IOAPIC_DM_INIT			0x5
#define IOAPIC_DM_SIPI			0x5
#define IOAPIC_DM_EXTINT		0x7

typedef struct IOAPICState IOAPICState;

struct IOAPICState {
    SysBusDevice busdev;
    uint8_t id;
    uint8_t ioregsel;

    uint32_t irr;
    uint64_t ioredtbl[IOAPIC_NUM_PINS];
};

static void ioapic_service(IOAPICState *s)
{
    uint8_t i;
    uint8_t trig_mode;
    uint8_t vector;
    uint8_t delivery_mode;
    uint32_t mask;
    uint64_t entry;
    uint8_t dest;
    uint8_t dest_mode;
    uint8_t polarity;

    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
        mask = 1 << i;
        if (s->irr & mask) {
            entry = s->ioredtbl[i];
            if (!(entry & IOAPIC_LVT_MASKED)) {
                trig_mode = ((entry >> 15) & 1);
                dest = entry >> 56;
                dest_mode = (entry >> 11) & 1;
                delivery_mode = (entry >> 8) & 7;
                polarity = (entry >> 13) & 1;
                if (trig_mode == IOAPIC_TRIGGER_EDGE)
                    s->irr &= ~mask;
                if (delivery_mode == IOAPIC_DM_EXTINT)
                    vector = pic_read_irq(isa_pic);
                else
                    vector = entry & 0xff;

                apic_deliver_irq(dest, dest_mode, delivery_mode,
                                 vector, polarity, trig_mode);
            }
        }
    }
}

static void ioapic_set_irq(void *opaque, int vector, int level)
{
    IOAPICState *s = opaque;

    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
     * to GSI 2.  GSI maps to ioapic 1-1.  This is not
     * the cleanest way of doing it but it should work. */

    DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector);
    if (vector == 0)
        vector = 2;

    if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
        uint32_t mask = 1 << vector;
        uint64_t entry = s->ioredtbl[vector];

        if ((entry >> 15) & 1) {
            /* level triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            } else {
                s->irr &= ~mask;
            }
        } else {
            /* edge triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            }
        }
    }
}

static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
{
    IOAPICState *s = opaque;
    int index;
    uint32_t val = 0;

    addr &= 0xff;
    if (addr == 0x00) {
        val = s->ioregsel;
    } else if (addr == 0x10) {
        switch (s->ioregsel) {
            case 0x00:
                val = s->id << 24;
                break;
            case 0x01:
                val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
                break;
            case 0x02:
                val = 0;
                break;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1)
                        val = s->ioredtbl[index] >> 32;
                    else
                        val = s->ioredtbl[index] & 0xffffffff;
                }
        }
        DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
    }
    return val;
}

static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    IOAPICState *s = opaque;
    int index;

    addr &= 0xff;
    if (addr == 0x00)  {
        s->ioregsel = val;
        return;
    } else if (addr == 0x10) {
        DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
        switch (s->ioregsel) {
            case 0x00:
                s->id = (val >> 24) & 0xff;
                return;
            case 0x01:
            case 0x02:
                return;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1) {
                        s->ioredtbl[index] &= 0xffffffff;
                        s->ioredtbl[index] |= (uint64_t)val << 32;
                    } else {
                        s->ioredtbl[index] &= ~0xffffffffULL;
                        s->ioredtbl[index] |= val;
                    }
                    ioapic_service(s);
                }
        }
    }
}

static const VMStateDescription vmstate_ioapic = {
    .name = "ioapic",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(id, IOAPICState),
        VMSTATE_UINT8(ioregsel, IOAPICState),
        VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
        VMSTATE_END_OF_LIST()
    }
};

static void ioapic_reset(DeviceState *d)
{
    IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
    int i;

    s->id = 0;
    s->ioregsel = 0;
    s->irr = 0;
    for(i = 0; i < IOAPIC_NUM_PINS; i++)
        s->ioredtbl[i] = 1 << 16; /* mask LVT */
}

static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
    ioapic_mem_readl,
    ioapic_mem_readl,
    ioapic_mem_readl,
};

static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
    ioapic_mem_writel,
    ioapic_mem_writel,
    ioapic_mem_writel,
};

static int ioapic_init1(SysBusDevice *dev)
{
    IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
    int io_memory;

    io_memory = cpu_register_io_memory(ioapic_mem_read,
                                       ioapic_mem_write, s);
    sysbus_init_mmio(dev, 0x1000, io_memory);

    qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);

    return 0;
}

static SysBusDeviceInfo ioapic_info = {
    .init = ioapic_init1,
    .qdev.name = "ioapic",
    .qdev.size = sizeof(IOAPICState),
    .qdev.vmsd = &vmstate_ioapic,
    .qdev.reset = ioapic_reset,
    .qdev.no_user = 1,
};

static void ioapic_register_devices(void)
{
    sysbus_register_withprop(&ioapic_info);
}

device_init(ioapic_register_devices)
Commit	Line	Data
610626af AL	1	/*
	2	* ioapic.c IOAPIC emulation logic
	3	*
	4	* Copyright (c) 2004-2005 Fabrice Bellard
	5	*
	6	* Split the ioapic logic from apic.c
	7	* Xiantao Zhang <[email protected]>
	8	*
	9	* This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU Lesser General Public
	11	* License as published by the Free Software Foundation; either
	12	* version 2 of the License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* Lesser General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU Lesser General Public
8167ee88	20	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
610626af AL	21	*/
	22
	23	#include "hw.h"
	24	#include "pc.h"
aa28b9bf	25	#include "apic.h"
610626af AL	26	#include "qemu-timer.h"
610626af AL	27	#include "host-utils.h"
96051119	28	#include "sysbus.h"
610626af AL	29
	30	//#define DEBUG_IOAPIC
	31
9af9b330 BS	32	#ifdef DEBUG_IOAPIC
	33	#define DPRINTF(fmt, ...) \
	34	do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
	35	#else
	36	#define DPRINTF(fmt, ...)
	37	#endif
	38
610626af AL	39	#define IOAPIC_LVT_MASKED (1<<16)
	40
	41	#define IOAPIC_TRIGGER_EDGE 0
	42	#define IOAPIC_TRIGGER_LEVEL 1
	43
	44	/io{apic,sapic} delivery mode/
	45	#define IOAPIC_DM_FIXED 0x0
	46	#define IOAPIC_DM_LOWEST_PRIORITY 0x1
	47	#define IOAPIC_DM_PMI 0x2
	48	#define IOAPIC_DM_NMI 0x4
	49	#define IOAPIC_DM_INIT 0x5
	50	#define IOAPIC_DM_SIPI 0x5
	51	#define IOAPIC_DM_EXTINT 0x7
	52
96051119 BS	53	typedef struct IOAPICState IOAPICState;
96051119 BS	54
610626af	55	struct IOAPICState {
96051119	56	SysBusDevice busdev;
610626af AL	57	uint8_t id;
	58	uint8_t ioregsel;
	59
	60	uint32_t irr;
	61	uint64_t ioredtbl[IOAPIC_NUM_PINS];
	62	};
	63
	64	static void ioapic_service(IOAPICState *s)
	65	{
	66	uint8_t i;
	67	uint8_t trig_mode;
	68	uint8_t vector;
	69	uint8_t delivery_mode;
	70	uint32_t mask;
	71	uint64_t entry;
	72	uint8_t dest;
	73	uint8_t dest_mode;
	74	uint8_t polarity;
	75
	76	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	77	mask = 1 << i;
	78	if (s->irr & mask) {
	79	entry = s->ioredtbl[i];
	80	if (!(entry & IOAPIC_LVT_MASKED)) {
	81	trig_mode = ((entry >> 15) & 1);
	82	dest = entry >> 56;
	83	dest_mode = (entry >> 11) & 1;
	84	delivery_mode = (entry >> 8) & 7;
	85	polarity = (entry >> 13) & 1;
	86	if (trig_mode == IOAPIC_TRIGGER_EDGE)
	87	s->irr &= ~mask;
	88	if (delivery_mode == IOAPIC_DM_EXTINT)
	89	vector = pic_read_irq(isa_pic);
	90	else
	91	vector = entry & 0xff;
	92
	93	apic_deliver_irq(dest, dest_mode, delivery_mode,
	94	vector, polarity, trig_mode);
	95	}
	96	}
	97	}
	98	}
	99
7d0500c4	100	static void ioapic_set_irq(void *opaque, int vector, int level)
610626af AL	101	{
	102	IOAPICState *s = opaque;
	103
	104	/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
	105	* to GSI 2. GSI maps to ioapic 1-1. This is not
	106	* the cleanest way of doing it but it should work. */
	107
9af9b330	108	DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector);
610626af AL	109	if (vector == 0)
	110	vector = 2;
	111
	112	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
	113	uint32_t mask = 1 << vector;
	114	uint64_t entry = s->ioredtbl[vector];
	115
	116	if ((entry >> 15) & 1) {
	117	/* level triggered */
	118	if (level) {
	119	s->irr \|= mask;
	120	ioapic_service(s);
	121	} else {
	122	s->irr &= ~mask;
	123	}
	124	} else {
	125	/* edge triggered */
	126	if (level) {
	127	s->irr \|= mask;
	128	ioapic_service(s);
	129	}
	130	}
	131	}
	132	}
	133
c227f099	134	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
610626af AL	135	{
	136	IOAPICState *s = opaque;
	137	int index;
	138	uint32_t val = 0;
	139
	140	addr &= 0xff;
	141	if (addr == 0x00) {
	142	val = s->ioregsel;
	143	} else if (addr == 0x10) {
	144	switch (s->ioregsel) {
	145	case 0x00:
	146	val = s->id << 24;
	147	break;
	148	case 0x01:
	149	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
	150	break;
	151	case 0x02:
	152	val = 0;
	153	break;
	154	default:
	155	index = (s->ioregsel - 0x10) >> 1;
	156	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	157	if (s->ioregsel & 1)
	158	val = s->ioredtbl[index] >> 32;
	159	else
	160	val = s->ioredtbl[index] & 0xffffffff;
	161	}
	162	}
9af9b330	163	DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
610626af AL	164	}
	165	return val;
	166	}
	167
c227f099	168	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
610626af AL	169	{
	170	IOAPICState *s = opaque;
	171	int index;
	172
	173	addr &= 0xff;
	174	if (addr == 0x00) {
	175	s->ioregsel = val;
	176	return;
	177	} else if (addr == 0x10) {
9af9b330	178	DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
610626af AL	179	switch (s->ioregsel) {
	180	case 0x00:
	181	s->id = (val >> 24) & 0xff;
	182	return;
	183	case 0x01:
	184	case 0x02:
	185	return;
	186	default:
	187	index = (s->ioregsel - 0x10) >> 1;
	188	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	189	if (s->ioregsel & 1) {
	190	s->ioredtbl[index] &= 0xffffffff;
	191	s->ioredtbl[index] \|= (uint64_t)val << 32;
	192	} else {
	193	s->ioredtbl[index] &= ~0xffffffffULL;
	194	s->ioredtbl[index] \|= val;
	195	}
	196	ioapic_service(s);
	197	}
	198	}
	199	}
	200	}
	201
3e9e9888 JQ	202	static const VMStateDescription vmstate_ioapic = {
	203	.name = "ioapic",
	204	.version_id = 1,
	205	.minimum_version_id = 1,
	206	.minimum_version_id_old = 1,
	207	.fields = (VMStateField []) {
	208	VMSTATE_UINT8(id, IOAPICState),
	209	VMSTATE_UINT8(ioregsel, IOAPICState),
	210	VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
	211	VMSTATE_END_OF_LIST()
610626af	212	}
3e9e9888	213	};
610626af	214
96051119	215	static void ioapic_reset(DeviceState *d)
610626af	216	{
96051119	217	IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
610626af AL	218	int i;
610626af AL	219
96051119 BS	220	s->id = 0;
	221	s->ioregsel = 0;
	222	s->irr = 0;
610626af AL	223	for(i = 0; i < IOAPIC_NUM_PINS; i++)
	224	s->ioredtbl[i] = 1 << 16; /* mask LVT */
	225	}
	226
d60efc6b	227	static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
610626af AL	228	ioapic_mem_readl,
	229	ioapic_mem_readl,
	230	ioapic_mem_readl,
	231	};
	232
d60efc6b	233	static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
610626af AL	234	ioapic_mem_writel,
	235	ioapic_mem_writel,
	236	ioapic_mem_writel,
	237	};
	238
96051119	239	static int ioapic_init1(SysBusDevice *dev)
610626af	240	{
96051119	241	IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
610626af AL	242	int io_memory;
610626af AL	243
1eed09cb	244	io_memory = cpu_register_io_memory(ioapic_mem_read,
610626af	245	ioapic_mem_write, s);
96051119	246	sysbus_init_mmio(dev, 0x1000, io_memory);
610626af	247
96051119	248	qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
610626af	249
96051119	250	return 0;
610626af	251	}
96051119 BS	252
	253	static SysBusDeviceInfo ioapic_info = {
	254	.init = ioapic_init1,
	255	.qdev.name = "ioapic",
	256	.qdev.size = sizeof(IOAPICState),
	257	.qdev.vmsd = &vmstate_ioapic,
	258	.qdev.reset = ioapic_reset,
	259	.qdev.no_user = 1,
	260	};
	261
	262	static void ioapic_register_devices(void)
	263	{
	264	sysbus_register_withprop(&ioapic_info);
	265	}
	266
	267	device_init(ioapic_register_devices)