[qemu.git] / hw / ioapic.c

/*
 *  ioapic.c IOAPIC emulation logic
 *
 *  Copyright (c) 2004-2005 Fabrice Bellard
 *
 *  Split the ioapic logic from apic.c
 *  Xiantao Zhang <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw.h"
#include "pc.h"
#include "qemu-timer.h"
#include "host-utils.h"

//#define DEBUG_IOAPIC

#define IOAPIC_NUM_PINS			0x18
#define IOAPIC_LVT_MASKED 		(1<<16)

#define IOAPIC_TRIGGER_EDGE		0
#define IOAPIC_TRIGGER_LEVEL		1

/*io{apic,sapic} delivery mode*/
#define IOAPIC_DM_FIXED			0x0
#define IOAPIC_DM_LOWEST_PRIORITY	0x1
#define IOAPIC_DM_PMI			0x2
#define IOAPIC_DM_NMI			0x4
#define IOAPIC_DM_INIT			0x5
#define IOAPIC_DM_SIPI			0x5
#define IOAPIC_DM_EXTINT		0x7

struct IOAPICState {
    uint8_t id;
    uint8_t ioregsel;

    uint32_t irr;
    uint64_t ioredtbl[IOAPIC_NUM_PINS];
};

static void ioapic_service(IOAPICState *s)
{
    uint8_t i;
    uint8_t trig_mode;
    uint8_t vector;
    uint8_t delivery_mode;
    uint32_t mask;
    uint64_t entry;
    uint8_t dest;
    uint8_t dest_mode;
    uint8_t polarity;

    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
        mask = 1 << i;
        if (s->irr & mask) {
            entry = s->ioredtbl[i];
            if (!(entry & IOAPIC_LVT_MASKED)) {
                trig_mode = ((entry >> 15) & 1);
                dest = entry >> 56;
                dest_mode = (entry >> 11) & 1;
                delivery_mode = (entry >> 8) & 7;
                polarity = (entry >> 13) & 1;
                if (trig_mode == IOAPIC_TRIGGER_EDGE)
                    s->irr &= ~mask;
                if (delivery_mode == IOAPIC_DM_EXTINT)
                    vector = pic_read_irq(isa_pic);
                else
                    vector = entry & 0xff;

                apic_deliver_irq(dest, dest_mode, delivery_mode,
                                 vector, polarity, trig_mode);
            }
        }
    }
}

void ioapic_set_irq(void *opaque, int vector, int level)
{
    IOAPICState *s = opaque;

    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
     * to GSI 2.  GSI maps to ioapic 1-1.  This is not
     * the cleanest way of doing it but it should work. */

    if (vector == 0)
        vector = 2;

    if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
        uint32_t mask = 1 << vector;
        uint64_t entry = s->ioredtbl[vector];

        if ((entry >> 15) & 1) {
            /* level triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            } else {
                s->irr &= ~mask;
            }
        } else {
            /* edge triggered */
            if (level) {
                s->irr |= mask;
                ioapic_service(s);
            }
        }
    }
}

static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
{
    IOAPICState *s = opaque;
    int index;
    uint32_t val = 0;

    addr &= 0xff;
    if (addr == 0x00) {
        val = s->ioregsel;
    } else if (addr == 0x10) {
        switch (s->ioregsel) {
            case 0x00:
                val = s->id << 24;
                break;
            case 0x01:
                val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
                break;
            case 0x02:
                val = 0;
                break;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1)
                        val = s->ioredtbl[index] >> 32;
                    else
                        val = s->ioredtbl[index] & 0xffffffff;
                }
        }
#ifdef DEBUG_IOAPIC
        printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
#endif
    }
    return val;
}

static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
{
    IOAPICState *s = opaque;
    int index;

    addr &= 0xff;
    if (addr == 0x00)  {
        s->ioregsel = val;
        return;
    } else if (addr == 0x10) {
#ifdef DEBUG_IOAPIC
        printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
#endif
        switch (s->ioregsel) {
            case 0x00:
                s->id = (val >> 24) & 0xff;
                return;
            case 0x01:
            case 0x02:
                return;
            default:
                index = (s->ioregsel - 0x10) >> 1;
                if (index >= 0 && index < IOAPIC_NUM_PINS) {
                    if (s->ioregsel & 1) {
                        s->ioredtbl[index] &= 0xffffffff;
                        s->ioredtbl[index] |= (uint64_t)val << 32;
                    } else {
                        s->ioredtbl[index] &= ~0xffffffffULL;
                        s->ioredtbl[index] |= val;
                    }
                    ioapic_service(s);
                }
        }
    }
}

static const VMStateDescription vmstate_ioapic = {
    .name = "ioapic",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(id, IOAPICState),
        VMSTATE_UINT8(ioregsel, IOAPICState),
        VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
        VMSTATE_END_OF_LIST()
    }
};

static void ioapic_reset(void *opaque)
{
    IOAPICState *s = opaque;
    int i;

    memset(s, 0, sizeof(*s));
    for(i = 0; i < IOAPIC_NUM_PINS; i++)
        s->ioredtbl[i] = 1 << 16; /* mask LVT */
}

static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
    ioapic_mem_readl,
    ioapic_mem_readl,
    ioapic_mem_readl,
};

static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
    ioapic_mem_writel,
    ioapic_mem_writel,
    ioapic_mem_writel,
};

qemu_irq *ioapic_init(void)
{
    IOAPICState *s;
    qemu_irq *irq;
    int io_memory;

    s = qemu_mallocz(sizeof(IOAPICState));
    ioapic_reset(s);

    io_memory = cpu_register_io_memory(ioapic_mem_read,
                                       ioapic_mem_write, s);
    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

    vmstate_register(0, &vmstate_ioapic, s);
    qemu_register_reset(ioapic_reset, s);
    irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);

    return irq;
}
Commit	Line	Data
610626af AL	1	/*
	2	* ioapic.c IOAPIC emulation logic
	3	*
	4	* Copyright (c) 2004-2005 Fabrice Bellard
	5	*
	6	* Split the ioapic logic from apic.c
	7	* Xiantao Zhang <[email protected]>
	8	*
	9	* This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU Lesser General Public
	11	* License as published by the Free Software Foundation; either
	12	* version 2 of the License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* Lesser General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU Lesser General Public
8167ee88	20	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
610626af AL	21	*/
	22
	23	#include "hw.h"
	24	#include "pc.h"
	25	#include "qemu-timer.h"
	26	#include "host-utils.h"
	27
	28	//#define DEBUG_IOAPIC
	29
	30	#define IOAPIC_NUM_PINS 0x18
	31	#define IOAPIC_LVT_MASKED (1<<16)
	32
	33	#define IOAPIC_TRIGGER_EDGE 0
	34	#define IOAPIC_TRIGGER_LEVEL 1
	35
	36	/io{apic,sapic} delivery mode/
	37	#define IOAPIC_DM_FIXED 0x0
	38	#define IOAPIC_DM_LOWEST_PRIORITY 0x1
	39	#define IOAPIC_DM_PMI 0x2
	40	#define IOAPIC_DM_NMI 0x4
	41	#define IOAPIC_DM_INIT 0x5
	42	#define IOAPIC_DM_SIPI 0x5
	43	#define IOAPIC_DM_EXTINT 0x7
	44
	45	struct IOAPICState {
	46	uint8_t id;
	47	uint8_t ioregsel;
	48
	49	uint32_t irr;
	50	uint64_t ioredtbl[IOAPIC_NUM_PINS];
	51	};
	52
	53	static void ioapic_service(IOAPICState *s)
	54	{
	55	uint8_t i;
	56	uint8_t trig_mode;
	57	uint8_t vector;
	58	uint8_t delivery_mode;
	59	uint32_t mask;
	60	uint64_t entry;
	61	uint8_t dest;
	62	uint8_t dest_mode;
	63	uint8_t polarity;
	64
	65	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	66	mask = 1 << i;
	67	if (s->irr & mask) {
	68	entry = s->ioredtbl[i];
	69	if (!(entry & IOAPIC_LVT_MASKED)) {
	70	trig_mode = ((entry >> 15) & 1);
	71	dest = entry >> 56;
	72	dest_mode = (entry >> 11) & 1;
	73	delivery_mode = (entry >> 8) & 7;
	74	polarity = (entry >> 13) & 1;
	75	if (trig_mode == IOAPIC_TRIGGER_EDGE)
	76	s->irr &= ~mask;
	77	if (delivery_mode == IOAPIC_DM_EXTINT)
	78	vector = pic_read_irq(isa_pic);
	79	else
	80	vector = entry & 0xff;
	81
	82	apic_deliver_irq(dest, dest_mode, delivery_mode,
	83	vector, polarity, trig_mode);
	84	}
85	}
86	}
87	}
88
89	void ioapic_set_irq(void *opaque, int vector, int level)
90	{
91	IOAPICState *s = opaque;
92
93	/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
94	* to GSI 2. GSI maps to ioapic 1-1. This is not
95	* the cleanest way of doing it but it should work. */
96
97	if (vector == 0)
98	vector = 2;
99
100	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
101	uint32_t mask = 1 << vector;
102	uint64_t entry = s->ioredtbl[vector];
103
104	if ((entry >> 15) & 1) {
105	/* level triggered */
106	if (level) {
107	s->irr \|= mask;
108	ioapic_service(s);
109	} else {
110	s->irr &= ~mask;
111	}
112	} else {
113	/* edge triggered */
114	if (level) {
115	s->irr \|= mask;
116	ioapic_service(s);
117	}
118	}
119	}
120	}
121
99a0949b	122	static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
610626af AL	123	{
	124	IOAPICState *s = opaque;
	125	int index;
	126	uint32_t val = 0;
	127
	128	addr &= 0xff;
	129	if (addr == 0x00) {
	130	val = s->ioregsel;
	131	} else if (addr == 0x10) {
	132	switch (s->ioregsel) {
	133	case 0x00:
	134	val = s->id << 24;
	135	break;
	136	case 0x01:
	137	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
	138	break;
	139	case 0x02:
	140	val = 0;
	141	break;
	142	default:
	143	index = (s->ioregsel - 0x10) >> 1;
	144	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	145	if (s->ioregsel & 1)
	146	val = s->ioredtbl[index] >> 32;
	147	else
	148	val = s->ioredtbl[index] & 0xffffffff;
	149	}
	150	}
	151	#ifdef DEBUG_IOAPIC
	152	printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
	153	#endif
	154	}
	155	return val;
	156	}
	157
99a0949b	158	static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
610626af AL	159	{
	160	IOAPICState *s = opaque;
	161	int index;
	162
	163	addr &= 0xff;
	164	if (addr == 0x00) {
	165	s->ioregsel = val;
	166	return;
	167	} else if (addr == 0x10) {
	168	#ifdef DEBUG_IOAPIC
	169	printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
	170	#endif
	171	switch (s->ioregsel) {
	172	case 0x00:
	173	s->id = (val >> 24) & 0xff;
	174	return;
	175	case 0x01:
	176	case 0x02:
	177	return;
	178	default:
	179	index = (s->ioregsel - 0x10) >> 1;
	180	if (index >= 0 && index < IOAPIC_NUM_PINS) {
	181	if (s->ioregsel & 1) {
	182	s->ioredtbl[index] &= 0xffffffff;
	183	s->ioredtbl[index] \|= (uint64_t)val << 32;
	184	} else {
	185	s->ioredtbl[index] &= ~0xffffffffULL;
	186	s->ioredtbl[index] \|= val;
	187	}
	188	ioapic_service(s);
	189	}
	190	}
	191	}
	192	}
	193
3e9e9888 JQ	194	static const VMStateDescription vmstate_ioapic = {
	195	.name = "ioapic",
	196	.version_id = 1,
	197	.minimum_version_id = 1,
	198	.minimum_version_id_old = 1,
	199	.fields = (VMStateField []) {
	200	VMSTATE_UINT8(id, IOAPICState),
	201	VMSTATE_UINT8(ioregsel, IOAPICState),
	202	VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
	203	VMSTATE_END_OF_LIST()
610626af	204	}
3e9e9888	205	};
610626af AL	206
	207	static void ioapic_reset(void *opaque)
	208	{
	209	IOAPICState *s = opaque;
	210	int i;
	211
	212	memset(s, 0, sizeof(*s));
	213	for(i = 0; i < IOAPIC_NUM_PINS; i++)
	214	s->ioredtbl[i] = 1 << 16; /* mask LVT */
	215	}
	216
d60efc6b	217	static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
610626af AL	218	ioapic_mem_readl,
	219	ioapic_mem_readl,
	220	ioapic_mem_readl,
	221	};
	222
d60efc6b	223	static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
610626af AL	224	ioapic_mem_writel,
	225	ioapic_mem_writel,
	226	ioapic_mem_writel,
	227	};
	228
1632dc6a	229	qemu_irq *ioapic_init(void)
610626af AL	230	{
610626af AL	231	IOAPICState *s;
1632dc6a	232	qemu_irq *irq;
610626af AL	233	int io_memory;
	234
	235	s = qemu_mallocz(sizeof(IOAPICState));
	236	ioapic_reset(s);
	237
1eed09cb	238	io_memory = cpu_register_io_memory(ioapic_mem_read,
610626af AL	239	ioapic_mem_write, s);
	240	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
	241
3e9e9888	242	vmstate_register(0, &vmstate_ioapic, s);
a08d4367	243	qemu_register_reset(ioapic_reset, s);
1632dc6a	244	irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);
610626af	245
1632dc6a	246	return irq;
610626af	247	}