[qemu.git] / hw / char / ipoctal232.c

/*
 * QEMU GE IP-Octal 232 IndustryPack emulation
 *
 * Copyright (C) 2012 Igalia, S.L.
 * Author: Alberto Garcia <[email protected]>
 *
 * This code is licensed under the GNU GPL v2 or (at your option) any
 * later version.
 */

#include "qemu/osdep.h"
#include "hw/ipack/ipack.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qemu/bitops.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
#include "qom/object.h"

/* #define DEBUG_IPOCTAL */

#ifdef DEBUG_IPOCTAL
#define DPRINTF2(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF2(fmt, ...) do { } while (0)
#endif

#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)

#define RX_FIFO_SIZE 3

/* The IP-Octal has 8 channels (a-h)
   divided into 4 blocks (A-D) */
#define N_CHANNELS 8
#define N_BLOCKS   4

#define REG_MRa  0x01
#define REG_MRb  0x11
#define REG_SRa  0x03
#define REG_SRb  0x13
#define REG_CSRa 0x03
#define REG_CSRb 0x13
#define REG_CRa  0x05
#define REG_CRb  0x15
#define REG_RHRa 0x07
#define REG_RHRb 0x17
#define REG_THRa 0x07
#define REG_THRb 0x17
#define REG_ACR  0x09
#define REG_ISR  0x0B
#define REG_IMR  0x0B
#define REG_OPCR 0x1B

#define CR_ENABLE_RX    BIT(0)
#define CR_DISABLE_RX   BIT(1)
#define CR_ENABLE_TX    BIT(2)
#define CR_DISABLE_TX   BIT(3)
#define CR_CMD(cr)      ((cr) >> 4)
#define CR_NO_OP        0
#define CR_RESET_MR     1
#define CR_RESET_RX     2
#define CR_RESET_TX     3
#define CR_RESET_ERR    4
#define CR_RESET_BRKINT 5
#define CR_START_BRK    6
#define CR_STOP_BRK     7
#define CR_ASSERT_RTSN  8
#define CR_NEGATE_RTSN  9
#define CR_TIMEOUT_ON   10
#define CR_TIMEOUT_OFF  12

#define SR_RXRDY   BIT(0)
#define SR_FFULL   BIT(1)
#define SR_TXRDY   BIT(2)
#define SR_TXEMT   BIT(3)
#define SR_OVERRUN BIT(4)
#define SR_PARITY  BIT(5)
#define SR_FRAMING BIT(6)
#define SR_BREAK   BIT(7)

#define ISR_TXRDYA BIT(0)
#define ISR_RXRDYA BIT(1)
#define ISR_BREAKA BIT(2)
#define ISR_CNTRDY BIT(3)
#define ISR_TXRDYB BIT(4)
#define ISR_RXRDYB BIT(5)
#define ISR_BREAKB BIT(6)
#define ISR_MPICHG BIT(7)
#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))

typedef struct IPOctalState IPOctalState;
typedef struct SCC2698Channel SCC2698Channel;
typedef struct SCC2698Block SCC2698Block;

struct SCC2698Channel {
    IPOctalState *ipoctal;
    CharBackend dev;
    bool rx_enabled;
    uint8_t mr[2];
    uint8_t mr_idx;
    uint8_t sr;
    uint8_t rhr[RX_FIFO_SIZE];
    uint8_t rhr_idx;
    uint8_t rx_pending;
};

struct SCC2698Block {
    uint8_t imr;
    uint8_t isr;
};

struct IPOctalState {
    IPackDevice parent_obj;

    SCC2698Channel ch[N_CHANNELS];
    SCC2698Block blk[N_BLOCKS];
    uint8_t irq_vector;
};

#define TYPE_IPOCTAL "ipoctal232"

#define IPOCTAL(obj) \
    OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)

static const VMStateDescription vmstate_scc2698_channel = {
    .name = "scc2698_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(rx_enabled, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
        VMSTATE_UINT8(mr_idx, SCC2698Channel),
        VMSTATE_UINT8(sr, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
        VMSTATE_UINT8(rhr_idx, SCC2698Channel),
        VMSTATE_UINT8(rx_pending, SCC2698Channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_scc2698_block = {
    .name = "scc2698_block",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(imr, SCC2698Block),
        VMSTATE_UINT8(isr, SCC2698Block),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ipoctal = {
    .name = "ipoctal232",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
        VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
                             vmstate_scc2698_channel, SCC2698Channel),
        VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
                             vmstate_scc2698_block, SCC2698Block),
        VMSTATE_UINT8(irq_vector, IPOctalState),
        VMSTATE_END_OF_LIST()
    }
};

/* data[10] is 0x0C, not 0x0B as the doc says */
static const uint8_t id_prom_data[] = {
    0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
    0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
};

static void update_irq(IPOctalState *dev, unsigned block)
{
    IPackDevice *idev = IPACK_DEVICE(dev);
    /* Blocks A and B interrupt on INT0#, C and D on INT1#.
       Thus, to get the status we have to check two blocks. */
    SCC2698Block *blk0 = &dev->blk[block];
    SCC2698Block *blk1 = &dev->blk[block^1];
    unsigned intno = block / 2;

    if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
        qemu_irq_raise(idev->irq[intno]);
    } else {
        qemu_irq_lower(idev->irq[intno]);
    }
}

static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
{
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[channel / 2];

    DPRINTF("Write CR%c %u: ", channel + 'a', val);

    /* The lower 4 bits are used to enable and disable Tx and Rx */
    if (val & CR_ENABLE_RX) {
        DPRINTF2("Rx on, ");
        ch->rx_enabled = true;
    }
    if (val & CR_DISABLE_RX) {
        DPRINTF2("Rx off, ");
        ch->rx_enabled = false;
    }
    if (val & CR_ENABLE_TX) {
        DPRINTF2("Tx on, ");
        ch->sr |= SR_TXRDY | SR_TXEMT;
        blk->isr |= ISR_TXRDY(channel);
    }
    if (val & CR_DISABLE_TX) {
        DPRINTF2("Tx off, ");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
    }

    DPRINTF2("cmd: ");

    /* The rest of the bits implement different commands */
    switch (CR_CMD(val)) {
    case CR_NO_OP:
        DPRINTF2("none");
        break;
    case CR_RESET_MR:
        DPRINTF2("reset MR");
        ch->mr_idx = 0;
        break;
    case CR_RESET_RX:
        DPRINTF2("reset Rx");
        ch->rx_enabled = false;
        ch->rx_pending = 0;
        ch->sr &= ~SR_RXRDY;
        blk->isr &= ~ISR_RXRDY(channel);
        break;
    case CR_RESET_TX:
        DPRINTF2("reset Tx");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
        break;
    case CR_RESET_ERR:
        DPRINTF2("reset err");
        ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
        break;
    case CR_RESET_BRKINT:
        DPRINTF2("reset brk ch int");
        blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
        break;
    default:
        DPRINTF2("unsupported 0x%x", CR_CMD(val));
    }

    DPRINTF2("\n");
}

static uint16_t io_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    uint16_t ret = 0;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ret = ch->mr[ch->mr_idx];
        DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
        ch->mr_idx = 1;
        break;

    case REG_SRa:
    case REG_SRb:
        ret = ch->sr;
        DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
        break;

    case REG_RHRa:
    case REG_RHRb:
        ret = ch->rhr[ch->rhr_idx];
        if (ch->rx_pending > 0) {
            ch->rx_pending--;
            if (ch->rx_pending == 0) {
                ch->sr &= ~SR_RXRDY;
                blk->isr &= ~ISR_RXRDY(channel);
                qemu_chr_fe_accept_input(&ch->dev);
            } else {
                ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
            }
            if (ch->sr & SR_BREAK) {
                ch->sr &= ~SR_BREAK;
                blk->isr |= ISR_BREAK(channel);
            }
        }
        DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
        break;

    case REG_ISR:
        ret = blk->isr;
        DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
        break;

    default:
        DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
    }

    if (old_isr != blk->isr) {
        update_irq(dev, block);
    }

    return ret;
}

static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    unsigned reg = val & 0xFF;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;
    uint8_t old_imr = blk->imr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ch->mr[ch->mr_idx] = reg;
        DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
        ch->mr_idx = 1;
        break;

    /* Not implemented */
    case REG_CSRa:
    case REG_CSRb:
        DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
        break;

    case REG_CRa:
    case REG_CRb:
        write_cr(dev, channel, reg);
        break;

    case REG_THRa:
    case REG_THRb:
        if (ch->sr & SR_TXRDY) {
            uint8_t thr = reg;
            DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&ch->dev, &thr, 1);
        } else {
            DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
        }
        break;

    /* Not implemented */
    case REG_ACR:
        DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
        break;

    case REG_IMR:
        DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
        blk->imr = reg;
        break;

    /* Not implemented */
    case REG_OPCR:
        DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
        break;

    default:
        DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
    }

    if (old_isr != blk->isr || old_imr != blk->imr) {
        update_irq(dev, block);
    }
}

static uint16_t id_read(IPackDevice *ip, uint8_t addr)
{
    uint16_t ret = 0;
    unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */

    if (pos < ARRAY_SIZE(id_prom_data)) {
        ret = id_prom_data[pos];
    } else {
        DPRINTF("Attempt to read unavailable PROM data at 0x%x\n",  addr);
    }

    return ret;
}

static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val; /* Undocumented, but the hw works like that */
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static uint16_t int_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
    if (addr != 0 && addr != 2) {
        DPRINTF("Attempt to read from 0x%x\n", addr);
        return 0;
    } else {
        /* Update interrupts if necessary */
        update_irq(dev, addr);
        return dev->irq_vector;
    }
}

static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val;
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static int hostdev_can_receive(void *opaque)
{
    SCC2698Channel *ch = opaque;
    int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
    return ch->rx_enabled ? available_bytes : 0;
}

static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
{
    SCC2698Channel *ch = opaque;
    IPOctalState *dev = ch->ipoctal;
    unsigned pos = ch->rhr_idx + ch->rx_pending;
    int i;

    assert(size + ch->rx_pending <= RX_FIFO_SIZE);

    /* Copy data to the RxFIFO */
    for (i = 0; i < size; i++) {
        pos %= RX_FIFO_SIZE;
        ch->rhr[pos++] = buf[i];
    }

    ch->rx_pending += size;

    /* If the RxFIFO was empty raise an interrupt */
    if (!(ch->sr & SR_RXRDY)) {
        unsigned block, channel = 0;
        /* Find channel number to update the ISR register */
        while (&dev->ch[channel] != ch) {
            channel++;
        }
        block = channel / 2;
        dev->blk[block].isr |= ISR_RXRDY(channel);
        ch->sr |= SR_RXRDY;
        update_irq(dev, block);
    }
}

static void hostdev_event(void *opaque, QEMUChrEvent event)
{
    SCC2698Channel *ch = opaque;
    switch (event) {
    case CHR_EVENT_OPENED:
        DPRINTF("Device %s opened\n", ch->dev->label);
        break;
    case CHR_EVENT_BREAK: {
        uint8_t zero = 0;
        DPRINTF("Device %s received break\n", ch->dev->label);

        if (!(ch->sr & SR_BREAK)) {
            IPOctalState *dev = ch->ipoctal;
            unsigned block, channel = 0;

            while (&dev->ch[channel] != ch) {
                channel++;
            }
            block = channel / 2;

            ch->sr |= SR_BREAK;
            dev->blk[block].isr |= ISR_BREAK(channel);
        }

        /* Put a zero character in the buffer */
        hostdev_receive(ch, &zero, 1);
    }
        break;
    default:
        DPRINTF("Device %s received event %d\n", ch->dev->label, event);
    }
}

static void ipoctal_realize(DeviceState *dev, Error **errp)
{
    IPOctalState *s = IPOCTAL(dev);
    unsigned i;

    for (i = 0; i < N_CHANNELS; i++) {
        SCC2698Channel *ch = &s->ch[i];
        ch->ipoctal = s;

        /* Redirect IP-Octal channels to host character devices */
        if (qemu_chr_fe_backend_connected(&ch->dev)) {
            qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
                                     hostdev_receive, hostdev_event,
                                     NULL, ch, NULL, true);
            DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
        } else {
            DPRINTF("Could not redirect channel %u, no chardev set\n", i);
        }
    }
}

static Property ipoctal_properties[] = {
    DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
    DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
    DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
    DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
    DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
    DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
    DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
    DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
    DEFINE_PROP_END_OF_LIST(),
};

static void ipoctal_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);

    ic->realize     = ipoctal_realize;
    ic->io_read     = io_read;
    ic->io_write    = io_write;
    ic->id_read     = id_read;
    ic->id_write    = id_write;
    ic->int_read    = int_read;
    ic->int_write   = int_write;
    ic->mem_read16  = mem_read16;
    ic->mem_write16 = mem_write16;
    ic->mem_read8   = mem_read8;
    ic->mem_write8  = mem_write8;

    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->desc    = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
    device_class_set_props(dc, ipoctal_properties);
    dc->vmsd    = &vmstate_ipoctal;
}

static const TypeInfo ipoctal_info = {
    .name          = TYPE_IPOCTAL,
    .parent        = TYPE_IPACK_DEVICE,
    .instance_size = sizeof(IPOctalState),
    .class_init    = ipoctal_class_init,
};

static void ipoctal_register_types(void)
{
    type_register_static(&ipoctal_info);
}

type_init(ipoctal_register_types)
Commit	Line	Data
be657dea AG	1	/*
	2	* QEMU GE IP-Octal 232 IndustryPack emulation
	3	*
	4	* Copyright (C) 2012 Igalia, S.L.
b996aed5	5	* Author: Alberto Garcia <[email protected]>
be657dea AG	6	*
	7	* This code is licensed under the GNU GPL v2 or (at your option) any
	8	* later version.
	9	*/
	10
0430891c	11	#include "qemu/osdep.h"
1f9c4cfd	12	#include "hw/ipack/ipack.h"
64552b6b	13	#include "hw/irq.h"
a27bd6c7	14	#include "hw/qdev-properties.h"
d6454270	15	#include "migration/vmstate.h"
be657dea	16	#include "qemu/bitops.h"
0b8fa32f	17	#include "qemu/module.h"
4d43a603	18	#include "chardev/char-fe.h"
db1015e9	19	#include "qom/object.h"
be657dea AG	20
	21	/* #define DEBUG_IPOCTAL */
	22
	23	#ifdef DEBUG_IPOCTAL
	24	#define DPRINTF2(fmt, ...) \
	25	do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
	26	#else
	27	#define DPRINTF2(fmt, ...) do { } while (0)
	28	#endif
	29
	30	#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
	31
	32	#define RX_FIFO_SIZE 3
	33
	34	/* The IP-Octal has 8 channels (a-h)
	35	divided into 4 blocks (A-D) */
	36	#define N_CHANNELS 8
	37	#define N_BLOCKS 4
	38
	39	#define REG_MRa 0x01
	40	#define REG_MRb 0x11
	41	#define REG_SRa 0x03
	42	#define REG_SRb 0x13
	43	#define REG_CSRa 0x03
	44	#define REG_CSRb 0x13
	45	#define REG_CRa 0x05
	46	#define REG_CRb 0x15
	47	#define REG_RHRa 0x07
	48	#define REG_RHRb 0x17
	49	#define REG_THRa 0x07
	50	#define REG_THRb 0x17
	51	#define REG_ACR 0x09
	52	#define REG_ISR 0x0B
	53	#define REG_IMR 0x0B
	54	#define REG_OPCR 0x1B
	55
	56	#define CR_ENABLE_RX BIT(0)
	57	#define CR_DISABLE_RX BIT(1)
	58	#define CR_ENABLE_TX BIT(2)
	59	#define CR_DISABLE_TX BIT(3)
	60	#define CR_CMD(cr) ((cr) >> 4)
	61	#define CR_NO_OP 0
	62	#define CR_RESET_MR 1
	63	#define CR_RESET_RX 2
	64	#define CR_RESET_TX 3
	65	#define CR_RESET_ERR 4
	66	#define CR_RESET_BRKINT 5
	67	#define CR_START_BRK 6
	68	#define CR_STOP_BRK 7
	69	#define CR_ASSERT_RTSN 8
	70	#define CR_NEGATE_RTSN 9
	71	#define CR_TIMEOUT_ON 10
	72	#define CR_TIMEOUT_OFF 12
	73
	74	#define SR_RXRDY BIT(0)
	75	#define SR_FFULL BIT(1)
	76	#define SR_TXRDY BIT(2)
	77	#define SR_TXEMT BIT(3)
	78	#define SR_OVERRUN BIT(4)
	79	#define SR_PARITY BIT(5)
	80	#define SR_FRAMING BIT(6)
	81	#define SR_BREAK BIT(7)
	82
	83	#define ISR_TXRDYA BIT(0)
84	#define ISR_RXRDYA BIT(1)
85	#define ISR_BREAKA BIT(2)
86	#define ISR_CNTRDY BIT(3)
87	#define ISR_TXRDYB BIT(4)
88	#define ISR_RXRDYB BIT(5)
89	#define ISR_BREAKB BIT(6)
90	#define ISR_MPICHG BIT(7)
91	#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
92	#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
93	#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
94
95	typedef struct IPOctalState IPOctalState;
96	typedef struct SCC2698Channel SCC2698Channel;
97	typedef struct SCC2698Block SCC2698Block;
98
99	struct SCC2698Channel {
100	IPOctalState *ipoctal;
becdfa00	101	CharBackend dev;
be657dea AG	102	bool rx_enabled;
	103	uint8_t mr[2];
	104	uint8_t mr_idx;
	105	uint8_t sr;
	106	uint8_t rhr[RX_FIFO_SIZE];
	107	uint8_t rhr_idx;
	108	uint8_t rx_pending;
	109	};
	110
	111	struct SCC2698Block {
	112	uint8_t imr;
	113	uint8_t isr;
	114	};
	115
	116	struct IPOctalState {
08c9cacf AF	117	IPackDevice parent_obj;
08c9cacf AF	118
be657dea AG	119	SCC2698Channel ch[N_CHANNELS];
	120	SCC2698Block blk[N_BLOCKS];
	121	uint8_t irq_vector;
	122	};
	123
	124	#define TYPE_IPOCTAL "ipoctal232"
	125
	126	#define IPOCTAL(obj) \
	127	OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
	128
	129	static const VMStateDescription vmstate_scc2698_channel = {
	130	.name = "scc2698_channel",
	131	.version_id = 1,
	132	.minimum_version_id = 1,
35d08458	133	.fields = (VMStateField[]) {
be657dea AG	134	VMSTATE_BOOL(rx_enabled, SCC2698Channel),
	135	VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
	136	VMSTATE_UINT8(mr_idx, SCC2698Channel),
	137	VMSTATE_UINT8(sr, SCC2698Channel),
	138	VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
	139	VMSTATE_UINT8(rhr_idx, SCC2698Channel),
	140	VMSTATE_UINT8(rx_pending, SCC2698Channel),
	141	VMSTATE_END_OF_LIST()
	142	}
	143	};
	144
	145	static const VMStateDescription vmstate_scc2698_block = {
	146	.name = "scc2698_block",
	147	.version_id = 1,
	148	.minimum_version_id = 1,
35d08458	149	.fields = (VMStateField[]) {
be657dea AG	150	VMSTATE_UINT8(imr, SCC2698Block),
	151	VMSTATE_UINT8(isr, SCC2698Block),
	152	VMSTATE_END_OF_LIST()
	153	}
	154	};
	155
	156	static const VMStateDescription vmstate_ipoctal = {
	157	.name = "ipoctal232",
	158	.version_id = 1,
	159	.minimum_version_id = 1,
35d08458	160	.fields = (VMStateField[]) {
08c9cacf	161	VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
be657dea AG	162	VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
	163	vmstate_scc2698_channel, SCC2698Channel),
	164	VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
	165	vmstate_scc2698_block, SCC2698Block),
	166	VMSTATE_UINT8(irq_vector, IPOctalState),
	167	VMSTATE_END_OF_LIST()
	168	}
	169	};
	170
	171	/* data[10] is 0x0C, not 0x0B as the doc says */
	172	static const uint8_t id_prom_data[] = {
	173	0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
	174	0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
	175	};
	176
	177	static void update_irq(IPOctalState *dev, unsigned block)
	178	{
08c9cacf	179	IPackDevice *idev = IPACK_DEVICE(dev);
be657dea AG	180	/* Blocks A and B interrupt on INT0#, C and D on INT1#.
	181	Thus, to get the status we have to check two blocks. */
	182	SCC2698Block *blk0 = &dev->blk[block];
	183	SCC2698Block *blk1 = &dev->blk[block^1];
	184	unsigned intno = block / 2;
	185
	186	if ((blk0->isr & blk0->imr) \|\| (blk1->isr & blk1->imr)) {
08c9cacf	187	qemu_irq_raise(idev->irq[intno]);
be657dea	188	} else {
08c9cacf	189	qemu_irq_lower(idev->irq[intno]);
be657dea AG	190	}
	191	}
	192
	193	static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
	194	{
	195	SCC2698Channel *ch = &dev->ch[channel];
	196	SCC2698Block *blk = &dev->blk[channel / 2];
	197
	198	DPRINTF("Write CR%c %u: ", channel + 'a', val);
	199
	200	/* The lower 4 bits are used to enable and disable Tx and Rx */
	201	if (val & CR_ENABLE_RX) {
	202	DPRINTF2("Rx on, ");
	203	ch->rx_enabled = true;
	204	}
	205	if (val & CR_DISABLE_RX) {
	206	DPRINTF2("Rx off, ");
	207	ch->rx_enabled = false;
	208	}
	209	if (val & CR_ENABLE_TX) {
	210	DPRINTF2("Tx on, ");
	211	ch->sr \|= SR_TXRDY \| SR_TXEMT;
	212	blk->isr \|= ISR_TXRDY(channel);
	213	}
	214	if (val & CR_DISABLE_TX) {
	215	DPRINTF2("Tx off, ");
	216	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	217	blk->isr &= ~ISR_TXRDY(channel);
	218	}
	219
	220	DPRINTF2("cmd: ");
	221
	222	/* The rest of the bits implement different commands */
	223	switch (CR_CMD(val)) {
	224	case CR_NO_OP:
	225	DPRINTF2("none");
	226	break;
	227	case CR_RESET_MR:
	228	DPRINTF2("reset MR");
	229	ch->mr_idx = 0;
	230	break;
	231	case CR_RESET_RX:
	232	DPRINTF2("reset Rx");
	233	ch->rx_enabled = false;
	234	ch->rx_pending = 0;
	235	ch->sr &= ~SR_RXRDY;
	236	blk->isr &= ~ISR_RXRDY(channel);
	237	break;
	238	case CR_RESET_TX:
	239	DPRINTF2("reset Tx");
	240	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	241	blk->isr &= ~ISR_TXRDY(channel);
	242	break;
	243	case CR_RESET_ERR:
	244	DPRINTF2("reset err");
	245	ch->sr &= ~(SR_OVERRUN \| SR_PARITY \| SR_FRAMING \| SR_BREAK);
	246	break;
	247	case CR_RESET_BRKINT:
	248	DPRINTF2("reset brk ch int");
	249	blk->isr &= ~(ISR_BREAKA \| ISR_BREAKB);
	250	break;
	251	default:
	252	DPRINTF2("unsupported 0x%x", CR_CMD(val));
	253	}
254
255	DPRINTF2("\n");
256	}
257
258	static uint16_t io_read(IPackDevice *ip, uint8_t addr)
259	{
260	IPOctalState *dev = IPOCTAL(ip);
261	uint16_t ret = 0;
262	/* addr[7:6]: block (A-D)
263	addr[7:5]: channel (a-h)
264	addr[5:0]: register */
265	unsigned block = addr >> 5;
266	unsigned channel = addr >> 4;
267	/* Big endian, accessed using 8-bit bytes at odd locations */
268	unsigned offset = (addr & 0x1F) ^ 1;
269	SCC2698Channel *ch = &dev->ch[channel];
270	SCC2698Block *blk = &dev->blk[block];
271	uint8_t old_isr = blk->isr;
272
273	switch (offset) {
274
275	case REG_MRa:
276	case REG_MRb:
277	ret = ch->mr[ch->mr_idx];
278	DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
279	ch->mr_idx = 1;
280	break;
281
282	case REG_SRa:
283	case REG_SRb:
284	ret = ch->sr;
285	DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
286	break;
287
288	case REG_RHRa:
289	case REG_RHRb:
290	ret = ch->rhr[ch->rhr_idx];
291	if (ch->rx_pending > 0) {
292	ch->rx_pending--;
293	if (ch->rx_pending == 0) {
294	ch->sr &= ~SR_RXRDY;
295	blk->isr &= ~ISR_RXRDY(channel);
fa394ed6	296	qemu_chr_fe_accept_input(&ch->dev);
be657dea AG	297	} else {
	298	ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
	299	}
	300	if (ch->sr & SR_BREAK) {
	301	ch->sr &= ~SR_BREAK;
	302	blk->isr \|= ISR_BREAK(channel);
	303	}
	304	}
	305	DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
	306	break;
	307
	308	case REG_ISR:
	309	ret = blk->isr;
	310	DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
	311	break;
	312
	313	default:
	314	DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
	315	}
	316
	317	if (old_isr != blk->isr) {
	318	update_irq(dev, block);
	319	}
	320
	321	return ret;
	322	}
	323
	324	static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	325	{
	326	IPOctalState *dev = IPOCTAL(ip);
	327	unsigned reg = val & 0xFF;
	328	/* addr[7:6]: block (A-D)
	329	addr[7:5]: channel (a-h)
	330	addr[5:0]: register */
	331	unsigned block = addr >> 5;
	332	unsigned channel = addr >> 4;
	333	/* Big endian, accessed using 8-bit bytes at odd locations */
	334	unsigned offset = (addr & 0x1F) ^ 1;
	335	SCC2698Channel *ch = &dev->ch[channel];
	336	SCC2698Block *blk = &dev->blk[block];
	337	uint8_t old_isr = blk->isr;
	338	uint8_t old_imr = blk->imr;
	339
	340	switch (offset) {
	341
	342	case REG_MRa:
	343	case REG_MRb:
	344	ch->mr[ch->mr_idx] = reg;
	345	DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
	346	ch->mr_idx = 1;
	347	break;
	348
	349	/* Not implemented */
	350	case REG_CSRa:
	351	case REG_CSRb:
	352	DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
	353	break;
	354
	355	case REG_CRa:
	356	case REG_CRb:
	357	write_cr(dev, channel, reg);
	358	break;
	359
	360	case REG_THRa:
361	case REG_THRb:
362	if (ch->sr & SR_TXRDY) {
fa394ed6	363	uint8_t thr = reg;
be657dea	364	DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
fa394ed6 MAL	365	/* XXX this blocks entire thread. Rewrite to use
	366	* qemu_chr_fe_write and background I/O callbacks */
	367	qemu_chr_fe_write_all(&ch->dev, &thr, 1);
be657dea AG	368	} else {
	369	DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
	370	}
	371	break;
	372
	373	/* Not implemented */
	374	case REG_ACR:
	375	DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
	376	break;
	377
	378	case REG_IMR:
	379	DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
	380	blk->imr = reg;
	381	break;
	382
	383	/* Not implemented */
	384	case REG_OPCR:
	385	DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
	386	break;
	387
	388	default:
	389	DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
	390	}
	391
	392	if (old_isr != blk->isr \|\| old_imr != blk->imr) {
	393	update_irq(dev, block);
	394	}
	395	}
	396
	397	static uint16_t id_read(IPackDevice *ip, uint8_t addr)
	398	{
	399	uint16_t ret = 0;
	400	unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
	401
	402	if (pos < ARRAY_SIZE(id_prom_data)) {
	403	ret = id_prom_data[pos];
	404	} else {
	405	DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
	406	}
	407
	408	return ret;
	409	}
	410
	411	static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	412	{
	413	IPOctalState *dev = IPOCTAL(ip);
	414	if (addr == 1) {
	415	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
	416	dev->irq_vector = val; /* Undocumented, but the hw works like that */
	417	} else {
	418	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
	419	}
	420	}
	421
	422	static uint16_t int_read(IPackDevice *ip, uint8_t addr)
	423	{
	424	IPOctalState *dev = IPOCTAL(ip);
	425	/* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
	426	if (addr != 0 && addr != 2) {
	427	DPRINTF("Attempt to read from 0x%x\n", addr);
	428	return 0;
	429	} else {
	430	/* Update interrupts if necessary */
	431	update_irq(dev, addr);
432	return dev->irq_vector;
433	}
434	}
435
436	static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
437	{
438	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
439	}
440
441	static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
442	{
443	DPRINTF("Attempt to read from 0x%x\n", addr);
444	return 0;
445	}
446
447	static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
448	{
449	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
450	}
451
452	static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
453	{
454	DPRINTF("Attempt to read from 0x%x\n", addr);
455	return 0;
456	}
457
458	static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
459	{
460	IPOctalState *dev = IPOCTAL(ip);
461	if (addr == 1) {
462	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
463	dev->irq_vector = val;
464	} else {
465	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
466	}
467	}
468
469	static int hostdev_can_receive(void *opaque)
470	{
471	SCC2698Channel *ch = opaque;
472	int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
473	return ch->rx_enabled ? available_bytes : 0;
474	}
475
476	static void hostdev_receive(void opaque, const uint8_t buf, int size)
477	{
478	SCC2698Channel *ch = opaque;
479	IPOctalState *dev = ch->ipoctal;
480	unsigned pos = ch->rhr_idx + ch->rx_pending;
481	int i;
482
483	assert(size + ch->rx_pending <= RX_FIFO_SIZE);
484
485	/* Copy data to the RxFIFO */
486	for (i = 0; i < size; i++) {
487	pos %= RX_FIFO_SIZE;
488	ch->rhr[pos++] = buf[i];
489	}
490
491	ch->rx_pending += size;
492
493	/* If the RxFIFO was empty raise an interrupt */
494	if (!(ch->sr & SR_RXRDY)) {
495	unsigned block, channel = 0;
496	/* Find channel number to update the ISR register */
497	while (&dev->ch[channel] != ch) {
498	channel++;
499	}
500	block = channel / 2;
501	dev->blk[block].isr \|= ISR_RXRDY(channel);
502	ch->sr \|= SR_RXRDY;
503	update_irq(dev, block);
504	}
505	}
506
083b266f	507	static void hostdev_event(void *opaque, QEMUChrEvent event)
be657dea AG	508	{
	509	SCC2698Channel *ch = opaque;
	510	switch (event) {
	511	case CHR_EVENT_OPENED:
	512	DPRINTF("Device %s opened\n", ch->dev->label);
	513	break;
	514	case CHR_EVENT_BREAK: {
	515	uint8_t zero = 0;
	516	DPRINTF("Device %s received break\n", ch->dev->label);
	517
	518	if (!(ch->sr & SR_BREAK)) {
	519	IPOctalState *dev = ch->ipoctal;
	520	unsigned block, channel = 0;
	521
	522	while (&dev->ch[channel] != ch) {
	523	channel++;
	524	}
	525	block = channel / 2;
	526
	527	ch->sr \|= SR_BREAK;
	528	dev->blk[block].isr \|= ISR_BREAK(channel);
	529	}
	530
	531	/* Put a zero character in the buffer */
	532	hostdev_receive(ch, &zero, 1);
	533	}
	534	break;
	535	default:
	536	DPRINTF("Device %s received event %d\n", ch->dev->label, event);
	537	}
	538	}
	539
5c570902	540	static void ipoctal_realize(DeviceState dev, Error *errp)
be657dea	541	{
5c570902	542	IPOctalState *s = IPOCTAL(dev);
be657dea AG	543	unsigned i;
	544
	545	for (i = 0; i < N_CHANNELS; i++) {
	546	SCC2698Channel *ch = &s->ch[i];
	547	ch->ipoctal = s;
	548
	549	/* Redirect IP-Octal channels to host character devices */
30650701	550	if (qemu_chr_fe_backend_connected(&ch->dev)) {
5345fdb4	551	qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
39ab61c6	552	hostdev_receive, hostdev_event,
81517ba3	553	NULL, ch, NULL, true);
b9936159 HG	554	DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
	555	} else {
	556	DPRINTF("Could not redirect channel %u, no chardev set\n", i);
be657dea AG	557	}
be657dea AG	558	}
be657dea AG	559	}
	560
	561	static Property ipoctal_properties[] = {
b9936159 HG	562	DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
	563	DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
	564	DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
	565	DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
	566	DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
	567	DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
	568	DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
	569	DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
be657dea AG	570	DEFINE_PROP_END_OF_LIST(),
	571	};
	572
	573	static void ipoctal_class_init(ObjectClass klass, void data)
	574	{
	575	DeviceClass *dc = DEVICE_CLASS(klass);
	576	IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
	577
5c570902	578	ic->realize = ipoctal_realize;
be657dea AG	579	ic->io_read = io_read;
	580	ic->io_write = io_write;
	581	ic->id_read = id_read;
	582	ic->id_write = id_write;
	583	ic->int_read = int_read;
	584	ic->int_write = int_write;
	585	ic->mem_read16 = mem_read16;
	586	ic->mem_write16 = mem_write16;
	587	ic->mem_read8 = mem_read8;
	588	ic->mem_write8 = mem_write8;
	589
125ee0ed	590	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
be657dea	591	dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
4f67d30b	592	device_class_set_props(dc, ipoctal_properties);
be657dea AG	593	dc->vmsd = &vmstate_ipoctal;
	594	}
	595
	596	static const TypeInfo ipoctal_info = {
	597	.name = TYPE_IPOCTAL,
	598	.parent = TYPE_IPACK_DEVICE,
	599	.instance_size = sizeof(IPOctalState),
	600	.class_init = ipoctal_class_init,
	601	};
	602
	603	static void ipoctal_register_types(void)
	604	{
	605	type_register_static(&ipoctal_info);
	606	}
	607
	608	type_init(ipoctal_register_types)