[qemu.git] / target / ppc / machine.c

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "mmu-hash64.h"
#include "migration/cpu.h"

static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    unsigned int i, j;
    target_ulong sdr1;
    uint32_t fpscr;
    target_ulong xer;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &xer);
    cpu_write_xer(env, xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &fpscr);
    env->fpscr = fpscr;
    qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->spr[SPR_ASR]);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    if (!env->external_htab) {
        ppc_store_sdr1(env, sdr1);
    }
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32(f); /* Discard unused mmu_idx */
    qemu_get_sbe32(f); /* Discard unused power_mode */

    /* Recompute mmu indices */
    hreg_compute_mem_idx(env);

    return 0;
}

static int get_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    v->u64[0] = qemu_get_be64(f);
    v->u64[1] = qemu_get_be64(f);

    return 0;
}

static void put_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    qemu_put_be64(f, v->u64[0]);
    qemu_put_be64(f, v->u64[1]);
}

static const VMStateInfo vmstate_info_avr = {
    .name = "avr",
    .get  = get_avr,
    .put  = put_avr,
};

#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)

#define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
    VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)

static bool cpu_pre_2_8_migration(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;

    return cpu->pre_2_8_migration;
}

static void cpu_pre_save(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    uint64_t insns_compat_mask =
        PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
        | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
        | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
        | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
        | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
        | PPC_64B | PPC_64BX | PPC_ALTIVEC
        | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
    uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
        | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
        | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
        | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
        | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
        | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;

    env->spr[SPR_LR] = env->lr;
    env->spr[SPR_CTR] = env->ctr;
    env->spr[SPR_XER] = cpu_read_xer(env);
#if defined(TARGET_PPC64)
    env->spr[SPR_CFAR] = env->cfar;
#endif
    env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
        env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
        env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
        env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
        env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
        env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
        env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
    }

    /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
    if (cpu->pre_2_8_migration) {
        cpu->mig_msr_mask = env->msr_mask;
        cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
        cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
        cpu->mig_nb_BATs = env->nb_BATs;
    }
}

static int cpu_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    target_ulong msr;

    /*
     * We always ignore the source PVR. The user or management
     * software has to take care of running QEMU in a compatible mode.
     */
    env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
    env->lr = env->spr[SPR_LR];
    env->ctr = env->spr[SPR_CTR];
    cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
    env->cfar = env->spr[SPR_CFAR];
#endif
    env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
        env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
        env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
        env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
        env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
        env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
        env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
    }

    if (!env->external_htab) {
        /* Restore htab_base and htab_mask variables */
        ppc_store_sdr1(env, env->spr[SPR_SDR1]);
    }

    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
    msr = env->msr;
    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
    ppc_store_msr(env, msr);

    hreg_compute_mem_idx(env);

    return 0;
}

static bool fpu_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_FLOAT);
}

static const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = fpu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
        VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool altivec_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_ALTIVEC);
}

static const VMStateDescription vmstate_altivec = {
    .name = "cpu/altivec",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = altivec_needed,
    .fields = (VMStateField[]) {
        VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
        VMSTATE_UINT32(env.vscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool vsx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags2 & PPC2_VSX);
}

static const VMStateDescription vmstate_vsx = {
    .name = "cpu/vsx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vsx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
/* Transactional memory state */
static bool tm_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    return msr_ts;
}

static const VMStateDescription vmstate_tm = {
    .name = "cpu/tm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = tm_needed,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
        VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
        VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
        VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};
#endif

static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
    PowerPCCPU *cpu = opaque;

    return !(cpu->env.mmu_model & POWERPC_MMU_64);
#else
    return true;
#endif
}

static const VMStateDescription vmstate_sr = {
    .name = "cpu/sr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = sr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
static int get_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    v->esid = qemu_get_be64(f);
    v->vsid = qemu_get_be64(f);

    return 0;
}

static void put_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    qemu_put_be64(f, v->esid);
    qemu_put_be64(f, v->vsid);
}

static const VMStateInfo vmstate_info_slbe = {
    .name = "slbe",
    .get  = get_slbe,
    .put  = put_slbe,
};

#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)

#define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
    VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)

static bool slb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    /* We don't support any of the old segment table based 64-bit CPUs */
    return (cpu->env.mmu_model & POWERPC_MMU_64);
}

static int slb_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    /* We've pulled in the raw esid and vsid values from the migration
     * stream, but we need to recompute the page size pointers */
    for (i = 0; i < env->slb_nr; i++) {
        if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
            /* Migration source had bad values in its SLB */
            return -1;
        }
    }

    return 0;
}

static const VMStateDescription vmstate_slb = {
    .name = "cpu/slb",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_needed,
    .post_load = slb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
        VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
        VMSTATE_END_OF_LIST()
    }
};
#endif /* TARGET_PPC64 */

static const VMStateDescription vmstate_tlb6xx_entry = {
    .name = "cpu/tlb6xx_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
        VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
        VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlb6xx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_6XX);
}

static const VMStateDescription vmstate_tlb6xx = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlb6xx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlb6xx_entry,
                                            ppc6xx_tlb_t),
        VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_tlbemb_entry = {
    .name = "cpu/tlbemb_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(RPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(PID, ppcemb_tlb_t),
        VMSTATE_UINTTL(size, ppcemb_tlb_t),
        VMSTATE_UINT32(prot, ppcemb_tlb_t),
        VMSTATE_UINT32(attr, ppcemb_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbemb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_EMB);
}

static bool pbr403_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    uint32_t pvr = cpu->env.spr[SPR_PVR];

    return (pvr & 0xffff0000) == 0x00200000;
}

static const VMStateDescription vmstate_pbr403 = {
    .name = "cpu/pbr403",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pbr403_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    },
};

static const VMStateDescription vmstate_tlbemb = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbemb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbemb_entry,
                                            ppcemb_tlb_t),
        /* 403 protection registers */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_pbr403,
        NULL
    }
};

static const VMStateDescription vmstate_tlbmas_entry = {
    .name = "cpu/tlbmas_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(mas8, ppcmas_tlb_t),
        VMSTATE_UINT32(mas1, ppcmas_tlb_t),
        VMSTATE_UINT64(mas2, ppcmas_tlb_t),
        VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbmas_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_MAS);
}

static const VMStateDescription vmstate_tlbmas = {
    .name = "cpu/tlbmas",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbmas_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbmas_entry,
                                            ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ppc_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .minimum_version_id_old = 4,
    .load_state_old = cpu_load_old,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */

        /* User mode architected state */
        VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
#if !defined(TARGET_PPC64)
        VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
#endif
        VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
        VMSTATE_UINTTL(env.nip, PowerPCCPU),

        /* SPRs */
        VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
        VMSTATE_UINT64(env.spe_acc, PowerPCCPU),

        /* Reservation */
        VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),

        /* Supervisor mode architected state */
        VMSTATE_UINTTL(env.msr, PowerPCCPU),

        /* Internal state */
        VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
        /* FIXME: access_type? */

        /* Sanity checking */
        VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
        VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
        VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
                            cpu_pre_2_8_migration),
        VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_fpu,
        &vmstate_altivec,
        &vmstate_vsx,
        &vmstate_sr,
#ifdef TARGET_PPC64
        &vmstate_tm,
        &vmstate_slb,
#endif /* TARGET_PPC64 */
        &vmstate_tlb6xx,
        &vmstate_tlbemb,
        &vmstate_tlbmas,
        NULL
    }
};
Commit	Line	Data
0d75590d	1	#include "qemu/osdep.h"
33c11879 PB	2	#include "qemu-common.h"
33c11879 PB	3	#include "cpu.h"
63c91552	4	#include "exec/exec-all.h"
8dd3dca3 AJ	5	#include "hw/hw.h"
8dd3dca3 AJ	6	#include "hw/boards.h"
9c17d615	7	#include "sysemu/kvm.h"
a90db158	8	#include "helper_regs.h"
cd6a9bb6	9	#include "mmu-hash64.h"
1e00b8d5	10	#include "migration/cpu.h"
8dd3dca3	11
a90db158	12	static int cpu_load_old(QEMUFile f, void opaque, int version_id)
8dd3dca3	13	{
a90db158 AK	14	PowerPCCPU *cpu = opaque;
a90db158 AK	15	CPUPPCState *env = &cpu->env;
a456d59c	16	unsigned int i, j;
bb593904	17	target_ulong sdr1;
30304420	18	uint32_t fpscr;
da91a00f	19	target_ulong xer;
a456d59c BS	20
	21	for (i = 0; i < 32; i++)
	22	qemu_get_betls(f, &env->gpr[i]);
	23	#if !defined(TARGET_PPC64)
	24	for (i = 0; i < 32; i++)
	25	qemu_get_betls(f, &env->gprh[i]);
	26	#endif
	27	qemu_get_betls(f, &env->lr);
	28	qemu_get_betls(f, &env->ctr);
	29	for (i = 0; i < 8; i++)
	30	qemu_get_be32s(f, &env->crf[i]);
da91a00f RH	31	qemu_get_betls(f, &xer);
da91a00f RH	32	cpu_write_xer(env, xer);
18b21a2f	33	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	34	qemu_get_betls(f, &env->msr);
	35	for (i = 0; i < 4; i++)
	36	qemu_get_betls(f, &env->tgpr[i]);
	37	for (i = 0; i < 32; i++) {
	38	union {
	39	float64 d;
	40	uint64_t l;
	41	} u;
	42	u.l = qemu_get_be64(f);
	43	env->fpr[i] = u.d;
	44	}
30304420 DG	45	qemu_get_be32s(f, &fpscr);
30304420 DG	46	env->fpscr = fpscr;
a456d59c	47	qemu_get_sbe32s(f, &env->access_type);
a456d59c	48	#if defined(TARGET_PPC64)
9baea4a3	49	qemu_get_betls(f, &env->spr[SPR_ASR]);
a456d59c BS	50	qemu_get_sbe32s(f, &env->slb_nr);
a456d59c BS	51	#endif
bb593904	52	qemu_get_betls(f, &sdr1);
a456d59c BS	53	for (i = 0; i < 32; i++)
	54	qemu_get_betls(f, &env->sr[i]);
	55	for (i = 0; i < 2; i++)
	56	for (j = 0; j < 8; j++)
	57	qemu_get_betls(f, &env->DBAT[i][j]);
	58	for (i = 0; i < 2; i++)
	59	for (j = 0; j < 8; j++)
	60	qemu_get_betls(f, &env->IBAT[i][j]);
	61	qemu_get_sbe32s(f, &env->nb_tlb);
	62	qemu_get_sbe32s(f, &env->tlb_per_way);
	63	qemu_get_sbe32s(f, &env->nb_ways);
	64	qemu_get_sbe32s(f, &env->last_way);
	65	qemu_get_sbe32s(f, &env->id_tlbs);
	66	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	67	if (env->tlb.tlb6) {
a456d59c BS	68	// XXX assumes 6xx
a456d59c BS	69	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	70	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	71	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	72	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	73	}
	74	}
	75	for (i = 0; i < 4; i++)
	76	qemu_get_betls(f, &env->pb[i]);
a456d59c BS	77	for (i = 0; i < 1024; i++)
a456d59c BS	78	qemu_get_betls(f, &env->spr[i]);
f3c75d42 AK	79	if (!env->external_htab) {
	80	ppc_store_sdr1(env, sdr1);
	81	}
a456d59c BS	82	qemu_get_be32s(f, &env->vscr);
	83	qemu_get_be64s(f, &env->spe_acc);
	84	qemu_get_be32s(f, &env->spe_fscr);
	85	qemu_get_betls(f, &env->msr_mask);
	86	qemu_get_be32s(f, &env->flags);
	87	qemu_get_sbe32s(f, &env->error_code);
	88	qemu_get_be32s(f, &env->pending_interrupts);
a456d59c BS	89	qemu_get_be32s(f, &env->irq_input_state);
	90	for (i = 0; i < POWERPC_EXCP_NB; i++)
	91	qemu_get_betls(f, &env->excp_vectors[i]);
	92	qemu_get_betls(f, &env->excp_prefix);
	93	qemu_get_betls(f, &env->ivor_mask);
	94	qemu_get_betls(f, &env->ivpr_mask);
	95	qemu_get_betls(f, &env->hreset_vector);
a456d59c BS	96	qemu_get_betls(f, &env->nip);
	97	qemu_get_betls(f, &env->hflags);
	98	qemu_get_betls(f, &env->hflags_nmsr);
9fb04491	99	qemu_get_sbe32(f); /* Discard unused mmu_idx */
011aba24	100	qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c	101
9fb04491 BH	102	/* Recompute mmu indices */
	103	hreg_compute_mem_idx(env);
	104
8dd3dca3 AJ	105	return 0;
8dd3dca3 AJ	106	}
a90db158 AK	107
	108	static int get_avr(QEMUFile f, void pv, size_t size)
	109	{
	110	ppc_avr_t *v = pv;
	111
	112	v->u64[0] = qemu_get_be64(f);
	113	v->u64[1] = qemu_get_be64(f);
	114
	115	return 0;
	116	}
	117
	118	static void put_avr(QEMUFile f, void pv, size_t size)
	119	{
	120	ppc_avr_t *v = pv;
	121
	122	qemu_put_be64(f, v->u64[0]);
	123	qemu_put_be64(f, v->u64[1]);
	124	}
	125
cfd54a04	126	static const VMStateInfo vmstate_info_avr = {
a90db158 AK	127	.name = "avr",
	128	.get = get_avr,
	129	.put = put_avr,
	130	};
	131
	132	#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
	133	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
	134
	135	#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
	136	VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
	137
146c11f1 DG	138	static bool cpu_pre_2_8_migration(void *opaque, int version_id)
	139	{
	140	PowerPCCPU *cpu = opaque;
	141
	142	return cpu->pre_2_8_migration;
	143	}
	144
a90db158 AK	145	static void cpu_pre_save(void *opaque)
	146	{
	147	PowerPCCPU *cpu = opaque;
	148	CPUPPCState *env = &cpu->env;
	149	int i;
16a2497b DG	150	uint64_t insns_compat_mask =
	151	PPC_INSNS_BASE \| PPC_ISEL \| PPC_STRING \| PPC_MFTB
	152	\| PPC_FLOAT \| PPC_FLOAT_FSEL \| PPC_FLOAT_FRES
	153	\| PPC_FLOAT_FSQRT \| PPC_FLOAT_FRSQRTE \| PPC_FLOAT_FRSQRTES
	154	\| PPC_FLOAT_STFIWX \| PPC_FLOAT_EXT
	155	\| PPC_CACHE \| PPC_CACHE_ICBI \| PPC_CACHE_DCBZ
	156	\| PPC_MEM_SYNC \| PPC_MEM_EIEIO \| PPC_MEM_TLBIE \| PPC_MEM_TLBSYNC
	157	\| PPC_64B \| PPC_64BX \| PPC_ALTIVEC
	158	\| PPC_SEGMENT_64B \| PPC_SLBI \| PPC_POPCNTB \| PPC_POPCNTWD;
	159	uint64_t insns_compat_mask2 = PPC2_VSX \| PPC2_VSX207 \| PPC2_DFP \| PPC2_DBRX
	160	\| PPC2_PERM_ISA206 \| PPC2_DIVE_ISA206
	161	\| PPC2_ATOMIC_ISA206 \| PPC2_FP_CVT_ISA206
	162	\| PPC2_FP_TST_ISA206 \| PPC2_BCTAR_ISA207
	163	\| PPC2_LSQ_ISA207 \| PPC2_ALTIVEC_207
	164	\| PPC2_ISA205 \| PPC2_ISA207S \| PPC2_FP_CVT_S64 \| PPC2_TM;
a90db158 AK	165
	166	env->spr[SPR_LR] = env->lr;
	167	env->spr[SPR_CTR] = env->ctr;
aa378598	168	env->spr[SPR_XER] = cpu_read_xer(env);
a90db158 AK	169	#if defined(TARGET_PPC64)
	170	env->spr[SPR_CFAR] = env->cfar;
	171	#endif
	172	env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
	173
	174	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	175	env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
	176	env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
	177	env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
	178	env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
	179	}
	180	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	181	env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
	182	env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
	183	env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
	184	env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
	185	}
16a2497b DG	186
16a2497b DG	187	/* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
146c11f1 DG	188	if (cpu->pre_2_8_migration) {
	189	cpu->mig_msr_mask = env->msr_mask;
	190	cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
	191	cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
	192	cpu->mig_nb_BATs = env->nb_BATs;
	193	}
a90db158 AK	194	}
	195
	196	static int cpu_post_load(void *opaque, int version_id)
	197	{
	198	PowerPCCPU *cpu = opaque;
	199	CPUPPCState *env = &cpu->env;
	200	int i;
2360b6e8	201	target_ulong msr;
a90db158	202
569be9f0 AK	203	/*
	204	* We always ignore the source PVR. The user or management
	205	* software has to take care of running QEMU in a compatible mode.
	206	*/
	207	env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
a90db158 AK	208	env->lr = env->spr[SPR_LR];
a90db158 AK	209	env->ctr = env->spr[SPR_CTR];
6a9620e6	210	cpu_write_xer(env, env->spr[SPR_XER]);
a90db158 AK	211	#if defined(TARGET_PPC64)
	212	env->cfar = env->spr[SPR_CFAR];
	213	#endif
	214	env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
	215
	216	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	217	env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
	218	env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
	219	env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
	220	env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
	221	}
	222	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	223	env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
	224	env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
	225	env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
	226	env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
	227	}
	228
f3c75d42 AK	229	if (!env->external_htab) {
	230	/* Restore htab_base and htab_mask variables */
	231	ppc_store_sdr1(env, env->spr[SPR_SDR1]);
	232	}
2360b6e8	233
993ebe4a	234	/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
2360b6e8	235	msr = env->msr;
993ebe4a	236	env->msr ^= ~((1ULL << MSR_TGPR) \| MSR_HVB);
2360b6e8 MCA	237	ppc_store_msr(env, msr);
2360b6e8 MCA	238
a90db158 AK	239	hreg_compute_mem_idx(env);
	240
	241	return 0;
	242	}
	243
	244	static bool fpu_needed(void *opaque)
	245	{
	246	PowerPCCPU *cpu = opaque;
	247
	248	return (cpu->env.insns_flags & PPC_FLOAT);
	249	}
	250
	251	static const VMStateDescription vmstate_fpu = {
	252	.name = "cpu/fpu",
	253	.version_id = 1,
	254	.minimum_version_id = 1,
5cd8cada	255	.needed = fpu_needed,
3aff6c2f	256	.fields = (VMStateField[]) {
a90db158 AK	257	VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
	258	VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
	259	VMSTATE_END_OF_LIST()
	260	},
	261	};
	262
	263	static bool altivec_needed(void *opaque)
	264	{
	265	PowerPCCPU *cpu = opaque;
	266
	267	return (cpu->env.insns_flags & PPC_ALTIVEC);
	268	}
	269
	270	static const VMStateDescription vmstate_altivec = {
	271	.name = "cpu/altivec",
	272	.version_id = 1,
	273	.minimum_version_id = 1,
5cd8cada	274	.needed = altivec_needed,
3aff6c2f	275	.fields = (VMStateField[]) {
a90db158 AK	276	VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
	277	VMSTATE_UINT32(env.vscr, PowerPCCPU),
	278	VMSTATE_END_OF_LIST()
	279	},
	280	};
	281
	282	static bool vsx_needed(void *opaque)
	283	{
	284	PowerPCCPU *cpu = opaque;
	285
	286	return (cpu->env.insns_flags2 & PPC2_VSX);
	287	}
	288
	289	static const VMStateDescription vmstate_vsx = {
	290	.name = "cpu/vsx",
	291	.version_id = 1,
	292	.minimum_version_id = 1,
5cd8cada	293	.needed = vsx_needed,
3aff6c2f	294	.fields = (VMStateField[]) {
a90db158 AK	295	VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
	296	VMSTATE_END_OF_LIST()
	297	},
	298	};
	299
80b3f79b AK	300	#ifdef TARGET_PPC64
	301	/* Transactional memory state */
	302	static bool tm_needed(void *opaque)
	303	{
	304	PowerPCCPU *cpu = opaque;
	305	CPUPPCState *env = &cpu->env;
	306	return msr_ts;
	307	}
	308
	309	static const VMStateDescription vmstate_tm = {
	310	.name = "cpu/tm",
	311	.version_id = 1,
	312	.minimum_version_id = 1,
	313	.minimum_version_id_old = 1,
5cd8cada	314	.needed = tm_needed,
80b3f79b AK	315	.fields = (VMStateField []) {
	316	VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
	317	VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
	318	VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
	319	VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
	320	VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
	321	VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
	322	VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
	323	VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
	324	VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
	325	VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
	326	VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
	327	VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
	328	VMSTATE_END_OF_LIST()
	329	},
	330	};
	331	#endif
	332
a90db158 AK	333	static bool sr_needed(void *opaque)
	334	{
	335	#ifdef TARGET_PPC64
	336	PowerPCCPU *cpu = opaque;
	337
	338	return !(cpu->env.mmu_model & POWERPC_MMU_64);
	339	#else
	340	return true;
	341	#endif
	342	}
	343
	344	static const VMStateDescription vmstate_sr = {
	345	.name = "cpu/sr",
	346	.version_id = 1,
	347	.minimum_version_id = 1,
5cd8cada	348	.needed = sr_needed,
3aff6c2f	349	.fields = (VMStateField[]) {
a90db158 AK	350	VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
	351	VMSTATE_END_OF_LIST()
	352	},
	353	};
	354
	355	#ifdef TARGET_PPC64
	356	static int get_slbe(QEMUFile f, void pv, size_t size)
	357	{
	358	ppc_slb_t *v = pv;
	359
	360	v->esid = qemu_get_be64(f);
	361	v->vsid = qemu_get_be64(f);
	362
	363	return 0;
	364	}
	365
	366	static void put_slbe(QEMUFile f, void pv, size_t size)
	367	{
	368	ppc_slb_t *v = pv;
	369
	370	qemu_put_be64(f, v->esid);
	371	qemu_put_be64(f, v->vsid);
	372	}
	373
cfd54a04	374	static const VMStateInfo vmstate_info_slbe = {
a90db158 AK	375	.name = "slbe",
	376	.get = get_slbe,
	377	.put = put_slbe,
	378	};
	379
	380	#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
	381	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
	382
	383	#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
	384	VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
	385
	386	static bool slb_needed(void *opaque)
	387	{
	388	PowerPCCPU *cpu = opaque;
	389
	390	/* We don't support any of the old segment table based 64-bit CPUs */
	391	return (cpu->env.mmu_model & POWERPC_MMU_64);
	392	}
	393
cd6a9bb6 DG	394	static int slb_post_load(void *opaque, int version_id)
	395	{
	396	PowerPCCPU *cpu = opaque;
	397	CPUPPCState *env = &cpu->env;
	398	int i;
	399
	400	/* We've pulled in the raw esid and vsid values from the migration
	401	* stream, but we need to recompute the page size pointers */
	402	for (i = 0; i < env->slb_nr; i++) {
	403	if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
	404	/* Migration source had bad values in its SLB */
	405	return -1;
	406	}
	407	}
	408
	409	return 0;
	410	}
	411
a90db158 AK	412	static const VMStateDescription vmstate_slb = {
	413	.name = "cpu/slb",
	414	.version_id = 1,
	415	.minimum_version_id = 1,
5cd8cada	416	.needed = slb_needed,
cd6a9bb6	417	.post_load = slb_post_load,
3aff6c2f	418	.fields = (VMStateField[]) {
a90db158	419	VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
d83af167	420	VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
a90db158 AK	421	VMSTATE_END_OF_LIST()
	422	}
	423	};
	424	#endif /* TARGET_PPC64 */
	425
	426	static const VMStateDescription vmstate_tlb6xx_entry = {
	427	.name = "cpu/tlb6xx_entry",
	428	.version_id = 1,
	429	.minimum_version_id = 1,
3aff6c2f	430	.fields = (VMStateField[]) {
a90db158 AK	431	VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
	432	VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
	433	VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
	434	VMSTATE_END_OF_LIST()
	435	},
	436	};
	437
	438	static bool tlb6xx_needed(void *opaque)
	439	{
	440	PowerPCCPU *cpu = opaque;
	441	CPUPPCState *env = &cpu->env;
	442
	443	return env->nb_tlb && (env->tlb_type == TLB_6XX);
	444	}
	445
	446	static const VMStateDescription vmstate_tlb6xx = {
	447	.name = "cpu/tlb6xx",
	448	.version_id = 1,
	449	.minimum_version_id = 1,
5cd8cada	450	.needed = tlb6xx_needed,
3aff6c2f	451	.fields = (VMStateField[]) {
a90db158 AK	452	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	453	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
	454	env.nb_tlb,
	455	vmstate_tlb6xx_entry,
	456	ppc6xx_tlb_t),
	457	VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
	458	VMSTATE_END_OF_LIST()
	459	}
	460	};
	461
	462	static const VMStateDescription vmstate_tlbemb_entry = {
	463	.name = "cpu/tlbemb_entry",
	464	.version_id = 1,
	465	.minimum_version_id = 1,
3aff6c2f	466	.fields = (VMStateField[]) {
a90db158 AK	467	VMSTATE_UINT64(RPN, ppcemb_tlb_t),
	468	VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
	469	VMSTATE_UINTTL(PID, ppcemb_tlb_t),
	470	VMSTATE_UINTTL(size, ppcemb_tlb_t),
	471	VMSTATE_UINT32(prot, ppcemb_tlb_t),
	472	VMSTATE_UINT32(attr, ppcemb_tlb_t),
	473	VMSTATE_END_OF_LIST()
	474	},
	475	};
	476
	477	static bool tlbemb_needed(void *opaque)
	478	{
	479	PowerPCCPU *cpu = opaque;
	480	CPUPPCState *env = &cpu->env;
	481
	482	return env->nb_tlb && (env->tlb_type == TLB_EMB);
	483	}
	484
	485	static bool pbr403_needed(void *opaque)
	486	{
	487	PowerPCCPU *cpu = opaque;
	488	uint32_t pvr = cpu->env.spr[SPR_PVR];
	489
	490	return (pvr & 0xffff0000) == 0x00200000;
	491	}
	492
	493	static const VMStateDescription vmstate_pbr403 = {
	494	.name = "cpu/pbr403",
	495	.version_id = 1,
	496	.minimum_version_id = 1,
5cd8cada	497	.needed = pbr403_needed,
3aff6c2f	498	.fields = (VMStateField[]) {
a90db158 AK	499	VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
	500	VMSTATE_END_OF_LIST()
	501	},
	502	};
	503
	504	static const VMStateDescription vmstate_tlbemb = {
	505	.name = "cpu/tlb6xx",
	506	.version_id = 1,
	507	.minimum_version_id = 1,
5cd8cada	508	.needed = tlbemb_needed,
3aff6c2f	509	.fields = (VMStateField[]) {
a90db158 AK	510	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	511	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
	512	env.nb_tlb,
	513	vmstate_tlbemb_entry,
	514	ppcemb_tlb_t),
	515	/* 403 protection registers */
	516	VMSTATE_END_OF_LIST()
	517	},
5cd8cada JQ	518	.subsections = (const VMStateDescription*[]) {
	519	&vmstate_pbr403,
	520	NULL
a90db158 AK	521	}
	522	};
	523
	524	static const VMStateDescription vmstate_tlbmas_entry = {
	525	.name = "cpu/tlbmas_entry",
	526	.version_id = 1,
	527	.minimum_version_id = 1,
3aff6c2f	528	.fields = (VMStateField[]) {
a90db158 AK	529	VMSTATE_UINT32(mas8, ppcmas_tlb_t),
	530	VMSTATE_UINT32(mas1, ppcmas_tlb_t),
	531	VMSTATE_UINT64(mas2, ppcmas_tlb_t),
	532	VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
	533	VMSTATE_END_OF_LIST()
	534	},
	535	};
	536
	537	static bool tlbmas_needed(void *opaque)
	538	{
	539	PowerPCCPU *cpu = opaque;
	540	CPUPPCState *env = &cpu->env;
	541
	542	return env->nb_tlb && (env->tlb_type == TLB_MAS);
	543	}
	544
	545	static const VMStateDescription vmstate_tlbmas = {
	546	.name = "cpu/tlbmas",
	547	.version_id = 1,
	548	.minimum_version_id = 1,
5cd8cada	549	.needed = tlbmas_needed,
3aff6c2f	550	.fields = (VMStateField[]) {
a90db158 AK	551	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	552	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
	553	env.nb_tlb,
	554	vmstate_tlbmas_entry,
	555	ppcmas_tlb_t),
	556	VMSTATE_END_OF_LIST()
	557	}
	558	};
	559
	560	const VMStateDescription vmstate_ppc_cpu = {
	561	.name = "cpu",
	562	.version_id = 5,
	563	.minimum_version_id = 5,
	564	.minimum_version_id_old = 4,
	565	.load_state_old = cpu_load_old,
	566	.pre_save = cpu_pre_save,
	567	.post_load = cpu_post_load,
3aff6c2f	568	.fields = (VMStateField[]) {
569be9f0	569	VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
a90db158 AK	570
	571	/* User mode architected state */
	572	VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
	573	#if !defined(TARGET_PPC64)
	574	VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
	575	#endif
	576	VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
	577	VMSTATE_UINTTL(env.nip, PowerPCCPU),
	578
	579	/* SPRs */
	580	VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
	581	VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
	582
	583	/* Reservation */
	584	VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
	585
	586	/* Supervisor mode architected state */
	587	VMSTATE_UINTTL(env.msr, PowerPCCPU),
	588
	589	/* Internal state */
	590	VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
	591	/* FIXME: access_type? */
	592
	593	/* Sanity checking */
146c11f1 DG	594	VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
	595	VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
	596	VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
	597	cpu_pre_2_8_migration),
	598	VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
a90db158 AK	599	VMSTATE_END_OF_LIST()
a90db158 AK	600	},
5cd8cada JQ	601	.subsections = (const VMStateDescription*[]) {
	602	&vmstate_fpu,
	603	&vmstate_altivec,
	604	&vmstate_vsx,
	605	&vmstate_sr,
a90db158	606	#ifdef TARGET_PPC64
5cd8cada JQ	607	&vmstate_tm,
5cd8cada JQ	608	&vmstate_slb,
a90db158	609	#endif /* TARGET_PPC64 */
5cd8cada JQ	610	&vmstate_tlb6xx,
	611	&vmstate_tlbemb,
	612	&vmstate_tlbmas,
	613	NULL
a90db158 AK	614	}
a90db158 AK	615	};