[qemu.git] / target-ppc / machine.c

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "mmu-hash64.h"
#include "migration/cpu.h"
#include "exec/exec-all.h"

static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    unsigned int i, j;
    target_ulong sdr1;
    uint32_t fpscr;
    target_ulong xer;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &xer);
    cpu_write_xer(env, xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &fpscr);
    env->fpscr = fpscr;
    qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->spr[SPR_ASR]);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    if (!env->external_htab) {
        ppc_store_sdr1(env, sdr1);
    }
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32s(f, &env->mmu_idx);
    qemu_get_sbe32(f); /* Discard unused power_mode */

    return 0;
}

static int get_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    v->u64[0] = qemu_get_be64(f);
    v->u64[1] = qemu_get_be64(f);

    return 0;
}

static void put_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    qemu_put_be64(f, v->u64[0]);
    qemu_put_be64(f, v->u64[1]);
}

static const VMStateInfo vmstate_info_avr = {
    .name = "avr",
    .get  = get_avr,
    .put  = put_avr,
};

#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)

#define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
    VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)

static void cpu_pre_save(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    env->spr[SPR_LR] = env->lr;
    env->spr[SPR_CTR] = env->ctr;
    env->spr[SPR_XER] = cpu_read_xer(env);
#if defined(TARGET_PPC64)
    env->spr[SPR_CFAR] = env->cfar;
#endif
    env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
        env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
        env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
        env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
        env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
        env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
        env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
    }
}

static int cpu_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    target_ulong msr;

    /*
     * We always ignore the source PVR. The user or management
     * software has to take care of running QEMU in a compatible mode.
     */
    env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
    env->lr = env->spr[SPR_LR];
    env->ctr = env->spr[SPR_CTR];
    cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
    env->cfar = env->spr[SPR_CFAR];
#endif
    env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
        env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
        env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
        env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
        env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
        env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
        env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
    }

    if (!env->external_htab) {
        /* Restore htab_base and htab_mask variables */
        ppc_store_sdr1(env, env->spr[SPR_SDR1]);
    }

    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
    msr = env->msr;
    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
    ppc_store_msr(env, msr);

    hreg_compute_mem_idx(env);

    return 0;
}

static bool fpu_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_FLOAT);
}

static const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = fpu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
        VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool altivec_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_ALTIVEC);
}

static const VMStateDescription vmstate_altivec = {
    .name = "cpu/altivec",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = altivec_needed,
    .fields = (VMStateField[]) {
        VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
        VMSTATE_UINT32(env.vscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool vsx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags2 & PPC2_VSX);
}

static const VMStateDescription vmstate_vsx = {
    .name = "cpu/vsx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vsx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
/* Transactional memory state */
static bool tm_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    return msr_ts;
}

static const VMStateDescription vmstate_tm = {
    .name = "cpu/tm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = tm_needed,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
        VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
        VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
        VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};
#endif

static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
    PowerPCCPU *cpu = opaque;

    return !(cpu->env.mmu_model & POWERPC_MMU_64);
#else
    return true;
#endif
}

static const VMStateDescription vmstate_sr = {
    .name = "cpu/sr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = sr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
static int get_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    v->esid = qemu_get_be64(f);
    v->vsid = qemu_get_be64(f);

    return 0;
}

static void put_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    qemu_put_be64(f, v->esid);
    qemu_put_be64(f, v->vsid);
}

static const VMStateInfo vmstate_info_slbe = {
    .name = "slbe",
    .get  = get_slbe,
    .put  = put_slbe,
};

#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)

#define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
    VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)

static bool slb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    /* We don't support any of the old segment table based 64-bit CPUs */
    return (cpu->env.mmu_model & POWERPC_MMU_64);
}

static int slb_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    /* We've pulled in the raw esid and vsid values from the migration
     * stream, but we need to recompute the page size pointers */
    for (i = 0; i < env->slb_nr; i++) {
        if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
            /* Migration source had bad values in its SLB */
            return -1;
        }
    }

    return 0;
}

static const VMStateDescription vmstate_slb = {
    .name = "cpu/slb",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_needed,
    .post_load = slb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
        VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
        VMSTATE_END_OF_LIST()
    }
};
#endif /* TARGET_PPC64 */

static const VMStateDescription vmstate_tlb6xx_entry = {
    .name = "cpu/tlb6xx_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
        VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
        VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlb6xx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_6XX);
}

static const VMStateDescription vmstate_tlb6xx = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlb6xx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlb6xx_entry,
                                            ppc6xx_tlb_t),
        VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_tlbemb_entry = {
    .name = "cpu/tlbemb_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(RPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(PID, ppcemb_tlb_t),
        VMSTATE_UINTTL(size, ppcemb_tlb_t),
        VMSTATE_UINT32(prot, ppcemb_tlb_t),
        VMSTATE_UINT32(attr, ppcemb_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbemb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_EMB);
}

static bool pbr403_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    uint32_t pvr = cpu->env.spr[SPR_PVR];

    return (pvr & 0xffff0000) == 0x00200000;
}

static const VMStateDescription vmstate_pbr403 = {
    .name = "cpu/pbr403",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pbr403_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    },
};

static const VMStateDescription vmstate_tlbemb = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbemb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbemb_entry,
                                            ppcemb_tlb_t),
        /* 403 protection registers */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_pbr403,
        NULL
    }
};

static const VMStateDescription vmstate_tlbmas_entry = {
    .name = "cpu/tlbmas_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(mas8, ppcmas_tlb_t),
        VMSTATE_UINT32(mas1, ppcmas_tlb_t),
        VMSTATE_UINT64(mas2, ppcmas_tlb_t),
        VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbmas_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_MAS);
}

static const VMStateDescription vmstate_tlbmas = {
    .name = "cpu/tlbmas",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbmas_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbmas_entry,
                                            ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ppc_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .minimum_version_id_old = 4,
    .load_state_old = cpu_load_old,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */

        /* User mode architected state */
        VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
#if !defined(TARGET_PPC64)
        VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
#endif
        VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
        VMSTATE_UINTTL(env.nip, PowerPCCPU),

        /* SPRs */
        VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
        VMSTATE_UINT64(env.spe_acc, PowerPCCPU),

        /* Reservation */
        VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),

        /* Supervisor mode architected state */
        VMSTATE_UINTTL(env.msr, PowerPCCPU),

        /* Internal state */
        VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
        /* FIXME: access_type? */

        /* Sanity checking */
        VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
        VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_fpu,
        &vmstate_altivec,
        &vmstate_vsx,
        &vmstate_sr,
#ifdef TARGET_PPC64
        &vmstate_tm,
        &vmstate_slb,
#endif /* TARGET_PPC64 */
        &vmstate_tlb6xx,
        &vmstate_tlbemb,
        &vmstate_tlbmas,
        NULL
    }
};
Commit	Line	Data
0d75590d	1	#include "qemu/osdep.h"
33c11879 PB	2	#include "qemu-common.h"
33c11879 PB	3	#include "cpu.h"
63c91552	4	#include "exec/exec-all.h"
8dd3dca3 AJ	5	#include "hw/hw.h"
8dd3dca3 AJ	6	#include "hw/boards.h"
9c17d615	7	#include "sysemu/kvm.h"
a90db158	8	#include "helper_regs.h"
cd6a9bb6	9	#include "mmu-hash64.h"
1e00b8d5	10	#include "migration/cpu.h"
63c91552	11	#include "exec/exec-all.h"
8dd3dca3	12
a90db158	13	static int cpu_load_old(QEMUFile f, void opaque, int version_id)
8dd3dca3	14	{
a90db158 AK	15	PowerPCCPU *cpu = opaque;
a90db158 AK	16	CPUPPCState *env = &cpu->env;
a456d59c	17	unsigned int i, j;
bb593904	18	target_ulong sdr1;
30304420	19	uint32_t fpscr;
da91a00f	20	target_ulong xer;
a456d59c BS	21
	22	for (i = 0; i < 32; i++)
	23	qemu_get_betls(f, &env->gpr[i]);
	24	#if !defined(TARGET_PPC64)
	25	for (i = 0; i < 32; i++)
	26	qemu_get_betls(f, &env->gprh[i]);
	27	#endif
	28	qemu_get_betls(f, &env->lr);
	29	qemu_get_betls(f, &env->ctr);
	30	for (i = 0; i < 8; i++)
	31	qemu_get_be32s(f, &env->crf[i]);
da91a00f RH	32	qemu_get_betls(f, &xer);
da91a00f RH	33	cpu_write_xer(env, xer);
18b21a2f	34	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	35	qemu_get_betls(f, &env->msr);
	36	for (i = 0; i < 4; i++)
	37	qemu_get_betls(f, &env->tgpr[i]);
	38	for (i = 0; i < 32; i++) {
	39	union {
	40	float64 d;
	41	uint64_t l;
	42	} u;
	43	u.l = qemu_get_be64(f);
	44	env->fpr[i] = u.d;
	45	}
30304420 DG	46	qemu_get_be32s(f, &fpscr);
30304420 DG	47	env->fpscr = fpscr;
a456d59c	48	qemu_get_sbe32s(f, &env->access_type);
a456d59c	49	#if defined(TARGET_PPC64)
9baea4a3	50	qemu_get_betls(f, &env->spr[SPR_ASR]);
a456d59c BS	51	qemu_get_sbe32s(f, &env->slb_nr);
a456d59c BS	52	#endif
bb593904	53	qemu_get_betls(f, &sdr1);
a456d59c BS	54	for (i = 0; i < 32; i++)
	55	qemu_get_betls(f, &env->sr[i]);
	56	for (i = 0; i < 2; i++)
	57	for (j = 0; j < 8; j++)
	58	qemu_get_betls(f, &env->DBAT[i][j]);
	59	for (i = 0; i < 2; i++)
	60	for (j = 0; j < 8; j++)
	61	qemu_get_betls(f, &env->IBAT[i][j]);
	62	qemu_get_sbe32s(f, &env->nb_tlb);
	63	qemu_get_sbe32s(f, &env->tlb_per_way);
	64	qemu_get_sbe32s(f, &env->nb_ways);
	65	qemu_get_sbe32s(f, &env->last_way);
	66	qemu_get_sbe32s(f, &env->id_tlbs);
	67	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	68	if (env->tlb.tlb6) {
a456d59c BS	69	// XXX assumes 6xx
a456d59c BS	70	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	71	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	72	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	73	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	74	}
	75	}
	76	for (i = 0; i < 4; i++)
	77	qemu_get_betls(f, &env->pb[i]);
a456d59c BS	78	for (i = 0; i < 1024; i++)
a456d59c BS	79	qemu_get_betls(f, &env->spr[i]);
f3c75d42 AK	80	if (!env->external_htab) {
	81	ppc_store_sdr1(env, sdr1);
	82	}
a456d59c BS	83	qemu_get_be32s(f, &env->vscr);
	84	qemu_get_be64s(f, &env->spe_acc);
	85	qemu_get_be32s(f, &env->spe_fscr);
	86	qemu_get_betls(f, &env->msr_mask);
	87	qemu_get_be32s(f, &env->flags);
	88	qemu_get_sbe32s(f, &env->error_code);
	89	qemu_get_be32s(f, &env->pending_interrupts);
a456d59c BS	90	qemu_get_be32s(f, &env->irq_input_state);
	91	for (i = 0; i < POWERPC_EXCP_NB; i++)
	92	qemu_get_betls(f, &env->excp_vectors[i]);
	93	qemu_get_betls(f, &env->excp_prefix);
	94	qemu_get_betls(f, &env->ivor_mask);
	95	qemu_get_betls(f, &env->ivpr_mask);
	96	qemu_get_betls(f, &env->hreset_vector);
a456d59c BS	97	qemu_get_betls(f, &env->nip);
	98	qemu_get_betls(f, &env->hflags);
	99	qemu_get_betls(f, &env->hflags_nmsr);
	100	qemu_get_sbe32s(f, &env->mmu_idx);
011aba24	101	qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c	102
8dd3dca3 AJ	103	return 0;
8dd3dca3 AJ	104	}
a90db158 AK	105
	106	static int get_avr(QEMUFile f, void pv, size_t size)
	107	{
	108	ppc_avr_t *v = pv;
	109
	110	v->u64[0] = qemu_get_be64(f);
	111	v->u64[1] = qemu_get_be64(f);
	112
	113	return 0;
	114	}
	115
	116	static void put_avr(QEMUFile f, void pv, size_t size)
	117	{
	118	ppc_avr_t *v = pv;
	119
	120	qemu_put_be64(f, v->u64[0]);
	121	qemu_put_be64(f, v->u64[1]);
	122	}
	123
cfd54a04	124	static const VMStateInfo vmstate_info_avr = {
a90db158 AK	125	.name = "avr",
	126	.get = get_avr,
	127	.put = put_avr,
	128	};
	129
	130	#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
	131	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
	132
	133	#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
	134	VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
	135
	136	static void cpu_pre_save(void *opaque)
	137	{
	138	PowerPCCPU *cpu = opaque;
	139	CPUPPCState *env = &cpu->env;
	140	int i;
	141
	142	env->spr[SPR_LR] = env->lr;
	143	env->spr[SPR_CTR] = env->ctr;
aa378598	144	env->spr[SPR_XER] = cpu_read_xer(env);
a90db158 AK	145	#if defined(TARGET_PPC64)
	146	env->spr[SPR_CFAR] = env->cfar;
	147	#endif
	148	env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
	149
	150	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	151	env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
	152	env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
	153	env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
	154	env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
	155	}
	156	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	157	env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
	158	env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
	159	env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
	160	env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
	161	}
	162	}
	163
	164	static int cpu_post_load(void *opaque, int version_id)
	165	{
	166	PowerPCCPU *cpu = opaque;
	167	CPUPPCState *env = &cpu->env;
	168	int i;
2360b6e8	169	target_ulong msr;
a90db158	170
569be9f0 AK	171	/*
	172	* We always ignore the source PVR. The user or management
	173	* software has to take care of running QEMU in a compatible mode.
	174	*/
	175	env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
a90db158 AK	176	env->lr = env->spr[SPR_LR];
a90db158 AK	177	env->ctr = env->spr[SPR_CTR];
6a9620e6	178	cpu_write_xer(env, env->spr[SPR_XER]);
a90db158 AK	179	#if defined(TARGET_PPC64)
	180	env->cfar = env->spr[SPR_CFAR];
	181	#endif
	182	env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
	183
	184	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	185	env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
	186	env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
	187	env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
	188	env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
	189	}
	190	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	191	env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
	192	env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
	193	env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
	194	env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
	195	}
	196
f3c75d42 AK	197	if (!env->external_htab) {
	198	/* Restore htab_base and htab_mask variables */
	199	ppc_store_sdr1(env, env->spr[SPR_SDR1]);
	200	}
2360b6e8	201
993ebe4a	202	/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
2360b6e8	203	msr = env->msr;
993ebe4a	204	env->msr ^= ~((1ULL << MSR_TGPR) \| MSR_HVB);
2360b6e8 MCA	205	ppc_store_msr(env, msr);
2360b6e8 MCA	206
a90db158 AK	207	hreg_compute_mem_idx(env);
	208
	209	return 0;
	210	}
	211
	212	static bool fpu_needed(void *opaque)
	213	{
	214	PowerPCCPU *cpu = opaque;
	215
	216	return (cpu->env.insns_flags & PPC_FLOAT);
	217	}
	218
	219	static const VMStateDescription vmstate_fpu = {
	220	.name = "cpu/fpu",
	221	.version_id = 1,
	222	.minimum_version_id = 1,
5cd8cada	223	.needed = fpu_needed,
3aff6c2f	224	.fields = (VMStateField[]) {
a90db158 AK	225	VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
	226	VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
	227	VMSTATE_END_OF_LIST()
	228	},
	229	};
	230
	231	static bool altivec_needed(void *opaque)
	232	{
	233	PowerPCCPU *cpu = opaque;
	234
	235	return (cpu->env.insns_flags & PPC_ALTIVEC);
	236	}
	237
	238	static const VMStateDescription vmstate_altivec = {
	239	.name = "cpu/altivec",
	240	.version_id = 1,
	241	.minimum_version_id = 1,
5cd8cada	242	.needed = altivec_needed,
3aff6c2f	243	.fields = (VMStateField[]) {
a90db158 AK	244	VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
	245	VMSTATE_UINT32(env.vscr, PowerPCCPU),
	246	VMSTATE_END_OF_LIST()
	247	},
	248	};
	249
	250	static bool vsx_needed(void *opaque)
	251	{
	252	PowerPCCPU *cpu = opaque;
	253
	254	return (cpu->env.insns_flags2 & PPC2_VSX);
	255	}
	256
	257	static const VMStateDescription vmstate_vsx = {
	258	.name = "cpu/vsx",
	259	.version_id = 1,
	260	.minimum_version_id = 1,
5cd8cada	261	.needed = vsx_needed,
3aff6c2f	262	.fields = (VMStateField[]) {
a90db158 AK	263	VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
	264	VMSTATE_END_OF_LIST()
	265	},
	266	};
	267
80b3f79b AK	268	#ifdef TARGET_PPC64
	269	/* Transactional memory state */
	270	static bool tm_needed(void *opaque)
	271	{
	272	PowerPCCPU *cpu = opaque;
	273	CPUPPCState *env = &cpu->env;
	274	return msr_ts;
	275	}
	276
	277	static const VMStateDescription vmstate_tm = {
	278	.name = "cpu/tm",
	279	.version_id = 1,
	280	.minimum_version_id = 1,
	281	.minimum_version_id_old = 1,
5cd8cada	282	.needed = tm_needed,
80b3f79b AK	283	.fields = (VMStateField []) {
	284	VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
	285	VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
	286	VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
	287	VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
	288	VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
	289	VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
	290	VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
	291	VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
	292	VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
	293	VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
	294	VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
	295	VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
	296	VMSTATE_END_OF_LIST()
	297	},
	298	};
	299	#endif
	300
a90db158 AK	301	static bool sr_needed(void *opaque)
	302	{
	303	#ifdef TARGET_PPC64
	304	PowerPCCPU *cpu = opaque;
	305
	306	return !(cpu->env.mmu_model & POWERPC_MMU_64);
	307	#else
	308	return true;
	309	#endif
	310	}
	311
	312	static const VMStateDescription vmstate_sr = {
	313	.name = "cpu/sr",
	314	.version_id = 1,
	315	.minimum_version_id = 1,
5cd8cada	316	.needed = sr_needed,
3aff6c2f	317	.fields = (VMStateField[]) {
a90db158 AK	318	VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
	319	VMSTATE_END_OF_LIST()
	320	},
	321	};
	322
	323	#ifdef TARGET_PPC64
	324	static int get_slbe(QEMUFile f, void pv, size_t size)
	325	{
	326	ppc_slb_t *v = pv;
	327
	328	v->esid = qemu_get_be64(f);
	329	v->vsid = qemu_get_be64(f);
	330
	331	return 0;
	332	}
	333
	334	static void put_slbe(QEMUFile f, void pv, size_t size)
	335	{
	336	ppc_slb_t *v = pv;
	337
	338	qemu_put_be64(f, v->esid);
	339	qemu_put_be64(f, v->vsid);
	340	}
	341
cfd54a04	342	static const VMStateInfo vmstate_info_slbe = {
a90db158 AK	343	.name = "slbe",
	344	.get = get_slbe,
	345	.put = put_slbe,
	346	};
	347
	348	#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
	349	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
	350
	351	#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
	352	VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
	353
	354	static bool slb_needed(void *opaque)
	355	{
	356	PowerPCCPU *cpu = opaque;
	357
	358	/* We don't support any of the old segment table based 64-bit CPUs */
	359	return (cpu->env.mmu_model & POWERPC_MMU_64);
	360	}
	361
cd6a9bb6 DG	362	static int slb_post_load(void *opaque, int version_id)
	363	{
	364	PowerPCCPU *cpu = opaque;
	365	CPUPPCState *env = &cpu->env;
	366	int i;
	367
	368	/* We've pulled in the raw esid and vsid values from the migration
	369	* stream, but we need to recompute the page size pointers */
	370	for (i = 0; i < env->slb_nr; i++) {
	371	if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
	372	/* Migration source had bad values in its SLB */
	373	return -1;
	374	}
	375	}
	376
	377	return 0;
	378	}
	379
a90db158 AK	380	static const VMStateDescription vmstate_slb = {
	381	.name = "cpu/slb",
	382	.version_id = 1,
	383	.minimum_version_id = 1,
5cd8cada	384	.needed = slb_needed,
cd6a9bb6	385	.post_load = slb_post_load,
3aff6c2f	386	.fields = (VMStateField[]) {
a90db158	387	VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
d83af167	388	VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
a90db158 AK	389	VMSTATE_END_OF_LIST()
	390	}
	391	};
	392	#endif /* TARGET_PPC64 */
	393
	394	static const VMStateDescription vmstate_tlb6xx_entry = {
	395	.name = "cpu/tlb6xx_entry",
	396	.version_id = 1,
	397	.minimum_version_id = 1,
3aff6c2f	398	.fields = (VMStateField[]) {
a90db158 AK	399	VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
	400	VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
	401	VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
	402	VMSTATE_END_OF_LIST()
	403	},
	404	};
	405
	406	static bool tlb6xx_needed(void *opaque)
	407	{
	408	PowerPCCPU *cpu = opaque;
	409	CPUPPCState *env = &cpu->env;
	410
	411	return env->nb_tlb && (env->tlb_type == TLB_6XX);
	412	}
	413
	414	static const VMStateDescription vmstate_tlb6xx = {
	415	.name = "cpu/tlb6xx",
	416	.version_id = 1,
	417	.minimum_version_id = 1,
5cd8cada	418	.needed = tlb6xx_needed,
3aff6c2f	419	.fields = (VMStateField[]) {
a90db158 AK	420	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	421	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
	422	env.nb_tlb,
	423	vmstate_tlb6xx_entry,
	424	ppc6xx_tlb_t),
	425	VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
	426	VMSTATE_END_OF_LIST()
	427	}
	428	};
	429
	430	static const VMStateDescription vmstate_tlbemb_entry = {
	431	.name = "cpu/tlbemb_entry",
	432	.version_id = 1,
	433	.minimum_version_id = 1,
3aff6c2f	434	.fields = (VMStateField[]) {
a90db158 AK	435	VMSTATE_UINT64(RPN, ppcemb_tlb_t),
	436	VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
	437	VMSTATE_UINTTL(PID, ppcemb_tlb_t),
	438	VMSTATE_UINTTL(size, ppcemb_tlb_t),
	439	VMSTATE_UINT32(prot, ppcemb_tlb_t),
	440	VMSTATE_UINT32(attr, ppcemb_tlb_t),
	441	VMSTATE_END_OF_LIST()
	442	},
	443	};
	444
	445	static bool tlbemb_needed(void *opaque)
	446	{
	447	PowerPCCPU *cpu = opaque;
	448	CPUPPCState *env = &cpu->env;
	449
	450	return env->nb_tlb && (env->tlb_type == TLB_EMB);
	451	}
	452
	453	static bool pbr403_needed(void *opaque)
	454	{
	455	PowerPCCPU *cpu = opaque;
	456	uint32_t pvr = cpu->env.spr[SPR_PVR];
	457
	458	return (pvr & 0xffff0000) == 0x00200000;
	459	}
	460
	461	static const VMStateDescription vmstate_pbr403 = {
	462	.name = "cpu/pbr403",
	463	.version_id = 1,
	464	.minimum_version_id = 1,
5cd8cada	465	.needed = pbr403_needed,
3aff6c2f	466	.fields = (VMStateField[]) {
a90db158 AK	467	VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
	468	VMSTATE_END_OF_LIST()
	469	},
	470	};
	471
	472	static const VMStateDescription vmstate_tlbemb = {
	473	.name = "cpu/tlb6xx",
	474	.version_id = 1,
	475	.minimum_version_id = 1,
5cd8cada	476	.needed = tlbemb_needed,
3aff6c2f	477	.fields = (VMStateField[]) {
a90db158 AK	478	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	479	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
	480	env.nb_tlb,
	481	vmstate_tlbemb_entry,
	482	ppcemb_tlb_t),
	483	/* 403 protection registers */
	484	VMSTATE_END_OF_LIST()
	485	},
5cd8cada JQ	486	.subsections = (const VMStateDescription*[]) {
	487	&vmstate_pbr403,
	488	NULL
a90db158 AK	489	}
	490	};
	491
	492	static const VMStateDescription vmstate_tlbmas_entry = {
	493	.name = "cpu/tlbmas_entry",
	494	.version_id = 1,
	495	.minimum_version_id = 1,
3aff6c2f	496	.fields = (VMStateField[]) {
a90db158 AK	497	VMSTATE_UINT32(mas8, ppcmas_tlb_t),
	498	VMSTATE_UINT32(mas1, ppcmas_tlb_t),
	499	VMSTATE_UINT64(mas2, ppcmas_tlb_t),
	500	VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
	501	VMSTATE_END_OF_LIST()
	502	},
	503	};
	504
	505	static bool tlbmas_needed(void *opaque)
	506	{
	507	PowerPCCPU *cpu = opaque;
	508	CPUPPCState *env = &cpu->env;
	509
	510	return env->nb_tlb && (env->tlb_type == TLB_MAS);
	511	}
	512
	513	static const VMStateDescription vmstate_tlbmas = {
	514	.name = "cpu/tlbmas",
	515	.version_id = 1,
	516	.minimum_version_id = 1,
5cd8cada	517	.needed = tlbmas_needed,
3aff6c2f	518	.fields = (VMStateField[]) {
a90db158 AK	519	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	520	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
	521	env.nb_tlb,
	522	vmstate_tlbmas_entry,
	523	ppcmas_tlb_t),
	524	VMSTATE_END_OF_LIST()
	525	}
	526	};
	527
	528	const VMStateDescription vmstate_ppc_cpu = {
	529	.name = "cpu",
	530	.version_id = 5,
	531	.minimum_version_id = 5,
	532	.minimum_version_id_old = 4,
	533	.load_state_old = cpu_load_old,
	534	.pre_save = cpu_pre_save,
	535	.post_load = cpu_post_load,
3aff6c2f	536	.fields = (VMStateField[]) {
569be9f0	537	VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
a90db158 AK	538
	539	/* User mode architected state */
	540	VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
	541	#if !defined(TARGET_PPC64)
	542	VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
	543	#endif
	544	VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
	545	VMSTATE_UINTTL(env.nip, PowerPCCPU),
	546
	547	/* SPRs */
	548	VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
	549	VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
	550
	551	/* Reservation */
	552	VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
	553
	554	/* Supervisor mode architected state */
	555	VMSTATE_UINTTL(env.msr, PowerPCCPU),
	556
	557	/* Internal state */
	558	VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
	559	/* FIXME: access_type? */
	560
	561	/* Sanity checking */
	562	VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
	563	VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
	564	VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
	565	VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
	566	VMSTATE_END_OF_LIST()
	567	},
5cd8cada JQ	568	.subsections = (const VMStateDescription*[]) {
	569	&vmstate_fpu,
	570	&vmstate_altivec,
	571	&vmstate_vsx,
	572	&vmstate_sr,
a90db158	573	#ifdef TARGET_PPC64
5cd8cada JQ	574	&vmstate_tm,
5cd8cada JQ	575	&vmstate_slb,
a90db158	576	#endif /* TARGET_PPC64 */
5cd8cada JQ	577	&vmstate_tlb6xx,
	578	&vmstate_tlbemb,
	579	&vmstate_tlbmas,
	580	NULL
a90db158 AK	581	}
a90db158 AK	582	};